Bottom-pinned spin-orbit torque magnetic random access memory and method of manufacturing the same

Abstract

This invention proposes a bottom-pinned spin-orbit torque magnetic memory, comprising a substrate, a lower electrode layer on the substrate, a magnetic tunneling interface on the lower electrode layer, a spin-orbit torque layer on the magnetic tunneling interface, a capping layer on the spin-orbit torque layer, and an injection layer on the capping layer, wherein the injection layer is divided into an independent first part and a second part, and the first part and the second part are respectively connected to both ends of the capping layer.

Description

Technical Field

[0001] This invention is generally related to a spin-orbit torque magnetic memory (SOT-MRAM), and more specifically, it relates to a bottom-pin type spin-orbit torque magnetic memory and its manufacturing method. Prior Technology

[0002] Magnetic random access memory (MRAM) has long been regarded by the industry as a crucial emerging memory technology due to its advantages such as fast read / write speeds, non-volatility, and ease of integration with semiconductor manufacturing processes. From early types that operated via magnetic fields, to the recently commercialized spin-transfer torque (STT) type, and now the spin-transfer orbit (SOT) type that the industry is actively researching and developing, the operating mode of MRAM has changed from indirectly supplying a magnetic field with an electric current to directly applying a very short pulse for read / write operations, achieving the goal of fast read / write speeds.

[0003] For spin-orbit torque magnetic random access memory (SOT-MRAM), depending on the position of its pinned layer, it can be divided into two types: top-pinned and bottom-pinned. In bottom-pinned SOT-MRAM, the pinned layer is located below the memory cell, hence the name. Its spin-orbit torque layer is located above the memory cell and current is injected into the spin-orbit torque layer through an injection layer to generate spin torque, thereby achieving the effect of flipping the magnetic moment of the magnetic film layer.

[0004] However, in current bottom-mounted SOT-MRAM designs, the current injected into the injection layer does not flow completely through the spin-orbit torque layer. It may be shunted by the injection layer itself, resulting in only a portion of the original current flowing through the spin-orbit torque layer. This necessitates a larger current than expected to achieve memory operation, which in turn requires a correspondingly larger transistor channel width, hindering memory miniaturization. Therefore, those skilled in the art must still improve the existing bottom-mounted SOT-MRAM structure to address the current efficiency issues caused by this design. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the current known technology, the present invention proposes a novel bottom-pin type spin-orbit torque magnetic memory structure and its manufacturing method. The feature is that the current injection layer is divided into two independent parts and connected to the two ends of the spin-orbit torque layer respectively, so as to achieve the effect of allowing the spin current to flow completely through the spin-orbit torque layer.

[0006] One aspect of this invention is to provide a bottom-pinned spin-orbit torque magnetic memory, the structure of which includes a substrate, a lower electrode layer on the substrate, a magnetic tunneling interface on the lower electrode layer, a spin-orbit torque layer on the magnetic tunneling interface, a cover layer on the spin-orbit torque layer, and an injection layer on the cover layer, wherein the injection layer is divided into an independent first part and a second part, the first part and the second part being connected to both ends of the cover layer respectively.

[0007] Another aspect of the present invention is to provide a method for fabricating a bottom-pinned spin-orbit torque magnetic memory, the steps of which include providing a substrate, sequentially forming a lower electrode layer, a pinned layer, a reference layer, a free layer, a spin-orbit torque layer and a capping layer on the substrate, performing a photolithography process to pattern the lower electrode layer, the pinned layer, the reference layer, the free layer, the spin-orbit torque layer and the capping layer to form a memory cell, forming an injection layer on the capping layer, and performing another photolithography process to pattern the injection layer into a first portion and a second portion, wherein the first portion and the second portion are respectively connected to both ends of the capping layer.

[0008] Another aspect of the present invention is to provide a method for fabricating a bottom-pinned spin-orbit torque magnetic memory, the steps of which include providing a substrate; sequentially forming a lower electrode layer, a pinned layer, a reference layer, a free layer, a spin-orbit torque layer, a capping layer, and a metal oxide layer on the substrate; performing a photolithography process to pattern the lower electrode layer, the pinned layer, the reference layer, the free layer, the spin-orbit torque layer, the capping layer, and the metal oxide layer to form a memory cell; forming an implantation layer on the capping layer, wherein a portion of the capping layer is in direct contact with the implantation layer; and performing an annealing process to allow oxygen atoms in the metal oxide layer to enter the implantation layer, thereby oxidizing the portion of the implantation layer in direct contact with the metal oxide layer into a barrier layer.

[0009] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Simple Explanation of the Diagram

[0010] This specification includes accompanying drawings, which form part of this specification, to provide the reader with a further understanding of the embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings: Figure 1 is a cross-sectional schematic diagram of a bottom-pinned spin-orbit torque magnetic memory (SOT-MRAM) according to an embodiment of the present invention; Figure 2 is a cross-sectional schematic diagram of a SOT-MRAM according to another embodiment of the present invention; Figures 3 to 9 are cross-sectional schematic diagrams of a SOT-MRAM fabrication process according to an embodiment of the present invention; and Figures 10 and 11 are cross-sectional schematic diagrams of a SOT-MRAM fabrication process according to another embodiment of the present invention. It should be noted that all illustrations in this specification are for illustrative purposes only. For clarity and ease of explanation, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments. Implementation

[0011] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0012] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" implies not only being "directly on" something but also includes being "on" something with an intervening feature or layer. Similarly, "above" or "above" implies not only being "above" or "above" something but also being "above" or "above" something without an intervening feature or layer (i.e., directly on something). Furthermore, spatially related terms such as "below," "under," "lower part," "above," and "upper part" are used herein for descriptive convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0013] As used herein, the term "substrate" refers to the material on which subsequent material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0014] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0015] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0016] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they explicitly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0017] First, please refer to Figure 1, which is a cross-sectional schematic diagram of a bottom-pinned spin-orbit torque magnetic memory (SOT-MRAM) according to an embodiment of the present invention. The SOT-MRAM 100 of the present invention is constructed on a substrate, which may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers. Since the focus of the present invention is on SOT-MRAM disposed in the CMOS back-end process (BEOL) layer, subsequent cross-sectional diagrams will only show these layers and the connections between related components. Taking the structure in Figure 1 as an example, the SOT-MRAM of the present invention is disposed within an inter-metal dielectric layer 126 (such as a third inter-metal dielectric layer IMD3), below which is a front dielectric layer structure, which may include an inter-metal dielectric layer (such as a second inter-metal dielectric layer IMD2) 102, a capping layer 104, and a bottom dielectric layer 106. The intermetallic dielectric layer 102 can be made of an ultra-low dielectric constant (ULK) material, in which a metal interconnect layer (such as a second metal interconnect layer) M2 can be formed. A thinner capping layer 104 is formed on the surfaces of the intermetallic dielectric layer 102 and the metal interconnect layer M2, and its material can be silicon carbonitride (SiCN), which can be used as an etch stop layer. A thicker bottom dielectric layer 106 is formed on the capping layer 104, and its material can be tetraethoxysilane (TEOS), which is the starting layer for the magnetic memory of the present invention.

[0018] Referring again to Figure 1, the SOT-MRAM 100, from the bottom dielectric layer 106 upwards, sequentially includes a lower electrode layer 108, a pinned layer 110, a reference layer 112, a free layer 114, a spin-orbit torque layer 116, and a capping layer 118. These layers are patterned into individual memory cells 119, completely overlapping in the direction perpendicular to the substrate, and connected from the lower electrode layer 108 through the lower tungsten via Wvia through the capping layer 104 to the lower metal interconnect layer M2. The material of the lower electrode layer 108 can be tantalum (Ta), platinum (Pt), gold (Au), ruthenium (Ru), or a multilayer structure thereof. The pinned layer 110, reference layer 112, and free layer 114 above the lower electrode layer 108 constitute the magnetic tunnel junction (MTJ) structure of the SOT-MRAM 100 in this invention. In this invention, since the needle-piercing layer 110 is located at the bottom of the MTJ structure, it is called bottom-needle-piercing SOT-MRAM.

[0019] In this embodiment of the invention, the needle-piercing layer 110 may be made of a ferromagnetic material, including but not limited to iron (Fe), cobalt (Co), nickel (Ni), or alloys thereof such as iron-cobalt-boron (CoFeB) or iron-cobalt (CoFe). Alternatively, the needle-piercing layer 110 may also be made of an antiferromagnetic (AFM) material, including but not limited to iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), or combinations thereof. The reference layer 112 may be made of a ferromagnetic material, including but not limited to cobalt (Co), iron-cobalt (CoFe), iron-nickel (NiFe), or nickel-iron-cobalt (CoFe), etc. The pinned layer 110 and the reference layer 112 serve to fix or restrict the direction of the magnetic moments in their adjacent layers, making them less susceptible to flipping due to an applied magnetic field. The magnetic moment of the reference layer 112 serves as a reference for the magnetization direction of the upper free layer 114, while the pinned layer 110 compensates for stray magnetic fields from the reference layer 112, and its magnetic moment may be opposite to that of the reference layer 112. The pinned layer 110 and the reference layer 112 can be collectively referred to as a synthetic antiferromagnet (SAF). The free layer 114 can be made of ferromagnetic materials, including but not limited to iron (Fe), cobalt (Co), nickel (Ni), or their alloys such as iron-cobalt-boron (CoFeB) or iron-cobalt (CoFe). The magnetic moment of the free layer 114 can freely flip and change with an applied electric field. When the magnetization directions of the reference layer 112 and the free layer 114 are aligned, the majority states of electrons in the two ferromagnetic materials have the same spin direction, resulting in a higher tunneling probability and a larger tunneling current. The MTJ will then exhibit a low-resistance state ("0" bit). Conversely, the MTJ will exhibit a high-resistance state ("1" bit). This method of changing the resistance by altering the electron spin direction is the principle behind how magnetic memory achieves data storage. In this embodiment, a tunneling barrier layer structure (not shown) may also be formed between the pinned layer 110, the reference layer 112, and the free layer 114. This layer may be made of an insulating material, including but not limited to magnesium oxide (MgO) or aluminum oxide (AlOx). A spacer 120 is also formed on the outer side of the memory cell, extending from the sidewalls of the capping layer 118, the spin-orbit torque layer 116, the free layer 114, the reference layer 112, the pinned layer 110, and the lower electrode layer 108 to the surface of the bottom dielectric layer 106 below. The spacer 120 can provide protection for the memory cell 119, and its material can be silicon nitride (SiNx).

[0020] Please now refer to Figure 7. In the conventional bottom-mounted SOT-MRAM structure, an injection layer 122 is disposed above the memory cell 119 to provide current flow through the spin orbital torque layer 116, thereby generating spin torque through the spin Hall effect (SHE) to change the magnetic moment of the magnetic material in the MTJ. The entire memory cell 119, including the injection layer 122, is formed within the intermetallic dielectric layer 126. The two ends of the injection layer 122 are respectively connected to the metal interconnect layer M4 formed in the intermetallic dielectric layer (such as the fourth intermetallic dielectric layer IMD4) 130 through vias V3, thereby inputting / outputting current. In the prior art, the current flowing into one end of the injection layer 122 is shunted at the interface between the injection layer 122 and the capping layer 118. A portion of the current I1 continues to flow through the injection layer 122 to the other end, while the other portion of the current I2 flows through the spin-orbit torque layer 116 below to the other end. This shunting phenomenon means that only a portion of the original input current (e.g., 310 µA) flows through the spin-orbit torque layer 116 (e.g., 169 µA) to achieve the effect of changing the magnetic moment. This results in a need for a larger current to be supplied from the injection layer 122 than expected to achieve the operation of the magnetic memory, which in turn requires a correspondingly wider transistor channel, hindering the miniaturization of the memory size.

[0021] Referring back to Figure 1, in this embodiment of the invention, a barrier layer 124 is formed at the midpoint where the injection layer contacts the capping layer 118. The barrier layer 124 divides the entire injection layer into two independent parts: a first part 122a and a second part 122b, which are respectively connected to the two ends of the capping layer 118 below. The barrier layer 124 can be an oxide of the injection layer material. For example, the injection layer material can be titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), or tantalum (Ta), and the barrier layer 124 material can be titanium oxide (TiOx) or tantalum oxide (TaOx). Because the resistance of the oxide barrier layer 124 is much higher than that of the spin-orbit torque layer 116, most of the current I flowing into the first part 122a of the injection layer will flow to the second part 122b of the injection layer through the lower spin-orbit torque layer 116, thus reducing the occurrence of current shunting by the injection layer. This structural design enables the SOT-MRAM of the present invention to achieve better current utilization efficiency. Taking the aforementioned conventional technology as an example, if the spin-orbit torque layer 116 requires a current flow of 169 µA to achieve the required spin-orbit torque, then the injection layer only needs to pass a current slightly greater than 169 µA, instead of the nearly twice the current of 310 µA required due to current shunting as in the conventional technology. This also means that the transistor width required by the present invention is only half that of the conventional technology, allowing the size and area of ​​the SOT-MRAM memory cell of the present invention to be reduced by half compared to the conventional technology, which is beneficial to the design requirements of device miniaturization. It should be noted that the width of the barrier layer 124 in the horizontal direction shown in the embodiment of Figure 1 is slightly smaller than the width of the memory cell 119 below in the horizontal direction. However, in other embodiments, such as Figure 9, the width of the barrier layer 124 in the horizontal direction may also be the same as the width of the memory cell 119 below in the horizontal direction.

[0022] Please now refer to Figure 2, which is a cross-sectional schematic diagram of a SOT-MRAM according to another embodiment of the present invention. The difference between this embodiment and the embodiment in Figure 1 is that, in this embodiment, a barrier layer is not formed in the injection layer; instead, the middle portion 122c of the injection layer is directly removed to divide the injection layer into independent first portions 122a and second portions 122b. The advantage of this embodiment is that it ensures that all current flowing from the injection layer passes through the spin-orbit torque layer 116, further improving the current utilization efficiency of the magnetic memory of the present invention.

[0023] Please now refer to Figures 3 through 9, which are cross-sectional schematic diagrams of a SOT-MRAM fabrication process according to an embodiment of the present invention. First, in Figure 3, a substrate is provided as the basis for the entire magnetic memory. The substrate may include the aforementioned intermetallic dielectric layer (such as the second intermetallic dielectric layer IMD2) 102, capping layer 104, and bottom dielectric layer 106, etc. The materials may be ultra-low dielectric constant material (ULK), silicon carbonitride (SiCN), and tetraethoxysilane (TEOS), respectively, and may be formed by deposition methods such as plasma-assisted chemical vapor deposition (PECVD), sub-atmospheric pressure chemical vapor deposition (APCVD), or low-pressure chemical vapor deposition (LPCVD). A metal interconnect layer (such as the second metal interconnect layer) M2 has been formed in the intermetallic dielectric layer 102, and a tungsten via has been formed in the bottom dielectric layer 106, which passes through the capping layer 104 and connects to the underlying metal interconnect layer M2.

[0024] Referring again to Figure 3, a layered structure of memory cells, including a lower electrode layer 108, a needled layer 110, a reference layer 112, a free layer 114, a spin-orbit torque layer 116, and a capping layer 118, is sequentially formed on the bottom dielectric layer 106 and the tungsten via Wvia. The lower electrode layer 108 can be made of tantalum (Ta), platinum (Pt), gold (Au), ruthenium (Ru), or a multilayer structure thereof. The needled layer 110 can be made of, but is not limited to, iron (Fe), cobalt (Co), nickel (Ni), or their alloys such as iron-cobalt-boron (CoFeB) or iron-cobalt (CoFe). The reference layer 112 can be made of, but is not limited to, cobalt (Co), iron-cobalt (CoFe), iron-nickel (NiFe), or nickel-iron-cobalt (CoFe). The free layer 114 can be made of, but is not limited to, iron (Fe), cobalt (Co), nickel (Ni), or their alloys such as iron-cobalt-boron (CoFeB) or iron-cobalt (CoFe). The material of the spin-orbit torque layer 116 may include tungsten (W). The material of the capping layer 118 may include ruthenium (Ru). The above layer structures can be formed by physical vapor deposition (PVD) or sputtering processes.

[0025] Please refer to Figure 4. After forming the above layer structure, an ion beam etching process is then performed to pattern these layer structures into individual memory cells 119. The pinned layer 110, reference layer 112, and free layer 114 serve as the magnetic tunneling junction (MTJ) structure of the magnetic memory, connecting the spin-orbit torque layer 116 and the lower electrode layer 108 above and below, respectively. The ruthenium capping layer 118 acts as a hard mask layer during this etching process to protect the underlying spin-orbit torque layer 116 and MTJ structure from damage. As shown in Figure 4, the etched bottom dielectric layer 106 will have a slightly raised cross-sectional profile towards the memory cells 119.

[0026] Please refer to Figure 5. After patterning the magnetic memory cell 119, a protective spacer 120 is then formed on the sidewall of the magnetic memory cell 119. The spacer 120 can be made of silicon nitride, and it can be formed by first forming a conformal spacer layer on the surface of the memory cell 119 and the bottom dielectric layer 106, and then performing a photolithography process to pattern it. It extends from the sidewall of the capping layer 118, the spin-orbit torque layer 116, the free layer 114, the reference layer 112, the pinned layer 110, and the lower electrode layer 108 all the way to the surface of the bottom dielectric layer 106 below. After the spacer 120 is formed, an intermetallic dielectric layer (such as a third intermetallic dielectric layer IMD3) 126 is then formed on the bottom dielectric layer 106 around the memory cell 119. The intermetallic dielectric layer 126 can be made of an ultra-low dielectric constant material (ULK), which can be formed by a PECVD process and will be subjected to a planarization process to make its top surface flush with the top surface of the cover layer 118 of the memory cell 119.

[0027] Please refer to Figure 6. After forming the spacer 120 and the intermetallic dielectric layer 126, an implantation layer 122 is then formed on the top surface of the intermetallic dielectric layer 126 and the memory cell 119. In this embodiment of the invention, the material of the implantation layer 122 can be titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), or tantalum (Ta). It can be formed on the surface by a sputtering process and then patterned by a reactive ion etching process. In this embodiment of the invention, the middle portion of the patterned implantation layer 122 will contact the capping layer 118 of the memory cell 119.

[0028] Please refer to Figure 7. After the injection layer 122 is formed, another dielectric layer is then applied over the injection layer 122, so that the entire memory cell 119, including the injection layer 122, is enclosed within the inter-metal dielectric layer 126. Subsequently, a capping layer 128 (material may be SiCN) and an inter-metal dielectric layer (such as a fourth inter-metal dielectric layer IMD4, material may be ULK) 130 are sequentially formed on the inter-metal dielectric layer 126, and interconnect structures such as a metal interconnect layer M4 and vias V3 are formed in the inter-metal dielectric layer 130. The two ends of the injection layer 122 are electrically connected to the upper metal interconnect layer M4 through vias V3. As can be seen from the figure, at this stage, the injection layer 122 is still entirely connected to the capping layer 118 of the memory cell 119, as in the prior art. Subsequent embodiments will explain how the present invention divides the injection layer 122 into two independent parts.

[0029] Please refer to Figure 8. In one embodiment, a metal oxide layer 123 is further formed between the implantation layer 122 and the capping layer 118 of the memory cell 119. In this embodiment, the metal oxide layer 123 serves as a deoxidizing layer to provide oxygen atoms to the upper implantation layer 122, thereby forming an oxide barrier layer. In this embodiment, the material of the metal oxide layer 123 corresponds to the material of the implantation layer 122. For example, when the material of the implantation layer 122 is titanium (Ti) or titanium nitride (TiN), the material of the metal oxide layer 123 can be titanium oxide (TiOx). Alternatively, when the material of the implantation layer 122 is tantalum (Ta) or tantalum nitride (TaN), the material of the metal oxide layer 123 can be tantalum oxide (TaOx). This material-matching design facilitates the diffusion of oxygen atoms from the metal oxide layer 123 to the implantation layer 122.

[0030] Please refer to Figure 9. Following the steps after the formation of implanted layer 122 in Figure 6, an annealing process is performed, allowing oxygen atoms in the metal oxide layer 123 to diffuse into the adjacent implanted layer 122. Thus, as shown in Figure 9, a portion of the implanted layer 122 adjacent to the metal oxide layer 123 will oxidize and transform into a barrier layer 124, which can be made of titanium oxide or tantalum oxide. The barrier layer 124 formed in this step divides the implanted layer 122 into two independent parts, a first part 122a and a second part 122b. Since the barrier layer 124 is made of the same material as the underlying metal oxide layer 123, their resistances will be very close. On the other hand, in this step, because the material of the metal oxide layer 123 corresponds to the material of the implanted layer 122, oxygen atoms diffuse more easily into the implanted layer 122. Also adjacent to the metal oxide layer 123 is the lower capping layer 118, but its material (such as ruthenium Ru) is not designed to correspond to the metal oxide layer 123, so no oxidation sites are formed. In this embodiment, since the resistance of the oxide barrier layer 124 (approximately 1040 Ω) is approximately the same as that of the metal oxide layer 123 and much higher than that of the spin-orbit torque layer 116 below (approximately 347 Ω), most of the current flowing in from the first part 122a of the injection layer will flow through the path of the spin-orbit torque layer 116 to the second part 122b of the injection layer, reducing the occurrence of current being diverted by the injection layer.

[0031] Please refer to Figure 10. In another embodiment, following the steps after the formation of the implantation layer 122 in Figure 6, the implantation layer of the present invention is directly patterned into independent first portions 122a and second portions 122b through a photolithography process. As shown in Figure 10, in this process, the middle portion 122c of the implantation layer is removed, so that the implantation layer is divided into independent first portions 122a and second portions 122b, and the first portions 122a and the second portions 122b are respectively connected to both ends of the underlying capping layer 118. In this way, all the current flowing from the first portion 122a of the implantation layer will flow to the second portion 122b of the implantation layer through the underlying spin-orbit torque layer 116, greatly improving the current utilization efficiency.

[0032] Please refer to Figure 11. After dividing the implanted layer into a first part 122a and a second part 122b, an insulating layer 126 can be further filled at the middle part 122c where the implanted layer has been removed, to further enhance the electrical isolation effect between the first part 122a and the second part 122b. The insulating layer 126 can be part of the intermetallic dielectric layer 126 that will be formed on the implanted layer 122 later, or it can be an additional dielectric layer, and its material can be an ultra-low dielectric constant material (ULK), but is not limited thereto.

[0033] Based on the above embodiments, the present invention divides the injection layer of the bottom-pinned spin-orbit torque magnetic memory into two independent parts, thereby enabling the current to flow through the spin-orbit torque layer path, which greatly improves the current efficiency of the memory and facilitates the miniaturization of transistor size. It is an invention that is both novel and progressive. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0034] 100: Spin-orbit torque magnetic memory (SOT-MRAM) 102: Intermetallic dielectric layer 104: Overlay 106: Bottom Dielectric Layer 108: Lower electrode layer 110: Needle-pierced layer 112: Reference Layer 114: Free Layer 116: Spin-orbit torque layer 118: Overlay 119: Memory Unit 120: Spacer 122: Injection Layer 122a: Part 1 122b: Part Two 122c: Middle part 123: Metal oxide layer (deoxidation layer) 124: Barrier Layer 126: Intermetallic dielectric layer (insulating layer) 128: Overlay 130: Intermetallic dielectric layer I, I 1, I 2: current MTJ: Magnetic Tunneling Joint M2, M4: Metal interconnect layers V3: Guide hole component Wvia: Tungsten guide hole components

Claims

1. A bottom-mounted spin-orbit torque magnetic memory, comprising: a substrate; a lower electrode layer located on the substrate; a magnetic tunneling interface located on the lower electrode layer; a spin-orbit torque layer located on the magnetic tunneling interface; a capping layer located on the spin-orbit torque layer, wherein the capping layer, the spin-orbit torque layer, the magnetic tunneling interface, and the lower electrode layer constitute a memory cell; an injection layer located on the capping layer, wherein the injection layer is divided into an independent first part and a second part, the first part and the second part being respectively connected to both ends of the capping layer; and an insulating layer located between the first part and the second part, wherein the top surface of the insulating layer is flush with the top surfaces of the first part and the second part.

2. The bottom-pinned spin-orbit torque magnetic memory as described in claim 1, wherein the magnetic tunneling interface comprises, from bottom to top, a pinned layer, a reference layer and a free layer from the substrate.

3. The bottom-pinned spin-orbit torque magnetic memory as described in claim 1, wherein the lower electrode layer is electrically connected to a lower metal interconnect layer through a via.

4. The bottom-pinned spin-orbit torque magnetic memory as described in claim 1, wherein the first part and the second part are respectively electrically connected to an upper metal interconnect layer through a via.

5. The bottom-pinned spin-orbit torque magnetic memory as described in claim 1 further includes a spacer formed on the sidewall of the memory cell.

6. The bottom-pinned spin-orbit torque magnetic memory as described in claim 1, wherein the lower electrode layer, the magnetic tunneling interface, the spin-orbit torque layer, and the cover layer completely overlap in the direction perpendicular to the substrate.

7. The bottom-pinned spin-orbit torque magnetic memory as described in claim 1, wherein the material of the spin-orbit torque layer is tungsten.

8. The bottom-pinned spin-orbit torque magnetic memory as described in claim 1, wherein the material of the covering layer is ruthenium.

9. The bottom-pinned spin-orbit torque magnetic memory as described in claim 1, wherein the material of the injection layer is titanium nitride, titanium, tantalum nitride, or tantalum.

10. A method for fabricating a bottom-pinned spin-orbit torque magnetic memory, comprising: providing a substrate; sequentially forming a lower electrode layer, a pinned layer, a reference layer, a free layer, a spin-orbit torque layer, and a capping layer on the substrate; performing a photolithography process to pattern the lower electrode layer, the pinned layer, the reference layer, the free layer, the spin-orbit torque layer, and the capping layer to form a memory cell; forming an injection layer on the capping layer; performing another photolithography process to pattern the injection layer into independent first and second portions, wherein the first and second portions are respectively connected to both ends of the capping layer; and forming an insulating layer between the first and second portions.

11. The method for manufacturing a bottom-pinned spin-orbit torque magnetic memory as described in claim 10 further includes forming a spacer wall on the sidewall of the memory cell.

12. The method for manufacturing a bottom-pinned spin-orbit torque magnetic memory as described in claim 10, wherein the material of the spin-orbit torque layer is tungsten.

13. The method for manufacturing a bottom-pinned spin-orbit torque magnetic memory as described in claim 10, wherein the material of the covering layer is ruthenium.

14. The method for manufacturing a bottom-pinned spin-orbit torque magnetic memory as described in claim 10, wherein the material of the injection layer is titanium nitride, titanium, tantalum nitride, or tantalum.

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