Semiconductor device and method for fabricating the same

Abstract

Embodiments of the present invention can provide a semiconductor device and a method thereof capable of covering the entire surface of a dielectric layer while maintaining the thickness of the upper electrode of a capacitor by increasing continuity. Furthermore, embodiments of the present invention can provide a semiconductor device and a method thereof capable of mitigating the bending of the lower electrode. According to one embodiment of the present invention, a semiconductor device includes: a lower electrode structure formed above a substrate; a dielectric layer formed above the lower electrode structure; and an upper electrode structure formed on the dielectric layer and including a silicon-containing amorphous layer in contact with the dielectric layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a capacitor for a semiconductor device and a method for manufacturing the capacitor. Prior Technology

[0002] With the integration of semiconductor devices, continuity becomes difficult to ensure due to bending of the lower electrode and reduction in the thickness of the upper electrode. As a result, the characteristics of capacitors may deteriorate.

[0003] Cross-referencing of related applications: This application claims priority to Korean Patent Application No. 10-2021-0135776, filed on October 13, 2021, the entire contents of which are incorporated herein by reference. Summary of the Invention

[0004] Embodiments of the present invention may provide a semiconductor device and a method for manufacturing the same, wherein the semiconductor device is capable of covering the entire surface of a dielectric layer by increasing continuity while maintaining the thickness of the upper electrode of a capacitor.

[0005] Furthermore, embodiments of the present invention can provide a semiconductor device and a method for manufacturing the same, which can reduce the occurrence of bending of the lower electrode.

[0006] A semiconductor device according to an embodiment of the present invention includes: a lower electrode structure formed above a substrate; a dielectric layer formed above the lower electrode structure; and an upper electrode structure formed on the dielectric layer and including a silicon-containing amorphous layer in contact with the dielectric layer.

[0007] A semiconductor device according to an embodiment of the present invention includes: a lower electrode structure including a stacked structure formed by a first lower electrode and a second lower electrode, the first lower electrode being formed above a substrate and having a cylindrical structure, the second lower electrode being disposed inside the first lower electrode and having a smaller grain size than the first lower electrode; a dielectric layer being formed above the lower electrode structure; and an upper electrode structure being formed above the dielectric layer.

[0008] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a lower electrode structure over a substrate; forming a dielectric layer over the lower electrode structure; and forming an upper electrode structure including a silicon-containing amorphous layer over the dielectric layer.

[0009] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a lower electrode structure comprising a stacked structure formed by a first lower electrode and a second lower electrode, the first lower electrode having a cylindrical structure and being formed above a substrate, the second lower electrode being disposed inside the first lower electrode and having a smaller grain size than the first lower electrode; forming a dielectric layer above the lower electrode structure; and forming an upper electrode structure above the dielectric layer.

[0010] The present invention has the following effect: by applying the upper electrode of the capacitor as a stacked structure of amorphous and crystalline layers to cover all surfaces of the dielectric layer, the reliability of the semiconductor device can be improved even with a thin thickness.

[0011] In addition, the present invention has the following effect: improving the reliability of semiconductor devices by reducing the occurrence of bending of the lower electrode. Simple Explanation of the Diagram

[0012] Figures 1 to 6 are cross-sectional views illustrating capacitors according to embodiments of the present invention. Figures 7A to 7H are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 8 is a timing diagram of the formation of titanium silicon nitride for the lower electrode according to an embodiment of the present invention. Figure 9 is a timing diagram of the formation of the upper electrode according to an embodiment of the present invention. Implementation

[0013] The embodiments described herein will be explained with reference to cross-sectional views, plan views, and block diagrams, which serve as schematic representations of the invention. Therefore, the structures in the drawings may be modified due to manufacturing techniques and / or tolerances. The embodiments of the invention are not limited to the specific structures shown in the drawings, but include any variations in the structures that may be produced according to the manufacturing process. Furthermore, any regions and their shapes shown in the drawings are schematic diagrams intended to illustrate specific examples of the regional structures of various elements and are not intended to limit the scope of the invention.

[0014] Figures 1 to 6 are diagrams illustrating capacitors according to embodiments of the present invention. Figure 8 is a timing diagram of titanium silicon nitride for forming the lower electrode according to an embodiment of the present invention. Figure 9 is a timing diagram for forming the upper electrode according to an embodiment of the present invention.

[0015] As shown in Figure 1, the semiconductor device includes a substrate 101, an interlayer insulating layer 102 formed on the substrate 101, and storage node contact structures 103 and 104 connected to the substrate 101 through the interlayer insulating layer 102. The semiconductor device also includes a capacitor structure formed on the interlayer insulating layer 102. The capacitor structure includes a lower electrode structure 110 connected to the storage node contact structures 103 and 104, a dielectric layer 120 covering the entire structure including the lower electrode structure 110, and an upper electrode structure 130 formed on the dielectric layer 120.

[0016] Substrate 101 may be a material suitable for semiconductor processing. Substrate 101 may include a semiconductor substrate. Substrate 101 may be made of a silicon-containing material. Substrate 101 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. Substrate 101 may include other semiconductor materials, such as germanium. Substrate 101 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate like GaAs. Substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0017] Although not shown in the figure, the buried gate structure can be disposed in the substrate 101, and the bit line structure can be disposed between the storage node contact structures 103 and 104 on the substrate 101.

[0018] Interlayer insulating layer 102 may comprise a single layer or multiple layers of dielectric material. Interlayer insulating layer 102 may comprise a multilayer dielectric material having multiple layers with the same etch selectivity. Interlayer insulating layer 102 may comprise a multilayer dielectric material having multiple layers with different etch selectivity. For example, interlayer insulating layer 102 may comprise nitrides, oxides, oxynitrides, or combinations thereof.

[0019] Storage node contact structures 103 and 104 can penetrate the interlayer insulating layer 102 to connect to the substrate 101. One end of storage node contact structures 103 and 104 can directly contact the bonding area of ​​the substrate 101 (not shown). The other end of storage node contact structures 103 and 104 can directly contact the lower electrode structure 110. Storage node contact structures 103 and 104 can electrically connect the substrate 101 and the lower electrode structure 110. Storage node contact structures 103 and 104 can be a stack of a lower plug 103 and an upper plug 104. The lower plug 103 may include a silicon plug. The upper plug 104 may include a metal plug.

[0020] The lower electrode structure 110 may include a first lower electrode 111 having a cylindrical structure and a second lower electrode 112 disposed inside the first lower electrode 111 and having a columnar structure. The first lower electrode 111 may have a U-shape in cross-sectional view. The first lower electrode 111 may have an annular shape in plan view. The second lower electrode 112 may have an I-shape in cross-sectional view. The second lower electrode 112 may have a circular shape in plan view. The lower electrode structure 110 may have a shape in cross-sectional view where the first lower electrode 111 covers the sidewalls and bottom surface of the second lower electrode 112. The lower electrode structure 110 may have a shape in plan view where the first lower electrode 111 surrounds the periphery of the second lower electrode 112.

[0021] The lower electrode structure 110 can have a high aspect ratio. The lower electrode structure 110 can have an aspect ratio of at least 1:1 or greater. For example, the lower electrode structure 110 can have an aspect ratio of 1:10 or greater. Aspect ratio refers to the ratio of width to height. The upper surface of the first lower electrode 111 and the upper surface of the second lower electrode 112 can be at the same horizontal plane. In another embodiment, the upper surface of the second lower electrode 112 can be located at a lower level than the upper surface of the first lower electrode 111.

[0022] The grain size of the second lower electrode 112 can be smaller than that of the first lower electrode 111. The hardness of the second lower electrode 112 can be greater than that of the first lower electrode 111. The second lower electrode 112 can include a material that is more suitable for gap filling than the first lower electrode 111. The resistivity of the first lower electrode 111 can be lower than that of the second lower electrode 112.

[0023] The first lower electrode 111 may include a metal nitride. For example, the metal nitride may include titanium nitride. In another embodiment, the metal nitride may include a low-resistivity metal nitride. For example, a low-resistivity metal nitride may include any one of tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN), but is not limited thereto. The second lower electrode 112 may include a silicon-containing metal nitride. For example, the second lower electrode 112 may include titanium silicon nitride.

[0024] The second lower electrode 112 can be formed through an atomic layer deposition process. According to one embodiment of the present invention, the second lower electrode 112 may comprise titanium silicon nitride. Therefore, the atomic layer deposition process for forming the second lower electrode 112 can be performed as a process for forming titanium silicon nitride. The atomic layer deposition process for forming the second lower electrode 112 can be referenced to the timing diagram of FIG8.

[0025] Referring to Figure 8, a unit cycle for forming titanium silicon nitride can be performed in the following order: supplying Ti precursor and Si source, supplying Si source, supplying purge gas, and supplying reactant gas and purge gas. That is, in a unit cycle for forming titanium silicon nitride according to an embodiment of the present invention, after two steps of supplying Si source, the steps of supplying purge gas and reactant gas can be performed sequentially.

[0026] The steps of supplying the Ti precursor and Si source can refer to the steps of forming a metal precursor layer, a silicon layer, and a metal-silicon layer. The steps of supplying the Ti precursor and Si source can include supplying a metal precursor and Si source gas in the reaction region onto the deposition target layer (in this embodiment, the deposition target layer refers to the mold structure M10 including the opening 16 shown in FIG. 7B). For example, the Ti precursor can include, but is not limited to, titanium tetrachloride (TiCl₄), and can include titanium-containing metal precursors. The Si source gas can include, for example, silicon tetrahydride (SiH₄), but is not limited to. The Si source can include any source gas including silicon.

[0027] The step of supplying the Si source can refer to the step of forming titanium silicon nitride by supplying Si source gas to a mold structure including an opening. The Si source gas may include, for example, SiH4, but is not limited to, it. The Si source may include any source gas containing silicon. In one embodiment of the invention, the silicon content in the film can be controlled by the step of supplying the Si source. That is, by controlling the silicon content in the film, the grain size and hardness of the film can be adjusted.

[0028] The step of supplying purge gas can refer to the process of supplying purge gas to a mold structure including openings to remove unwanted byproducts from the reaction zone. Purge gas may include, for example, nitrogen (N₂).

[0029] The step of supplying the reactant gas can refer to the step of forming titanium silicon nitride by supplying the reactant gas to a mold structure including an opening. The reactant gas may include, for example, ammonia (NH3), but is not limited to this, and may include reactant gases having nitrides.

[0030] As the silicon content in the film of the second lower electrode 112 increases, the grain size decreases and the film hardness increases. In other words, when external stress is applied, dislocations move along the slip plane of the grains, and at grain boundaries where grain orientation changes, dislocation movement becomes difficult. Therefore, the film hardness may increase because there are relatively more grain boundaries as the grain size decreases.

[0031] As a result, as the overall hardness of the lower electrode structure 110 increases, bending of the lower electrode structure 110 can be prevented during the dip-out process.

[0032] The dielectric layer 120 may cover the entire structure including the lower electrode structure 110. The dielectric layer 120 may be formed to directly contact the first lower electrode 111, which, as previously described, has a lower resistivity than the second lower electrode 112.

[0033] The dielectric layer 120 may include a single-layer structure, a multilayer structure, or a stacked structure. The dielectric layer 120 may have a doped structure or a hybrid structure. The dielectric layer 120 may include a high-k material. The dielectric layer 120 may have a higher dielectric constant than silicon oxide (SiO₂). Silicon oxide may have a dielectric constant of about 3.9, and the dielectric layer 120 may include a material with a dielectric constant of 4 or greater. The high-k material may have a dielectric constant of about 20 or greater. The high-k material may include hafnium oxide (HfO₂), zirconium oxide (ZrO₂), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), tantalum oxide (Ta₂O₅), niobium oxide (Nb₂O₅), or strontium titanium oxide (SrTiO₃). In another embodiment, the dielectric layer 120 may be formed of a composite layer comprising two or more layers of the above-described high-k material. The dielectric layer 120 may be formed of zirconium-based oxide. The dielectric layer 120 may have a stacked structure comprising zirconium oxide (ZrO₂). The stacked structure comprising zirconium oxide (ZrO₂) may include ZA (ZrO₂ / Al₂O₃) or ZAZ (ZrO₂ / Al₂O₃ / ZrO₂). ZA may have a structure in which alumina is stacked on top of zirconium oxide. ZAZ may have a structure in which zirconium oxide, alumina, and zirconium oxide are stacked sequentially. ZrO₂, ZA, and ZAZ may be referred to as zirconium oxide (ZrO₂)-based layers. In another embodiment, the dielectric layer 120 may be formed of a hafnium (Hf)-based oxide. The dielectric layer 120 may have a stacked structure comprising hafnium oxide (HfO₂). The stacked structure comprising hafnium oxide (HfO₂) may include HA (HfO₂ / Al₂O₃) or HAH (HfO₂ / Al₂O₃ / HfO₂). HA can have a structure in which alumina is stacked on hafnium oxide. HAH can have a structure in which hafnium oxide, alumina, and hafnium oxide are stacked in sequence. HfO2, HA, and HAH can be referred to as hafnium oxide (HfO2) based layers.

[0034] In ZA, ZAZ, HA, and HAH, alumina (Al₂O₃) can have a larger band gap than zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). The dielectric constant of alumina (Al₂O₃) can be lower than that of zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). Therefore, dielectric layer 120 can include a stack of high-k materials and high-bandgap materials with band gaps greater than those of the high-k materials. Dielectric layer 120 can include silicon oxide (SiO₂) as a high-bandgap material other than alumina. Because dielectric layer 120 includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be very thin. The high-bandgap material can be thinner than the high-k material.

[0035] In another embodiment, the dielectric layer 120 may include a stacked structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the dielectric layer 120 may include ZAZA (ZrO 2 / Al 2O 3 / ZrO 2 / Al 2O 3), ZAZAZ (ZrO 2 / Al 2O 3 / ZrO 2 / Al 2O 3 / ZrO 2), HAHA (HfO 2 / Al 2O 3 / HfO 2 / Al 2O 3), or HAHAH (HfO 2 / Al 2O 3 / HfO 2 / Al 2O 3 / HfO 2). In the above stacked structures, the alumina (Al 2O 3) can be very thin.

[0036] The upper electrode structure 130 can cover the entire surface of the dielectric layer 120. The upper electrode structure 130 may not have a non-contact portion between the dielectric layer 120 and the upper electrode structure 130, and the effective area of ​​the capacitor structure is increased by having continuity and covering the entire surface of the dielectric layer 120.

[0037] The upper electrode structure 130 may include an amorphous first upper electrode 131 in direct contact with the dielectric layer 120 and a crystalline second upper electrode 132 formed on the first upper electrode 131. The first upper electrode 131 and the second upper electrode 132 may cover the entire surface of the dielectric layer 120 and may be formed to have a uniform thickness along the steps of the lower electrode structure 110 and the dielectric layer 120.

[0038] For example, the upper electrode structure 130 may include a stacked structure of a continuous amorphous first upper electrode 131 and a discontinuous crystalline second upper electrode 132. In another embodiment, the upper electrode structure 130 may include a stacked structure of a discontinuous amorphous first upper electrode 131 and a continuous crystalline second upper electrode 132. In another embodiment, the upper electrode structure 130 may include a continuous amorphous first upper electrode 131 and a continuous crystalline second upper electrode 132. In another embodiment, each of the first upper electrode 131 and the second upper electrode 132 may be formed to be discontinuous, but the entire surface of the dielectric layer 120 may be in direct contact with either the first upper electrode 131 or the second upper electrode 132. As a result, the upper electrode structure 130 may be formed to be continuous. In particular, in this embodiment, the roughness and continuity of the crystalline second upper electrode 132 can be improved by first forming the amorphous first upper electrode 131 on the dielectric layer 120.

[0039] The first upper electrode 131 can be formed to have a minimum thickness so as not to degrade the resistivity characteristics of the electrode. The total thickness of the upper electrode 130, including the first upper electrode 131 and the second upper electrode 132, can be adjusted to not exceed 30 angstroms. For example, when the total thickness of the upper electrode 130 is about 30 angstroms, the thickness of the first upper electrode 131 can be about 7 angstroms, but the invention is not limited thereto.

[0040] The first upper electrode 131 may include a metal nitride having silicon in its composition. For example, the first upper electrode 131 may include amorphous titanium silicon nitride (TiSiN). The second upper electrode 132 may include a metal nitride. For example, the second upper electrode 132 may include titanium nitride (TiN).

[0041] The amorphous first upper electrode 131 and the crystalline second upper electrode 132 can be formed in situ in the same chamber. The amorphous first upper electrode 131 and the crystalline second upper electrode 132 can be formed through an atomic layer deposition process. The atomic layer deposition process used to form the amorphous first upper electrode 131 and the crystalline second upper electrode 132 can be referred to in the timing diagram of Figure 9.

[0042] The timing diagram in Figure 9 uses a titanium precursor as the metal precursor, but the invention is not limited thereto. In another embodiment, any metal precursor suitable for the upper electrode can be used.

[0043] The process of forming the upper electrode 130 of the present invention can be divided into a process of forming an amorphous first upper electrode 131 and a process of forming a crystalline second upper electrode 132. In this embodiment, timing diagrams for forming the amorphous first upper electrode 131 and for forming the crystalline second upper electrode 132 are shown sequentially, but each timing diagram is to show the unit cycle for forming each upper electrode. Therefore, each upper electrode can be formed by repeating the unit cycle. That is, after repeating the unit cycle of forming an amorphous layer to form the amorphous first upper electrode 131, the unit cycle of forming a metal layer can then be repeated to form the crystalline second upper electrode 132.

[0044] The unit cycle for forming the amorphous first upper electrode 131 can be performed in the following order: supplying Ti precursor, supplying purge gas, supplying reactant gas, supplying purge gas, supplying Si source, and supplying purge gas.

[0045] The step of supplying the Ti precursor may refer to the step of supplying a metal-containing precursor on the dielectric layer 120 in the reaction region to form a metal precursor layer. For example, the Ti precursor may include TiCl4, but is not limited thereto. The Ti precursor may include any metal precursor including titanium.

[0046] The step of supplying purge gas can refer to the step of supplying purge gas to the dielectric layer 120 to remove unwanted byproducts on the dielectric layer 120. The purge gas may include, for example, nitrogen (N2).

[0047] The step of supplying the reactive gas can refer to the step of forming titanium nitride by supplying the reactive gas onto the dielectric layer 120. The reactive gas may include, for example, NH3, but is not limited thereto. The reactive gas may include any reactive gas that includes nitrides.

[0048] The step of supplying the Si source can refer to the step of forming titanium silicon nitride by supplying a source gas on the dielectric layer 120. The source gas may include, for example, SiH4, but is not limited to, it. The Si source may include any source gas containing silicon. When a silicon source is supplied to the titanium nitride formed by the step of supplying the reactive gas, silicon diffuses into the previously formed titanium nitride to increase the silicon concentration in the film, promote amorphization, and increase the deposition rate. As the silicon concentration in the film increases, the crystallinity may deteriorate. In detail, since the adsorption of TiCl4 molecules as a titanium source is higher on the Si-N surface than on the Ti-N surface, TiCl4 supplied in the Ti precursor stage is adsorbed on the Si-N surface while the unit cycle is repeated. Therefore, as the surface diffusion of Ti-N is suppressed, a thin and continuous amorphous TiSiN film can be formed.

[0049] The step of supplying purge gas to remove unwanted byproducts can be performed between the steps of supplying the reactant gas and the source gas, and after the step of supplying the Si source.

[0050] As described above, the atomic layer deposition process may include a unit cycle performed in the following order: supplying a precursor, supplying a purge gas, supplying a reactant gas, supplying a purge gas, supplying a source gas, and supplying another purge gas. The unit cycle may be repeated multiple times until the first upper electrode 131 is formed to have a predetermined thickness. The first upper electrode 131 may be formed to have a minimum thickness so as not to degrade the resistivity characteristics of the electrode.

[0051] The unit cycle of the second upper electrode 132 forming crystals can be carried out in the following order: supplying Ti precursor, supplying purge gas, supplying reactant gas, and supplying purge gas.

[0052] The step of supplying the Ti precursor can refer to the step of supplying the metal-containing precursor to the first upper electrode 131 in the reaction space to form a metal precursor layer. For example, the Ti precursor may include TiCl4, but is not limited thereto. The Ti precursor may include any metal precursor including titanium.

[0053] The step of supplying purge gas can be performed after the steps of supplying the Ti precursor and the steps of supplying the reactant gas. It can refer to the step of removing unwanted byproducts from the first upper electrode 131 by supplying purge gas to the first upper electrode 131. The purge gas may include, for example, nitrogen (N₂).

[0054] The step of supplying the reactive gas can refer to the step of forming titanium nitride by supplying the reactive gas to the first upper electrode 131. The reactive gas may include, for example, NH3, but is not limited to, it. The reactive gas may include any reactive gas that includes nitrides.

[0055] As described above, the atomic layer deposition process is performed in a unit cycle including the steps of supplying Ti precursor, supplying purge gas, supplying reactant gas, and supplying purge gas again. This unit cycle can be repeated multiple times until the second upper electrode 132 is formed to have a predetermined thickness. The continuity of the second upper electrode 132 can be improved through the amorphous first upper electrode 131. The thickness of the second upper electrode 132 can be greater than the thickness of the first upper electrode 131.

[0056] In this embodiment, the continuity of the upper electrode can be improved by using a stacked structure of an amorphous first upper electrode 131 and a crystalline second upper electrode 132. By improving the continuity of the upper electrode, the effective area of ​​the capacitor can be increased. By increasing the effective area, the capacitance value can be increased, and leakage current can be reduced.

[0057] As a comparative example, the direct formation of crystalline titanium nitride (TiN) on a dielectric layer is as follows. Titanium nitride can be formed through an atomic layer deposition (ALD) process. In an ALD process, a unit cycle can be repeatedly performed, including a Ti precursor supply step, a purge gas supply step, a reactant gas supply step, and a purge gas supply step. In the Ti precursor supply step, spaced-apart nuclei can be formed on the dielectric layer. When the reactant gas supply step is performed after the purge gas supply step, the previously formed nuclei can grow in both vertical and horizontal directions, and the roughness increases simultaneously. With the repetition of the unit cycle for forming titanium nitride, adjacent grains merge to suppress horizontal growth as the nuclei grow, and the roughness decreases simultaneously. However, since vertical growth continues under the state of suppressed horizontal growth, a columnar structure is eventually formed, and the overall roughness of the film increases. During the crystallization nucleation and growth stages, small-sized grains (embryos) disappear, and only large grains (nuclei) can grow, making it difficult to ensure continuity due to the formation of voids between large grains.

[0058] To ensure continuity, it is important to grow the film in an amorphous state, without crystallinity. During film growth, molecules that have reached the substrate surface require surface diffusion to move to stable positions (lattice positions of crystals). By suppressing this surface diffusion, the film can be grown in an amorphous state. In other words, if initial nucleation is suppressed while the reaction of reactive gas molecules occurs at the substrate surface, a continuous film with a relatively low thickness compared to crystalline films can be formed.

[0059] Therefore, in this embodiment, an amorphous first upper electrode 131 can be formed by supplying a silicon source into titanium nitride formed through the step of supplying reactive gases. The supplied silicon diffuses into the titanium nitride, thereby increasing the silicon concentration in the film and simultaneously promoting amorphization.

[0060] In addition, the upper electrode needs to be thin to prevent the support from cracking due to tensile stress, but it is difficult to form an upper electrode with the required thickness due to insufficient embedding space caused by device integration and step coverage.

[0061] Therefore, in this embodiment, the amorphous first upper electrode 131 is formed to have continuity even at a low thickness, covering the entire surface of the dielectric layer 120, and a crystalline second upper electrode 132 is applied on the amorphous first upper electrode 131. Thus, capacitor characteristics such as capacitance and leakage current can be improved by increasing the effective area of ​​the capacitor and reducing resistivity without increasing the electrode thickness.

[0062] The third upper electrode 133 can be formed on the second upper electrode 132, which fills the space between adjacent lower electrode structures 110.

[0063] The third upper electrode 133 may include a silicon-containing material, a germanium-containing material, a metallic material, or a combination thereof. The third upper electrode 133 may include a metal, a metal nitride, a metal carbide, a conductive metal oxide, or a combination thereof. The third upper electrode 133 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO₂), iridium oxide (IrO₂), or a combination thereof. The third upper electrode 132 may include a silicon (Si) layer, a germanium (Ge) layer, a silicon-germanium (SiGe) layer, or a combination thereof. The third upper electrode 133 may be formed by stacking a silicon-germanium layer on a silicon layer (Si / SiGe). The third upper electrode 133 may be formed by stacking a silicon-germanium layer on a germanium layer (Ge / SiGe). The third upper electrode 133 may include a stack of silicon-containing materials and metallic materials. The third upper electrode 133 can be formed by stacking silicon-germanium layers and tungsten nitride (SiGe / WN).

[0064] In this embodiment, the third upper electrode 133 may include a gap-filling material and a low-resistivity material. The gap-filling material may include silicon-germanium (SiGe), and the low-resistivity material may include tungsten (W). The gap-filling material can fill the narrow gaps between the lower electrode structures 110 without leaving any vacancies. The low-resistivity material can reduce the resistivity of the upper electrode structure 130.

[0065] As shown in Figure 2, the semiconductor device includes a substrate 101, an interlayer insulating layer 102 formed on the substrate 101, and storage node contact structures 103 and 104 connected to the substrate 101 through the interlayer insulating layer 102. The semiconductor device also includes a capacitor structure formed on the interlayer insulating layer 102. The capacitor structure includes a lower electrode structure 210 connected to the storage node contact structures 103 and 104, a dielectric layer 120 covering the entire structure including the lower electrode structure 210, and an upper electrode structure 130 formed on the dielectric layer 120.

[0066] The substrate 101, interlayer insulating layer 102, storage node contact structures 103 and 104, dielectric layer 120, and upper electrode structure 130 shown in Figure 2 have the same structure as those shown in Figure 1. For ease of description, descriptions of repeated structures will be omitted.

[0067] The lower electrode structure 210 may include a first lower electrode 211, a second lower electrode 212, and a third lower electrode 112. The first lower electrode 211 has a cylindrical structure, the second lower electrode 212 has a cylindrical structure and is formed conformally along the inner surface of the first lower electrode 211, and the third lower electrode 112 is disposed inside the second lower electrode 111 and has a columnar structure. The first lower electrode 211 and the second lower electrode 212 may have a U-shape in cross-sectional view. The first lower electrode 211 and the second lower electrode 212 may have an annular shape in plan view. The third lower electrode 213 may have an I-shape in cross-sectional view. The third lower electrode 213 may have a circular shape in plan view. In cross-sectional view, the lower electrode structure 210 may have the shape of the first lower electrode 211 surrounding the sidewall and bottom surface of the second lower electrode 212, and the second lower electrode 121 surrounding the sidewall and bottom surface of the third lower electrode 213. In the plan view, the lower electrode structure 210 may have a shape in which the first lower electrode 211 surrounds the periphery of the second lower electrode 212 and the second lower electrode 212 surrounds the periphery of the third lower electrode 213.

[0068] The lower electrode structure 210 can have a high aspect ratio. The lower electrode structure 210 can have an aspect ratio of at least 1:1 or greater. For example, the lower electrode structure 210 can have an aspect ratio of 1:10 or greater. Aspect ratio refers to the ratio of width to height. The upper surfaces of the first lower electrode 211, the second lower electrode 212, and the third lower electrode 213 can be at the same horizontal plane. In another embodiment, the upper surface of the second lower electrode 212 can be located at a lower level than the upper surface of the first lower electrode 211. The third lower electrode 213 can fill the step formed between the second lower electrode 212 and the first lower electrode 211. The upper surface of the third lower electrode 213 can be at the same horizontal level as the upper surface of the first lower electrode 211.

[0069] The grain size of the second lower electrode 212 can be smaller than that of the first lower electrode 211. The hardness of the second lower electrode 212 can be greater than that of the first lower electrode 211. The second lower electrode 212 can include a material that is more suitable for gap filling than the first lower electrode 211. The resistivity of the first lower electrode 211 can be lower than that of the second lower electrode 212.

[0070] The first lower electrode 211 may include a metal nitride. For example, the metal nitride may include titanium nitride. In another embodiment, the metal nitride may include a low-resistivity metal nitride. The second lower electrode 212 may include a silicon-containing metal nitride. For example, the second lower electrode 212 may include titanium silicon nitride. The third lower electrode 213 may include polycrystalline silicon.

[0071] The second lower electrode 212 can be formed through an atomic layer deposition process. The atomic layer deposition process used to form the second lower electrode 212 can be referred to in the timing diagram of Figure 8, but is not limited thereto.

[0072] In particular, the second lower electrode 212 according to an embodiment of the present invention can control the silicon content in the film during the deposition process. That is, the second lower electrode 212 can adjust the grain size and hardness of the film according to the silicon content in the film.

[0073] As the silicon content in the film of the second lower electrode 212 increases, the grain size decreases, and the film hardness increases. More specifically, when external stress is applied, dislocations move along the slip plane of the grains, and at grain boundaries where grain orientation changes, dislocation movement becomes difficult. Therefore, the film hardness may increase because there are relatively more grain boundaries as the grain size decreases.

[0074] As a result, as the overall hardness of the lower electrode structure 210 increases, bending of the lower electrode structure 210 during the leaching process can be prevented.

[0075] As shown in Figure 3, the semiconductor device includes a substrate 101, an interlayer insulating layer 102 formed on the substrate 101, and storage node contact structures 103 and 104 connected to the substrate 101 through the interlayer insulating layer 102. The semiconductor device also includes a capacitor structure formed on the interlayer insulating layer 102. The capacitor structure is connected to the storage node contact structures 103 and 104 and includes a lower electrode 310 with a columnar structure, a dielectric layer 120 covering the entire structure including the lower electrode 310, and an upper electrode structure 130 formed on the dielectric layer 120.

[0076] The lower electrode 310 may include a metal silicon nitride. For example, the lower electrode 310 may include a titanium silicon nitride.

[0077] The lower electrode 310 can be formed through an atomic layer deposition process. According to an embodiment of the invention, the lower electrode 310 may comprise titanium silicon nitride, and therefore, an atomic layer deposition process for forming the lower electrode 310 can be performed as a process for forming titanium silicon nitride. The atomic layer deposition process for forming the lower electrode 310 can be referred to in the timing diagram of FIG8.

[0078] Referring to Figure 8, a unit cycle for forming titanium silicon nitride can be performed in the following order: supplying Ti precursor and Si source, supplying Si source, supplying purge gas, supplying reactant gas, and supplying purge gas again. That is, in a unit cycle for forming titanium silicon nitride according to an embodiment of the present invention, the steps of supplying purge gas and reactant gas can be performed sequentially after performing two steps of supplying Si source.

[0079] The step of supplying the Ti precursor and Si source can refer to the step of forming a precursor layer, a silicon layer, and a metallic silicon layer by supplying a metal-containing precursor and Si source gas to the target deposition layer (in this embodiment, referring to the mold structure M10 including the opening 16 shown in FIG. 7B) in a reaction space. For example, the Ti precursor may include TiCl4, but is not limited thereto. The Ti precursor may include any metallic precursor including titanium. The Si source gas may include, for example, SiH4, but is not limited thereto. The Si source may include any source gas including silicon.

[0080] The step of supplying the Si source can refer to the step of forming titanium silicon nitride by supplying Si source gas to a mold structure including an opening. The Si source gas may include, for example, SiH4, but is not limited to, it. The Si source may include any source gas containing silicon. In one embodiment of the invention, the silicon content in the film can be controlled by the step of supplying the Si source. That is, by controlling the silicon content in the film, the grain size and hardness of the film can be adjusted.

[0081] The step of supplying purge gas can refer to the process of supplying purge gas to a mold structure including openings to remove unwanted byproducts from the reaction space. Purge gas may include, for example, nitrogen (N₂).

[0082] The step of supplying the reactant gas can refer to the step of forming titanium silicon nitride by supplying the reactant gas to a mold structure including an opening. The reactant gas may include, for example, NH3, but is not limited to, and may include any reactant gas that includes nitrides.

[0083] As the silicon content in the film of the lower electrode 310 increases, the grain size decreases, and the film hardness increases. In other words, when external stress is applied, dislocations move along the slip plane of the grains, and at grain boundaries where grain orientation changes, dislocation movement becomes difficult. Therefore, the film hardness increases because there are relatively more grain boundaries as the grain size decreases.

[0084] As a result, as the hardness of the lower electrode structure 310 increases, bending of the lower electrode structure 310 during the leaching process can be prevented.

[0085] As shown in Figure 4, the semiconductor device includes a substrate 101, an interlayer insulating layer 102 formed on the substrate 101, and storage node contact structures 103 and 104 connected to the substrate 101 through the interlayer insulating layer 102. The semiconductor device also includes a capacitor structure formed on the interlayer insulating layer 102. The capacitor structure includes a lower electrode structure 110 connected to the storage node contact structures 103 and 104, a dielectric layer 120 covering the entire structure including the lower electrode structure 110, and an upper electrode structure 130 formed on the dielectric layer 120. Support layers 141 and 142, having two ends in contact with the sidewalls of each lower electrode structure 110, can be disposed between adjacent lower electrode structures 110. The lower electrode structure 110 can be supported by the support layers 141 and 142.

[0086] The outer wall of the lower electrode structure 110 can be supported by a first support 141 and a second support 142. The first support 141 and the second support 142 can be referred to as a multilayer support. In another embodiment, the multilayer support can be at least three or more layers. The first support 141 and the second support 142 can include silicon nitride (Si3N4) or silicon nitride (SiCN).

[0087] The lower electrode structure 110 shown in Figure 4 has the same configuration as the lower electrode structure 110 shown in Figure 1.

[0088] As shown in Figure 5, the semiconductor device includes a substrate 101, an interlayer insulating layer 102 formed on the substrate 101, and storage node contact structures 103 and 104 connected to the substrate 101 through the interlayer insulating layer 102. The semiconductor device also includes a capacitor structure formed on the interlayer insulating layer 102. The capacitor structure includes a lower electrode structure 210 connected to the storage node contact structures 103 and 104, a dielectric layer 120 covering the entire structure including the lower electrode structure 210, and an upper electrode structure 130 formed on the dielectric layer 120. Support layers 141 and 142, having two ends in contact with the sidewalls of each lower electrode structure 210, can be disposed between adjacent lower electrode structures 210. The lower electrode structure 210 can be supported by the support layers 141 and 142.

[0089] The outer wall of the lower electrode structure 210 can be supported by a first support 141 and a second support 142. The first support 141 and the second support 142 can be referred to as a multilayer support. In another embodiment, the multilayer support can have at least three or more layers. The first support 141 and the second support 142 can include silicon nitride (Si3N4) or silicon carbide (SiCN).

[0090] The lower electrode structure 210 shown in Figure 5 has the same configuration as the lower electrode structure 210 shown in Figure 2.

[0091] As shown in Figure 6, the semiconductor device includes a substrate 101, an interlayer insulating layer 102 formed on the substrate 101, and storage node contact structures 103 and 104 connected to the substrate 101 through the interlayer insulating layer 102. The semiconductor device also includes a capacitor structure formed on the interlayer insulating layer 102. The capacitor structure is connected to the storage node contact structures 103 and 104 and includes a lower electrode 310 with a columnar structure, a dielectric layer 120 covering the entire structure including the lower electrode 310, and an upper electrode structure 130 formed on the dielectric layer 120. Support layers 141 and 142, having two ends in contact with the sidewalls of each lower electrode 310, can be disposed between adjacent lower electrodes 310. The lower electrodes 310 can be supported by the support layers 141 and 142.

[0092] The outer wall of the lower electrode 310 can be supported by a first support 141 and a second support 142. The first support 141 and the second support 142 can be referred to as a multilayer support. In another embodiment, the multilayer support can have at least three or more layers. The first support 141 and the second support 142 can include silicon nitride (Si3N4) or silicon carbide (SiCN).

[0093] The lower electrode 310 shown in Figure 6 can have the same configuration as the lower electrode 310 shown in Figure 3.

[0094] Figures 7A to 7H are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. A method for manufacturing a semiconductor device including the capacitor structure of Figure 4 will be described with reference to Figures 7A to 7H. The method for manufacturing a semiconductor device according to an embodiment of the present invention can also be applied to a method for manufacturing a semiconductor device including the capacitor structure of Figures 1 to 6.

[0095] As shown in Figure 7A, a lower structure 11L can be formed. The lower structure 11L may include a semiconductor substrate, a semiconductor device, and an interlayer insulating layer. The lower structure 11L may include a region where memory cells are disposed. The lower structure 11L may include a substrate 11 and storage node contact plugs disposed on the substrate 11. The storage node contact plugs may be a stack of a lower plug L1 and an upper plug L2. The storage node contact plugs may be connected to the substrate 11 through the interlayer insulating layer L3.

[0096] A mold structure M10 can be formed on a lower structure 11L. The mold structure M10 may include a first mold layer 12', a first support layer 13', a second mold layer 14', and a second support layer 15' sequentially stacked on the lower structure 11L. The first mold layer 12' and the second mold layer 14' may be, for example, silicon oxide (SiO2). The first mold layer 12' and the second mold layer 14' may be formed by a deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). An etch stop layer may be placed between the lower structure 11L and the mold structure M10. The etch stop layer can be used to protect the lower structure 11L during subsequent manufacturing processes, such as etching the mold structure M10.

[0097] The first and second support layers 13' and 15' may be formed of a material having etch selectivity relative to the first and second mold layers 12' and 14'. The first support layer 13' and the second support layer 15' may comprise silicon nitride or silicon carbide (SiCN). The second support layer 15' may be formed to be thicker than the first support layer 13'. The first support layer 13' and the second support layer 15' may be formed to be thinner than the first mold layer 12' and the second mold layer 14'.

[0098] As shown in Figure 7B, multiple openings 16 can be formed. The openings 16 can be formed by etching the mold structure M10 using a photomask pattern. The openings 16 can be formed by an etching process that involves forming a photomask pattern on the mold structure M10, and then sequentially etching the second support layer 15', the second mold layer 14', the first support layer 13', and the first mold layer 12' using the photomask pattern as an etching barrier layer. The etching process used to form the openings 16 can include dry etching, wet etching, or a combination thereof. The openings 16 can be referred to as lower electrode (or storage node) holes.

[0099] The mold structure M10, which is etched to form the opening 16, includes a stacked structure of a first mold pattern 12, a first support 13, a second mold pattern 14, and a second support 15.

[0100] Opening 16 may have a high aspect ratio. Opening 16 may have an aspect ratio of at least 1:1 or greater. For example, opening 16 may have an aspect ratio of 1:10 or greater. Aspect ratio refers to the ratio of width to height.

[0101] As shown in Figure 7C, a lower electrode structure BE with gap-filling opening 16 can be formed.

[0102] The lower electrode structure BE can be formed through a series of processes, including, for example, forming a first lower electrode inside the opening 16 by conformally depositing a first conductive material in the opening 16. Then, a gap-filling process can be performed to fill the gaps in the opening 16 with a second conductive material to form a second lower electrode 18 in the opening 16. Then, the first and second conductive materials are planarized with the upper surface of the second support 15 as the first and second conductive materials in the opening 16, leaving the first and second conductive materials as the first and second lower electrodes 17 and 18. Adjacent lower electrode structures BE can be spaced apart from each other by a mold structure M10. For example, the planarization process can be performed by an etch-back process or a chemical mechanical polishing (CMP) process. In another embodiment, in the planarization process, the CMP process can be performed after the etch-back process, or the etch-back process can be performed after the CMP process.

[0103] The upper surface of the lower electrode structure BE can be at the same level as the upper surface of the second support 15 (i.e. the upper surface of the mold structure M10).

[0104] The first lower electrode 17 may have a cylindrical structure. The first lower electrode 17 may comprise the same material as the first lower electrode shown in Figures 1 and 2. The second lower electrode 18 is disposed inside the first lower electrode 17 and may comprise a columnar structure. The second lower electrode 18 may comprise the second lower electrode shown in Figure 1 or a stacked structure of the second and third lower electrodes shown in Figure 2. In another embodiment, the lower electrode structure BE may comprise a lower electrode comprising the columnar structure shown in Figure 3 or Figure 6.

[0105] As shown in Figure 7D, the second support 15 can be patterned. In the process of patterning the second support 15, a support photomask pattern SM can be formed on the second support 15, and then the portion of the second support layer 15 exposed by the support photomask pattern SM can be etched. As the second support 15 is patterned, a first support opening S1 can be formed.

[0106] The patterned second support 15 can contact the upper sidewall of the lower electrode structure BE. Some surfaces of the second mold pattern 14 can be exposed by the opening S1 of the first support. The second support 15 can have a shape that surrounds a portion of the outer wall of the lower electrode BE. As described above, the second support 15 can prevent the lower electrode BE, which has a large aspect ratio, from falling over during the subsequent removal of the second mold layer 14.

[0107] As shown in Figure 7E, the second mold pattern 14 can be removed. For example, the second mold pattern 14 can be removed by a wet leaching process. A wet chemical for removing the second mold pattern 14 can be supplied through the first support opening S1. For example, the wet chemical may include one or a combination of two or more of the following wet chemicals: HF, NH4F / NH4OH, H2O2, HCl, HNO3, and H2SO4.

[0108] For example, when the second mold pattern 14 is formed of silicon oxide, it can be removed by a wet leaching process using chemicals containing hydrofluoric acid. When the second mold pattern 14 is removed, the second support 15, which has etching selectivity relative to the second mold pattern 14, can be retained without being removed. Therefore, since the adjacent lower electrode structure BE is supported by the second support 15, the collapse of the lower electrode structure BE can be prevented.

[0109] As shown in Figure 7E, the first support 13 can be patterned. The first support 13 can be partially etched using a support photomask layer SM. As the first support 13 is patterned, a second support opening S2 can be formed.

[0110] The first mold pattern 12 can be removed. For example, the first mold pattern 12 can be removed by a wet leaching process. Wet chemicals for removing the first mold pattern 12 can be supplied through the second support opening S2. For example, the wet chemicals may include one or a combination of two or more of the wet chemicals composed of HF, NH4F / NH4OH, H2O2, HCl, HNO3 and H2SO4.

[0111] For example, when the first mold pattern 12 is formed of silicon oxide, the first mold pattern 12 can be removed by a wet leaching process. When the first mold pattern 12 is removed, the lower electrode structure BE can be prevented from collapsing because it is supported by the second support 15 and the first support 13, which have etching selectivity relative to the first mold pattern 12.

[0112] With the removal of the second mold pattern 14 and the first mold pattern 12, the outer wall of the lower electrode structure BE can be exposed, except for the portions in contact with the first and second supports 13 and 15. The upper part of the lower electrode structure BE can be supported by the second support 15. The middle part of the lower electrode structure BE can be supported by the first support 13.

[0113] Subsequently, the support photomask pattern SM can be removed.

[0114] As shown in Figure 7G, a dielectric layer 19 can be formed. The dielectric layer 19 can be formed on the lower electrode structure BE and on the first and second supports 13 and 15. A portion of the dielectric layer 19 can cover the lower structure 11L. The dielectric layer 19 can include the same material as the dielectric layers shown in Figures 1 through 6.

[0115] As shown in Figure 7H, the upper electrode structure TE can be formed on the dielectric layer 19. The upper electrode structure TE can include the same material as the upper electrode structure 130 shown in Figures 1 to 6, and can be formed through the same process.

[0116] The present invention is not limited to the above embodiments and figures, and it will be apparent to those skilled in the art that various substitutions, modifications and changes can be made to it without departing from the spirit and scope of the present invention.

[0117] 11:Substrate 11L: Lower structure 12: First mold pattern 12': First mold layer 13: First support 13': First support layer 14: Second mold pattern 14': Second mold layer 15: Second support 15': Second support layer 16: Opening 17: First lower electrode 18: Second lower electrode 19: Dielectric layer 101:Substrate 102: Interlayer insulation layer 103: Storage Node Contact Structure 104: Storage Node Contact Structure 110: Lower electrode structure 111: First lower electrode 112: Second lower electrode 120: Dielectric layer 130: Upper electrode structure 131: First upper electrode 132: Second upper electrode 133: Third upper electrode 141: First support 142: Second support 210: Lower electrode structure 211: First lower electrode 212: Second lower electrode 213: Third lower electrode 310: Lower electrode BE: Lower electrode structure L1: Lower plug L2: Upper plug L3: Interlayer insulation layer M10: Mold Structure S1: Opening of the first support S2: Opening of the second support SM: Supporting light mask pattern TE: Upper electrode structure

Claims

1. A semiconductor device, comprising: A lower electrode structure is formed above the substrate; a dielectric layer is formed above the lower electrode structure. The upper electrode structure is formed on the dielectric layer and includes a silicon-containing amorphous layer in contact with the dielectric layer, wherein the upper electrode structure includes a stacked structure of an amorphous metal silicon nitride layer and a crystalline metal nitride layer.

2. The semiconductor device as claimed in claim 1, wherein, The upper electrode structure is continuous and covers the entire surface of the dielectric layer.

3. The semiconductor device as claimed in claim 1, wherein, The silicon-containing amorphous layer includes amorphous titanium silicon nitride.

4. The semiconductor device as claimed in claim 1, wherein, The crystalline metal nitride layer includes titanium nitride.

5. The semiconductor device as claimed in claim 1, wherein, The thickness of the amorphous metal silicon nitride layer is less than the thickness of the crystalline metal nitride layer.

6. The semiconductor device as claimed in claim 1, wherein, The upper electrode structure comprises a stacked structure of an amorphous metal silicon nitride layer, a crystalline metal nitride layer, and a semiconductor material layer.

7. The semiconductor device as claimed in claim 1, wherein, The upper electrode structure comprises a stacked structure of an amorphous metal silicon nitride layer, a crystalline metal nitride layer, a silicon-germanium layer, and a tungsten layer.

8. The semiconductor device as claimed in claim 1, wherein, The lower electrode structure includes: a first lower electrode having a cylindrical structure; and a second lower electrode disposed inside the first lower electrode, the second lower electrode having a smaller grain size than the first lower electrode and having a columnar structure.

9. The semiconductor device as claimed in claim 8, wherein, The hardness of the second lower electrode is greater than that of the first lower electrode.

10. The semiconductor device as claimed in claim 8, wherein, The first lower electrode comprises a metal nitride, and the second lower electrode comprises a metal silicon nitride.

11. The semiconductor device as claimed in claim 8, wherein, The first lower electrode comprises titanium nitride or a low resistivity metal nitride.

12. The semiconductor device as claimed in claim 8, wherein, The second lower electrode comprises titanium silicon nitride.

13. The semiconductor device as claimed in claim 1, wherein, The lower electrode structure includes: a first lower electrode having a cylindrical structure; a second lower electrode formed along the inner surface of the first lower electrode, the second lower electrode having a smaller grain size than the first lower electrode and having a cylindrical structure; and a third lower electrode disposed inside the second lower electrode and having a columnar structure.

14. The semiconductor device of claim 13, wherein the first lower electrode comprises a metal nitride, the second lower electrode comprises a metal silicon nitride, and the third lower electrode comprises polycrystalline silicon.

15. The semiconductor device as claimed in claim 1, wherein, The lower electrode structure includes a columnar structure and a conductive material layer having a smaller grain size than titanium nitride.

16. The semiconductor device as claimed in claim 1, wherein, The lower electrode structure is formed of titanium silicon nitride and has a columnar structure.

17. The semiconductor device of claim 1, further comprising a support for the outer wall of the lower electrode structure.

18. A semiconductor device, comprising: The lower electrode structure includes a stacked structure formed by a first lower electrode and a second lower electrode, the first lower electrode being formed above a substrate and having a cylindrical structure, the second lower electrode being disposed inside the first lower electrode, wherein the first lower electrode is a crystal with a first grain size and the second lower electrode is a crystal with a second grain size, the second grain size being smaller than the first grain size; a dielectric layer is formed above the lower electrode structure; and an upper electrode structure is formed above the dielectric layer.

19. The semiconductor device as claimed in claim 18, wherein, The second lower electrode has a columnar structure.

20. The semiconductor device as claimed in claim 18, wherein, The first lower electrode comprises a metal nitride, and the second lower electrode comprises a metal silicon nitride.

21. The semiconductor device as claimed in claim 18, wherein, The first lower electrode comprises titanium nitride or a low-resistivity metal nitride.

22. The semiconductor device as claimed in claim 18, wherein, The second lower electrode comprises titanium silicon nitride.

23. The semiconductor device of claim 18, wherein the second lower electrode comprises a stacked structure formed of a metal silicon nitride layer and a polycrystalline silicon layer, the metal silicon nitride layer being formed along the inner surface of the first lower electrode and having a cylindrical structure, and the polycrystalline silicon layer being disposed inside the metal silicon nitride layer and having a columnar structure.

24. The semiconductor device as claimed in claim 18, wherein, The dielectric layer is in direct contact with the first lower electrode.

25. The semiconductor device of claim 18 further includes a support for the outer wall of the lower electrode structure.

26. The semiconductor device as claimed in claim 18, wherein, The upper electrode structure includes a silicon-containing amorphous layer that is in direct contact with the dielectric layer.

27. The semiconductor device as claimed in claim 18, wherein, The upper electrode structure comprises a stacked structure of amorphous metal silicon nitride layers and crystalline metal nitride layers.

28. The semiconductor device as claimed in claim 18, wherein, The upper electrode structure is continuous and covers the entire surface of the dielectric layer.

29. The semiconductor device as claimed in claim 26, wherein, The silicon-containing amorphous layer includes amorphous titanium silicon nitride.

30. The semiconductor device as claimed in claim 27, wherein, The crystalline metal nitride layer includes titanium nitride.

31. The semiconductor device as claimed in claim 27, wherein, The thickness of the amorphous metal silicon nitride layer is less than the thickness of the crystalline metal nitride layer.

32. The semiconductor device as claimed in claim 18, wherein, The upper electrode structure comprises a stacked structure of an amorphous metal silicon nitride layer, a crystalline metal nitride layer, and a semiconductor material layer.

33. The semiconductor device as claimed in claim 18, wherein, The upper electrode structure comprises a stacked structure of an amorphous metal silicon nitride layer, a crystalline metal nitride layer, a silicon-germanium layer, and a tungsten layer.

34. A method of manufacturing a semiconductor device, the method comprising: A lower electrode structure is formed above the substrate; A dielectric layer is formed above the lower electrode structure; The upper electrode structure, including a silicon-containing amorphous layer, is formed above the dielectric layer, wherein forming the upper electrode structure includes: forming an amorphous metal silicon nitride layer above the dielectric layer; and forming a metal nitride layer on the amorphous metal silicon nitride layer.

35. The method as described in request item 34, wherein, The formation of the amorphous metal silicon nitride layer and the formation of the metal nitride layer are performed in situ.

36. The method as described in request item 34, wherein, The formation of the amorphous metal silicon nitride layer and the formation of the metal nitride layer are performed through an atomic layer deposition process.

37. The method as described in request item 34, wherein, The amorphous metal silicon nitride layer includes amorphous titanium silicon nitride, and the metal nitride layer includes titanium nitride.

38. The method as described in request item 36, wherein, The atomic layer deposition process for forming the amorphous metallic silicon nitride layer is performed by repeating a unit cycle, which includes the steps of supplying Ti precursor, supplying purge gas, supplying reactant gas, supplying purge gas, and supplying Si source and purge gas.

39. The method as described in claim 36, wherein, The atomic layer deposition process for forming the metal nitride layer is performed by repeating a unit cycle, which includes a step of supplying a Ti precursor, a step of supplying a purge gas, and a step of supplying a reactant gas and a purge gas.

40. The method as described in request item 34, wherein, Forming the lower electrode structure includes: forming a mold structure above the substrate; forming an opening by etching the mold structure; forming a first lower electrode along the inner surface of the opening, the first lower electrode having a cylindrical structure; forming a second lower electrode with a gap filling the interior of the first lower electrode, the second lower electrode having a smaller grain size than the first lower electrode and having a columnar structure; and exposing the outer wall of the lower electrode structure by removing the mold structure.

41. The method as described in request item 39, wherein, The first lower electrode comprises a metal nitride, and the second lower electrode comprises a metal silicon nitride.

42. The method as described in request item 34, wherein, Forming the lower electrode includes: forming a mold structure above the substrate; forming an opening by etching the mold structure; forming a first lower electrode along the inner surface of the opening, the first lower electrode having a cylindrical structure; forming a second lower electrode along the inner surface of the first lower electrode, the second lower electrode having a smaller grain size than the first lower electrode and having a cylindrical structure; and forming a third lower electrode with a columnar structure that fills the interior of the second lower electrode with gaps.

43. The method of claim 42, wherein the first lower electrode comprises a metal nitride, the second lower electrode comprises a metal silicon nitride, and the third lower electrode comprises polycrystalline silicon.

44. The method as described in request item 34, wherein, Forming the lower electrode includes: forming a mold structure above the substrate; forming an opening by etching the mold structure; forming a lower electrode with a columnar structure that fills the interior of the opening; and exposing the outer wall of the lower electrode structure by removing the mold structure.

45. The method as described in request item 44, wherein, The lower electrode, which has a columnar structure, comprises titanium silicon nitride.

46. ​​The method as described in claim 45, wherein, The titanium silicon nitride is formed through an atomic layer deposition process.

47. The method as described in request item 46, wherein, The atomic layer deposition process is performed by repeating a unit cycle, which includes the steps of supplying Ti precursor and Si source, supplying Si source, supplying purge gas, and supplying reactant gas and purge gas.

48. A method of manufacturing a semiconductor device, the method comprising: A lower electrode structure is formed, the lower electrode structure comprising a stacked structure formed by a first lower electrode and a second lower electrode, the first lower electrode having a cylindrical structure and being formed above a substrate, the second lower electrode being disposed inside the first lower electrode and having a smaller grain size than the first lower electrode; a dielectric layer is formed above the lower electrode structure; and an upper electrode structure is formed above the dielectric layer.

49. The method as described in request item 48, wherein, Forming the lower electrode structure includes: forming a first lower electrode above the substrate, the first lower electrode having a cylindrical structure; and forming a second lower electrode disposed inside the first lower electrode and having a columnar structure.

50. The method as described in request item 48, wherein, Forming the lower electrode structure includes: forming a first lower electrode above the substrate, the first lower electrode having a cylindrical structure; forming a second lower electrode along the inner surface of the first lower electrode, the second lower electrode having a cylindrical structure; and forming a third lower electrode with a columnar structure that fills the interior of the second lower electrode with a gap.

51. The method as described in request item 48, wherein, Forming the upper electrode structure includes: forming an amorphous metal silicon nitride layer above the dielectric layer; and forming a metal nitride layer on the amorphous metal silicon nitride layer.

52. The method as described in request item 51, wherein, The amorphous metal silicon nitride layer and the metal nitride layer are formed in situ in the same chamber through an atomic layer deposition process.

53. The method as described in request item 52, wherein, The atomic layer deposition process for forming the amorphous metal silicon nitride layer is performed by repeating a unit cycle, the unit cycle including the steps of supplying a Ti precursor, supplying a purge gas, supplying a reactant gas, supplying a purge gas, and supplying a Si source and a purge gas; and wherein the atomic layer deposition process for forming the metal nitride layer is performed by repeating a unit cycle, the unit cycle including the steps of supplying a Ti precursor, supplying a purge gas, and supplying a reactant gas and a purge gas.

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