Low-power high-speed CMOS clock generation circuit

Abstract

The low-power clock generation circuit includes: a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs a phase-adjusted clock signal; a frequency multiplier circuit that receives a plurality of phase-adjusted clock signals and outputs two frequency-multiplied clock signals with a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-multiplied clock signals and provides four output signals, the four output signals including in-phase and quadrature versions of the two frequency-multiplied clock signals.

Description

[Technical Field]

[0001] This patent application claims priority to pending U.S. Application No. 17 / 481,666, filed on September 22, 2021, entitled “Low-Power High-Speed ​​CMOS Clock Generation Circuit,” which has been assigned to its assignee and is expressly incorporated herein by reference as if fully set forth below and used for all applicable purposes.

[0002] This case relates generally to clock and data recovery circuitry, and more specifically to circuitry for generating multiple clock signals of different phases. [Previous Technology]

[0003] Electronic device technology has experienced explosive growth in recent years. For example, better communication, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding array of features and services, providing users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (such as mobile phones, tablets, laptops, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components.

[0004] For example, when integrated circuit (IC) devices require reduced power consumption and a smaller footprint, high-speed serial buses offer advantages over parallel communication links. In a serial interface, a serializer is used to convert data from parallel words into a serial bit stream, and a deserializer is used to convert the data back to parallel words at the receiver. For example, a high-speed bus interface can be implemented using peripheral component connection fast (PCIe) buses, universal serial buses (USB), or serial advanced technology accessories (SATA), etc.

[0005] IC devices may include serializers / deserializers (SERDES) for sending and receiving via serial communication links. In high-speed applications, the operating timing of SERDES can be controlled by multiple clock signals. Using multiple clock signals with increasing frequencies leads to increased power consumption. Furthermore, SERDES typically receive clock signals with the same frequency but different phases. The performance, accuracy, or reliability of SERDES may depend on the phase relationship of the clock signals, and drift or other changes in the phase relationship of the clock signals can cause errors in the received data. Therefore, there is a continuous need for new technologies that can provide reliable low-power clock generation and management circuitry for high-speed serial links. [Summary of the Invention]

[0006] Certain aspects of this application relate to systems, apparatuses, methods, and techniques for implementing and managing phase relationships in high-frequency deserializers. A low-power, high-speed clock generation circuit is disclosed, which can generate multiple sampled clocks of different phases from a single-ended input circuit. Power consumption can be reduced by implementing most of the clock generation circuitry in a complementary metal-oxide-semiconductor (CMOS) circuit and by limiting the number of high-speed signals in the clock generation circuitry.

[0007] In various embodiments of this invention, the clock generation circuit includes: a phase generator that receives an input clock signal and uses the input clock signal to generate a plurality of intermediate clock signals with different phase shifts; a phase rotator circuit that outputs a phase-adjusted clock signal; a frequency multiplier circuit that receives a plurality of phase-adjusted clock signals and outputs two frequency-multiplied clock signals with a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-multiplied clock signals and provides four output signals, the four output signals including in-phase and quadrature versions of the two frequency-multiplied clock signals.

[0008] In various embodiments of this invention, an apparatus includes: a unit for generating a plurality of intermediate clock signals having different phase shifts from an input clock signal; a unit for configuring a phase rotator circuit to generate phase-adjusted clock signals, each phase-adjusted clock signal having a phase within a range bounded by the phases of two of the intermediate clock signals; a unit for generating two frequency-multiplied clock signals, including a frequency multiplier circuit configured to generate two frequency-multiplied clock signals having a 180° phase difference with the plurality of phase-adjusted clock signals; and a unit for configuring a quadrature clock generation circuit to provide four output signals based on the two frequency-multiplied clock signals, the four output signals including in-phase and quadrature versions of the two frequency-multiplied clock signals.

[0009] In various aspects of this case, a method for providing multiple in-phase and quadrature signals includes: using a phase generator to generate multiple intermediate clock signals having different phase shifts from input clock signals; configuring a phase rotator circuit to generate phase-adjusted clock signals, each phase-adjusted clock signal having a phase within a range bounded by the phases of the two intermediate clock signals; using a frequency multiplier circuit to generate two multiplied clock signals having a 180° phase difference with the plurality of phase-adjusted clock signals; and configuring a quadrature clock generation circuit to provide four output signals based on the two multiplied clock signals, the four output signals including in-phase and quadrature versions of the two multiplied clock signals.

[0010] In some configurations, the phase generator includes a delay-locked loop (LLL) in which an input clock signal is coupled to a plurality of delay elements. The plurality of delay elements includes eight delay elements, and the LLL provides nine intermediate clock signals with different phase shifts to the phase rotator circuit.

[0011] In one example, the phase rotator circuit includes: a first plurality of gates coupled between a first terminal of a corresponding switch in a first plurality of switches and a first intermediate clock signal, and a second plurality of gates coupled between a first terminal of a corresponding switch in a second plurality of switches and a second intermediate clock signal. Each of the first plurality of switches and the second plurality of switches has a second terminal coupled to a first phase adjustment clock signal. The phase of the first phase adjustment clock signal can be determined by the number of closed switches in the first plurality of switches and the number of closed switches in the second plurality of switches.

[0012] In one example, the frequency multiplier circuit includes an XOR gate configured to receive a first phase-adjusted clock signal and a second phase-adjusted clock signal as its inputs, and an XOR gate configured to receive the first phase-adjusted clock signal and the second phase-adjusted clock signal as its inputs. The first phase-adjusted clock signal and the second phase-adjusted clock signal may have a 90° phase difference.

[0013] In some instances, the four output signals are used by a deserializer circuit configured to sample serialized data from the serial bus. An input clock signal is received from the serial bus.

[0014] In one example, the multiplexer is configured to receive a phase-adjusted clock signal from a phase rotator circuit, select two of the phase-adjusted clock signals, and couple the two selected phase-adjusted clock signals to a frequency multiplier circuit.

Implementation Method

[0025] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art to which this invention pertains that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form in order to avoid confusion with these concepts.

[0026] Several exemplary embodiments of this invention are now described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "as an example, illustration, or description." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or superior to other embodiments.

[0027] The terms "computing device" and "mobile device" are used interchangeably herein to refer to any or all of the following: servers, personal computers, smartphones, cellular phones, tablets, laptops, netbooks, ultrabooks, handheld computers, personal assistants (PDAs), wireless email receivers, cellular phones with multimedia internet access, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices including programmable processors. While these forms are particularly useful in mobile devices (e.g., smartphones, laptops, etc.) with limited resources (e.g., processing power, battery, size, etc.), they are generally useful in any computing device that may benefit from improved processor performance and reduced power consumption.

[0028] As used herein, the term "multi-core processor" refers to a single integrated circuit (IC) chip or chip package containing two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute program instructions. The term "multi-processor" is used herein to represent a system or device comprising two or more processing units configured to read and execute program instructions.

[0029] The term "System-on-a-Chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip containing multiple resources and / or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose and / or special-purpose processors (digital signal processors (DSPs), modem processors, video processors, etc.), memory blocks (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, regulators, oscillators, etc.), any one or all of which may be contained in one or more cores.

[0030] The memory technologies described herein can be adapted to store instructions, programs, control signals, and / or data for use in or by a computer or other digital electronic device. Any references to terms and / or technical details relating to a single type of memory, interface, standard, or memory technology are for illustrative purposes only and are not intended to limit the scope of the claim to a particular memory system or technology, unless specifically stated in the language of the claim. Mobile computing device architectures are becoming increasingly complex and now typically include multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, complex electrical interconnects (e.g., buses and / or structures), and many other resources for executing complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0031] Process technologies for manufacturing semiconductor devices, including IC devices, are constantly being improved. Process technologies include manufacturing methods for IC devices and define transistor dimensions, operating voltages, and switching speeds. Features that are components of circuits in an IC device can be referred to as technology nodes and / or process nodes. The terms technology node, process node, and process technology can be used to characterize specific semiconductor manufacturing processes and corresponding design rules. Faster and more energy-efficient technology nodes are being developed by using smaller feature sizes to produce smaller transistors (smaller transistors enable the manufacture of higher-density ICs).

[0032] Figure 1 illustrates example components and interconnections in a System-on-Chip (SoC) 100, which can be adapted to implement certain configurations of this invention. The SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may operate independently of the other processors / cores. The processors 102, 104, 106, 108 may be organized very close to each other (e.g., on a single substrate, die, integrated wafer, etc.), allowing the processors to operate at much higher frequencies / clock rates than would be possible if signals were to propagate outside the chip. The proximity of the cores also allows for the sharing of on-chip memory and resources (e.g., voltage rails), as well as more coordinated cooperation between the cores.

[0033] The SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting the processor and software clients running on the computing device. System components and resources 110 may also include circuitry for interacting with peripheral devices, such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0034] The SoC 100 may also include a general-purpose serial bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a centralized resource manager (CRM) 116. The SoC 100 may also include input / output modules (not shown) for communicating with resources outside the SoC, each of which may be shared by two or more internal SoC components.

[0035] Processors 102, 104, 106, and 108 can be interconnected to USB controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components via interconnect / bus module 122. Interconnect / bus module 122 may include a reconfigurable logic gate array and / or implement a bus architecture. Communication may also be provided by advanced interconnects, such as high-performance on-chip networks (NoC).

[0036] The interconnect / bus module 122 may include or provide a bus master system configured to grant exclusive control of the bus (e.g., data transmission in high-load mode, block transfer mode, etc.) to SoC components (e.g., processors, peripherals, etc.) based on set duration, computational load, number of bytes, etc. In some cases, the interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from simultaneously attempting to drive the bus. The memory controller 114 may be a dedicated hardware module configured to manage data streams entering and exiting memory 124 via memory interface / bus 126.

[0037] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gate logic, individual hardware circuitry, and other suitable hardware configured to perform the various functions described herein. In some cases, the memory 124 may be part of the SoC 100.

[0038] Figure 2 illustrates an example of a data communication system 200 that can be adjusted according to certain aspects of this invention. The data communication system 200 includes a transmitter 202, a data communication channel 210, and a receiver 222. The transmitter 202 can be located in a first device configured to transmit data signals to a second device. The data communication channel 210 provides a transmission medium through which data signals are propagated from the first device to the second device. The receiver 222 can be located in the second device and can be configured to receive and process data signals.

[0039] In one example, transmitter 202 includes serializer 204 configured to convert parallel data into serial data. Transmitter 202 also includes transmit driver 206 configured to generate data signals based on the serial data for transmission to receiver 222 via data communication channel 210.

[0040] The data communication channel 210 can be implemented using any type of transmission medium, through which data signals can be transmitted from the transmitter 202 to the receiver 222. Examples of the data communication channel 210 include one or more metallized traces (which may include one or more through-holes) on a printed circuit board (PCB), striplines, microstrip lines, coaxial cables, twisted pairs, etc.

[0041] Receiver 222 includes: a variable gain amplifier (VGA) with a continuous isochronous linear equalizer (CTLE) (VGA / CTLE 224), which can be implemented in a single stage or multiple stages; a clock data recovery circuit (CDR 226); and a deserializer 228. CTLE can represent a technique used to amplify the higher frequency components of the signal at the receiver so that all frequency components of the signal have similar amplitudes, improve signal interference, and enhance eye diagram performance. As disclosed herein, VGA / CTLE 224 is configured to perform equalization and amplification of the received data signal. CDR 226 is configured to recover the clock associated with the data signal and use the clock to sample serial data from the data signal or otherwise recover the serial data. Deserializer 228 is configured to convert the serial data back to parallel data.

[0042] Data or clock signals may become distorted as they reach receiver 222. Distortion can occur due to various reasons, including impedance mismatch, interference, and reflected energy in the data communication channel 210. Signal distortion may make it difficult for CDR 226 to recover clock and data, and may limit the stability of the window during which data can be sampled. In some instances, distortion caused by high-frequency attenuation can be addressed by VGA / CTLE 224, which can be configured to perform equalization and amplification of the high-frequency components of the data signal to increase the data rate at which the data signal can be transmitted via data communication channel 210 and reliably recovered at receiver 222. In some instances, a high-speed amplifier can be used to perform amplification, implemented using a current-mode logic (CML) structure. The CML structure can also be referred to as a source-coupled logic (SCL) structure.

[0043] The CDR 226 can be configured to generate multiple signals from a recovered clock signal, wherein the multiple signals may include phase-shifted versions of the recovered clock signal. In many implementations, the CDR 226 may use a phase interpolator to generate the phase-shifted versions of the recovered clock signal. Phase interpolators are widely used in high-speed timing circuits, including in systems incorporating SERDES circuitry. Limiting power consumption is a major challenge in SERDES-based designs. In mobile communication devices, reduced power consumption supports increased battery life between charges. SERDES using higher-frequency clock signals with multiple phase shifts are associated with significant power consumption, including the power consumption of the phase interpolator.

[0044] Certain embodiments of this invention provide a phase interpolator that receives an input clock signal having a first clock rate and can generate multiple outputs at higher clock rates. In some instances, the input to the phase interpolator is provided as a single-ended signal, although some implementations may provide a differential clock signal as the input to the phase interpolator.

[0045] In some embodiments of this invention, power savings can be achieved by configuring most of the circuitry in the phase interpolator to operate at a clock rate of the input signal that is lower than the clock rate of the output signal. In one example, the phase interpolator receives a quarter-rate clock signal and generates four half-rate clock signals at different phases. In this example, half-rate and quarter-rate refer to the frequencies of the clock signals, which are fractions (½ and ¼) of the clock frequency used on the data communication channel 210. Most of the circuitry in the phase interpolator can operate at a quarter-rate frequency. For example, phase generator circuitry such as delay-locked loops (DLLs) and phase rotator circuit mixers can operate at a quarter-rate frequency. Many of the circuitry in the phase interpolator can be implemented using CMOS circuitry. Compared to conventional circuitry that generates four half-rate clock signals in four phases, the phase interpolator configured according to certain embodiments disclosed herein can operate at a very low power consumption level.

[0046] Figure 3 is a block diagram 300 illustrating certain features of the clock generation circuit 304. The clock generation circuit 304 can be used in a high-speed receiver. A clock and data recovery circuit (CDR 302) is configured to receive or extract a clock signal 322 from a serial data link and uses a frequency multiplier circuit 324 to provide a differential clock signal 326 to the clock generation circuit 304. The clock generation circuit 304 includes a polyphase filter 306 that receives the differential clock signal 326 and generates a set of in-phase and quadrature signals 328 {i, q, ib, and qb} from the differential clock signal 326.

[0047] The clock generation circuit 304 includes two phase rotators 308 and 310, configured to selectively adjust the phase shift between the signals in the set of in-phase and quadrature signals 328 generated by the multiphase filter 306. The phase rotators 308 and 310 can be configured to maintain a 90° phase separation between the set of in-phase and quadrature signals 328 under the control of a digital loop including a feedback filter 316. Each phase rotator 308 and 310 generates a differential pair of output signals. The differential pair of the output signal from the first phase rotator 308 is used to generate 0° and 180° phase signals in a set of sampled signals 340. The differential pair of the output signal from the second phase rotator 310 is used to generate 90° and 270° phase signals in a set of sampled signals 340.

[0048] The feedback filter 316 provides phase interpolation encoded characters in the digital feedback signal 334 used to control the phase of the phase rotators 308, 310. In one example, the feedback loop can be configured such that the transitions (edges) in the 0° and 180° phase signals occur at the center of the bit time of the received data signal, and that the transitions in the 90° and 270° phase signals coincide with the edges in the received data signal. The set of sampled signals 340 can be provided to the sampling circuit 320 and the deserializer (not shown), wherein the sampling circuit 320 extracts data from the received data signal and provides the extracted samples to the deserializer for deserialization.

[0049] In the illustrated high-speed receiver circuit 300, the polyphase filter 306 and phase rotators 308, 310 use CML and operate at a frequency corresponding to the frequency of the sampling circuit 320, which is the same as the half-rate clock frequency. The outputs of the phase rotators 308, 310 are provided to the CML-to-CMOS converters 312, 314, which convert the CML clock signal from the phase rotators 308, 310 into a CMOS sampling signal 340. The operation of the polyphase filter 306 and the phase rotators 308, 310 at the half-rate clock frequency results in high power consumption.

[0050] Certain aspects of this invention relate to an architecture for a clock generation circuit that can reduce power consumption by using fewer clock signals and lower clock frequencies in most parts of the clock generation circuit. In one example, the clock generation circuit can be used for a half-data rate CDR compatible with known SERDES designs. In one aspect, the currently disclosed clock generation circuit can operate with very low power consumption and can generate the same 4-phase half-data rate sampling signal 340 provided by the high-speed receiver circuit 300 shown in FIG3.

[0051] Figure 4 is a block diagram illustrating an example of the architecture of a clock generation circuit 400 provided according to certain embodiments of the present invention. The clock generation circuit 400 includes a phase generator 402, a phase rotator 404, a multiplexer (Mux 406), a frequency multiplier circuit 408, and a quadrature clock generation circuit 410. In one example, the phase generator 402 includes a delay-locked loop (DLL) circuit. In one example, the quadrature clock generation circuit 410 includes an injection-locked oscillator (ILO). The clock generation circuit 400 receives a single-phase, quarter-rate, single-ended input clock signal 412 and outputs a set of half-rate sampled signals 422. In this example, half-rate and quarter-rate refer to the frequencies of clock signals that are fractions (½ and ¼) of the clock frequency used on the corresponding data communication channel. The clock generation circuit 400 operates primarily at the quarter-rate frequency. For example, the phase generator 402 and the phase rotator 404 may operate at the quarter-rate frequency.

[0052] The clock generation circuit 400 configured according to certain embodiments of this invention can achieve reduced power consumption compared to conventional phase interpolators due to the use of CMOS circuitry, the reduction of the phase rotator path, and the use of a quarter-rate by the phase generator 402 and the phase rotator 404. In the illustrated example, the phase generator 402 generates eight phase signals 414, which can be phase-shifted by 45°. The phase rotator 404 can be configured to select a phase shift of up to 45° for each phase signal 414, thereby allowing desired alignment of the eight phase signals 416. A multiplexer (Mux 406) selects two of the eight phase signals 416 to provide two quarter-rate clock signals 418 to the frequency multiplier circuit 408. The quarter-rate clock signals 418 include in-phase and quadrature clock signals with a 90° phase difference. The frequency multiplier circuit 408 generates a differential half-rate clock signal 420 based on the quarter-rate clock signals 418. The differential half-rate clock signal 420 has a 180° phase difference. The differential half-rate clock signal 420 is provided to a quadrature clock generation circuit 410, which outputs a set of half-rate clock signals 422. This set of half-rate clock signals 422 can be used by a sampling circuit to capture and deserialize data received from a serial data link. The sampling circuit can also be referred to as sampler 430 and deserializer circuit (not shown). The clock signals in this set of half-rate clock signals 422 include in-phase and quadrature signals {hsclockI, hsclockQ, hsclockIb, and hsclockQb}, where the in-phase signal has a 90° phase separation from the corresponding quadrature signal. The quadrature clock generation circuit 410 can use an injection-locked loop circuit (e.g., an injection-locked oscillator) to generate the half-rate in-phase and quadrature signals 422.

[0053] Figure 5 illustrates an example of a clock generation circuit 500 configured according to certain aspects of this invention. The clock generation circuit 500 is configured to receive a single-ended clock signal 522. The clock signal 522 may be a quarter-rate clock signal derived from a clock signal transmitted via a serial data communication channel. In this example, half-rate and quarter-rate refer to the frequencies of the clock signal, which are fractions (½ and ¼) of the clock frequency used on the corresponding data communication channel. The clock signal 522 is provided to a delay-locked loop 502, which is configured to generate a set of phase signals 524, which includes a delayed version of the clock signal 522. In one example described herein, the set of phase signals 524 includes at least nine signals provided at 45° phase intervals.

[0054] The set of phase signals 524 is provided to a phase rotator 504, which is configured to selectively respond to the phase shifts between the signals in the set of phase signals 524 and generate a set of calibration phase signals 526. The phase rotator 504 can be configured to maintain a precise or highly accurate 45° phase separation in the set of calibration phase signals 526. The expected level of precision or accuracy of the phase separation can be determined by the application, data rate, and sampling circuit design. In one instance, the phase separation can be maintained within ±1%. In another instance, the phase separation can be maintained within ±5%. In yet another instance, maintaining the phase separation within ±10% may be sufficient.

[0055] The delay-locked loop 502 and the phase rotator 504 can be controlled or calibrated using a feedback loop including a processor, controller, finite state machine, or other control or calibration circuitry 518. In one example, the control or calibration circuitry 518 may respond to a buffered version of the set of phase signals 524 and provide a delay code 534 in the control signals for configuring the delay elements of the delay-locked loop 502. In one example, the set of phase signals 524 may be buffered using a buffer circuitry 542 configured to limit the load applied to the output of the delay-locked loop 502. In another example, the control or calibration circuitry 518 may provide code 536 for configuring one or more phase rotation elements in the phase rotator 504. In yet another example, the control or calibration circuitry 518 may provide calibration code 538 for configuring the injection-locked oscillator 514. In some cases, the control or calibration circuitry 518 operates during calibration events that may occur during power-on, system initialization, the start of certain transmissions, and / or between transmissions.

[0056] Phase rotator 504 provides a set of calibration phase signals 526 to multiplexer 506, which can be configured to select two quarter-rate clock signals 528 with 90° phase separation. The quarter-rate clock signals 528 are coupled to frequency multiplier 510 via tri-state buffer 508, which includes XOR gate 512a and XNOR gate 512b. XOR gate 512a and XNOR gate 512b receive the buffered quarter-rate clock signals 528 and output a high-speed clock signal 530. The high-speed clock signal 530 includes a pair of half-rate clock signals with 180° phase separation. The high-speed clock signal 530 is coupled to an injection-locked circuit, such as an injection-locked oscillator 514, which generates a set of sampled clock signals 532, including four half-rate clock signals with 90° phase separation. Sampling clock signal 532 is coupled to sampling circuit 520 via tri-state buffer 516, which provides buffered sampling clock signal 540. Injection-locked oscillator 514 can be calibrated or controlled using code 538 provided by control or calibration circuitry 518 to ensure precise or highly accurate 90° phase separation in the set of buffered sampling clock signals 540. The expected or desired level of accuracy or precision of the phase separation can be determined by the application, data rate, and sampling circuit design. In one instance, phase separation may be maintained within ±1%. In another instance, phase separation may be maintained within ±5%. In yet another instance, maintaining phase separation within ±10% may be sufficient.

[0057] The delay-locked loop 502, phase rotator 504, and multiplexer 506 of the clock generation circuit 500 operate at quarter-rate frequencies, resulting in a significant reduction in power consumption compared to the high-speed receiver circuit 300 of FIG3. In some instances, additional power savings are achieved by implementing most of the clock generation circuit 500 (including the delay-locked loop 502, phase rotator 504, multiplexer 506, and frequency multiplier 510) in CMOS. Further power savings are achieved through a limited number of quarter-rate and half-rate signals in the clock generation circuit 500. For example, the use of the single-phase rotator 504 limits the number of quarter-rate and half-rate signals 530 used by the clock generation circuit 500.

[0058] Figure 6 illustrates an example of circuit 600, which shows the operation of a delay-locked loop circuit 602 and a phase rotation circuit 612 configured according to certain configurations of this invention. In some cases, the delay-locked loop circuit 602 corresponds to the delay-locked loop 502 of Figure 5, and the phase rotation circuit 612 corresponds to the phase rotator 504 in the clock generation circuit 500.

[0059] The delay-locked loop circuit 602 can be configured to receive a single-ended clock signal 622 and provide multiple output signals 610 generated by a series of delay elements, including delay element 606. Each delay element 606 can be configurable during a calibration or configuration procedure to provide a desired delay. In some instances, the capacitor 630 of the interconnect between the gates or inverters can be changed to alter the delay provided by the delay element 606. In one instance, the capacitor 630 can be provided by a transistor (not shown) and can be based on a bias voltage provided to the transistor. The capacitor 630 can be configured using a digital-to-analog converter (not shown) that provides a bias voltage based on a register configured by a controller or processor. In some cases, the capacitor 630 can be dynamically configured in operation using a delay code 534 provided by the control or calibration circuit 518.

[0060] The delay-locked loop circuit 602 may include any number of elements. In some cases, the output of the last delay element may be coupled to the input of the first delay element to form a loop. In some instances, a bypass switch 604 may be used to bypass one or more inverters 628 to adjust the total delay of the loop. In the illustrated example, the delay-locked loop circuit 602 uses eight delay elements to provide nine DLL output signals 610, each delay element providing the same nominal delay. In the illustrated example, the total delay provided by the eight delay elements is configured to be nominally equal to the period of the clock signal 622, and therefore the nine DLL output signals 610 are phase-shifted versions of the clock signal 622.

[0061] The DLL output signal 610 provided by the delay-locked loop circuit 602 is coupled to a phase rotation circuit 612, which includes eight phase rotation elements that can adjust the phase of the nine DLL output signals 610 to provide eight phase signals 626 separated by a 45° phase shift. Each phase rotation element can shift the output phase signal to provide a phase shift between the phases of two of the DLL output signals 610. In one example, the first phase rotation element 614 shifts the phase of the PI0 output phase signal 620 to provide a phase shift between the phases of the DLL0 output signal 616 and the DLL1 output signal 618.

[0062] Figure 7 illustrates an example of a phase rotation element 700 configured according to certain aspects of this invention. The phase rotation element 700 may correspond to the phase rotation element 614 of Figure 6 and receives the DLL0 output signal 616 and DLL1 output signal 618 shown in Figure 6 via one or more buffers 720. The DLL0 output signal 616 is provided to the negative shift circuit 706 and the DLL1 output signal 618 is provided to the positive shift circuit 708. The gate 712 in the negative shift circuit 706 is configured to be coupled in parallel when the corresponding switch 716 is closed. In some instances, the switch 716 is controlled by a code received in a multi-bit selection signal 702, which may be provided by a control or calibration circuit 518. The multi-bit selection signals 702, 704 are used to determine the number of switches 716, 718 to be closed. In some instances, switch 718 is controlled by a code received in a multi-bit select signal 704, which may be provided by control or calibration circuitry 518. In one instance, switches 716, 718 may be indexed such that corresponding multi-bit select signals 702, 704 identify the highest-numbered switch to be closed (e.g., switch -N) and all switches 0-N are closed accordingly.

[0063] Gates 714 in the positive shift circuit 708 are configured to be coupled in parallel when the corresponding switches 718 are closed. Switches 716 and 718 can be used to select the phase of the output signal 710. Gates 712 in each of the negative shift circuits 706 coupled via closed switches pull the phase of the output signal 710 toward the phase of the DLL0 output signal 616. Gates 714 in the positive shift circuit 708 coupled via closed switches pull the phase of the output signal 710 toward the phase of the DLL1 output signal 618. Therefore, the phase of the output signal 710 is determined based on the number of closed switches in the negative shift circuit 706 and the positive shift circuit 708. Power savings can be achieved by turning off those gates that do not actively contribute to the output signal 710 and certain associated control circuits. For example, one or more buffers 722 can be used to drive the output signal 710 and ensure a constant output impedance.

[0064] Figure 8 illustrates an example of a quadrature clock generator 800 configured according to certain aspects of this invention. The quadrature clock generator 800 can operate as an injection-locked oscillator, such as the injection-locked oscillator 514 of Figure 5. The quadrature clock generator 800 receives a first input signal 802 and a second input signal 804 with a phase relationship of 180°. For example, the first input signal 802 may have a nominal phase of 0°, while the second input signal 804 may have a phase of 180°. The quadrature clock generator 800 outputs four phase signals with a 90° phase separation. The quadrature clock generator 800 may include one or more delay elements 806, which may be calibrated or configured to maintain the phase separation between the output phase signals. In some instances, the delay element 806 is calibrated using a code 538 generated by control or calibration circuitry 518.

[0065] Figure 9 is a timing diagram 900 illustrating certain states of operation of the clock generation circuit 500 illustrated in Figure 5. Also refer to the delay-locked loop circuit 602 and phase rotation circuit 612 shown in Figure 6. Timing diagram 900 omits certain signals to facilitate the description of the operation of the clock generation circuit 500. For example, two of the nine DLL output signals 610 and two of the eight phase signals 626 are illustrated. Additionally, signal transmission associated with the multiplexer 506 is omitted from timing diagram 900, and the illustrated example addresses the situation when the PI0 output phase signal 620 and the PI2 output phase signal 624 are provided to the frequency multiplier 510 (via the tri-state buffer 508).

[0066] The clock generation circuit 500 receives a single-ended clock signal 522 as input. For the purposes of this description, the single-ended clock signal 522 is shown as having a 50% period and a frequency closely matched to the quarter-rate clock frequency of the receiving device. The clock generation circuit 500 can operate using input signals with different duty cycles.

[0067] A single-ended clock signal 522 is provided to a delay-locked loop 502, which generates a set of phase signals 524. The delay-locked loop circuit 602 generates nine output signals 610 with different phase delays, including a DLL0 output signal 616 and a DLL1 output signal 618. In one example, the DLL0 output signal 616 corresponds directly in phase to the single-ended clock signal 522, while the DLL1 output signal 618 is phase-shifted by 45° relative to the single-ended clock signal 522. The output signals 610 generated by the delay-locked loop circuit 602 are provided to a phase rotation circuit 612. In the illustrated example, the phase rotation circuit 612 is operable or configurable to generate a PI0 output phase signal 620 by adding a phase shift to the DLL0 output signal 616. A phase shift can be added by delaying the edge duration 906 in the single-ended clock signal 522. The duration 906 causes the edge 908 in the PI0 output phase signal 620 to appear between the edges 902 and 904 in the DLL0 output signal 616 and the DLL1 output signal 618, respectively.

[0068] The PI0 output phase signal 620 and its quadrature PI2 output phase signal 624 are provided to the frequency multiplier 510. The frequency multiplier 510 includes an XOR gate 512a and an XNOR gate 512b. The XOR gate 512a and XNOR gate 512b receive buffered versions of the PI0 output phase signal 620 and its quadrature PI2 output phase signal 624, and generate clk1 and clkb in the high-speed clock signal 530. The phase separation between the half-rate clock signals is approximately 180°, with variations relative to 180° phase separation due to the different switching characteristics of the XOR gate 512a and XNOR gate 512b.

[0069] The operation of the frequency multiplier 510 can be understood from the consideration of the XOR gate 512a. The XNOR gate 512b generates an inverted version of the output of the XOR gate 512a. Initially, both the PI0 output phase signal 620 and the PI2 output phase signal 624 are low, and the output of the XOR gate 512a is also low. At edge 908, the PI0 output phase signal 620 transitions to high, while the PI2 output phase signal 624 remains low, causing the output of the XOR gate 512a to transition to high at edge 916. At edge 910, the PI2 output phase signal 624 transitions to high, while the PI0 output phase signal 620 remains high, causing the output of the XOR gate 512a to transition to low at edge 918. At edge 912, the PI0 output phase signal 620 transitions to low, while the PI2 output phase signal 624 remains high, causing the output of the XOR gate 512a to transition to high at edge 920. At edge 914, the PI2 output phase signal 624 transitions low, while the PI0 output phase signal 620 remains low, causing the output of the XOR gate 512a to transition low at edge 922. Therefore, the output signal generated by the XOR operation on the quadrature inputs switches at twice the frequency of the input signal.

[0070] The high-speed clock signal 530 output by the frequency multiplier 510 can be provided to the injection-locked oscillator 514, which can ensure a precise or highly accurate 90° phase separation in a set of sampled clock signals 532.

[0071] Figure 10 is a flowchart illustrating an example of a method 1000 for providing multiple in-phase and quadrature signals according to certain states of this invention. Method 1000 can be implemented in a receiver coupled to a serial bus and can correspond to the circuit described with respect to Figures 4-8.

[0072] In block 1002, the phase generator can be used to generate multiple intermediate clock signals with a phase shift different from the input clock signal. The number of intermediate clock signals can be determined based on the application, the frequency of the input clock signal, and other parameters. The phase separation of the intermediate clock signals can be configured as needed or desired. In block 1004, the phase rotator circuit can be configured to generate phase-adjusted clock signals. In some instances, each phase-adjusted clock signal can have a phase within a range bounded by the phases of two of the intermediate clock signals. For example, when the phase separation between two intermediate clock signals is 45°, the corresponding phase-adjusted clock signal can have the same phase as either of the two intermediate clock signals, or the phase of the corresponding phase-adjusted clock signal can be located between the two intermediate clock signals.

[0073] In block 1006, the frequency multiplier circuit can be used to generate two multiplied clock signals with a 180° phase difference from a plurality of phase-adjusted clock signals. In some cases, the combined two multiplied clock signals can be considered, or referred to as, differential phase-adjusted clock signals. In one example, a pair of XOR gates is used to provide the frequency multiplier circuit. Each XOR gate receives in-phase and quadrature phase-adjusted clock signals. In block 1008, the quadrature clock generation circuit is configured to provide four output signals from the two multiplied clock signals. The four output signals include in-phase and quadrature versions of the two multiplied clock signals. For example, the first output signal may have a 0° phase relative to the input signal, the second output signal may have a 90° phase relative to the input signal, the third output signal may have a 180° phase relative to the input signal, and the fourth output signal may have a 270° phase relative to the input signal.

[0074] In some instances, the phase generator includes a delay-locked loop configured to couple an input clock signal to a plurality of delay elements. The plurality of delay elements may include eight delay elements, and the delay-locked loop may provide nine intermediate clock signals with different phase shifts to the phase rotator circuit.

[0075] In one example, the phase rotator circuit includes a first plurality of gates coupled between a first terminal of a corresponding switch in a first plurality of switches and a first intermediate clock signal, and a second plurality of gates coupled between a first terminal of a corresponding switch in a second plurality of switches and a second intermediate clock signal. Each of the first plurality of switches and the second plurality of switches has a second terminal coupled to the first phase adjustment clock signal. The phase of the first phase adjustment clock signal lies within a range bounded by the phases of the first intermediate clock signal and the second intermediate clock signal. The phase of the first phase adjustment clock signal can be determined by the number of closed switches in the first plurality of switches and the number of closed switches in the second plurality of switches. The phase of the first phase adjustment clock signal can be selected by closing a first number of switches in the first plurality of switches and a second number of switches in the second plurality of switches via the phase rotator circuit.

[0076] In some instances, the quadrature clock generation circuit includes an injection-locked oscillator. Four output signals are used by a deserializer circuit configured to sample serialized data from the serial bus. Input clock signals can be received from the serial bus.

[0077] In some instances, method 1000 includes configuring a multiplexer to select four of the phase-adjusted clock signals and coupling the four selected phase-adjusted clock signals to a frequency multiplier circuit.

[0078] The operational steps described in any of the exemplary embodiments herein are also described to provide examples. The described operations can be performed in many different orders other than the order shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary embodiments can be combined. It should be understood that the operational steps shown in the flowcharts can be modified in many different ways, as will be apparent to those skilled in the art to which this invention pertains. Those skilled in the art to which this invention pertains will also understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0079] The various operations of the above method can be performed by any suitable unit capable of performing the corresponding function. This unit may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Typically, in the presence of the operations shown in the figures, those operations may have corresponding units plus functional components (which have similar numbering). In some configurations, there are units for generating multiple intermediate clock signals with different phase shifts based on an input clock signal; units for configuring a phase rotator circuit to generate phase-adjusted clock signals, each phase-adjusted clock signal having a phase within a range bounded by the phases of two intermediate clock signals; units for generating two frequency-multiplied clock signals, including a frequency multiplier circuit configured to generate two frequency-multiplied clock signals having a 180° phase difference with the plurality of phase-adjusted clock signals; and units for configuring a quadrature clock generation circuit to provide four output signals based on the two frequency-multiplied clock signals, the four output signals including in-phase and quadrature versions of the two frequency-multiplied clock signals.

[0080] In some instances, the unit for generating multiple intermediate clock signals includes a delay-locked loop configured to couple an input clock signal to a plurality of delay elements. The plurality of delay elements may include eight delay elements, and the delay-locked loop may provide nine intermediate clock signals with different phase shifts to the phase rotator circuit. In one instance, the phase rotator circuit has a first plurality of gates coupled between a first terminal of a corresponding switch in a first plurality of switches and a first intermediate clock signal, and a second plurality of gates coupled between a first terminal of a corresponding switch in a second plurality of switches and a second intermediate clock signal. Each of the first plurality of switches and the second plurality of switches has a second terminal coupled to a first phase adjustment clock signal. The phase of the first phase adjustment clock signal may be determined by the number of closed switches in the first plurality of switches and the second plurality of switches.

[0081] In one example, the unit for configuring the phase rotator circuit is configured to select the phase of the first phase adjustment clock signal by turning off a first number of switches from a first plurality of switches and a second number of switches from a second plurality of switches.

[0082] In one example, the frequency multiplier circuit includes a pair of XOR gates, each receiving a clock signal adjusted for in-phase and quadrature phases. In one example, the quadrature clock generation circuit includes an injection-locked oscillator. In some examples, four output signals are used by a deserializer circuit configured to sample serialized data from a serial bus. Input clock signals can be received from the serial bus.

[0083] In one example, the device includes a unit for selecting four phase-adjustable clock signals and for coupling the four selected phase-adjustable clock signals to a frequency multiplier circuit.

[0084] Examples of embodiments are described in the following numbered clauses: 1. A clock generation circuit, comprising: a phase generator that receives an input clock signal and uses the input clock signal to generate a plurality of intermediate clock signals with different phase shifts; a phase rotator circuit that outputs a phase-adjusted clock signal; a frequency multiplier circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-multiplied clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-multiplied clock signals and provides four output signals, the four output signals including in-phase and quadrature versions of the two frequency-multiplied clock signals. 2. The clock generation circuit of claim 1, wherein the phase generator includes a delay-locked loop in which the input clock signal is coupled to a plurality of delay elements. 3. The clock generation circuit of claim 2, wherein the plurality of delay elements includes eight delay elements, and the delay-locked loop provides the phase rotator circuit with nine intermediate clock signals with different phase shifts. 4. A clock generating circuit according to any one of clauses 1-3, wherein the phase rotator circuit comprises: a first plurality of gates coupled between a first terminal of a corresponding switch in the first plurality of switches and a first intermediate clock signal; and a second plurality of gates coupled between a first terminal of a corresponding switch in the second plurality of switches and a second intermediate clock signal, wherein each of the first plurality of switches and the second plurality of switches has a second terminal coupled to the first phase adjustment clock signal. 5. A clock generating circuit according to clause 4, wherein the phase of the first phase adjustment clock signal is located within a range bounded by the phases of the first intermediate clock signal and the second intermediate clock signal, and is determined by the number of closed switches in the first plurality of switches and the number of closed switches in the second plurality of switches. 6. A clock generation circuit according to any one of Clauses 1-5, wherein the frequency multiplier circuit comprises: an XOR gate configured to receive a first phase-adjusted clock signal and a second phase-adjusted clock signal as its input, the first phase-adjusted clock signal and the second phase-adjusted clock signal having a 90° phase difference; and an XOR gate configured to receive the first phase-adjusted clock signal and the second phase-adjusted clock signal as its input. 7. A clock generation circuit according to Clause 6, wherein the first phase-adjusted clock signal and the second phase-adjusted clock signal have a 90° phase difference. 8. A clock generation circuit according to any one of Clauses 1-7, wherein the quadrature clock generation circuit comprises an injection-locked oscillator. 9. A clock generation circuit according to any one of Clauses 1-8, wherein the four output signals are used by a deserializer circuit configured to sample serialized data from a serial bus. 10. A clock generation circuit according to Clause 9, wherein the input clock signal is received from the serial bus.11. The clock generation circuit according to any one of claims 1-10, further comprising a multiplexer configured to receive a phase-adjusted clock signal from the phase rotator circuit. 12. The clock generation circuit according to any one of claims 11, wherein the multiplexer is further configured to: receive a phase-adjusted clock signal from the phase rotator circuit; select two of the phase-adjusted clock signals; and couple the two selected phase-adjusted clock signals to a frequency multiplier circuit. 13. An apparatus comprising: a unit for generating a plurality of intermediate clock signals having a different phase shift from an input clock signal; a unit for configuring a phase rotator circuit to generate the phase-adjusted clock signal; a unit for generating two frequency-multiplied clock signals, including a frequency multiplier circuit configured to generate two frequency-multiplied clock signals having a 180° phase difference based on the plurality of phase-adjusted clock signals; and a unit for configuring a quadrature clock generation circuit to provide four output signals based on the two frequency-multiplied clock signals, the four output signals including in-phase and quadrature versions of the two frequency-multiplied clock signals. 14. The apparatus of claim 13, wherein the unit for generating a plurality of intermediate clock signals includes a delay-locked loop configured to couple the input clock signal to a plurality of delay elements. 15. The apparatus of claim 14, wherein the plurality of delay elements includes eight delay elements, and the delay-locked loop provides nine intermediate clock signals with different phase shifts to the phase rotator circuit. 16. The apparatus according to any one of claims 13-15, wherein the phase rotator circuit comprises: a first plurality of gates coupled between a first terminal of a corresponding switch in the first plurality of switches and a first intermediate clock signal; and a second plurality of gates coupled between a first terminal of a corresponding switch in the second plurality of switches and a second intermediate clock signal, wherein each of the first plurality of switches and the second plurality of switches has a second terminal coupled to the first phase adjustment clock signal, and wherein the phase of the first phase adjustment clock signal is located within a range bounded by the phases of the first intermediate clock signal and the second intermediate clock signal, and is determined by the number of closed switches in the first plurality of switches and the number of closed switches in the second plurality of switches. 17. The apparatus according to claim 13, wherein a unit for configuring the phase rotator circuit is configured to select the phase of the first phase adjustment clock signal by causing the phase rotator circuit to close a first number of switches in the first plurality of switches and a second number of switches in the second plurality of switches. 18. The apparatus according to any one of claims 13-17, wherein the frequency multiplier circuit comprises: an XOR gate configured to receive a first phase-adjusted clock signal and a second phase-adjusted clock signal as its input; and an XOR gate configured to receive the first phase-adjusted clock signal and the second phase-adjusted clock signal as its input.19. The apparatus of claim 18, wherein the first phase-adjusted clock signal and the second phase-adjusted clock signal have a 90° phase difference. 20. The apparatus of any one of claims 13-19, wherein the quadrature clock generation circuit includes an injection-locked oscillator. 21. The apparatus of any one of claims 13-20, wherein the four output signals are used by a deserializer circuit configured to sample serialized data from a serial bus. 22. The apparatus of claim 21, wherein the input clock signal is received from the serial bus. 23. The apparatus of any one of claims 13-22, further comprising: a unit for selecting two of the phase-adjusted clock signals and coupling the two selected phase-adjusted clock signals to the frequency multiplier circuit. 24. A method for providing a plurality of in-phase and quadrature signals, comprising: using a phase generator to generate a plurality of intermediate clock signals having a phase shift different from an input clock signal; configuring a phase rotator circuit to generate a phase-adjusted clock signal; using a frequency multiplier circuit to generate two multiplied clock signals with a phase difference of 180° based on a plurality of the phase-adjusted clock signals; and configuring a quadrature clock generation circuit to provide four output signals based on the two multiplied clock signals, the four output signals including in-phase and quadrature versions of the two multiplied clock signals. 25. The method of claim 24, wherein the phase generator includes a delay-locked loop configured to couple the input clock signal to a plurality of delay elements. 26. The method of claim 24 or claim 25, wherein the plurality of delay elements includes eight delay elements, and the delay-locked loop provides the phase rotator circuit with nine intermediate clock signals having different phase shifts. 27. The method of any one of Clauses 24-26, wherein the phase rotator circuit comprises: a first plurality of gates coupled between a first terminal of a corresponding switch in the first plurality of switches and a first intermediate clock signal; and a second plurality of gates coupled between a first terminal of a corresponding switch in the second plurality of switches and a second intermediate clock signal, wherein each of the first plurality of switches and the second plurality of switches has a second terminal coupled to the first phase adjustment clock signal. 28. The method of Clause 27, wherein the phase of the first phase adjustment clock signal lies within a range bounded by the phases of the first intermediate clock signal and the second intermediate clock signal, and is determined by the number of closed switches in the first plurality of switches and the number of closed switches in the second plurality of switches. 29. The method of Clause 27, further comprising: selecting the phase of the first phase adjustment clock signal by causing the phase rotator circuit to close a first number of switches in the first plurality of switches and a second number of switches in the second plurality of switches.30. The method of any one of Clauses 24-29, wherein the frequency multiplier circuit comprises: an XOR gate configured to receive a first phase-adjusted clock signal and a second phase-adjusted clock signal as its input; and an XOR gate configured to receive the first phase-adjusted clock signal and the second phase-adjusted clock signal as its input. 31. The method of Clause 30, wherein the first phase-adjusted clock signal and the second phase-adjusted clock signal have a 90° phase difference. 32. The method of any one of Clauses 24-31, wherein the quadrature clock generation circuit comprises an injection-locked oscillator. 33. The method of any one of Clauses 24-32, wherein the four output signals are used by a deserializer circuit configured to sample serialized data from a serial bus. 34. The method of Clause 33, wherein the input clock signal is received from the serial bus. 35. The method according to any one of clauses 24-34 further includes: configuring a multiplexer to select two of the phase-adjusted clock signals and coupling the two selected phase-adjusted clock signals to the frequency multiplier circuit. 36. A data communication circuit comprising: a phase generator that receives an input clock signal and outputs a plurality of intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals; and a frequency multiplier circuit comprising: an XOR gate configured to receive a first phase-adjusted clock signal and a second phase-adjusted clock signal as its input; and an XOR gate configured to receive the first phase-adjusted clock signal and the second phase-adjusted clock signal as its input; and a quadrature clock generation circuit that receives the frequency-multiplied clock signals from the XOR gate and the XOR gate, and outputs four output signals according to the frequency-multiplied clock signals.

[0085] As used herein, the phrase “at least one of” in a list of items refers to any combination of those items, including a single member. For example, “at least one of a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0086] This invention is provided to enable any person skilled in the art to make or use various forms of this invention. Various modifications to this invention will be readily apparent to those skilled in the art, and the known principles defined herein can be applied to other variations without departing from the scope of this invention. Therefore, this invention is not intended to be limited to the examples and designs described herein, but is to be given the broadest scope consistent with the principles and novel features disclosed herein. [Simplified Explanation of the Diagram]

[0015] Figure 1 illustrates an example of a System-on-a-Chip (SOC) according to certain aspects of this case.

[0016] Figure 2 illustrates an example of a data communication system that can be adjusted according to certain aspects of this case.

[0017] Figure 3 is a block diagram illustrating certain features of the clock generation circuit.

[0018] Figure 4 is a block diagram illustrating an example of the architecture of a clock generation circuit provided according to certain aspects of this case.

[0019] Figure 5 illustrates an example of a clock generation circuit configured according to certain conditions of this case.

[0020] Figure 6 illustrates an example of a circuit that describes the operation of a delay-locked loop circuit and a phase rotation circuit configured according to certain conditions of this case.

[0021] Figure 7 illustrates an example of a phase rotation element configured according to certain conditions of this case.

[0022] Figure 8 illustrates an example of an orthogonal clock generator configured according to certain conditions of this case.

[0023] Figure 9 is a timing diagram showing some states of the operation of the clock generation circuit illustrated in Figure 5.

[0024] Figure 10 is a flowchart illustrating an example of a method for providing multiple in-phase and quadrature signals according to certain states of this case. [Biomaterial Storage]

[0088] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A clock generating circuit, comprising: A phase generator receives an input clock signal and outputs a plurality of intermediate clock signals with different phase shifts; a phase rotator circuit receives the plurality of intermediate clock signals and outputs a phase-adjusted clock signal; a frequency multiplier circuit receives a plurality of phase-adjusted clock signals and outputs two multiplied clock signals with a 180° phase difference; and a quadrature clock generation circuit receives the two multiplied clock signals and provides four output signals, the four output signals including in-phase and quadrature versions of the two multiplied clock signals, wherein the four output signals are used by a deserializer circuit configured to sample serialized data from a serial bus.

2. The clock generation circuit according to claim 1, wherein the phase generator includes a delay-locked loop in which the input clock signal is coupled to a plurality of delay elements.

3. The clock generation circuit according to claim 2, wherein the plurality of delay elements includes eight delay elements, and the delay-locked loop provides the phase rotator circuit with nine intermediate clock signals having different phase shifts.

4. The clock generating circuit according to claim 1, wherein the phase rotator circuit includes: A first plurality of gates, wherein the first plurality of gates are coupled between the first terminal of a corresponding switch in the first plurality of switches and a first intermediate clock signal; and a second plurality of gates, the second plurality of gates being coupled between a first terminal of a corresponding switch in the second plurality of switches and a second intermediate clock signal, wherein each of the first plurality of switches and the second plurality of switches has a second terminal coupled to a first phase adjustment clock signal.

5. The clock generation circuit according to claim 4, wherein the phase of the first phase adjustment clock signal is located within a range bounded by the phases of the first intermediate clock signal and the second intermediate clock signal, and is determined by the number of closed switches among the first plurality of switches and the number of closed switches among the second plurality of switches.

6. The clock generation circuit according to claim 1, wherein the quadrature clock generation circuit includes an injection-locked oscillator.

7. The clock generation circuit according to request item 1, wherein the input clock signal is received from the serial bus.

8. The clock generation circuit according to claim 1 also includes a multiplexer configured to receive a phase adjustment clock signal from the phase rotator circuit.

9. The clock generation circuit according to claim 8, wherein the multiplexer is also configured to: select two of the phase-adjusted clock signals; and couple the two selected phase-adjusted clock signals to the frequency multiplier circuit.

10. A clock generating circuit, comprising: A phase generator receives an input clock signal and outputs a plurality of intermediate clock signals with different phase shifts; a phase rotator circuit receives the plurality of intermediate clock signals and outputs a phase-adjusted clock signal; a frequency multiplier circuit receives a plurality of phase-adjusted clock signals and outputs two multiplied clock signals with a 180° phase difference; and a quadrature clock generation circuit receives the two multiplied clock signals and provides four output signals, the four output signals including in-phase and quadrature versions of the two multiplied clock signals, wherein the frequency multiplier circuit includes: an XOR gate configured to receive a first phase-adjusted clock signal and a second phase-adjusted clock signal as its input; and an XOR gate configured to receive the first phase-adjusted clock signal and the second phase-adjusted clock signal as its input.

11. The clock generation circuit according to claim 10, wherein the first phase-adjusted clock signal and the second phase-adjusted clock signal have a 90° phase difference.

12. An apparatus for managing phase relationships, comprising: A unit for generating multiple intermediate clock signals with different phase shifts from an input clock signal; A unit for generating phase-adjusted clock signals based on the plurality of intermediate clock signals; a unit for generating two frequency-multiplied clock signals, including a frequency multiplier circuit configured to generate two frequency-multiplied clock signals having a 180° phase difference from the plurality of phase-adjusted clock signals; and a unit for configuring a quadrature clock generation circuit to provide four output signals based on the two frequency-multiplied clock signals, the four output signals including in-phase and quadrature versions of the two frequency-multiplied clock signals, wherein the four output signals are used by a deserializer circuit configured to sample serialized data from a serial bus.

13. The apparatus of claim 12, wherein the unit for generating a plurality of intermediate clock signals includes a delay-locked loop configured to couple the input clock signal to a plurality of delay elements.

14. The apparatus according to claim 13, wherein the plurality of delay elements includes eight delay elements, and the delay-locked loop provides nine intermediate clock signals with different phase shifts to a phase rotator circuit.

15. The apparatus of claim 12, wherein the unit for generating a phase-adjusted clock signal includes a phase rotator circuit, the phase rotator circuit comprising: A first plurality of gates, wherein the first plurality of gates are coupled between the first terminal of a corresponding switch in the first plurality of switches and a first intermediate clock signal; and a second plurality of gates, the second plurality of gates being coupled between a first terminal of a corresponding switch in the second plurality of switches and a second intermediate clock signal, wherein each of the first plurality of switches and the second plurality of switches has a second terminal coupled to a first phase adjustment clock signal, and wherein the phase of the first phase adjustment clock signal is determined by the number of closed switches in the first plurality of switches and the number of closed switches in the second plurality of switches.

16. The apparatus according to claim 15, wherein the phase of the first phase adjustment clock signal is located within a range bounded by the phases of the first intermediate clock signal and the second intermediate clock signal, and is determined by a number of closed switches in the first plurality of switches and a number of closed switches in the second plurality of switches.

17. The apparatus according to claim 12, wherein the quadrature clock generating circuit includes an injection-locked oscillator.

18. The apparatus according to claim 12, wherein the input clock signal is received from the serial bus.

19. The apparatus according to claim 12 also includes: A unit for selecting two of the phase adjustment clock signals and coupling the two selected phase adjustment clock signals to the frequency multiplier circuit.

20. An apparatus for managing phase relationships, comprising: A unit for generating multiple intermediate clock signals with different phase shifts from an input clock signal; A unit for generating phase-adjusted clock signals based on the plurality of intermediate clock signals; a unit for generating two multiplied clock signals, including a frequency multiplier circuit configured to generate two multiplied clock signals having a 180° phase difference from the plurality of phase-adjusted clock signals; and a unit for configuring a quadrature clock generation circuit to provide four output signals based on the two multiplied clock signals, the four output signals including in-phase and quadrature versions of the two multiplied clock signals, wherein the frequency multiplier circuit includes: an XOR gate configured to receive a first phase-adjusted clock signal and a second phase-adjusted clock signal as its input; and an XOR gate configured to receive the first phase adjustment clock signal and the second phase adjustment clock signal as its inputs.

21. The apparatus according to claim 20, wherein the first phase adjustment clock signal and the second phase adjustment clock signal have a 90° phase difference.

22. A method for providing a plurality of in-phase and quadrature signals, comprising the steps of: generating a plurality of intermediate clock signals having a phase shift different from an input clock signal using a phase generator; configuring a phase rotator circuit to generate phase-adjusted clock signals based on the plurality of intermediate clock signals; generating two multiplied clock signals having a 180° phase difference based on the plurality of phase-adjusted clock signals using a frequency multiplier circuit; and configuring a quadrature clock generation circuit to provide four output signals based on the two multiplied clock signals, the four output signals including in-phase and quadrature versions of the two multiplied clock signals, wherein the four output signals are used by a deserializer circuit configured to sample serialized data from a serial bus.

23. The method of claim 22, wherein the phase generator includes a delay-locked loop configured to couple the input clock signal to a plurality of delay elements.

24. The method of claim 23, wherein the plurality of delay elements comprises eight delay elements, and the delay-locked loop provides the phase rotator circuit with nine intermediate clock signals having different phase shifts.

25. The method of claim 22, wherein the phase rotator circuit includes the following steps: a first plurality of gates, the first plurality of gates being coupled between a first terminal of a corresponding switch in a first plurality of switches and a first intermediate clock signal; and a second plurality of gates, the second plurality of gates being coupled between a first terminal of a corresponding switch in a second plurality of switches and a second intermediate clock signal, wherein each of the first plurality of switches and the second plurality of switches has a second terminal coupled to a first phase adjustment clock signal.

26. The method of claim 25, wherein the phase of the first phase adjustment clock signal is located within a range bounded by the phases of the first intermediate clock signal and the second intermediate clock signal, and is determined by a number of closed switches among the first plurality of switches and a number of closed switches among the second plurality of switches.

27. The method according to claim 25 also includes the following steps: selecting a phase of the first phase adjustment clock signal by turning off a first number of switches from the first plurality of switches and a second number of switches from the second plurality of switches.

28. The method of claim 22, wherein the quadrature clock generation circuit includes an injection-locked oscillator.

29. The method according to request item 22, wherein the input clock signal is received from the serial bus.

30. The method according to claim 22 also includes the steps of: configuring a multiplexer to select two of the phase-adjusted clock signals and coupling the two selected phase-adjusted clock signals to the frequency multiplier circuit.

31. A method for providing a plurality of in-phase and quadrature signals, comprising the steps of: generating a plurality of intermediate clock signals having a phase shift different from an input clock signal using a phase generator; configuring a phase rotator circuit to generate phase-adjusted clock signals according to the plurality of intermediate clock signals; generating two multiplied clock signals having a 180° phase difference using a frequency multiplier circuit according to the plurality of phase-adjusted clock signals; and configuring a quadrature clock generation circuit to provide four output signals according to the two multiplied clock signals, the four output signals including in-phase and quadrature versions of the two multiplied clock signals, wherein the frequency multiplier circuit includes: An XOR gate configured to receive a first phase-adjusted clock signal and a second phase-adjusted clock signal as its input; and an XOR gate configured to receive the first phase adjustment clock signal and the second phase adjustment clock signal as its inputs.

32. The method of claim 31, wherein the first phase-adjusted clock signal and the second phase-adjusted clock signal have a 90° phase difference.

33. A data communication circuit, comprising: A phase generator that receives an input clock signal and outputs multiple intermediate clock signals with different phase shifts; A phase rotator circuit that outputs a phase adjustment clock signal; A frequency multiplier circuit, the frequency multiplier circuit including: an XOR gate, the XOR gate being configured to receive a first phase-adjusted clock signal and a second phase-adjusted clock signal as its input; The circuit includes an XOR gate configured to receive the first phase adjustment clock signal and the second phase adjustment clock signal as its inputs; and a quadrature clock generation circuit that receives a frequency multiplied clock signal from the XOR gate and the XOR gate, and outputs four output signals according to the frequency multiplied clock signal.

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