System and method for adaptive clock duty-cycle controller

Abstract

This case relates to a method for compensating for duty cycle distortion in a system including a clock generator configured to generate a clock signal. The method includes: measuring one or more parameters of the clock signal; determining a duty cycle adjustment based on the measured parameters; and adjusting the duty cycle of the clock signal based on the determined duty cycle adjustment.

Description

[Technical Field]

[0001] This patent application claims priority and benefits over non-provisional patent application No. 17 / 485,361, filed with the U.S. Patent and Trademark Office on September 25, 2022.

[0002] In general, the content of this case concerns clock distribution, and more specifically, the content of this case concerns duty cycle distortion in clock distribution networks. [Previous Technology]

[0003] The system may include a clock generator (e.g., a phase-locked loop) configured to generate clock signals for the timing operation of one or more circuits (e.g., flip-flops) in the system. The system may also include a clock distribution network (also known as a clock tree) for distributing clock signals from the clock generator to one or more circuits. One challenge in clock distribution is that asymmetric aging in one or more signal paths of the clock distribution network can cause distortion of the clock signal's duty cycle, leading to timing problems (e.g., timing violations) in one or more circuits. [Summary of the Invention]

[0004] The following provides a simplified summary of one or more embodiments to provide a basic understanding of these embodiments. This summary is not an exhaustive overview of all contemplated embodiments, and is not intended to identify key or essential elements of all embodiments, nor to describe the scope of any or all embodiments. Its sole purpose is to present some ideas of one or more embodiments in a simplified form as a prelude to the more detailed description provided later.

[0005] The first embodiment relates to a system. The system includes a duty cycle adjuster having a signal input, a control input, and an output, wherein the duty cycle adjuster is configured to: receive a clock signal at the signal input, receive a control signal at the control input, adjust the duty cycle of the clock signal based on the control signal to generate a duty cycle adjusted clock signal, and output the duty cycle adjusted clock signal at the output of the duty cycle adjuster. The system also includes a timing measurement circuit having an input coupled to the output of the duty cycle adjuster, wherein the timing measurement circuit is configured to: receive the duty cycle adjusted clock signal at the input of the timing measurement circuit, measure one or more parameters of the duty cycle adjusted clock signal, and generate a measurement signal based on the measured one or more parameters.

[0006] The second aspect relates to a method for compensating for duty cycle distortion in a system including a clock generator configured to generate a clock signal. The method includes: measuring one or more parameters of the clock signal; determining a duty cycle adjustment based on the measured one or more parameters; and adjusting the duty cycle of the clock signal based on the determined duty cycle adjustment.

Implementation Method

[0033] The embodiments provided below in conjunction with the accompanying drawings are intended as a description of various configurations, and not as representing the only configuration in which the concepts herein can be implemented. Specific details are included in the detailed description to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art to which this invention pertains that these design concepts can be implemented without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0034] Figure 1 illustrates an example of system 110, which includes a clock generator 115, a clock distribution network 120, and multiple circuits 150-1 to 150-3 according to certain patterns. The clock generator 115 is configured to generate clock signals for timing operations of circuits 150-1 to 150-3. The clock generator 115 can be implemented using a phase-locked loop (PLL) or other type of clock generator 115. The clock distribution network 120 (also referred to as a clock tree) is configured to distribute clock signals from the clock generator 115 to circuits 150-1 to 150-3. As used herein, a "clock signal" can be a periodic signal oscillating between high and low. For example, a clock signal can be used to time the operation of synchronous digital circuits or other types of circuits. A clock signal has a duty cycle, which can be expressed as a percentage or fraction of the clock period (i.e., clock cycle) during which the clock signal is high (i.e., 1). Clock signals can be gated to save power (e.g., when circuits 150-1 through 150-3 are inactive). Clock gating is a known technique for reducing dynamic power consumption when one or more circuits are inactive.

[0035] In the example shown in Figure 1, each of the circuits 150-1 to 150-3 may include corresponding flip-flops 155-1 to 155-3, which are timed by a clock signal. It should be understood that the circuits 150-1 to 150-3 are not limited to flip-flops, and may include other devices besides or in place of flip-flops 155-1 to 155-3.

[0036] In this example, clock generator 115 is coupled to input 122 of clock distribution network 120, and each of circuits 150-1 to 150-3 is coupled to a corresponding output 124-1 to 124-3 of clock distribution network 120. Clock distribution network 120 receives clock signals from clock generator 115 via input 122 (also referred to as the root node) and distributes clock signals to circuits 150-1 to 150-3 via outputs 124-1 to 124-3 (also referred to as leaf nodes).

[0037] In the example shown in FIG1, clock distribution network 120 includes signal path 125 and delay buffers 132, 134 and 136. Signal path 125 includes series-coupled delay buffers 130-1 to 130-n. It should be understood that clock distribution network 120 may include additional delay buffers and / or other components not shown in FIG1. ​​For example, clock distribution network 120 may include self-adjusting clock distribution (not shown) to mitigate the effects of power supply voltage drops. Clock distribution network 120 may also include one or more clock gating circuits (also referred to as clock gating units) for gating clock signals when circuits 150-1 to 150-3 are idle to reduce dynamic power consumption when circuits 150-1 to 150-3 are idle. As used herein, a “signal path” is the path through which a signal (e.g., a clock signal) propagates and may include one or more delay buffers and / or one or more other components (e.g., splitters, amplifiers, switches, voltage level shifters, clock gate circuits, etc.).

[0038] One challenge of the clock distribution network 120 is that asymmetric aging in the clock distribution network 120 can cause duty cycle distortion in the clock signal at the leaf nodes (i.e., outputs 124-1 to 124-3), which are coupled to circuits 150-1 to 150-3. If not corrected, duty cycle distortion can lead to timing problems (e.g., timing violations) in circuits 150-1 to 150-3.

[0039] An example of duty cycle distortion due to asymmetric aging in the signal path 125 of the clock distribution network 120 will now be discussed with reference to Figures 2A to 2C. Figure 2A illustrates an example of signal path 125 including series-coupled delay buffers 130-1 to 130-8. It should be understood that signal path 125 is not limited to the number of delay buffers 130-1 to 130-8 shown in Figure 2A, and signal path 125 may include different numbers of delay buffers.

[0040] In the example shown in FIG2A, each of the delay buffers 130-1 to 130-8 is implemented together with a corresponding complementary inverter, which includes a first corresponding transistor 225-1 to 225-8 (e.g., an n-type field-effect transistor (NFET)) and a second corresponding transistor 230-1 to 230-8 (e.g., a p-type field-effect transistor (PFET)). However, it should be understood that each of the delay buffers 130-1 to 130-8 can be implemented using another type of circuit or logic gate. It should also be understood that the delay buffer may include two series-coupled inverters to implement a non-inverting delay buffer. In this case, delay buffers 130-1 and 130-2 in FIG2A can be considered as the first non-inverting delay buffer, delay buffers 130-3 and 130-4 in FIG2A can be considered as the second non-inverting delay buffer, and so on.

[0041] In some configurations, a clock gating circuit (not shown) may be coupled between the clock generator 115 and the input of the signal path 125. In this example, the clock gating circuit may be configured to deliver a clock signal in an active mode and to gating (i.e., locking) the clock signal in an idle mode to save power in the idle mode.

[0042] Figure 2B illustrates an example where the clock signal is gated in idle mode, and the input of signal path 125 remains low (i.e., logic zero) in idle mode. Figure 2B also illustrates the logic state at the output of each of delay buffers 130-1 to 130-8 in idle mode. As shown in Figure 2B, the logic state at the output of delay buffers 130-1 to 130-8 alternates between 1 and 0 because delay buffers 130-1 to 130-8 are implemented using inverters in this example.

[0043] In this example, transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8 are switched on in idle mode, while transistors 225-1, 230-2, 225-3, 230-4, 225-5, 230-6, 225-7, and 230-8 are switched off in idle mode. In Figure 2B, the switched-on transistors are indicated by bold lines. Transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8, which are turned on in idle mode, are subjected to stress in idle mode, wherein a DC voltage approximately equal to the power supply voltage Vdd is applied to the source of each of the transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8. Voltage stress in idle mode causes transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8 to age more than transistors 225-1, 230-2, 225-3, 230-4, 225-5, 230-6, 225-7, and 230-8 that are turned off in idle mode, resulting in asymmetrical aging of transistors in signal path 125.

[0044] In this example, asymmetric aging increases the threshold voltage of transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7 and 225-8, which causes transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7 and 225-8 to decelerate relative to transistors 225-1, 230-2, 225-3, 230-4, 225-5, 230-6, 225-7 and 230-8. The deceleration of transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8 causes an increase in the falling edge delay at the output of signal path 125 relative to the rising edge delay. This is because the falling edge (i.e., the falling transition) of the clock signal propagates to the output of signal path 125 via transistors 230-1, 225-2, 230-3, 225-4, 230-5, 225-6, 230-7, and 225-8, which are under stress in idle mode, while the rising edge (i.e., the rising transition) of the clock signal propagates to the output of signal path 125 via transistors 225-1, 230-2, 225-3, 230-4, 225-5, 230-6, 225-7, and 230-8, which are not under stress in idle mode. The increase in falling edge delay relative to rising edge delay causes duty cycle distortion in signal path 125.

[0045] An example of duty cycle distortion is shown in the timing diagram of Figure 2C. In the example shown in Figure 2C, clock signal 250 is the input to signal path 125 when signal path 125 is not in idle mode (i.e., signal path 125 is active). In this example, clock signal 250 has 50% duty cycle at the input of signal path 125. Figure 2C also illustrates clock signal 260 at the output of signal path 125 after the clock signal has propagated through signal path 125. Signal path 125 delays the rising edge of clock signal 260 by a delay amount Tr and delays the falling edge of clock signal 260 by a delay amount Tf. As shown in Figure 2C, as mentioned above, due to the asymmetric aging of the transistors in signal path 125, the delay amount Tf of the falling edge is longer than the delay amount Tr of the rising edge. The longer delay of the falling edge results in an increase in the duty cycle of the clock signal 260 at the output of signal path 125 (i.e., causing the duty cycle to be greater than 50%). Therefore, in this example, the duty cycle distortion due to asymmetric aging increases the duty cycle of the clock signal.

[0046] Asymmetric aging also occurs when the input of signal path 125 remains high in idle mode. In this case, asymmetric aging causes the rise time delay of signal path 125 to increase relative to the fall time delay of signal path 125, resulting in duty cycle distortion that reduces the duty cycle of the clock signal. Therefore, asymmetric aging of the transistor in signal path 125 causes duty cycle distortion over time. Duty cycle distortion can increase or decrease the duty cycle of the clock signal, for example, depending on whether the input of signal path 125 remains low or high in idle mode, the number of delay buffers in signal path 125, and / or other factors.

[0047] Figure 3 illustrates an example of a self-adjusting duty cycle controller 305 configured to compensate for duty cycle distortion according to certain conditions. The self-adjusting duty cycle controller 305 includes a timing measurement circuit 310, a duty cycle adjuster 320, and a duty cycle control circuit 330.

[0048] The timing measurement circuit 310 has an input 312 and an output 314. In the example of FIG3, the input 312 of the timing measurement circuit 310 is coupled to a leaf node (i.e., output 124-3) of the clock distribution network 120. However, it should be understood that in other embodiments, the input 312 of the timing measurement circuit 310 may be coupled to another node, as further discussed below. The timing measurement circuit 310 is configured to receive a clock signal at input 312, measure one or more timing parameters of the clock signal, and output a measurement signal based on the measured one or more timing parameters. The one or more timing parameters provide information related to the duty cycle of the clock signal received at input 312 of the timing measurement circuit 310. For example, the one or more timing parameters may include a measurement of the high phase of the clock signal, where the high phase is the duration for which the clock signal is high (i.e., 1) within one clock cycle (i.e., one period of the clock signal). In this example, for a given clock cycle, a larger high phase indicates a larger duty cycle, while a smaller high phase indicates a smaller duty cycle. One or more timing parameters may also include measurements of the low phase of the clock signal, where the low phase is the duration for which the clock signal is low (i.e., zero) within a clock cycle. In this example, for a given clock cycle, a larger low phase indicates a smaller duty cycle, while a smaller low phase indicates a larger duty cycle.

[0049] In the example of Figure 3, the timing measurement circuit 310 is coupled to the leaf node (i.e., output 124-3). Therefore, in this example, the timing measurement circuit 310 receives the clock signal after it has undergone duty cycle distortion in the clock distribution network 120. As a result, the measurement signal from the timing measurement circuit 310 provides information about the duty cycle distortion of the clock signal at the leaf node due to aging effects in the clock distribution network 120. The timing measurement circuit 310 may also be referred to as a duty cycle monitor, duty cycle measurement circuit, duty cycle detector, or other terms.

[0050] The duty cycle adjuster 320 has a signal input 322, a control input 326, and an output 324. The signal input 322 is coupled to the clock generator 115, and the output 324 is coupled to the clock distribution network 120. In the example of FIG3, the output 324 of the duty cycle adjuster 320 is coupled to a leaf node (i.e., input 3) of the clock distribution network 120. The duty cycle adjuster 320 is configured to receive a clock signal at the signal input 322, adjust the duty cycle of the clock signal (i.e., perform duty cycle adjustment on the clock signal), and output a clock signal at the output 324 after duty cycle adjustment. The clock signal at the output 324 can also be referred to as a duty cycle adjusted clock signal because the duty cycle adjuster 320 adjusts the duty cycle of the clock signal received at the input 322 to generate a duty cycle adjusted clock signal at the output 324. The duty cycle adjuster 320 is configured to adjust the duty cycle of the clock signal based on a control signal received at control input 326, as further discussed below. In this example, since the output 324 of the duty cycle adjuster 320 is coupled to the root node (i.e., input 122) of the clock distribution network 120, the duty cycle adjuster 320 provides duty cycle adjustment of the clock signal at the root node. However, it should be understood that the scope of this invention is not limited to this example.

[0051] The duty cycle controller circuit 330 has an input 332 and an output 334. The input 332 is coupled to the output 314 of the timing measurement circuit 120, while the output 334 is coupled to the control input 326 of the duty cycle adjuster 320. The duty cycle control circuit 330 is configured to receive a measurement signal from the timing measurement circuit 310, and the duty cycle adjuster 320 sets the duty cycle adjustment of the clock signal based on the measurement signal via the control input 326.

[0052] In one example, the duty cycle control circuit 330 determines a duty cycle adjustment based on a measurement signal from the timing measurement circuit 310, and sets the duty cycle adjustment of the duty cycle adjuster 320 based on the determined duty cycle adjustment to compensate for duty cycle distortion in the clock distribution network 120. For example, the measurement signal from the timing measurement circuit 310 may indicate the high phase of a clock signal measured at a leaf node. In this example, the duty cycle control circuit 330 may compare the measured high phase with a target high phase corresponding to a target duty cycle to determine the duty cycle adjustment for the duty cycle adjuster 320. For an example where the target duty cycle is 50% of the duty cycle, the target high phase is approximately equal to half a clock cycle. If the measured high phase is greater than the target high phase (occurring when the duty cycle of the clock signal at the leaf node is greater than the target duty cycle), the duty cycle control circuit 330 may determine to reduce the duty cycle adjustment of the clock signal at the leaf node for the duty cycle adjuster 320. In this case, reducing the duty cycle decreases the difference between the duty cycle of the clock signal at the leaf node and the target duty cycle. Alternatively, if the measured high phase is less than the target high phase (occurring when the duty cycle of the clock signal at the leaf node is less than the target duty cycle), the duty cycle control circuit 330 can determine to increase the duty cycle adjustment of the clock signal at the leaf node for the duty cycle adjuster 320. Other examples of determining the duty cycle adjustment of the duty cycle adjuster 320 are further discussed below.

[0053] Therefore, in this example, the self-adjusting duty cycle controller 305 uses the timing measurement circuit 310 to monitor the duty cycle of the clock signal at the leaf node, and adjusts the duty cycle of the clock signal at the root node based on the measurement signal from the timing measurement circuit 310 to compensate for duty cycle distortion in the clock distribution network 120. In some cases, the self-adjusting duty cycle controller 305 can perform duty cycle adjustment each time the system 110 is booted.

[0054] In the example of Figure 3, the self-tuning cycle controller 305 uses timing measurement circuitry 310 to monitor the duty cycle of the clock signal at a leaf node (i.e., output 124-3). In this example, there can be a high correlation between the duty cycle distortion at the leaf node coupled to timing measurement circuitry 310 and the duty cycle distortion at each of the other leaf nodes (i.e., outputs 124-1 and 124-2). However, it should be understood that the self-tuning cycle controller 305 is not limited to this example. In another example, the self-tuning cycle controller 305 may include multiple timing measurement circuits, each coupled to a corresponding leaf node for monitoring the duty cycle of the clock signal at that leaf node.

[0055] It should be understood that the timing measurement circuit 310 is not limited to coupling to a leaf node. For example, in some applications, the timing measurement circuit 310 may be coupled to a node located before or within the clock distribution network 120. Such operations can be performed, for example, to provide duty cycle compensation for effects other than the aging effects in the clock distribution network 120 discussed above that cause duty cycle distortion in the clock signal. In one example, the clock generator 115 may introduce duty cycle distortion into the clock signal. In this example, to provide compensation for duty cycle distortion in the clock generator 115, the timing measurement circuit 310 may be coupled to the output 324 of the duty cycle adjuster 320 before the clock distribution network 120. In another example, the timing measurement circuit 310 may be coupled to a node within the clock distribution network 120 to provide duty cycle compensation within the clock distribution network 120. Therefore, it should be understood that the timing measurement circuit 310 can be coupled to any of the multiple nodes in the system (e.g., system 110) to provide duty cycle compensation for various effects in the system that cause duty cycle distortion.

[0056] One challenge in implementing the timing measurement circuit 310 is achieving high-resolution timing measurement. High resolution enables more accurate compensation for duty cycle distortion (e.g., in the clock distribution network 120 and / or clock generator 115). As the frequency of clock signals increases to achieve faster processing speeds, achieving high-resolution timing measurement becomes more challenging, as discussed further below.

[0057] Figure 4 illustrates an example of a current embodiment of the timing measurement circuit 410. The timing measurement circuit 410 includes a flip-flop 420, a ring oscillator 430, and a counter 440. The flip-flop 420 has a signal input (labeled "D") configured to receive a clock signal, a clock input (labeled "CK"), and an output (labeled "Q"). The ring oscillator 430 has an enable input 432 and an output 434. The counter 440 has a target input 446, a count input 442, an enable input 444, and an output 448.

[0058] In this example, the timing measurement circuit 410 measures the high phase of the clock signal (i.e., the duration of the clock signal being high within one clock cycle). For this purpose, the ring oscillator 430 is enabled by inputting an enable signal to its enable input 432. This causes the ring oscillator 430 to generate a ring oscillator (RO) signal oscillating at its own frequency. The ring oscillator 430 outputs the RO signal at its output 434, which is coupled to the clock input of the flip-flop 420 and the count input 442 of the counter 440.

[0059] In this example, flip-flop 420 is timed by the RO signal. Flip-flop 420 is configured to latch the logic state of the clock signal on the rising edge of the RO signal and output the latched logic state of the clock signal to the enable input 444 of counter 440. In this example, flip-flop 420 latches 1 when the clock signal is high, and therefore outputs 1 to the enable input 444 of counter 440 for a duration approximately equal to the high phase of the clock signal.

[0060] In this example, counter 440 counts the number of oscillations of the RO signal at count input 442, while trigger 420 outputs 1 to enable input 444 of counter 440. Since trigger 420 outputs 1 to enable input 444 of counter 440 for a duration approximately equal to the high phase of the clock signal, counter 440 counts the number of oscillations of the RO signal during the high phase of the clock signal. As a result, the count value of counter 440 provides a measurement of the high phase of the clock signal (i.e., the duration during which the clock signal is high within one clock cycle).

[0061] Counter 440 receives a target count value at target input 446, wherein the target count value indicates the count value of a target high phase corresponding to a target duty cycle (e.g., 50% duty cycle). Counter 440 then compares the count value from the RO signal with the target count value to determine whether the duty cycle of the clock signal is higher or lower than the target duty cycle, and outputs a signal at output 448 based on the comparison result, indicating whether to increase or decrease the duty cycle of the clock signal to compensate for duty cycle distortion.

[0062] The challenge of the RO-based timing measurement circuit 410 shown in Figure 4 is that, in order to achieve high resolution, the frequency of the ring oscillator 430 needs to be much higher than the frequency of the clock signal. As the frequency of the clock signal increases, it becomes increasingly difficult to achieve high resolution using the RO-based timing measurement circuit 410. For example, for a clock frequency of 2 GHz, the corresponding clock period is 500 ps, ​​while a ring oscillator frequency of 10 GHz, with a corresponding clock period of 100 ps, ​​can only provide 20% of the resolution of a clock cycle, which is quite low.

[0063] In order to solve the above problems, the present invention provides a timing measurement circuit that can use an adjustable delay circuit and / or a time-to-digital converter (TDC) to measure one or more timing parameters of a clock signal at high resolution, as further discussed below.

[0064] Figure 5 illustrates an exemplary timing measurement circuit 510 according to certain states. The timing measurement circuit 510 can be used to implement the timing measurement circuit 310 in Figure 3 (i.e., the timing measurement circuit 310 can be an instance of the timing measurement circuit 510).

[0065] The timing measurement circuit 510 has an input 512 and an output 514. The timing measurement circuit 510 is configured to receive a clock signal (labeled "clk") via the input 512. In one example, the input 512 may be coupled to a leaf node of a clock distribution network (e.g., clock distribution network 120). However, it should be understood that the scope of this invention is not limited to this example, and the input 512 may be coupled to another node (e.g., a node before clock distribution network 120, a node within clock distribution network 120, etc.). The timing measurement circuit 510 is configured to output a measurement signal at the output 514, as further discussed below. For an example in which the timing measurement circuit 510 is used to implement the timing measurement circuit 310 in FIG3, the input 512 corresponds to the input 312 in FIG3 and the output 514 corresponds to the output 314 in FIG3. In the example where input 512 of timing measurement circuit 510 is coupled to output 324 of duty cycle adjuster 320, the clock signal at input 512 of timing measurement circuit 510 can also be referred to as a duty cycle adjusted clock signal because duty cycle adjuster 320 adjusts the duty cycle of the clock signal received at input 322 of duty cycle adjuster 320. Input 512 of timing measurement circuit 510 can be coupled to output 324 of duty cycle adjuster 320 via signal path 125.

[0066] In this example, the timing measurement circuit 510 includes a measurement control circuit 520, a startup circuit 530, a delay circuit 550, a time-to-digital converter (TDC) 560, and an acquisition circuit 540. As further discussed below, the measurement control circuit 520 controls the operation of the timing measurement circuit 510.

[0067] The startup circuit 530 has an enable input 532, a clock input 534, a control input 536, and an output 538. The enable input 532 is coupled to a first output 523 of the measurement control circuit 520, the clock input 534 is coupled to an input 512 of the timing measurement circuit 510 to receive a clock signal, and the control input 536 is coupled to a second output 524 of the measurement control circuit 520. The startup circuit 530 is configured to receive an enable signal from the measurement control circuit 520 via the enable input 532 to initiate a measurement. In response to the enable signal, the startup circuit 530 initiates (i.e., outputs) the edge of the timing signal at the output 538 on the edge of the clock signal. The edge of the clock signal used to initiate the timing signal can be a rising edge or a falling edge. In some configurations, the startup circuit 530 selects the edge of a clock signal for starting a timing signal based on a first edge selection signal received from the measurement control circuit 520 via control input 536. For example, if the first edge selection signal has a first logic value, the startup circuit 530 can start the timing signal edge on the rising edge of the clock signal, and if the first edge selection signal has a second logic value, it can start the timing signal edge on the falling edge of the clock signal. The first logic value can be 1 and the second logic value can be zero, or vice versa. The edge of the timing signal can be either a rising edge or a falling edge.

[0068] The delay circuit 550 has a signal input 552, a control input 554, and an output 556. The signal input 552 is coupled to the output 538 of the startup circuit 530. The control input 554 is coupled to the third output 525 of the measurement control circuit 520. The delay circuit 550 is configured to receive the edge of a timing signal from the startup circuit 530 via the signal input 552, delay the edge of the timing signal by a certain time delay, and output the delayed edge of the timing signal at the output 556. In some states, the time delay of the delay circuit 550 is adjustable (i.e., programmable). In these states, the delay circuit 550 is configured to set the time delay of the delay circuit 550 based on a delay control signal received from the measurement control circuit 520 via the control input 554.

[0069] The acquisition circuit 540 has a clock input 542, a control input 544, and an output 546. The clock input 542 is coupled to the input 512 of the timing measurement circuit 510 to receive a clock signal, and the control input 544 is coupled to the fourth output 526 of the measurement control circuit 520. The acquisition circuit 540 is configured to generate an acquisition signal and output the acquisition signal at the output 546. In some states, the acquisition circuit 540 is configured to output an edge of the acquisition signal on the rising or falling edge of the clock signal based on a second edge selection signal received from the measurement control circuit 520 via the control input 544. For example, if the second edge selection signal has a first logic value, the acquisition circuit 540 may output an edge of the acquisition signal on the rising edge of the clock signal, and if the second edge selection signal has a second logic value, it may output an edge of the acquisition signal on the falling edge of the clock signal. The first logic value can be 1 and the second logic value can be zero, or vice versa. The edge of the captured signal can be a rising edge or a falling edge. In some states, the captured signal can be a clock signal, as discussed further below.

[0070] TDC 560 has a signal input 562, an acquisition input 564, and an output 566. The signal input 562 of TDC 560 is coupled to the output 556 of delay circuit 550 for receiving a delayed edge of a timing signal from delay circuit 550. The acquisition input 564 is coupled to the output 546 of acquisition circuit 540 for receiving an edge of an acquired signal from acquisition circuit 540. The output 566 of TDC 560 is coupled to a time measurement input 522 of measurement control circuit 520. TDC 560 is configured to measure the time delay (i.e., elapsed time) between the time when TDC 560 receives the edge of the timing signal at signal input 562 and the time when TDC 560 receives the edge of the acquired signal at acquisition input 564, and to output a digital time measurement signal at output 566 indicating the measured time delay. In this example, the time delay measurement can begin at the edge of the timing signal and stop at the edge of the capture signal.

[0071] In some configurations, the measurement control circuit 520 can measure various timing parameters of the clock signal by selecting the edge of the clock signal used to initiate the timing signal using a first edge selection signal and selecting the edge of the clock signal used to output the capture signal using a second edge selection signal. Figure 6 illustrates an example of this situation, showing an exemplary timing diagram of the clock signal. It should be understood that the clock signal may have a duty cycle different from the duty cycle shown in Figure 6.

[0072] For example, the measurement control circuit 520 can measure the high phase of the clock signal by selecting the rising edge 610 of the clock signal to initiate the timing signal edge and selecting the falling edge 620 of the clock signal to output the capture signal edge. As mentioned above, the high phase is the duration for which the clock signal is high (i.e., 1) within one clock cycle. In this example, the high phase begins at the rising edge 610 of the clock signal and ends at the falling edge 620 of the clock signal, as shown in FIG6. In this example, the high phase is approximately equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. This is because the high phase is approximately equal to the time delay from initiating the timing signal edge at the rising edge 610 of the clock signal to outputting the capture signal edge at the falling edge 620 of the clock signal, which is equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. Assuming the time delay of the delay circuit 550 is known, the measurement control circuit 520 can use the measurement time delay indicated by the digital time measurement signal from the TDC 560 and the known time delay of the delay circuit 550 to determine the high phase.

[0073] In another example, the measurement control circuit 520 can measure the low phase of the clock signal by selecting the falling edge 620 of the clock signal to initiate the timing signal edge and selecting the rising edge 630 of the clock signal to output the capture signal edge. The low phase is the duration for which the clock signal is low within one clock cycle. In this example, the low phase begins at the falling edge 620 of the clock signal and ends at the rising edge 630 of the clock signal, as shown in Figure 6. In this example, the low phase is equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. This is because the low phase is approximately equal to the time delay from initiating the timing signal edge at the falling edge 620 of the clock signal to outputting the capture signal edge at the rising edge 630 of the clock signal, which is equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. Assuming the time delay of the delay circuit 550 is known, the measurement control circuit 520 can use the measurement time delay indicated by the digital time measurement signal from the TDC 560 and the known time delay of the delay circuit 550 to determine the low phase.

[0074] In another example, the measurement control circuit 520 can measure the period of the clock signal by selecting a first rising edge 610 of the clock signal to initiate the timing signal edge and selecting a second rising edge 630 of the clock signal to output the capture signal edge. In this example, the period of the clock signal is approximately equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. This is because the clock period is approximately equal to the time delay from the time the timing signal edge is initiated at the first rising edge 610 of the clock signal to the time the capture signal edge is output at the second rising edge 630 of the clock signal, which is approximately equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. Assuming the time delay of the delay circuit 550 is known, the measurement control circuit 520 can determine the period of the clock signal using the measured time delay indicated by the digital time measurement signal from the TDC 560 and the known time delay of the delay circuit 550.

[0075] The measurement control circuit 520 can also measure the period of the clock signal by selecting the first falling edge 620 of the clock signal to activate the timing signal edge and selecting the second falling edge 640 of the clock signal to output the capture signal edge. In this example, the period of the clock signal is approximately equal to the sum of the time delay of the delay circuit 550 and the time delay measured by the TDC 560. Therefore, in this example, the timing measurement circuit 510 supports two methods for measuring the clock period (i.e., measuring the period between two consecutive rising edges of the clock signal or measuring the period between two consecutive falling edges of the clock signal). Either method can be used to measure the clock period, or both methods can be used to measure the clock period.

[0076] Therefore, the measurement control circuit 520 can measure any one of one or more timing parameters of the clock signal, including the high phase of the clock signal, the low phase of the clock signal, and the period of the clock signal. The measurement control circuit 520 selects the timing parameter to be measured by selecting a start clock edge (i.e., the edge of the clock signal used to start the timing signal) and correspondingly selecting a capture clock edge (i.e., the edge of the clock signal used to output the capture signal). For example, to measure the high phase, the measurement control circuit 520 selects the rising edge of the clock signal for the start clock edge and the falling edge of the clock signal for the capture clock edge. In some cases, the start clock edge may also be referred to as the first edge of the clock signal, and the capture clock edge may also be referred to as the second edge of the clock signal.

[0077] In some configurations, the measurement control circuit 520 is configured to generate a measurement signal based on timing parameters of one or more measurements of the clock signal, and outputs the measurement signal at a fifth output 527 of the output 514 coupled to the timing measurement circuit 510. In one example, the measurement signal may indicate one or more of the following: the high phase of the measured clock signal, the low phase of the measured clock signal, and the period of the measured clock signal.

[0078] In another example, the measurement control circuit 520 may determine the duty cycle of the clock signal based on two or more of the following: the high phase of the measured clock signal, the low phase of the measured clock signal, and the period of the measured clock signal. For example, the measurement control circuit 520 may determine the duty cycle of the clock signal based on the ratio of the high phase of the measured clock signal to the period of the measured clock signal. In this example, a ratio of 0.5 corresponds to 50% of the duty cycle. The measurement control circuit 520 may then output a measurement signal indicating the determined duty cycle.

[0079] In another example, the measurement control circuit 520 may determine the duty cycle adjustment of the clock signal based on one or more of the following: the high phase of the measured clock signal, the low phase of the measured clock signal, and the period of the measured clock signal. For example, the clock signal may have a target duty cycle of 50%. In this example, the measurement control circuit 520 may compare the high phase of the measured clock signal with the low phase of the measured clock signal to determine the duty cycle adjustment. For example, if the measured high phase is greater than the measured low phase (occurring when the duty cycle of the clock signal is greater than the target duty cycle of 50%), the measurement control circuit 520 may determine the duty cycle adjustment by decreasing the duty cycle of the clock signal to make the duty cycle of the clock signal closer to the target duty cycle of 50%. Alternatively, if the measured high phase is less than the measured low phase (occurring when the duty cycle of the clock signal is less than the target duty cycle), the measurement control circuit 520 may determine the duty cycle adjustment by increasing the duty cycle of the clock signal to make the duty cycle of the clock signal closer to the target duty cycle of 50%. The measurement control circuit 520 can then output a measurement signal indicating the determined duty cycle adjustment. It should be understood that this invention is not limited to this example, and the measurement control circuit 520 can determine the duty cycle adjustment in different ways based on timing parameters of one or more measurements of the clock signal.

[0080] It should be understood that in some embodiments, the measurement signal may include two or more signals. For example, the measurement signal may include a first signal indicating a duty cycle adjustment (i.e., indicating whether the duty cycle of the clock signal is being increased or decreased), and a second signal indicating the amount by which the duty cycle will be adjusted. In this example, the first and second signals may be output in series on one line or on two parallel lines.

[0081] The duty cycle control circuit 330 can receive a measurement signal from the timing measurement circuit 510, determine the duty cycle adjustment for the duty cycle adjuster 320 based on the measurement signal, and set the duty cycle adjustment of the duty cycle adjuster 320 based on the determined duty cycle adjustment (that is, generate a control signal to control the duty cycle adjustment of the duty cycle adjuster 320 based on the determined duty cycle adjustment, and input the control signal to the control input 326 of the duty cycle adjuster). As further discussed below, the duty cycle adjuster 320 can increase the duty cycle of the clock signal by increasing the high phase of the clock signal or decreasing the low phase of the clock signal, and the duty cycle adjuster 320 can decrease the duty cycle of the clock signal by decreasing the high phase of the clock signal or increasing the low phase of the clock signal.

[0082] For an instance where the measured high phase of the clock signal indicates that the measurement signal indicates a high phase, the duty cycle control circuit 330 can compare the measured high phase with a target high phase corresponding to a target duty cycle (e.g., 50% duty cycle). If the measured high phase is greater than the target high phase (occurring when the duty cycle of the clock signal is greater than the target duty cycle), the duty cycle control circuit 330 can determine a duty cycle adjustment for the duty cycle adjuster 320, which reduces the duty cycle of the clock signal coupled to the node of input 512 of the timing measurement circuit 510. Alternatively, if the measured high phase is less than the target high phase (occurring when the duty cycle of the clock signal is less than the target duty cycle), the duty cycle control circuit 330 can determine a duty cycle adjustment for the duty cycle adjuster 320, which increases the duty cycle of the clock signal coupled to the node of input 512 of the timing measurement circuit 510.

[0083] For an instance where the measured signal indicates a measured low phase of the clock signal, the duty cycle control circuit 330 can compare the measured low phase with a target low phase corresponding to a target duty cycle (e.g., 50% duty cycle). If the measured low phase is less than the target low phase (occurring when the clock signal's duty cycle is less than the target duty cycle), the duty cycle control circuit 330 can determine a duty cycle adjustment for the duty cycle adjuster 320, which increases the duty cycle of the clock signal coupled to the node of input 512 of the timing measurement circuit 510. Alternatively, if the measured low phase is less than the target low phase (occurring when the clock signal's duty cycle is greater than the target duty cycle), the duty cycle control circuit 330 can determine a duty cycle adjustment for the duty cycle adjuster 320, which decreases the duty cycle of the clock signal coupled to the node of input 512 of the timing measurement circuit 510.

[0084] For instances where the measurement signal indicates the duty cycle adjustment based on one or more measured timing parameters of the clock signal, the duty cycle control circuit 330 sets the duty cycle adjustment of the duty cycle adjuster 320 based on the indicated duty cycle adjustment.

[0085] For an instance where the measurement signal indicates both the high phase and the low phase of the clock signal being measured, and the target duty cycle is 50%, the duty cycle control circuit 330 can compare the measured high phase and the measured low phase of the clock signal to determine a duty cycle adjustment. For example, if the measured high phase is greater than the measured low phase (occurring when the clock signal's duty cycle is greater than 50% of the target duty cycle), the duty cycle control circuit 330 can determine a duty cycle adjustment that reduces the duty cycle of the clock signal coupled to the node at input 512 of the timing measurement circuit 510. Alternatively, if the measured high phase is less than the measured low phase (occurring when the clock signal's duty cycle is less than the target duty cycle), the duty cycle control circuit 330 can determine a duty cycle adjustment that increases the duty cycle of the clock signal coupled to the node at input 512 of the timing measurement circuit 510.

[0086] In an example where the measurement signal indicates the duty cycle of the clock signal, the duty cycle control circuit 330 can compare the indicated duty cycle with a target duty cycle to determine a duty cycle adjustment. For example, if the indicated duty cycle is greater than the target duty cycle, the duty cycle control circuit 330 can determine a duty cycle adjustment that reduces the duty cycle of the clock signal coupled to the node of input 512 of the timing measurement circuit 510. If the indicated duty cycle is less than the target duty cycle, the duty cycle control circuit 330 can determine a duty cycle adjustment that increases the duty cycle of the clock signal coupled to the node of input 512 of the timing measurement circuit 510.

[0087] FIG7 illustrates an exemplary embodiment of a startup circuit 530 and a capture circuit 540 according to certain states.

[0088] In this example, the startup circuit 530 includes an inverter 710, a multiplexer 720, a first flip-flop 730, a second flip-flop 740, and a startup flip-flop 750. The multiplexer 720 has a first input 722, a second input 724, a selection input 726, and an output 728. The first input 722 is coupled to the clock input 534 of the startup circuit 530, while the selection input 726 is coupled to the control input 536 of the startup circuit 530. The inverter 710 is coupled between the clock input 534 of the startup circuit 530 and the second input 724 of the multiplexer 720. Therefore, the first input 722 of the multiplexer 720 receives a clock signal, and the second input 724 of the multiplexer 720 receives an inverted clock signal. Multiplexer 720 is configured to select either a clock signal at first input 722 or an inverted clock signal at second input 724 based on a control signal at selection input 726, and output the selected clock signal and inverted clock signal at output 728. The selected clock signal and inverted clock signal at output 728 are referred to as the start clock signal (denoted as "clk_l") in the following discussion. As further discussed below, multiplexer 720 allows measurement control circuitry 520 to select either a rising clock edge or a falling clock edge to initiate the timing signal.

[0089] The first flip-flop 730 has a signal input 732 coupled to the enable input 532 of the startup circuit 530, a clock input 734 coupled to the clock input 534 of the startup circuit 530, and an output 736. The second flip-flop 740 has a signal input 742 coupled to the output 736 of the first flip-flop 730, a clock input 744 coupled to the output 728 of the multiplexer 720, and an output 746. The startup flip-flop 750 has a signal input 752 coupled to the output 746 of the second flip-flop 740, a clock input 754 coupled to the output 728 of the multiplexer 720, and an output 756 coupled to the output 538 of the startup circuit 530.

[0090] In this example, the startup circuit 530 uses an enable signal from the measurement control circuit 520 to provide a timing signal, and, depending on whether the multiplexer 720 selects a clock signal or an inverted clock signal, initiates the timing signal on the rising or falling edge of the clock signal. In one example, the enable signal from the measurement control circuit 520 is set high to initiate a duty cycle measurement. In this example, the rising edge of the enable signal propagates via the first flip-flop 730 and the second flip-flop 740 to the signal input 752 of the startup flip-flop 750, where the first flip-flop 730 is timed by the clock signal, and the second flip-flop 740 is timed by the startup clock signal (i.e., one of the clock signal and the inverted clock signal).

[0091] The start trigger 750 is configured to start the rising edge of the enable signal on the rising edge of the start clock signal (labeled "clk_l"). In this example, the rising edge of the enable signal provides the rising edge of the timing signal (labeled "din"). When the clock signal is selected by the multiplexer 720, the start trigger 750 starts the edge of the timing signal on the rising edge of the clock signal (i.e., the rising edge of the enable signal in this example). When the inverting clock signal is selected by the multiplexer 720, the start trigger 750 starts the edge of the timing signal on the falling edge of the clock signal (i.e., the rising edge of the enable signal in this example).

[0092] Therefore, in this example, the start circuit 530 responds to the edge of the timing signal received from the measurement control circuit 520 to start the timing signal, and depending on whether the multiplexer 720 selects the clock signal as an inverted clock signal, starts the timing signal on the rising or falling edge of the clock signal.

[0093] In the example of FIG. 7, the enable signal propagates via the first flip-flop 730 and the second flip-flop 740 to reach the signal input 752 of the start flip-flop 750. In this example, the first flip-flop 730 and the second flip-flop 740 can be used to adjust the timing of the rising edge of the enable signal to ensure that the rising edge of the enable signal satisfies the timing (e.g., setup time and / or hold time) at the start flip-flop 750. It should be understood that the scope of this invention is not limited to this example, and in some embodiments (e.g., embodiments where the timing of the enable signal is not the issue), one or both of the first flip-flop 730 and the second flip-flop 740 may be omitted.

[0094] In the example of FIG. 7, the acquisition circuit 540 includes a first inverter 755, a multiplexer 760, a flip-flop 770, a second inverter 780, and a clock gate circuit 790 (also referred to as a clock gate unit). The multiplexer 760 has a first input 762, a second input 764, a selection input 766, and an output 768. The first input 762 is coupled to the clock input 542 of the acquisition circuit 540, while the selection input 766 is coupled to the control input 544 of the acquisition circuit 540. The first inverter 755 is coupled between the clock input 542 of the acquisition circuit 540 and the second input 764 of the multiplexer 760. Therefore, the first input 762 of the multiplexer 760 receives a clock signal, and the second input 764 of the multiplexer 760 receives an inverted clock signal. Multiplexer 760 is configured to select either a clock signal at first input 762 or an inverted clock signal at second input 764 based on a second edge selection signal at selection input 766, and output the selected clock signal and inverted clock signal at output 768. The selected clock signal and inverted clock signal at output 768 are referred to as the captured clock signal in the following discussion. As further discussed below, multiplexer 760 allows measurement control circuitry 520 to select either a rising edge or a falling edge to output the edge of the captured clock signal.

[0095] The flip-flop 770 has a signal input 772 coupled to the output 538 of the startup circuit 530, a clock input 774 coupled to the output 768 of the multiplexer 760, and an output 776. The input of the second inverter 780 is coupled to the output 776 of the flip-flop 770.

[0096] The clock gate circuit 790 has an enable input 792 coupled to the output of the second inverter 780, a signal input 794 coupled to the output 768 of the multiplexer 760, and an output 796 coupled to the fetch input 564 of the TDC 560. The clock gate circuit 790 is configured to pass or gate a fetch clock signal from the multiplexer 760 (i.e., a clock signal or an inverted clock signal) based on the logic value at the enable input 792. For example, the clock gate circuit 790 may pass the fetch clock signal when the enable input 792 is high and gate (i.e., block) the fetch signal when the enable input 792 is low, or vice versa in an alternative implementation. The fetch clock signal following the clock gate circuit 790 is labeled "clk_c" in FIG. 7.

[0097] In this example, the acquisition circuit 540 uses the acquisition clock signal output at output 546 to provide the acquisition signal discussed above. The edge of the clock signal used to output the acquisition clock signal depends on whether the multiplexer 760 selects a clock signal or an inverted clock signal. For example, when the multiplexer 760 selects a clock signal, the edge of the acquisition clock signal can be output on the rising edge of the clock signal; and when the multiplexer 760 selects an inverted clock signal, the edge of the acquisition clock signal can be output on the falling edge of the clock signal.

[0098] Flip-flop 770 and second inverter 780 are used to gate the clock signal after the edge of the clock signal is captured. This is done so that TDC 560 maintains a time delay measurement at output 566 of TDC 560 after the edge of the clock signal is captured.

[0099] The exemplary startup circuit 530 and capture circuit 540 shown in FIG7 can be used to measure any of the following: the high phase of the clock signal, the low phase of the clock signal, and the period of the clock signal. In this regard, FIG8A is a timing diagram illustrating an example of measuring the high phase of a clock signal according to certain conditions. FIG8A illustrates examples of the following: clock signal (labeled "clk"), startup clock signal (labeled "clk_l"), timing signal (labeled "din"), signal at enable input 792 of clock gate circuit 790 (labeled "clk_c_en"), capture clock signal at output of clock gate circuit 790 (labeled "clk_c"), and output of TDC 560 (labeled "tdc_q").

[0100] In the example of Figure 8A, the multiplexer 720 in the startup circuit 530 selects the clock signal, while the multiplexer 760 in the acquisition circuit 540 selects the inverted clock signal. Therefore, in this example, the startup clock signal is provided by the clock signal, while the acquisition clock signal is provided by the inverted clock signal. In this example, the startup flip-flop 750 starts the timing signal (labeled "din") at the rising edge 814 on the rising edge 812 of the startup clock signal (labeled "clk_l"), which corresponds to the rising edge 810 of the clock signal. In this example, the startup flip-flop 750 is a rising edge triggered flip-flop (also known as a positive edge triggered flip-flop). The rising edge 814 of the timing signal propagates through the delay circuit 550 and enters the TDC 560.

[0101] The acquisition circuit 540 outputs the rising edge 816 of the acquisition clock signal on the falling edge 818 of the clock signal. Note that in this example, the acquisition circuit 540 generates the acquisition clock signal (labeled "clk_c"). The rising edge 816 of the acquisition clock signal causes the TDC 560 to acquire the time delay measurement of the timing signal in the TDC 560 and output the corresponding digital time measurement signal (labeled "tdc_q") to the measurement control circuit 520. In this example, the TDC 560 is rising edge triggered (i.e., the time delay measurement is acquired on the rising edge of the acquisition clock signal).

[0102] After the rising edge 816 of the captured clock signal, the signal at the enable input 792 of the clock gate circuit 790 (labeled "clk_c_en") goes low. This causes the clock gate circuit 790 to gate the captured clock signal, and the TDC 560 maintains the time delay measurement. The TDC 560 can maintain the time delay measurement until the measurement control circuit 520 resets the startup circuit 530 and the capture circuit 540 (e.g., by outputting zero to the enable input 532 of the startup circuit 530).

[0103] Figure 8B is a timing diagram illustrating an example of low-phase measurement based on a certain type of clock signal. In the example of Figure 8B, the multiplexer 720 in the start circuit 530 selects an inverted clock signal, while the multiplexer 760 in the capture circuit 540 selects a clock signal. Therefore, in this example, the start clock signal is provided by the inverted clock signal, while the capture clock signal is provided by the clock signal. In this example, the start trigger 750 starts the rising edge 824 of the timing signal (labeled "din") on the rising edge 822 of the start clock signal (labeled "clk_l"), which corresponds to the falling edge 820 of the clock signal. The rising edge 824 of the timing signal propagates through the delay circuit 550 and enters the TDC 560.

[0104] The acquisition circuit 540 outputs the rising edge 826 of the acquisition clock signal on the rising edge 828 of the clock signal. Note that in this example, the acquisition circuit 540 generates the acquisition clock signal (labeled "clk_c"). The rising edge 826 of the acquisition clock signal causes the TDC 560 to acquire the time delay measurement of the timing signal in the TDC 560 and output the corresponding digital time measurement signal (labeled "tdc_q") to the measurement control circuit 520.

[0105] After the rising edge 826 of the captured clock signal, the signal at the enable input 792 of the clock gate circuit 790 (labeled "clk_c_en") goes low. This causes the clock gate circuit 790 to gate the captured clock signal, and the TDC 560 maintains the time delay measurement. The TDC 560 can maintain the time delay measurement until the measurement control circuit 520 resets the startup circuit 530 and the capture circuit 540 (e.g., by outputting zero to the enable input 532 of the startup circuit 530).

[0106] Figure 8C is a timing diagram illustrating an example of clock cycle measurement according to certain conditions. In the example of Figure 8C, multiplexer 720 in startup circuit 530 selects the clock signal, and multiplexer 760 in capture circuit 540 selects the clock signal. Therefore, in this example, the startup clock signal is provided by the clock signal, and the capture clock signal is provided by the clock signal. In this example, startup trigger 750 starts the rising edge 834 of timing signal (labeled "din") on the rising edge 832 of startup clock signal (labeled "clk_l"), which corresponds to the rising edge 830 of clock signal. The rising edge 834 of timing signal propagates through delay circuit 550 and enters TDC 560.

[0107] The acquisition circuit 540 outputs the rising edge 836 of the acquisition clock signal on the rising edge 838 of the clock signal. Note that in this example, the acquisition circuit 540 generates the acquisition clock signal (labeled "clk_c"). The rising edge 836 of the acquisition clock signal causes the TDC 560 to acquire the time delay measurement of the timing signal in the TDC 560 and output the corresponding digital time measurement signal (labeled "tdc_q") to the measurement control circuit 520.

[0108] After the rising edge 836 of the captured clock signal, the signal at the enable input 792 of the clock gate circuit 790 (labeled "clk_c_en") goes low. This causes the clock gate circuit 790 to gate the captured clock signal, and the TDC 560 maintains the time delay measurement. The TDC 560 can maintain the time delay measurement until the measurement control circuit 520 resets the startup circuit 530 and the capture circuit 540 (e.g., by outputting zero to the enable input 532 of the startup circuit 530).

[0109] Figure 8D is a timing diagram illustrating another example of clock cycle measurement according to certain conditions. In the example of Figure 8D, the multiplexer 720 in the start circuit 530 selects an inverted clock signal, and the multiplexer 760 in the capture circuit 540 selects an inverted clock signal. Therefore, in this example, the start clock signal is provided by the inverted clock signal, and the capture clock signal is provided by the inverted clock signal. In this example, the start trigger 750 starts the rising edge 844 of the timing signal (labeled "din") on the rising edge 842 of the start clock signal (labeled "clk_l"), which corresponds to the falling edge 840 of the clock signal. The rising edge 844 of the timing signal propagates through the delay circuit 550 and enters the TDC 560.

[0110] The acquisition circuit 540 outputs the rising edge 846 of the acquisition clock signal on the falling edge 848 of the clock signal. Note that in this example, the acquisition circuit 540 generates the acquisition clock signal (labeled "clk_c"). The rising edge 846 of the acquisition clock signal causes the TDC 560 to acquire the time delay measurement of the timing signal in the TDC 560 and output the corresponding digital time measurement signal (labeled "tdc_q") to the measurement control circuit 520.

[0111] After the rising edge 846 of the captured clock signal, the signal at the enable input 792 of the clock gate circuit 790 (labeled "clk_c_en") goes low. This causes the clock gate circuit 790 to gate the captured clock signal, and the TDC 560 maintains the time delay measurement. The TDC 560 can maintain the time delay measurement until the measurement control circuit 520 resets the startup circuit 530 and the capture circuit 540 (e.g., by outputting zero to the enable input 532 of the startup circuit 530).

[0112] Figure 9 illustrates an exemplary implementation of a TDC 560 according to certain configurations. In this example, the TDC 560 is configured to receive a timing signal at signal input 562 and measure the time delay between the time when the timing signal is received at signal input 562 of the TDC 560 and the time when the capture clock signal is received at capture input 564 of the TDC 560. In this example, the digital time measurement signal (labeled "tdc_q") includes multiple bits (labeled "tdc_q[0]" to "tdc_q[k]") indicating the measured time delay.

[0113] In the example of Figure 9, the TDC 560 includes a delay line 915 and a plurality of flip-flops 930-1 to 930-n coupled to the delay line 915. The flip-flops 930-1 to 930-n are timed by a captured clock signal received at the captured input 564. The delay line 915 has an input 918 coupled to a signal input 562 of the TDC 560 and a plurality of nodes 922-1 to 922-n, each node corresponding to a different delay along the delay line 915. In the example of Figure 9, the delay line 915 includes a plurality of series-coupled delay buffers 920-1 to 920-n, each of which corresponds to a corresponding node among the nodes 922-1 to 922-n. In operation, the timing signal received by the TDC 560 propagates via the delay line 915. The outputs of each delay buffer 920-1 to 920-n provide different delayed versions of the timing signal at the corresponding nodes 922-1 to 922-n.

[0114] Each of the flip-flops 930-1 to 930-n has signal inputs 932-1 to 932-n, outputs 934-1 to 934-n, and clock inputs 936-1 to 936-n. The clock inputs 936-1 to 936-n of each flip-flop 930-1 to 930-n are coupled to a capture input 564 and configured to receive a capture clock signal. Each flip-flop 930-1 to 930-n is configured to latch the bit value at the corresponding signal input 932-1 to 932-n on the edge of the capture clock signal and output the latched bit value at the corresponding output 934-1 to 934-n. For instances where flip-flops 930-1 to 930-n are implemented using rising-edge triggered flip-flops, the edge of the capture clock signal can be a rising edge. Note that in the examples shown in Figures 8A to 8D, the edge of the capture clock signal is a rising edge. However, it should be understood that the content of this case is not limited to this example.

[0115] The signal inputs 932-1 to 932-n of each flip-flop 930-1 to 930-n are coupled to a corresponding node among nodes 922-1 to 922-n on delay line 915. Thus, the signal inputs 932-1 to 932-n of each flip-flop 930-1 to 930-n receive different delayed versions of the timing signal. In the example of Figure 9, the signal inputs 932-1 to 932-n of each flip-flop 930-1 to 930-n are coupled to the output of a corresponding delay buffer among delay buffers 920-1 to 920-n. The outputs 934-1 to 934-n of each flip-flop 930-1 to 930-n provide a corresponding bit (labeled "tdc_q[0]" to "tdc_q[k]") of the digital time measurement signal (labeled "tdc_q"). In this example, each flip-flop 930-1 to 930-n latches the bit value at the corresponding node 922-1 to 922-n on the edge of the fetch clock signal (e.g., the rising edge of the fetch clock signal) and outputs the latched bit value as the bit value of the corresponding bit of the digital time measurement signal (labeled "tdc_q").

[0116] In this example, the time delay of the timing signal is indicated by the number of 1 bits (labeled "tdc_q[0]" to "tdc_q[k]") in the digital time measurement signal. The more 1 bits there are, the longer the time delay. This is because there are more 1 bits as the timing signal propagates further along the delay line 915 (which occurs when the time delay is longer).

[0117] In this example, the TDC 560 measures the time delay of the timing signal with a time increment equal to the delay of a delay buffer, which provides a much higher resolution than that provided by the RO-based timing measurement circuit 410. This is because the ring oscillator 430 includes multiple delay buffers coupled in the loop, where the RO signal needs to propagate twice through the multiple delay buffers to generate each oscillation of the RO signal. As a result, the time increment in the RO-based timing measurement circuit 410 is equal to twice the sum of the delays of the multiple delay buffers in the ring oscillator 430. Therefore, the time increment used by the RO-based timing measurement circuit 410 to measure the time delay is much larger than that of the TDC 560, resulting in a much lower resolution for the RO-based timing measurement circuit 410.

[0118] It should be understood that the timing measurement circuit 510 is not limited to the examples shown in Figures 5 and 7. For example, in some embodiments, the delay circuit 550 may have a fixed time delay or the delay circuit 550 may be omitted (e.g., for the case where the TDC 560 has a time measurement range spanning clock cycles). In embodiments where the delay circuit 550 is omitted, the signal input 562 of the TDC 560 may be directly coupled to the output 538 of the startup circuit 530.

[0119] Figure 10 illustrates another exemplary embodiment of the TDC 560 according to certain configurations. In this example, the TDC 560 includes a flip-flop 1010 having a signal input 1012, a clock input 1014, and an output 1016. The signal input 1012 is coupled to a signal input 562 of the TDC 560, the clock input 1014 is coupled to a capture input 564 of the TDC 560, and the output 1016 is coupled to an output 566 of the TDC 560.

[0120] In this example, flip-flop 1010 is timed by an acquisition clock signal received at acquisition input 564 of TDC 560. Flip-flop 1010 is configured to latch a logic value at signal input 1012 on the edge (e.g., rising edge) of the acquisition clock signal and output the latched logic value to measurement control circuitry 520. Therefore, in this example, the latched logic value provides a digital time measurement signal output by TDC 560.

[0121] In this example, the latched logic value output by flip-flop 1010 indicates whether the edge of the timing signal reaches TDC 560 when the edge of the capture clock signal is received at clock input 1014. For example, if the edge of the timing signal is a rising edge (as shown in the examples in Figures 8A to 8D), the latched logic value is 1 if the edge of the timing signal arrives before the edge of the capture clock signal, and zero if the edge of the timing signal arrives after the edge of the capture clock signal. Since the edge of the timing signal arrives at TDC 560 after the time delay of the delay circuit 550, the latched value output by flip-flop 1010 indicates whether the time delay of the delay circuit 550 is less than or greater than the time delay between the edge of the start clock and the edge of the capture clock. As further discussed below, this information can be used to measure the high phase, low phase, or period of the clock signal by adjusting the time delay sequence of the delay circuit 550 to different delay settings and observing the latched logic value for each delay setting.

[0122] To measure the high phase of the clock signal in this example, the measurement control circuit 520 can use a first edge selection signal to select a rising edge for the start clock edge and a second edge selection signal to select a falling edge for the capture clock edge. Subsequently, the measurement control circuit 520 can use a delay control signal to sequentially adjust the time delay of the delay circuit 550 to different delay settings. For each delay setting, the measurement control circuit 520 initiates a measurement and receives a latched logic value from the TDC 560, which indicates whether the time delay of the delay circuit 550 is less than or greater than the high phase of the clock signal. For example, for an example where the timing signal edge is a rising edge, the latched value is 0 when the time delay of the delay circuit 550 is greater than the high phase, and 1 when the time delay of the delay circuit 550 is less than the high phase. In this example, the measurement control circuit 520 can determine the high phase by determining the highest delay setting where the latched value is 1 and the lowest delay setting where the latched value is 0. In this scenario, the high phase of the clock signal can be between the time delay corresponding to the highest delay setting with a latched value of 1 and the time delay corresponding to the lowest delay setting with a latched value of 0. The measurement control circuit 520 can then estimate that the high phase equals one of the two time delays. Alternatively, the measurement control circuit 520 can estimate that the high phase equals the time delay between the two time delays. Therefore, in this example, the measurement control circuit 520 measures the high phase by sequentially adjusting the time delay order of the delay circuit 550 to different delay settings and observing the latched logic value for each delay setting to determine a time delay approximately equal to the high phase.

[0123] In this example, the low phase and clock period can each be measured in a manner similar to the high phase described above. For low phase measurement, the measurement control circuit 520 can use a first edge selection signal to select a falling edge for the start clock edge and a second edge selection signal to select a rising edge for the capture clock edge. For clock period measurement, the measurement control circuit 520 can select a rising edge for both the start clock edge and the capture clock edge, or select a falling edge for both the start clock edge and the capture clock edge.

[0124] FIG11 illustrates an exemplary embodiment of a delay circuit 550 according to certain forms of the present invention. In this example, the delay circuit 550 includes a plurality of delay devices 1110-1 to 1110-N connected in series to form a delay line (e.g., a delay chain). Each of the delay devices 1110-1 to 1110-N has a corresponding input (labeled "in") and a corresponding output (labeled "out"). Each of the delay devices 1110-1 to 1110-N may have substantially the same delay τ. The input of delay device 1110-1 is coupled to a signal input 552 of the delay circuit 550. The output of each of the delay devices 1110-1 to 1110-(N-1) is coupled to the input of the next delay device 1110-2 to 1110-N in the delay line. Each of the delay devices 1110-1 to 1110-N may also be referred to as a delay stage, delay element, delay unit, delay buffer, or other terms.

[0125] The delay circuit 550 also includes a multiplexer 1130 having multiple inputs 1132-1 to 1132-N, an output 1134, and a selection input 1136. Each of the inputs 1132-1 to 1132-N of the multiplexer 1130 is coupled to the output of a corresponding delay device among the delay devices 1110-1 to 1110-N in the delay line. As a result, each of the inputs 1132-1 to 1132-N is coupled to a different point on the delay line corresponding to a different time delay. The output 1134 of the multiplexer 1130 is coupled to the output 556 of the delay circuit 550, and the selection input 1136 of the multiplexer 1130 is coupled to the control input 554 of the delay circuit 550.

[0126] The multiplexer 1130 is configured to receive a delay control signal from the measurement control circuit 520 at the selection input 1136, and select one of the inputs 1132-1 to 1132-N of the multiplexer 1130 based on the received delay control signal, wherein one of the selected inputs 1132-1 to 1132-N is coupled to the output 1134 of the multiplexer 1130. Because each of the inputs 1132-1 to 1132-N is coupled to a different point on the delay line corresponding to a different time delay, the delay control signal controls which input of the multiplexer 1130 to select to control the time delay of the delay circuit 550.

[0127] It should be understood that the delay circuit 550 is not limited to the exemplary embodiment shown in FIG11. Generally, the delay circuit 550 may include a plurality of delay devices and circuits for selectively switching the delay devices into and out of the delay path between the signal input 552 and the output 556 of the delay circuit 550 based on a delay control signal. The circuit may include a switch, one or more multiplexers, logic gates, or any combination thereof.

[0128] FIG12 illustrates an exemplary embodiment of a duty cycle adjuster 1220 according to certain configurations. The duty cycle adjuster 1220 can be used to implement the duty cycle adjuster 320 in FIG3 (i.e., the duty cycle adjuster 320 can be an instance of the duty cycle adjuster 320). The duty cycle adjuster 1220 has a signal input 1222, a first control input 1226, a second control input 1228, and an output 1224. For the example of the duty cycle adjuster 1220 implementing the duty cycle adjuster 320 in FIG3, the signal input 1222 corresponds to the signal input 322, the output 1224 corresponds to the output 324, and the first control input 1226 and the second control input 1228 correspond to the control input 326 (i.e., the control input 326 includes two inputs in this example).

[0129] In this example, the duty cycle adjuster 1220 includes a first inverter 1235, a first multiplexer 1240, a high-phase extender 1250, a second inverter 1265, and a second multiplexer 1270. The first multiplexer 1240 has a first input 1242, a second input 1244, a selection input 1246, and an output 1248. The first input 1242 of the first multiplexer 1240 is coupled to the signal input 1222 of the duty cycle adjuster 1220, and the selection input 1246 of the first multiplexer 1240 is coupled to the first control input 1226. The first inverter 1235 is coupled between the signal input 1222 of the duty cycle adjuster 1220 and the second input 1244 of the first multiplexer 1240. As used herein, "inverter" encompasses any circuit implementation capable of performing an inverting function, such as using an inverting gate, a complementary metal-oxide-semiconductor (CMOS) inverter, or any logic gate or combination of logic gates capable of performing an inverting function.

[0130] The high-phase extender 1250 has a signal input 1252, a control input 1254, and an output 1256. The signal input 1252 of the high-phase extender 1250 is coupled to the output 1248 of the first multiplexer 1240, and the control input 1254 of the high-phase extender 1250 is coupled to a second control input 1228 of the duty cycle adjuster 1220. As further discussed below, the high-phase extender 1250 is configured to extend the high phase of the clock signal by an adjustable amount based on the phase control signal received at the control input 1254.

[0131] The second multiplexer 1270 has a first input 1272, a second input 1274, a selection input 1276, and an output 1278. The first input 1272 of the second multiplexer 1270 is coupled to the output 1256 of the high-phase expander 1250, and the selection input 1276 of the second multiplexer 1270 is coupled to a first control input 1226. A second inverter 1265 is coupled between the output 1256 of the high-phase expander 1250 and the second input 1274 of the second multiplexer 1270. The output 1278 of the second multiplexer 1270 is coupled to the output 1224.

[0132] The duty cycle adjuster 1220 is configured to receive a clock signal at signal input 1222 (e.g., from clock generator 115), adjust the duty cycle of the clock signal, and output the duty cycle adjusted clock signal at output 1224. The duty cycle adjuster 1220 can increase or decrease the duty cycle of the clock signal. Therefore, the duty cycle adjuster 1220 supports duty cycle adjustment in any direction.

[0133] To increase the duty cycle of the clock signal input to the duty cycle adjuster 1220, the duty cycle control circuit 330 (shown in FIG. 3) causes each of the first multiplexer 1240 and the second multiplexer 1270 to select a corresponding first input 1242 and 1272 via the first control input 1226. In this case, the first multiplexer 1240 passes the clock signal to the signal input 1252 of the high-phase extender 1250. The high-phase extender 1250 then extends the high phase of the clock signal by an adjustable amount based on the phase control signal received from the duty cycle control circuit 330 via the second control input 1228. By extending the high phase of the clock signal, the high-phase extender 1250 increases the duty cycle of the clock signal. The greater the high-phase extension of the high-phase extender 1250, the greater the increase in the duty cycle of the clock signal. In this example, the second multiplexer 1270 passes the high-phase extended clock signal to the output 1224 of the duty cycle adjuster 1220.

[0134] To reduce the duty cycle of the clock signal input to the duty cycle adjuster 1220, the duty cycle control circuit 330 (shown in FIG. 3) causes each of the first multiplexer 1240 and the second multiplexer 1270 to select a corresponding second input 1244 and 1274 via the first control input 1226. In this case, the first inverter 1235 inverts the clock signal, and the first multiplexer 1240 passes the inverted clock signal to the signal input 1252 of the high-phase extender 1250. The high-phase extender 1250 then extends the high phase of the inverted clock signal by an adjustable amount based on the phase control signal received from the duty cycle control circuit 330 via the second control input 1228. In this case, extending the high phase of the inverted clock signal is equivalent to extending the low phase of the clock signal, which reduces the duty cycle of the clock signal. The greater the amount by which the high-phase extender 1250 extends the high phase of the inverted clock signal, the greater the reduction in the duty cycle of the clock signal. In this example, the second inverter 1265 inverts the high-phase extended inverted clock signal to obtain a clock signal, and the second multiplexer 1270 transmits the clock signal from the second inverter 1265 to the output 1224 of the duty cycle adjuster 1220.

[0135] Therefore, the duty cycle adjuster 1220 can increase or decrease the duty cycle of the clock signal. To increase the duty cycle of the clock signal, the high-phase extender 1250 extends the high phase of the clock signal. To decrease the duty cycle of the clock signal, the first inverter 1235 inverts the clock signal, the high-phase extender 1250 extends the high phase of the inverted clock signal (which is equivalent to extending the low phase of the clock signal), and the second inverter 1265 inverts the inverted clock signal back to the clock signal. For applications that only use high-phase extension, the multiplexers 1240 and 1270 and the inverters 1235 and 1265 can be omitted.

[0136] FIG13 illustrates an exemplary embodiment of a high-phase expander 1250 according to certain types. In this example, the high-phase expander 1250 includes an OR gate 1330 and a delay circuit 1320. It should be understood that the OR gate 1330 can be implemented using a combination of two or more gates to produce equivalent logic functionality. For example, in some embodiments, the OR gate 1330 may include an inverse OR gate and an inverter.

[0137] The OR gate 1330 has a first input 1332, a second input 1334, and an output 1336. The first input 1332 is coupled to the signal input 1252 of the high-phase expander 1250, and the output 1336 is coupled to the output 1256 of the high-phase expander 1250. The delay circuit 1320 has a signal input 1322, a control input 1324, and an output 1326. The signal input 1322 of the delay circuit 1320 is coupled to the signal input 1252 of the high-phase expander 1250, the control input 1324 of the delay circuit 1320 is coupled to the control input 1254 of the high-phase expander 1250, and the output 1326 of the delay circuit 1320 is coupled to the second input 1334 of the OR gate 1330.

[0138] The delay circuit 1320 is configured to delay the clock signal by an adjustable time delay based on a delay control signal received via control input 1254. The resulting delayed clock signal is input to the second input 1334 of the OR gate 1330. The OR gate 1330 performs an OR function on the clock signal at the first input 1332 and the delayed clock signal at the second input 1334 to generate a clock signal at output 1336. Compared to the clock signal at signal input 1252, the clock signal at output 1336 has an extended high phase, wherein the high phase extension is controlled by the time delay of the delay circuit 1320. The greater the time delay of the delay circuit 1320, the greater the high phase extension of the clock signal at output 1336. Therefore, in this example, the duty cycle control circuit 330 (as shown in FIG. 3) controls the high phase extension of the clock signal at output 1256 of the high phase extender 1250 by controlling the time delay of the delay circuit 1320. In this example, the phase control signal discussed above corresponds to the delay control signal input to the control input 1324 of the delay circuit 1320.

[0139] In this example, the time delay of the delay circuit 1320 may be limited by the high phase of the clock signal at the signal input 1252 (i.e., the time delay of the delay circuit 1320 ≦ the high phase of the input). This is because increasing the time delay beyond the high phase of the input will cause a clock excitation trajectory. Thus, FIG14A illustrates an example of the clock signal at the signal input 1252 (labeled "hpe_in") and the clock signal at the output 1256 (labeled "hpe_out") when the time delay is less than the high phase of the clock signal at the signal input 1252, and FIG14B illustrates an example of the clock signal at the signal input 1252 (labeled "hpe_in") and the clock signal at the output 1256 (labeled "hpe_out") when the time delay is greater than the high phase of the clock signal at the signal input 1252. As shown in Figure 14B, causing the time delay of the delay circuit 1320 to be greater than the high phase of the clock signal at the signal input 1252 may result in clock excitation trajectory 1410. Therefore, an exemplary implementation of the high phase extender 1250 can be limited to extending the high phase of the output clock signal by an amount equal to or less than the high phase of the input clock signal for a maximum output high phase equal to twice the input high phase (i.e., the time delay of the delay circuit 1320 ≤ input high phase), and thus may not be suitable for use cases requiring a larger high phase extension.

[0140] To address this problem, FIG15A illustrates an exemplary embodiment of a delay circuit 1320 that provides a greater high phase extension range according to certain specifications. In this example, the delay circuit 1320 includes a plurality of delay devices 1510-1 to 1510-m coupled in series to form a delay line. The delay devices 1510-1 to 1510-m may also be referred to as delay segments or other terms. Each of the delay devices 1510-1 to 1510-m has a corresponding first signal input 1512-1 to 1512-m, a corresponding second signal input 1514-1 to 1514-m, a corresponding control input 1516-1 to 1516-m, and a corresponding delay output 1518-1 to 1518-m. The first signal input 1512-1 of the delay device 1510-1 is coupled to the signal input 1252 of the high phase extender 1250. In the example of Figure 15A, the second signal input 1514-1 of delay device 1510-1 is coupled to ground. The delay outputs 1518-1 to 1518-(m-1) of each of delay devices 1510-1 to 1510-(m-1) are coupled to the second signal inputs 1514-2 to 1514-m of the next delay devices 1510-2 to 1510-m in the delay line, and as shown in Figure 15A, the delay output 1518-m of delay device 1510-m is coupled to the second input 1334 of OR gate 1330. The first signal inputs 1512-2 to 1512-m of each of delay devices 1510-2 to 1510-m are coupled to the signal input 1252 of high phase extender 1250.

[0141] Each of the delay devices 1510-1 to 1510-m is configured to receive a corresponding control signal (e.g., control bits) via a corresponding control input 1516-1 to 1516-m. In this example, the control input 1254 of the high-phase extender 1250 includes a plurality of control inputs 1254-1 to 1254-m, wherein each of the plurality of control inputs 1254-1 to 1254-m is coupled to the control input 1516-1 to 1516-m of a corresponding delay device among the delay devices 1510-1 to 1510-m.

[0142] In this example, each of the delay devices 1510-1 to 1510-m is configured to enable or disable the corresponding delay outputs 1518-1 to 1518-m based on a corresponding control signal. For example, each of the delay devices 1510-1 to 1510-m can be configured to enable the corresponding delay outputs 1518-1 to 1518-m when the corresponding control signal has a first logic value, and disable the corresponding delay outputs 1518-1 to 1518-m when the corresponding control signal has a second logic value. The first logic value can be 1 and the second logic value can be zero, or vice versa.

[0143] Each of the delay devices 1510-1 to 1510-m is configured to: when the corresponding delay outputs 1518-1 to 1518-m are enabled, pass a high phase (i.e., logic 1) at the corresponding first signal inputs 1512-1 to 1512-m to the corresponding delay outputs 1518-1 to 1518-m, and pass a high phase (i.e., logic 1) at the corresponding second signal inputs 1514-1 to 1514-m to the corresponding delay outputs 1518-1 to 1518-m. In the example of FIG15A, the second signal input 1514-1 of the delay device 1510-1 is coupled to ground. Each of the delay devices 1510-1 to 1510-m is configured to: block the signal (i.e., the clock signal) at the corresponding first signal input 1512-1 to 1512-m and block (i.e., gate) the signal (i.e., the clock signal) at the corresponding second signal input 1514-2 to 1514-m when the corresponding delay output 1518-1 to 1518-m is disabled. In this example, each of the delay devices 1510-1 to 1510-m can output a static logic value at the corresponding delay output 1518-1 to 1518-m when the corresponding delay output 1518-1 to 1518-m is disabled. The static logic value can be zero or one.

[0144] In this example, the duty cycle control circuit 330 (as shown in FIG3) controls the high-phase extension of the high-phase extender 1250 by controlling the number of delay devices 1510-1 to 1510-m with enabled delay outputs 1518-1 to 1518-m via control inputs 1254-1 to 1254-m. The greater the number of delay devices 1510-1 to 1510-m with enabled delay outputs 1518-1 to 1518-m, the greater the high-phase extension of the clock signal at output 1256. In this example, the duty cycle control circuit 330 enables the delay outputs 1518-1 to 1518-m (also referred to as delay segments) of the delay devices 1510-1 to 1510-m from right to left in FIG15A, starting from the delay output 1518-m of the delay device 1510-m. Therefore, in order to enable the delayed output of one of the delay devices 1510-1 to 1510-m, the duty cycle control circuit 330 enables the delayed output 1518-m of the delay device 1510-m. In order to enable the delayed output of two of the delay devices 1510-1 to 1510-m, the duty cycle control circuit 330 enables the delayed outputs 1518-m and 1518-(m-1) of the delay devices 1510-m and 1510-(m-1). In order to enable the delayed output of three of the delay devices 1510-1 to 1510-m, the duty cycle control circuit 330 enables the delayed outputs 1518-m, 1518-(m-1), and 1518-(m-2) of the delay devices 1510-m, 1510-(m-1), and 1510-(m-2), and so on. Note that, for ease of illustration, delay devices 1510-(m-1) and 1510-(m-2) are not explicitly shown in Figure 15A.

[0145] In this example, delay devices 1510-1 to 1510-m increase the high-phase extension range of the high-phase extender 1250. This is because the delay devices with enabled delay outputs generate multiple delayed versions of the clock signal with different time delays. The high phases of the multiple delayed versions of the clock signal are combined at the output 1326 of the delay circuit 1320 and ORed with the clock signal at the OR gate 1330. This enables the high-phase extender 1250 to achieve a large high-phase extension range for the output clock signal, as further discussed below.

[0146] Figure 15B illustrates an example of multiple delayed versions of a clock signal, specifically an example where the delayed outputs 1518-m, 1518-(m-1), and 1518-(m-2) of three delay devices 1510-m, 1510-(m-1), and 1510-(m-2) are enabled. Figure 15B illustrates the clock signal at the signal input 1252 (labeled "hpe_in") of the high-phase extender 1250 and the clock signal at the output 1256 (labeled "hpe_out") of the high-phase extender 1250. In this example, Figure 15B also conceptually illustrates a first delayed version of the clock signal (labeled "clk1"), a second delayed version of the clock signal (labeled "clk2"), and a third delayed version of the clock signal (labeled "clk3"). For clarity, delayed versions of clock signals clk1, clk2, and clk3 are shown at output 1326 of delay circuit 1320 in Figure 15B. In fact, the high phases of the delayed versions of clock signals clk1, clk2, and clk3 are combined (i.e., merged) at output 1326 of delay circuit 1320 to form the delayed output signal shown in Figure 15B (labeled "D_out").

[0147] In this example, the first delayed version of clock signal clk1 is generated from the clock signal entering the first signal input 1512-m of delay device 1510-m, and is delayed by the time delay amount of delay device 1510-m to reach output 1326. The second delayed version of clock signal clk2 is generated from the clock signal entering the first signal input 1512-(m-1) of delay device 1510-(m-1), and is delayed by the time delay amounts of delay devices 1510-(m-1) and 1510-m to reach output 1326. The third delayed version of clock signal clk3 is generated from the clock signal entering the first signal input 1512-(m-2) of delay device 1510-(m-2), and is delayed by the time delay amounts of delay devices 1510-(m-2), 1510-(m-1), and 1510-m to reach output 1326. Note that the high phases of multiple delayed versions of clock signals clk1, clk2, and clk3 overlap in time.

[0148] In this example, the delayed output signal D_out at the output 1326 of the delay circuit 1320 is ORed with the clock signal at the signal input 1252 (labeled "hpe_in") via an OR gate 1330 to generate a clock signal with a large high-phase spread at the output 1256 (labeled "hpe_out"). In this example, clock tracing is prevented by making the individual time delay of each of the delay devices 1510-1 to 1510-m smaller than the high phase of the input clock signal so that the delayed versions of the clock signal overlap in time. However, since the delay circuit 1320 includes multiple delay devices 1510-1 to 1510-m, the high-phase spreader 1250 can achieve a high-phase spread greater than the high phase of the input clock signal without tracing.

[0149] FIG16 illustrates an exemplary embodiment of each of the delay devices 1510-1 to 1510-m according to certain types of delay devices. In this example, each of the delay devices 1510-1 to 1510-m includes corresponding OR gates 1610-1 to 1610-m, corresponding AND gates 1620-1 to 1620-m, and corresponding delay buffers 1630-1 to 1630-m and 1640-1 to 1640-m. In each of the delay devices 1510-1 to 1510-m, the corresponding OR gates 1610-1 to 1610-m have a first input coupled to the corresponding first signal inputs 1512-1 to 1512-m, and a second input coupled to the corresponding second signal inputs 1514-1 to 1514-m. In each of the delay devices 1510-1 to 1510-m, the corresponding gates 1620-1 to 1620-m have a first input coupled to the output of the corresponding gates 1610-1 to 1610-m, and a second input coupled to the corresponding control inputs 1516-1 to 1516-m. In each of the delay devices 1510-1 to 1510-m, the corresponding delay buffers 1630-1 to 1630-m and 1640-1 to 1640-m are coupled in series between the output of the corresponding gates 1620-1 to 1620-m and the corresponding delay outputs 1518-1 to 1518-m.

[0150] In this example, in each of the delay devices 1510-1 to 1510-m, the corresponding OR gates 1610-1 to 1610-m transmit the high phase of the corresponding first signal input at 1512-1 to 1512-m, and transmit the high phase of the corresponding second signal input at 1514-1 to 1514-m to the output of the corresponding OR gates 1610-1 to 1610-m. In each of the delay devices 1510-1 to 1510-m, the corresponding AND gates 1620-1 to 1620-m enable the corresponding delay output when the corresponding control signal is 1 (i.e., the AND gate transmits the high phase to the corresponding delay output) and disable the corresponding delay output when the corresponding control signal is zero (i.e., the AND gate blocks the high phase and outputs zero).

[0151] It should be understood that each of the delay devices 1510-1 to 1510-m may include a number of delay buffers different from the number shown in the example of FIG. 16, depending on, for example, the desired delay in each of the delay devices 1510-1 to 1510-m. In some embodiments, delay buffers 1630-1 to 1630-m and 1640-1 to 1640-m may be omitted together, for example, when the delays of gates 1610-1 to 1610-m and gates 1620-1 to 1620-m have already provided the desired delay for each of the delay devices 1510-1 to 1510-m.

[0152] In the exemplary embodiment of the high-phase extender 1250 shown in Figures 15A and 16, only the time delay of a single delay device (i.e., 1510-m, 1510-(m-1), ..., 1510-1) needs to be less than or equal to the high phase of the input clock signal to avoid clock excitation tracks, while the high phase of the output clock can be extended by the accumulation of the time delays from the enabled delay devices. The exemplary embodiment of the high-phase extender 1250 in Figures 15A and 16 allows the extension of the high phase of the output clock signal to be greater than the high phase of the input clock signal, thereby enabling a wider range of high-phase extension while avoiding clock excitation tracks.

[0153] It should be understood that the duty cycle adjuster 1220 is not limited to the high-phase extender 1250. In this regard, FIG17 illustrates an example in which the duty cycle adjuster 1220 includes a low-phase extender 1750 instead of a high-phase extender 1250. In this example, the low-phase extender has a signal input 1752 coupled to the output 1248 of the first multiplexer 1240, a control input 1754 coupled to the second control input 1228, and an output 1756 of the first input 1272 of the second multiplexer 1270. In this example, the low-phase extender 1750 is configured to extend the low phase of the clock signal by an adjustable amount based on the phase control signal received via the control input 1754.

[0154] To reduce the duty cycle of the clock signal input to the duty cycle adjuster 1220, the duty cycle control circuit 330 (shown in FIG. 3) causes each of the first multiplexer 1240 and the second multiplexer 1270 to select a corresponding first input 1242 and 1272 via the first control input 1226. In this case, the first multiplexer 1240 transmits the clock signal to the signal input 1752 of the low-phase extender 1750. The low-phase extender 1750 then extends the low phase of the clock signal by an adjustable amount based on the phase control signal received from the duty cycle control circuit 330 via the second control input 1228. By extending the low phase of the clock signal, the low-phase extender 1750 reduces the duty cycle of the clock signal.

[0155] To increase the duty cycle of the clock signal input to the duty cycle adjuster 1220, the duty cycle control circuit 330 (shown in FIG. 3) causes each of the first multiplexer 1240 and the second multiplexer 1270 to select a corresponding second input 1244 and 1274 via the first control input 1226. In this case, the first inverter 1235 inverts the clock signal, and the first multiplexer 1240 passes the inverted clock signal to the low-phase extender 1750. The low-phase extender 1750 then extends the low phase of the inverted clock signal by an adjustable amount based on the phase control signal received from the duty cycle control circuit 330 via the second control input 1228. In this case, extending the low phase of the inverted clock signal is equivalent to extending the high phase of the clock signal, which increases the duty cycle of the clock signal. In this example, the second inverter 1265 inverts the low-phase extended inverted clock signal to obtain a clock signal, while the second multiplexer 1270 transmits the clock signal from the second inverter 1265 to the output 1224 of the duty cycle adjuster 1220.

[0156] Typically, the duty cycle adjuster 1220 includes a high-phase extender (e.g., high-phase extender 1250) or a low-phase extender (e.g., low-phase extender 1750) between the output 1248 of the first multiplexer 1240 and the first input 1272 of the second multiplexer 1270, wherein the high-phase extender extends the high phase of the clock signal or the low-phase extender extends the low phase of the clock signal by an adjustable amount based on a phase control signal received via the second control input 1228.

[0157] FIG18 illustrates an exemplary embodiment of a low-phase extender 1750 according to certain types. In this example, the low-phase extender 1750 includes a gate 1830 and a delay circuit 1820. The gate 1830 has a first input 1832, a second input 1834, and an output 1836. The first input 1832 of the gate 1830 is coupled to the signal input 1752 of the low-phase extender 1750, the delay circuit 1820 is coupled between the signal input 1752 of the low-phase extender 1750 and the second input 1834 of the gate 1830, and the output 1836 of the gate 1830 is coupled to the output 1756 of the low-phase extender 1750. It should be understood that the gate can be implemented using a combination of an inverting gate and an inverter, or any other combination of logic gates capable of performing an AND operation.

[0158] In this example, the delay circuit 1820 includes a plurality of delay devices 1810-1 to 1810-m coupled in series to form a delay line. Each of the delay devices 1810-1 to 1810-m has a corresponding first signal input 1812-1 to 1812-m, a corresponding second signal input 1814-1 to 1814-m, a corresponding control input 1816-1 to 1816-m, and a corresponding delay output 1818-1 to 1818-m. The first signal input 1812-1 of the delay device 1810-1 is coupled to the signal input 1752 of the low-phase extender 1750, while the second signal input 1814-1 of the delay device 1810-1 is coupled to the power supply rail (i.e., 1). The delay outputs 1818-1 to 1818-(m-1) of each of the delay devices 1810-1 to 1810-(m-1) are coupled to the second signal inputs 1814-2 to 1814-m of the next delay devices 1810-2 to 1810-m in the delay line, and the delay output 1818-m of delay device 1810-m is coupled to the output 1826 of delay circuit 1820, and the output 1826 of delay circuit 1820 is coupled to the second input 1834 of gate 1830. The first signal inputs 1812-2 to 1812-m of each of the delay devices 1810-2 to 1810-m are coupled to the signal input 1752 of low-phase extender 1750.

[0159] Each of the delay devices 1810-1 to 1810-m is configured to receive a corresponding control signal (e.g., control bits) via a corresponding control input 1816-1 to 1816-m. In this example, the control input 1754 of the low-phase extender 1750 includes a plurality of control inputs 1754-1 to 1754-m, wherein each of the plurality of control inputs 1754-1 to 1754-m is coupled to the control input 1816-1 to 1816-m of a corresponding delay device among the delay devices 1810-1 to 1810-m.

[0160] In this example, each of the delay devices 1810-1 to 1810-m is configured to enable or disable the corresponding delay output 1818-1 to 1818-m based on a corresponding control signal. For example, each of the delay devices 1810-1 to 1810-m can be configured to enable the corresponding delay output 1818-1 to 1818-m when the corresponding control signal has a first logic value, and disable the corresponding delay output 1818-1 to 1818-m when the corresponding control signal has a second logic value. The first logic value can be zero and the second logic value can be 1, or vice versa.

[0161] Each of the delay devices 1810-1 to 1810-m is configured to: when the corresponding delay output 1818-1 to 1818-m is enabled, pass a low phase (i.e., logic 0) at the corresponding first signal input 1812-1 to 1812-m to the corresponding delay output 1818-1 to 1818-m, and pass a low phase (i.e., logic 0) at the corresponding second signal input 1814-1 to 1814-m to the corresponding delay output 1818-1 to 1818-m. In the example of FIG18, the second signal input 1814-1 of the delay device 1810-1 is coupled to a power supply rail. Each of the delay devices 1810-1 to 1810-m is configured to: block the signal (i.e., the clock signal) at the corresponding first signal input 1812-1 to 1812-m and block (i.e., gate) the signal (i.e., the clock signal) at the corresponding second signal input 1814-2 to 1814-m when the corresponding delay output 1818-1 to 1818-m is disabled. In this example, each of the delay devices 1810-1 to 1810-m can output a static logic value at the corresponding delay output 1818-1 to 1818-m when the corresponding delay output 1818-1 to 1818-m is disabled. The static logic value can be 1 or 0.

[0162] In this example, the duty cycle control circuit 330 (as shown in FIG3) controls the low-phase extension of the low-phase extender 1750 by controlling the number of delay devices 1810-1 to 1810-m with enabled delay outputs 1818-1 to 1818-m via control inputs 1754-1 to 1754-m. The greater the number of delay devices 1810-1 to 1810-m with enabled delay outputs 1818-1 to 1818-m, the greater the low-phase extension of the clock signal at output 1756. In this example, the duty cycle control circuit 330 enables the delay outputs 1818-1 to 1818-m (also referred to as delay segments) of the delay devices 1810-1 to 1810-m from right to left in FIG18, starting from the delay output 1818-m of the delay device 1810-m. Delay devices 1810-1 to 1810-m with enabled delay outputs 1818-1 to 1818-m generate multiple versions of a clock signal, wherein the low phase of the multiple versions of the clock signal is combined at output 1826 of delay circuit 1820 to provide a delayed output signal with extended low phase. The greater the number of delay devices 1810-1 to 1810-m with enabled delay outputs 1818-1 to 1818-m, the greater the low phase extension. The delayed output signal is ANDed with the clock signal at signal input 1752 via gate 1830 to provide a clock signal at output 1756.

[0163] FIG18 illustrates an exemplary embodiment of each of the delay devices 1810-1 to 1810-m according to certain types of delay devices. In this example, each of the delay devices 1810-1 to 1810-m includes corresponding AND gates 1840-1 to 1840-m, corresponding OR gates 1850-1 to 1850-m, and corresponding delay buffers 1860-1 to 1860-m and 1870-1 to 1870-m. In each of the delay devices 1810-1 to 1810-m, the corresponding AND gates 1840-1 to 1840-m have a first input coupled to a corresponding first signal input 1812-1 to 1812-m, and a second input coupled to a corresponding second signal input 1814-1 to 1814-m. In each of the delay devices 1810-1 to 1810-m, the corresponding OR gates 1850-1 to 1850-m have a first input coupled to the output of the corresponding AND gates 1840-1 to 1840-m, and a second input coupled to the corresponding control inputs 1816-1 to 1816-m. In each of the delay devices 1810-1 to 1810-m, the respective delay buffers 1860-1 to 1860-m and 1870-1 to 1870-m are coupled in series between the output of the corresponding OR gates 1850-1 to 1850-m and the corresponding delay outputs 1818-1 to 1818-m.

[0164] In this example, in each of the delay devices 1810-1 to 1810-m, the corresponding gates 1840-1 to 1840-m transmit the low phase of the corresponding first signal input at 1812-1 to 1812-m, and the low phase of the corresponding second signal input at 1814-1 to 1814-m to the output of the corresponding gates 1840-1 to 1840-m. In each of the delay devices 1810-1 to 1810-m, the corresponding gates 1850-1 to 1850-m enable the corresponding delay output when the corresponding control signal is 0 (i.e., the gate transmits the low phase to the corresponding delay output) and disable the corresponding delay output when the corresponding control signal is 1 (i.e., the gate blocks the low phase and outputs 1).

[0165] It should be understood that each of the delay devices 1810-1 to 1810-m may include a number of delay buffers that is different from the number of delay buffers shown in the example in FIG18, depending on, for example, the desired delay in each of the delay devices 1810-1 to 1810-m.

[0166] Figure 19 illustrates a method 1900 for compensating for duty cycle distortion in a system of certain states. The system (e.g., system 110) includes a clock generator (e.g., clock generator 115) configured to generate clock signals.

[0167] At block 1910, one or more parameters of the clock signal are measured. For example, one or more parameters may be measured by timing measurement circuit 310. In some cases, one or more parameters include one or more of the following: the high phase of the clock signal, the low phase of the clock signal, and the period of the clock signal.

[0168] At block 1920, the duty cycle adjustment is determined based on one or more measured parameters. For example, the duty cycle adjustment may be determined by measurement control circuit 520 and / or duty cycle control circuit 330.

[0169] At block 1930, the clock signal's duty cycle is adjusted based on the determined duty cycle adjustment. For example, the clock signal's duty cycle can be adjusted by duty cycle adjuster 320.

[0170] In some embodiments, the system includes circuitry (e.g., circuitry 150-3) and a signal path (e.g., signal path 125) coupled between the clock generator and the circuitry. In these embodiments, measuring one or more parameters of the clock signal may include measuring one or more parameters of the clock signal at a first node (e.g., a leaf node) between the signal path and the circuitry, and adjusting the duty cycle of the clock signal may include adjusting the duty cycle of the clock signal at a second node (e.g., a root node) between the clock generator and the signal path. The signal path may include series-coupled delay buffers (e.g., 130-1 to 130-n), and the circuitry may include one or more flip-flops (e.g., flip-flop 155-3).

[0171] In some states, one or more parameters include the high phase of the clock signal. In these states, determining the duty cycle adjustment may include comparing the high phase of the clock signal with a target high phase and determining the duty cycle adjustment based on that comparison.

[0172] In some states, one or more parameters include the low phase of the clock signal. In these states, determining the duty cycle adjustment may include comparing the low phase of the clock signal with a target low phase and determining the duty cycle adjustment based on that comparison.

[0173] In some states, one or more parameters include the high phase and the low phase of the clock signal. In these states, determining the duty cycle adjustment may include comparing the high phase of the clock signal with the low phase of the clock signal and determining the duty cycle adjustment based on that comparison. For example, if the high phase is greater than the low phase (occurring when the duty cycle is higher than 50%), the duty cycle adjustment may reduce the duty cycle of the clock signal to bring the duty cycle of the clock signal closer to the target duty cycle of 50%. If the low phase is greater than the high phase (occurring when the duty cycle is lower than 50%), the duty cycle adjustment may increase the duty cycle of the clock signal to bring the duty cycle of the clock signal closer to the target duty cycle of 50%.

[0174] In some states, adjusting the duty cycle of a clock signal may include extending the high or low phase of the clock signal. In some states, extending the high or low phase of the clock signal may include generating multiple delayed versions of the clock signal, and combining the high or low phases of the multiple delayed versions of the clock signal. For example, multiple delayed versions of the clock signal may be generated by enabling the delayed outputs 1518-1 to 1518-m of two or more of the delayed devices 1510-1 to 1510-m in the exemplary high-phase extender 1250, or by enabling the delayed outputs 1818-1 to 1818-m of two or more of the delayed devices 1810-1 to 1810-m in the exemplary low-phase extender 1750. In some states, the multiple delayed versions of the clock signal overlap in time, for example, to prevent clock excitation tracks.

[0175] Examples of implementation methods are described in the following numbered clauses:

[0176] 1. A system comprising:

[0177] A duty cycle adjuster having a signal input, a control input, and an output, wherein the duty cycle adjuster is configured to: receive a clock signal at the signal input, receive a control signal at the control input, adjust the duty cycle of the clock signal based on the control signal to generate a duty cycle adjusted clock signal, and output the duty cycle adjusted clock signal at the output of the duty cycle adjuster; and

[0178] A timing measurement circuit having an input coupled to the output of the duty cycle adjuster, wherein the timing measurement circuit is configured to: receive the duty cycle adjusted clock signal at the input of the timing measurement circuit, measure one or more parameters of the duty cycle adjusted clock signal, and generate a measurement signal based on the measured one or more parameters.

[0179] 2. The system according to Clause 1 also includes: a signal path coupled between the output of the duty cycle adjuster and the input of the timing measurement circuit.

[0180] 3. The system according to Clause 2, wherein the signal path includes a series-coupled delay buffer.

[0181] 4. The system pursuant to Clause 2 or Clause 3 also includes one or more triggers coupled to the signal path.

[0182] 5. The system according to any one of clauses 1 to 4, wherein the timing measurement circuit includes:

[0183] A time-to-digital converter (TDC) configured to: measure the time delay between a first edge of the duty cycle adjusted clock signal and a second edge of the duty cycle adjusted clock signal; and

[0184] Measurement control circuit coupled to the TDC, wherein the measurement control circuit is configured to generate the measurement signal based on the time delay of the measurement.

[0185] 6. The system according to Clause 5, wherein the first edge of the duty cycle adjusted clock signal is a rising edge and the second edge of the duty cycle adjusted clock signal is a falling edge.

[0186] 7. The system according to Clause 5, wherein the first edge of the duty cycle adjusted clock signal is a falling edge and the second edge of the duty cycle adjusted clock signal is a rising edge.

[0187] 8. The system according to any one of clauses 1 to 7, wherein the timing measurement circuit also includes:

[0188] A startup circuit configured to start the timing signal on the first edge of the clock signal adjusted for the duty cycle;

[0189] A capture circuit configured to output the edge of the capture signal on the second edge of the clock signal adjusted by the duty cycle;

[0190] A time-to-digital converter (TDC) having a signal input and an acquisition input, wherein the signal input of the TDC is configured to receive the timing signal, the acquisition input of the TDC is configured to receive the acquisition signal, and the TDC is configured to: measure the time delay between the time of receiving the edge of the timing signal and the time of receiving the edge of the acquisition signal; and

[0191] A measurement control circuit coupled to the TDC, wherein the measurement control circuit is configured to generate the measurement signal based on the time delay of the measurement.

[0192] 9. The system pursuant to Clause 8, wherein the TDC includes:

[0193] A flip-flop having a signal input, a clock input and an output, wherein the signal input of the flip-flop is coupled to the signal input of the TDC, the clock input of the flip-flop is coupled to the capture input of the TDC, and the output of the flip-flop is coupled to the output of the TDC.

[0194] 10. The system pursuant to Clause 8, wherein the TDC includes:

[0195] A delay line coupled to the signal input of the TDC, the delay line including a series-coupled delay buffer; and

[0196] A trigger, each of the triggers having a corresponding signal input, a corresponding clock input and a corresponding output, wherein the signal input of each of the triggers is coupled to the output of a corresponding delay buffer among the delay buffers in the delay line, and the clock input of each of the triggers is coupled to the fetch input of the TDC.

[0197] 11. A system according to any one of clauses 1 to 10, wherein the duty cycle adjuster is configured as follows:

[0198] Multiple delayed versions that generate this clock signal; and

[0199] Combine the high phases of the multiple delayed versions of the clock signal, or combine the low phases of the multiple delayed versions of the clock signal.

[0200] 12. A system pursuant to Clause 11, wherein the multiple delayed versions of the clock signal overlap in time.

[0201] 13. A system pursuant to Clause 11 or Clause 12, wherein the duty cycle adjuster is configured to: set the number of the plurality of delay versions of the clock signal generated based on the control signal.

[0202] 14. The system according to any one of the clauses 1 to 13 also includes a duty cycle control circuit coupled to the duty cycle adjustment and the timing measurement circuit, wherein the duty cycle control circuit is configured to: receive the measurement signal from the timing measurement circuit and generate the control signal based on the measurement signal.

[0203] 15. The system pursuant to Clause 14, wherein the one or more parameters include one or more of the following: the high phase of the duty cycle adjusted clock signal, the low phase of the duty cycle adjusted clock signal, and the period of the duty cycle adjusted clock signal.

[0204] 16. The system according to Clause 15, wherein:

[0205] This measurement signal indicates the high phase of the duty cycle adjusted clock signal; and

[0206] The working cycle control circuit is configured as follows:

[0207] Compare the high phase of the clock signal adjusted for the duty cycle with the target high phase; and

[0208] The control signal is generated based on this comparison.

[0209] 17. The system according to Clause 15, wherein:

[0210] This measurement signal indicates the low phase of the duty cycle adjusted clock signal; and

[0211] The duty cycle control circuit is configured as follows:

[0212] Compare the low phase of the clock signal adjusted for the duty cycle with the target low phase; and

[0213] The control signal is generated based on this comparison.

[0214] 18. The system according to Clause 15, wherein:

[0215] The measurement signal indicates the high phase of the duty cycle adjusted clock signal and the low phase of the duty cycle adjusted clock signal; and

[0216] The duty cycle control circuit is configured as follows:

[0217] Compare the high phase of the duty cycle adjusted clock signal with the low phase of the duty cycle adjusted clock signal; and

[0218] The control signal is generated based on this comparison.

[0219] 19. A method for compensating for duty cycle distortion in a system including a clock generator configured to generate a clock signal, the method comprising:

[0220] Measure one or more parameters of the clock signal;

[0221] The working cycle adjustment is determined based on one or more measured parameters; and

[0222] Adjust the clock cycle of the clock signal based on the determined duty cycle adjustment.

[0223] 20. The method according to Clause 19, wherein:

[0224] The system includes circuitry and a signal path coupled between the clock generator and the circuitry;

[0225] Measuring the one or more parameters of the clock signal includes: measuring the one or more parameters of the clock signal at a first node between the signal path and the circuit; and

[0226] Adjusting the duty cycle of the clock signal includes: adjusting the duty cycle of the clock signal at a second node between the clock generator and the signal path.

[0227] 21. The method according to Clause 20, wherein the signal path includes a serially coupled delay buffer.

[0228] 22. The method according to Clause 20 or Clause 21, wherein the circuit includes one or more flip-flops.

[0229] 23. The method described in any of the provisions of clauses 19 to 20, wherein the one or more parameters include one or more of the following: the high phase of the clock signal, the low phase of the clock signal, and the period of the clock signal.

[0230] 24. The method according to Clause 23, wherein the one or more parameters include the high phase of the clock signal, and determining the duty cycle adjustment includes:

[0231] Compare this high phase of the clock signal with the target high phase; and

[0232] Based on this comparison, the work cycle adjustment is determined.

[0233] 25. The method according to Clause 23, wherein the one or more parameters include the low phase of the clock signal, and determining the duty cycle adjustment includes:

[0234] Compare this low phase of the clock signal with the target low phase; and

[0235] The work cycle adjustment is determined based on this comparison.

[0236] 26. The method according to Clause 23, wherein the one or more parameters include the high phase of the clock signal and the low phase of the clock signal, and determining the duty cycle adjustment includes:

[0237] Compare the high phase of the clock signal with the low phase of the clock signal; and

[0238] The work cycle adjustment is determined based on this comparison.

[0239] 27. The method described in any of the clauses 19 to 26, wherein adjusting the duty cycle of the clock signal includes extending the high phase of the clock signal.

[0240] 28. The method according to Clause 27, wherein extending the high phase of the clock signal includes:

[0241] Multiple delayed versions that generate the clock signal; and

[0242] Combine the high phases of the multiple delayed versions of the clock signal.

[0243] 29. The method described in any of the clauses 19 to 26, wherein adjusting the duty cycle of the clock signal includes extending the low phase of the clock signal.

[0244] 30. The method according to Clause 29, wherein extending the low phase of the clock signal includes:

[0245] Multiple delayed versions that generate this clock signal; and

[0246] Combine the low phases of the multiple delayed versions of the clock signal.

[0247] It should be understood that the content of this case is not limited to the exemplary terms used above to describe the state of the content of this case. For example, a clock generator may also be referred to as a clock source, clock synthesizer, or other terms. In another instance, a delay buffer may also be referred to as a delay element, delay unit, or other terms. In another instance, a timing measurement circuit may also be referred to as a duty cycle measurement circuit, duty cycle detector, or other terms. The signal input of a flip-flop may also be referred to as a data entry (e.g., a D input) or other terms. The signal path used for a clock signal may also be referred to as a clock path. Furthermore, the edge of the start signal may also be referred to as the edge of the output signal.

[0248] The duty cycle control circuit 330 and the measurement control circuit 520 may be implemented using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, individual hardware components (e.g., logic gates), a state machine, or any combination thereof designed to perform the functions described herein. The processor may perform the functions described herein by executing software including code for performing these functions. The software may be stored on a computer-readable storage medium, such as RAM, ROM, EEPROM, optical disc, and / or magnetic disk.

[0249] In this context, the term "exemplary" means "serving as an example, illustration, or description." Any implementation or pattern described herein as "exemplary" is not necessarily to be construed as preferred or superior to other patterns in this context. Similarly, the term "pattern" does not require all patterns in this context to include the discussed features, advantages, or modes of operation. The term "coupled" is used herein to refer to direct or indirect electrical coupling between two structures.

[0250] To enable anyone skilled in the art to implement or use the content of this application, a description of the application has been provided above. Various modifications to the application will be readily apparent to those skilled in the art, and the overall principles defined herein may be applied to other variations without departing from the spirit or scope of the application. Therefore, the application is not intended to be limited to the instances described herein, but rather to conform to the broadest scope consistent with the principles and novel features disclosed herein. [Simplified Explanation of the Diagram]

[0007] Figure 1 illustrates an example of a system including a clock distribution network of certain types according to the contents of this case.

[0008] Figure 2A illustrates an example of a signal path including a delay buffer, according to certain states of the content of this case.

[0009] Figure 2B illustrates an example of certain states according to the content of this case, in which the input of the signal path remains low in idle mode.

[0010] Figure 2C illustrates an example of duty cycle distortion in a signal path due to asymmetric aging, according to certain aspects of the present case.

[0011] Figure 3 illustrates an example of a self-adjusting clock cycle controller in certain states according to the contents of this case.

[0012] Figure 4 illustrates an example of a timing measurement circuit including a ring oscillator according to certain states of the present case.

[0013] Figure 5 illustrates an example of a timing measurement circuit including a time-to-digital converter, according to certain aspects of the present case.

[0014] Figure 6 is a timing diagram illustrating an example of a clock signal of a certain state according to the contents of this case.

[0015] Figure 7 illustrates an exemplary implementation of a startup circuit and a capture circuit according to certain states of the present invention.

[0016] Figure 8A is a timing diagram illustrating an example of high-phase measurement of certain states according to the contents of this case.

[0017] Figure 8B is a timing diagram illustrating an example of low-phase measurement of certain states according to the contents of this case.

[0018] Figure 8C is a timing diagram illustrating an example of clock cycle measurement for certain states according to the contents of this case.

[0019] Figure 8D is a timing diagram illustrating another example of clock cycle measurement according to certain states of the present case.

[0020] Figure 9 illustrates an exemplary implementation of a time-to-digital converter according to certain aspects of the present invention.

[0021] Figure 10 illustrates another exemplary implementation of a time-to-digital converter according to certain aspects of the present invention.

[0022] Figure 11 illustrates an exemplary implementation of a delay circuit of certain states according to the present invention.

[0023] Figure 12 illustrates an exemplary implementation of a work cycle adjuster of certain states according to the contents of this case.

[0024] Figure 13 illustrates an exemplary implementation of a high-phase extender of certain states according to the present invention.

[0025] Figure 14A is a timing diagram illustrating an example of high-phase extension of certain states according to the content of this case.

[0026] Figure 14B is a timing diagram illustrating an example of a high-phase extension of the excitation trajectory in certain states according to the content of this case.

[0027] Figure 15A illustrates another exemplary embodiment of a high-phase extender of certain states according to the present invention.

[0028] Figure 15B is a timing diagram illustrating an example of multiple delayed versions of a clock signal generated in a high-phase extender according to certain states of the present invention.

[0029] Figure 16 illustrates another exemplary embodiment of a high-phase extender of certain states according to the present invention.

[0030] Figure 17 illustrates another exemplary implementation of a duty cycle adjuster according to certain conditions.

[0031] Figure 18 illustrates an exemplary implementation of a low-phase extender of certain types according to the present invention.

[0032] Figure 19 is a flowchart illustrating a method for compensating work cycles for certain states based on the content of this case. [Biomaterial Storage]

[0252] Domestic storage information (please note in order of storage institution, date, and number) None Foreign storage information (please note in order of storage country, institution, date, and number) None

Claims

1. A system for clock distribution, comprising: A duty cycle adjuster having a signal input, a control input, and an output, wherein the duty cycle adjuster is configured to: receive a clock signal at the signal input, receive a control signal at the control input, adjust a duty cycle of the clock signal based on the control signal to generate a duty cycle adjusted clock signal, and output the duty cycle adjusted clock signal at the output of the duty cycle adjuster; a timing measurement circuit having an input coupled to the output of the duty cycle adjuster, wherein the timing measurement circuit is configured to: receive the duty cycle adjusted clock signal at the input of the timing measurement circuit, measure one or more parameters of the duty cycle adjusted clock signal, and generate a measurement signal based on the measured one or more parameters; a signal path coupled between the output of the duty cycle adjuster and the input of the timing measurement circuit, the signal path including a series-coupled delay buffer; and one or more flip-flops coupled to the signal path.

2. The system according to claim 1, wherein the timing measurement circuit includes: A time-to-digital converter (TDC) configured to measure the time delay between a first edge and a second edge of a duty-cycle-adjusted clock signal; and a measurement control circuit coupled to the TDC, wherein the measurement control circuit is configured to generate the measurement signal based on the measured time delay.

3. The system according to claim 2, wherein the first edge of the duty cycle adjusted clock signal is a rising edge, and the second edge of the duty cycle adjusted clock signal is a falling edge.

4. The system according to claim 2, wherein the first edge of the duty cycle adjusted clock signal is a falling edge, and the second edge of the duty cycle adjusted clock signal is a rising edge.

5. The system according to claim 1, wherein the timing measurement circuit also includes: A startup circuit configured to initiate an edge of a timing signal on a first edge of the duty cycle adjusted clock signal; a capture circuit configured to output an edge of a capture signal on a second edge of the duty cycle adjusted clock signal; a time-to-digital converter (TDC) having a signal input and a capture input, wherein the signal input of the TDC is configured to receive the timing signal, the capture input of the TDC is configured to receive the capture signal, and the TDC is configured to measure a time delay between a time at which the edge of the timing signal is received and a time at which the edge of the capture signal is received; and a measurement control circuit coupled to the TDC, wherein the measurement control circuit is configured to generate the measurement signal based on the measured time delay.

6. The system according to request item 5, wherein the TDC includes: A flip-flop has a signal input, a clock input, and an output, wherein the signal input of the flip-flop is coupled to the signal input of the TDC, the clock input of the flip-flop is coupled to the capture input of the TDC, and the output of the flip-flop is coupled to an output of the TDC.

7. The system according to request item 5, wherein the TDC includes: A delay line coupled to the signal input of the TDC, the delay line including a series-coupled delay buffer; and a trigger, each of the triggers having a corresponding signal input, a corresponding clock input and a corresponding output, wherein the signal input of each of the triggers is coupled to an output of a corresponding delay buffer in the delay line, and the clock input of each of the triggers is coupled to the fetch input of the TDC.

8. The system according to request item 1, wherein the duty cycle adjuster is configured to: generate multiple delayed versions of the clock signal; and combine the high phases of the multiple delayed versions of the clock signal, or combine the low phases of the multiple delayed versions of the clock signal.

9. The system according to request item 8, wherein the multiple delayed versions of the clock signal overlap in time.

10. The system according to request item 8, wherein the duty cycle adjuster is configured to: set a number of the plurality of delay versions of the clock signal generated based on the control signal.

11. The system according to claim 1 also includes a duty cycle control circuit coupled to the duty cycle adjustment and the timing measurement circuit, wherein the duty cycle control circuit is configured to: receive the measurement signal from the timing measurement circuit and generate the control signal based on the measurement signal.

12. The system according to claim 11, wherein the one or more parameters include one or more of the following: a high phase of the duty cycle adjusted clock signal, a low phase of the duty cycle adjusted clock signal, and a period of the duty cycle adjusted clock signal.

13. The system according to request item 12, wherein: The measurement signal indicates the high phase of the duty cycle adjusted clock signal; and the duty cycle control circuit is configured to: compare the high phase of the duty cycle adjusted clock signal with a target high phase; and generate the control signal based on the comparison.

14. The system according to request item 12, wherein: The measurement signal indicates the low phase of the duty cycle adjusted clock signal; and the duty cycle control circuit is configured to: compare the low phase of the duty cycle adjusted clock signal with a target low phase; and generate the control signal based on the comparison.

15. The system according to request item 12, wherein: The measurement signal indicates the high phase and the low phase of the duty cycle adjusted clock signal; and the duty cycle control circuit is configured to: compare the high phase of the duty cycle adjusted clock signal with the low phase of the duty cycle adjusted clock signal; and generate the control signal based on the comparison.

16. A method for compensating for duty cycle distortion in a system including a clock generator, a circuit, and a signal path coupled between the clock generator and the circuit, the clock generator being configured to generate a clock signal, the method comprising the steps of: measuring one or more parameters of the clock signal at a first node between the signal path and the circuit; determining a duty cycle adjustment based on the measured one or more parameters; and adjusting the duty cycle of the clock signal at a second node between the clock generator and the signal path based on the determined duty cycle adjustment, wherein the signal path includes a series-coupled delay buffer, and wherein the circuit includes one or more flip-flops.

17. The method of claim 16, wherein the one or more parameters include one or more of the following: a high phase of the clock signal, a low phase of the clock signal, and a period of the clock signal.

18. The method of claim 17, wherein the one or more parameters include the high phase of the clock signal, and determining the duty cycle adjustment includes the steps of: comparing the high phase of the clock signal with a target high phase; and determining the duty cycle adjustment based on the comparison.

19. The method of claim 17, wherein the one or more parameters include the low phase of the clock signal, and determining the duty cycle adjustment includes the steps of: comparing the low phase of the clock signal with a target low phase; and determining the duty cycle adjustment based on the comparison.

20. The method of claim 17, wherein the one or more parameters include the high phase of the clock signal and the low phase of the clock signal, and determining the duty cycle adjustment includes: The high phase of the clock signal is compared with the low phase of the clock signal; And based on this comparison, the adjustment of the work cycle is determined.

21. The method of claim 16, wherein adjusting the duty cycle of the clock signal includes extending a high phase of the clock signal.

22. The method of claim 21, wherein extending the high phase of the clock signal comprises the steps of: generating multiple delayed versions of the clock signal; and combining the high phases of the multiple delayed versions of the clock signal.

23. The method of claim 16, wherein adjusting the duty cycle of the clock signal includes extending a low phase of the clock signal.

24. The method of claim 23, wherein extending the low phase of the clock signal comprises the steps of: generating multiple delayed versions of the clock signal; and combining the low phases of the multiple delayed versions of the clock signal.

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