System on chip having three-dimensional chiplet structure and electronic device including the system on chip

Abstract

This disclosure provides a system-on-a-chip (SoC) with a three-dimensional (3D) wafer structure and an electronic device. The electronic device includes: a printed circuit board, a SoC on the printed circuit board, and a memory device on the SoC, wherein the SoC includes: a SoC packaging substrate, a first die disposed on the SoC packaging substrate and having logic circuitry thereon, and a second die disposed on the first die and having logic circuitry thereon.

Description

Technical Field

[0001] [[] [Cross - Reference to Related Applications] []]

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2021 - 0126724, filed with the Korean Intellectual Property Office on September 24, 2021, the disclosure of which is incorporated herein by reference in its entirety.

[0003] The inventive concept relates to an integrated circuit (IC), and more particularly, to a system - on - chip having a three - dimensional (3D) die structure, and an electronic device including the system - on - chip. Prior Art

[0004] In the semiconductor industry, there is an increasing demand for high - capacity, thin - type, and miniaturization of semiconductor devices and electronic products using such semiconductor devices, and various packaging technologies related thereto have continuously emerged. The semiconductor packaging of an electronic device is implemented by using an IC chip in a form suitable for use in an electronic product. Generally, in semiconductor packaging, a semiconductor chip is mounted on a printed circuit board (PCB) and electrically connected to the PCB by bonding wires or bumps. Due to the progress of the electronic industry, there has been an increasing demand for high - functionality, high - speed, and miniaturization of electronic devices. Summary of the Invention

[0005] The inventive concept provides a system - on - chip (SoC) with improved performance such as reduced size, reduced power consumption, etc., and an electronic device including the system - on - chip.

[0006] According to some exemplary embodiments of the inventive concept, there is provided an electronic device including: a printed circuit board; a system - on - chip disposed on the printed circuit board; and a memory device on the system - on - chip, wherein the system - on - chip includes: a system - on - chip packaging substrate; a first die on the system - on - chip packaging substrate and having a logic circuit thereon; and a second die on the first die and having a logic circuit thereon.

[0007] According to some exemplary embodiments of the inventive concept, there is provided an electronic device including: a printed circuit board; a system-on-chip on the printed circuit board and including at least one logic die having a logic circuit thereon; a memory device on the system-on-chip; and an interconnect via vertically extending in a direction from at least one logic die to the memory device to electrically connect the at least one logic die to the memory device.

[0008] According to some exemplary embodiments of the inventive concept, there is provided a system-on-chip having a three-dimensional (3D) die structure, the system-on-chip including: a system-on-chip package substrate; a first die on the system-on-chip package substrate by using a first bump and having a first logic circuit thereon; and a second die on the first die and having a second logic circuit thereon. Wherein the first logic circuit and the second logic circuit receive an output voltage from a voltage regulator on the system-on-chip package substrate via an output voltage path, and a plurality of functional blocks are on at least one of the first die and the second die. Brief Description of the Drawings

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] FIGS. 1 and 2 are block diagrams of an electronic device according to an exemplary embodiment.

[0011] FIG. 3A is a cross-sectional view of an electronic device according to some exemplary embodiments.

[0012] FIG. 3B is an enlarged cross-sectional view of region A of FIG. 3A.

[0013] FIG. 4A is a cross-sectional view of an electronic device according to some exemplary embodiments.

[0014] FIG. 4B is an enlarged cross-sectional view of region B of FIG. 4A.

[0015] FIGS. 5 and 6 are cross-sectional views of an electronic device according to an exemplary embodiment.

[0016] FIGS. 7 to 9 are cross-sectional views of an electronic device according to an exemplary embodiment.

[0017] FIG. 10 is a cross-sectional view of a memory device included in an electronic device according to some exemplary embodiments.

[0018] FIG. 11 is a block diagram of a system-on-chip included in an electronic device according to some example embodiments.

[0019] FIG. 12 is a diagram of a system-on-chip having a three-dimensional (3D) die structure. Embodiments

[0020]

[0021] Hereinafter, various embodiments of the inventive concept will be described in conjunction with the accompanying drawings.

[0022] FIGS. 1 and 2 are block diagrams of an electronic device 10 and an electronic device 10A according to example embodiments, respectively.

[0023] Referring to FIG. 1, the electronic device 10 may include a system-on-chip (SoC) 100, a memory device 200, a power management integrated circuit (PMIC) 300, and a voltage regulator VR. The electronic device 10 may include a smartphone, a smartwatch, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a display, a tablet computer, a laptop computer, a netbook, a television, an electronic game, an automobile, and the like. However, the example embodiments are not limited thereto, and furthermore, the electronic device 10 may also include any electronic device that processes data.

[0024] The PMIC 300 may provide an input voltage Vin to the voltage regulator VR through an input voltage path VIP. A capacitor Cin may be connected to the input voltage path VIP such that the input voltage Vin is stably provided to the voltage regulator VR by the PMIC 300. For example, the PMIC 300 may include a direct current (DC)-DC converter, such as a buck converter, a boost converter, and a buck-boost converter.

[0025] The voltage regulator VR may receive the input voltage Vin and generate an output voltage Vout for the operation of the system-on-chip 100. The voltage regulator VR may provide the output voltage Vout to the system-on-chip 100 via an output voltage path VOP. For example, the output voltage Vout may be provided to a memory controller 110 of the system-on-chip 100.

[0026] The voltage regulator VR may include a DC linear regulator such as a low-dropout (LDO) regulator and a high-bandwidth regulator. The output voltage Vout is shown as a voltage in FIG. 1, but may include more than one voltage.

[0027] The system-on-chip 100 may execute applications supported by the electronic device 10 by using the memory device 200. The system-on-chip 100 may also be referred to as a host, an application processor (AP), etc. The system-on-chip 100 may control the memory device 200 and include a memory controller 110 that performs data input / output together with the memory device 200. For example, the memory controller 110 may access the memory device 200 by a direct memory access (DMA) method.

[0028] The memory controller 110 may include an interface circuit 111 electrically connected to the interface circuit 210 of the memory device 200. The interface circuit 111 of the memory controller 110 may send a data input / output signal DQ to the memory device 200 or receive a data input / output signal DQ from the memory device 200 via a signal path DP, that is, the signal path DP may include a data path. Alternatively, the interface circuit 111 may send at least one of the following to the memory device 200 via the signal path DP: a command (e.g., CMD in FIG. 11), an address (e.g., ADD in FIG. 11), a clock (e.g., CK in FIG. 11), and other control signals.

[0029] In addition to the memory controller 110, the system-on-chip 100 may further include a processor, etc. A detailed example configuration of the system-on-chip 100 will be described below with reference to FIG. 11.

[0030] In some example embodiments, the voltage regulator VR may be mounted on the system-on-chip package substrate of the system-on-chip 100. Therefore, in the electronic device 10 according to the inventive concept, the number of capacitors for compensating the voltage drop (or IR drop) of the output voltage path VOP may be reduced, and the number of bumps for electrically connecting the system-on-chip 100 to a printed circuit board may be reduced.

[0031] The memory device 200 can receive or transmit data input / output signals DQ via a signal path DP, and can receive commands CMD, addresses ADD, clocks CK, or other control signals. For example, the memory device 200 can include volatile memory elements such as dynamic random-access memory (DRAM) elements and static RAM (SRAM) elements, and non-volatile memory elements such as phase-change RAM (PRAM) elements, magnetoresistive RAM (MRAM) elements, ferroelectric RAM (FeRAM) elements, and resistive RAM (RRAM) elements. For example, the memory device 200 can include high-bandwidth memory (HBM) DRAM elements. A detailed example configuration of the memory device 200 is described below with reference to FIG. 10.

[0032] In some example embodiments, each of the system-on-chip 100 and the memory device 200 can form a semiconductor package, and the electronic device 10 can have a package-on-package (PoP) structure with the memory device 200 disposed on the system-on-chip 100.

[0033] Referring to FIG. 2, compared with the electronic device 10 of FIG. 1, the electronic device 10A can include a system-on-chip 100A, and the system-on-chip 100A includes a voltage regulator VR. In some example embodiments, the system-on-chip 100A can include a plurality of vertically stacked dies, and the voltage regulator VR can be formed on at least one of the plurality of dies included in the system-on-chip 100A. Therefore, in the electronic device 10A according to the inventive concept, the number of capacitors for compensating the voltage drop (or IR drop) of the output voltage path VOP can be reduced, and the number of bumps for electrically connecting the system-on-chip 100A to a printed circuit board can be reduced.

[0034] FIG. 3A is a cross-sectional view of an electronic device according to some example embodiments. FIG. 3B is an enlarged cross-sectional view of region A of FIG. 3A.

[0035] Referring to FIG. 3A, an electronic device (e.g., 10 of FIG. 1) may include a printed circuit board PSUB, and a system-on-chip 100 and a memory device 200 may be disposed on the printed circuit board PSUB. Each of the system-on-chip 100 and the memory device 200 may be implemented as a semiconductor package, and may be disposed on the printed circuit board PSUB as a PoP type semiconductor package.

[0036] The printed circuit board PSUB may be electrically connected to a motherboard via an external connection terminal SB, and may be electrically connected to a PMIC 300 and a capacitor Cin. The external connection terminal SB may include, for example, solder balls or solder bumps. In FIG. 3A, the capacitor Cin is shown as being electrically connected to the printed circuit board PSUB outside the printed circuit board PSUB, but the exemplary embodiments are not limited thereto, and the capacitor Cin may also be formed inside the printed circuit board PSUB.

[0037] The printed circuit board PSUB may include connection wirings and vias therein. The printed circuit board PSUB may be provided with connection wirings and vias in an input voltage path VIP, and may electrically connect the PMIC 300 to a voltage regulator VR. Each of the connection wirings and vias may include a metal material, such as tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), manganese (Mn), and cobalt (Co), nitrides or oxides of metals such as Ti, Ta, Ru, Mn, Co, and W, cobalt tungsten phosphide (CoWP), cobalt tungsten boron (CoWB), cobalt tungsten boron phosphide (CoWBP), or a combination thereof.

[0038] The printed circuit board PSUB may include a wiring insulating layer surrounding the connection wirings and vias, and may include at least one of the following: silicon oxide (SiO), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), a polymer material, and an insulating material having a dielectric constant lower than that of SiO.

[0039] The system-on-chip 100 may include a system-on-chip package substrate SSUB, and at least one logic die mounted on the system-on-chip package substrate SSUB, such as a first die DIE1 and a second die DIE2. The system-on-chip package substrate SSUB may be electrically connected to the printed circuit board PSUB via an internal connection terminal BP.

[0040] A plurality of logic dies can be stacked on a system wafer package substrate SSUB in a direction perpendicular to the main surface of the system wafer package substrate SSUB. For example, a second die DIE2 can be disposed on a first die DIE1. The first die DIE1 can be electrically connected to the system wafer package substrate SSUB through a first bump BP1, and the second die DIE2 can be electrically connected to the first die DIE1 and the system wafer package substrate SSUB through a second bump BP2. In FIG. 3A, an example is shown in which two logic dies (i.e., a first die DIE1 and a second die DIE2) are stacked in sequence on the system wafer package substrate SSUB. However, the electronic device 10 according to the inventive concept is not limited thereto, and three or more logic dies can also be stacked in sequence on the system wafer package substrate SSUB.

[0041] When the system wafer 100 includes a plurality of vertically stacked logic dies, the area occupied by the system wafer 100 on the printed circuit board PSUB can be reduced, that is, the platform form factor can be reduced. In addition, the number of internal connection terminals BP for electrically connecting the system wafer 100 to the printed circuit board PSUB can be reduced.

[0042] The logic circuits included in the system wafer 100 can be implemented on the first die DIE1 and the second die DIE2, and a plurality of intellectual properties (IP) can be implemented. For example, each component of the system wafer 1000 described with reference to FIG. 11 can be implemented on the first die DIE1 and the second die DIE2. For example, the first die DIE1 and the second die DIE2 can include a processor and a memory controller (e.g., 110 in FIG. 1).

[0043] The first die DIE1 can include a first substrate SUB1 and a first active layer ACL1. The first logic circuit can be formed on the first active layer ACL1. For example, the first active layer ACL1 can include a plurality of first semiconductor elements and a wiring layer on the plurality of first semiconductor elements.

[0044] The second die DIE2 can include a second substrate SUB2 and a second active layer ACL2. The second logic circuit can be formed on the second active layer ACL2. For example, the second active layer ACL2 can include a plurality of second semiconductor elements formed on the second substrate SUB2 and a wiring layer on the plurality of second semiconductor elements. The wiring layer of each of the first active layer ACL1 and the second active layer ACL2 can include a metal wiring layer and a via plug.

[0045] Each of the first substrate SUB1 and the second substrate SUB2 may include, for example, silicon (Si). Alternatively, each of the first substrate SUB1 and the second substrate SUB2 may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

[0046] The first semiconductor element formed on the first active layer ACL1 and the second semiconductor element formed on the second active layer ACL2 may include microelectronic components such as metal-oxide-semiconductor field effect transistors (MOSFETs), large scale integration (LSI) systems, image sensors (such as complementary metal-oxide-semiconductor (CMOS) image sensors (CIS)), micro-electro-mechanical systems (MEMS), active components, passive components, and the like.

[0047] In some exemplary embodiments, the first active layer ACL1 of the first die DIE1 and the second active layer ACL2 of the second die DIE2 may be disposed face to face. Additionally, in some exemplary embodiments, the size of the first die DIE1 disposed relatively closer to the system wafer packaging substrate SSUB may be larger than the size of the second die DIE2.

[0048] The system wafer 100 may include a molding layer 101 surrounding the first die DIE1 and the second die DIE2. The molding layer 101 may protect the first die DIE1 and the second die DIE2 from external influences such as impact and contamination. For protection, the molding layer 101 may include an epoxy molding compound or resin, etc. Additionally, the molding layer 101 may be formed by processes such as compression molding, lamination, screen printing, etc. However, even though the molding layer 101 is shown in FIG. 3A as not surrounding the voltage regulator VR, exemplary embodiments are not limited thereto, and the molding layer 101 may also be formed to surround the voltage regulator VR.

[0049] In some example embodiments, the voltage regulator VR may include an integrated voltage regulator IVR, which is mounted on the system-on-chip package substrate SSUB. In other words, the first die DIE1 and the voltage regulator VR may be disposed parallel to each other on the same plane. The voltage regulator VR may be electrically connected to the system-on-chip package substrate SSUB via the third bump BP3. The system-on-chip package substrate SSUB may be provided with connection wirings and vias included in the input voltage path VIP of the voltage regulator VR. In addition, connection wirings and vias included in the output voltage path VOP of the voltage regulator VR may be provided. Although the voltage regulator VR is shown in FIG. 3A as being disposed on the right side of the first die DIE1 as a reference, the example embodiments are not limited thereto, and the voltage regulator VR may also be disposed on the left side of the first die DIE1 as a reference.

[0050] In the electronic device 10 according to the inventive concept, by including the voltage regulator VR mounted on the system-on-chip package substrate SSUB, the total length of the output voltage path VOP of the voltage regulator VR can be shortened. For example, when it is预想 that the voltage regulator VR according to the comparative example is connected to the external connection terminal SB of the printed circuit board PSUB, the voltage transmission line inside the printed circuit board PSUB may be formed such that the output voltage Vout is transmitted to the system-on-chip 100, and due to the length of the voltage transmission line, a voltage drop (or IR drop) may occur. Therefore, in the electronic device 10 according to the inventive concept, by including the voltage regulator VR mounted on the system-on-chip package substrate SSUB, the area used to form the output voltage path VOP can be reduced, and the number of capacitors used to compensate for the voltage drop of the output voltage path VOP can be reduced.

[0051] The interposer substrate IS may include a redistribution layer substrate and may be configured to electrically connect the system-on-chip 100 to the memory device 200. Wiring layers and vias connecting the wiring layers to each other may be formed in the interposer substrate IS. The first surface of the interposer substrate IS may face the system-on-chip 100, and the second surface facing the first surface of the interposer substrate IS may face the memory device 200.

[0052] The memory device 200 may be disposed on the interposer substrate IS and may be electrically connected to the interposer substrate IS via the interconnect terminals IM. The memory device 200 may have a structure in which a plurality of memory dies are stacked. For example, the memory device 200 may have a structure in which a plurality of memory dies are stacked on the buffer die.

[0053] It should be noted that the term "预想" in the original text seems incorrect. It might be a misspelling. I translated it as "预想" as it was in the original, but it should probably be something like "presumed" or "assumed" for a more accurate translation.Referring to FIGS. 3A and 3B, the system-on-chip 100 can transmit at least one of data input / output signals (e.g., DQ in FIG. 1), control signals, and clocks to the memory device 200 via the interconnect vias IV. In other words, the signal path DP can include the interconnect vias IV.

[0054] In some example embodiments, the interconnect vias IV can include through-silicon vias (TSVs) penetrating the interposer substrate IS and through-mold vias (TMVs) penetrating the molding layer 101.

[0055] In some example embodiments, the interface circuit (e.g., 111 in FIG. 1) included in the memory controller (e.g., 110 in FIG. 1) of the system-on-chip 100 can be formed on the first active layer ACL1 of the first die DIE1. The interconnect vias IV can be formed to extend from the first active layer ACL1 in a vertical direction to the interconnect terminals IM to electrically connect the interface circuit 111 formed on the first active layer ACL1 to the memory device 200. However, different from that shown, the interface circuit 111 can also be formed on the second die DIE2, and the interconnect vias IV can also be formed to contact the second active layer ACL2 of the second die DIE2.

[0056] The interconnect vias IV can include Cu, copper tin (CuSn), copper magnesium (CuMg), copper nickel (CuNi), copper zinc (CuZn), copper palladium (CuPd), copper gold (CuAu), copper rhenium (CuRe), copper tungsten (CuW), W, or W alloy, but are not limited thereto. The interconnect vias IV can include Al, Au, beryllium (Be), bismuth (Bi), cobalt (Co), Cu, hafnium (Hf), indium (In), Mn, molybdenum (Mo), Ni, lead (Pb), Pd, platinum (Pt), rhodium (Rh), Re, Ru, Ta, tellurium (Te), Ti, W, Zn, and zirconium (Zr), and can include one or more stacked structures.

[0057] In the electronic device 10 according to the inventive concept, the signal path DP connected to the system-on-chip 100 and the memory device 200 can be formed to be directly connected to the system-on-chip 100 and the memory device 200 via the interconnect vias IV without passing through the system-on-chip package substrate SSUB. Therefore, when the size of the wiring area for forming the signal path DP is reduced and the length of the signal path DP is reduced, the power consumption in the signal path DP can be reduced, and the possibility of electromagnetic interference (EMI) occurring in the signal path DP can be reduced. In other words, the characteristics of the electronic device 10 can be improved.

[0058] FIG. 4A is a cross-sectional view of an electronic device according to some example embodiments. FIG. 4B is an enlarged cross-sectional view of region B of FIG. 4A. In the description with reference to FIG. 4A, repeated descriptions of the same component symbols as in FIG. 3 are omitted.

[0059] Referring to FIGS. 4A and 4B, the system-on-chip 100 can transmit at least one of data input / output signals (e.g., DQ in FIG. 1), control signals, and clock signals to the memory device 200 via the signal path DP'. In addition, the system-on-chip 100 can receive the data input / output signal DQ from the memory device 200 via the signal path DP'.

[0060] The signal path DP' can include an interconnect via IV' and internal wiring IW of the interposer substrate IS. The interconnect via IV' can include a through-hole formed through the molding layer 101.

[0061] The internal wiring IW of the interposer substrate IS can include an upper pad P1, a lower pad P2, and a vertical internal wiring CP. The upper pad P1 of the interposer substrate IS can be connected to the interconnect terminal IM, and the lower pad P2 of the interposer substrate IS can be connected to the interconnect via IV'.

[0062] At least one wiring layer can be formed in the interposer substrate IS. The vertical internal wiring CP can extend in the vertical direction of the interposer substrate IS to connect the upper pad P1 to at least one wiring layer, or to connect the lower pad P2 to at least one wiring layer. In addition, the vertical internal wiring CP can extend in the vertical direction to connect different wirings to each other. In some example embodiments, the internal wiring IW of the signal path DP' can be formed on at least one wiring layer of the interposer substrate IS, and can further include horizontal internal wiring extending in the horizontal direction of the interposer substrate IS.

[0063] In some example embodiments, the upper pad P1 and the lower pad P2 of the interposer substrate IS can include at least one of Cu, Ni, stainless steel, and BeCu. In some example embodiments, the vertical internal wiring CP or the horizontal internal wiring of the interposer substrate IS can include a metal such as Cu, Ni, Au, silver (Ag), aluminum (Al), W, Ti, Ta, In, Mo, Mn, Co, Sn, Mg, Re, Be, Ga, and Ru, or a combination thereof.

[0064] FIG. 5 and FIG. 6 are cross-sectional views of an electronic device according to an exemplary embodiment. FIGS. 5 and 6 are detailed views of the SoC, voltage regulator, and memory device in the electronic device, and a repeated description of the same component symbols as in FIG. 3A is omitted in the description given with reference to FIGS. 5 and 6. The system-on-chip 100 in FIG. 5 and the system-on-chip 100A in FIG. 6 can be mounted on a printed circuit board (PSUB in FIG. 3A) in the same manner as the system-on-chip 100 in FIG. 3A, respectively.

[0065] Referring to FIG. 5, the voltage regulator VR can be disposed on the first die DIE1. In other words, the voltage regulator VR can be disposed in parallel with the second die DIE2 on the same plane. The voltage regulator VR can be electrically connected to the first die DIE1 via the third bump BP3a contacting the first die DIE1. Alternatively, different from that shown in FIG. 5, the voltage regulator VR can be disposed in parallel with the second die DIE2, but can also be electrically connected to the system-on-chip package substrate SSUB via a bump contacting the system-on-chip package substrate SSUB.

[0066] Referring to FIG. 6, the system-on-chip 100A can include the voltage regulator VR. For example, the voltage regulator VR can also be embedded in the first die DIE1 or the second die DIE2. Therefore, the total length of the output voltage path VOP can be relatively further reduced.

[0067] FIGS. 7 to 9 are cross-sectional views of an electronic device according to an exemplary embodiment. FIGS. 7 to 9 are detailed views of the system-on-chip, voltage regulator, and memory device in the electronic device, and a repeated description of the same component symbols as in FIG. 3 will be omitted in the description given with reference to FIGS. 7 to 9. The system-on-chip 100 in FIGS. 7 to 9 can be mounted on a printed circuit board (PSUB in FIG. 3A) in the same manner as the system-on-chip 100 in FIG. 3A.

[0068] Referring to FIG. 7, the first die DIE1 can include a first substrate SUB1 and a first active layer ACL1, and the second die DIE2 can include a second substrate SUB2 and a second active layer ACL2. The first active layer ACL1 of the first die DIE1 and the second active layer ACL2 of the second die DIE2 can be disposed back-to-back. For example, the first active layer ACL1 of the first die DIE1 can be disposed to face the system-on-chip package substrate SSUB, and the second active layer ACL2 of the second die DIE2 can be disposed to face the first die DIE1.

[0069] The system-on-chip 100 can transmit and receive (send and / or receive) data input / output signals (e.g., DQ in FIG. 1) to and from the memory device 200 via the interconnect vias IVa. In other words, the signal path (e.g., DP in FIG. 1) can include the interconnect vias IVa. The interconnect vias IVa can include through-silicon vias penetrating the interposer substrate IS, mold vias penetrating the molding layer 101, and through-silicon vias penetrating the first substrate SUB1 of the first die DIE1. In some exemplary embodiments, the interface circuit (e.g., 111 in FIG. 1) included in the memory controller (e.g., 110 in FIG. 1) of the system-on-chip 100 can be formed on the first active layer ACL1 of the first die DIE1. The interconnect vias IVa can be formed to extend in a vertical direction from the first active layer ACL1 to the interconnect terminal IM to electrically connect the interface circuit 111 formed on the first active layer ACL1 to the memory device 200. Alternatively, as described above with reference to FIGS. 4A and 4B, the signal path can also include internal wiring within the interposer substrate IS.

[0070] As described above with reference to FIGS. 3A, 5, and 6, the voltage regulator VR can also be mounted on the system-on-chip package substrate SSUB, or on the first die DIE1, or can also be formed in at least one of the first die DIE1 and the second die DIE2.

[0071] Referring to FIG. 8, the size of the first die DIE1 disposed relatively close to the system-on-chip package substrate SSUB can be smaller than the size of the second die DIE2. The first active layer ACL1 of the first die DIE1 and the second active layer ACL2 of the second die DIE2 can be disposed face to face.

[0072] The system-on-chip 100 can transmit and receive the data input / output signal DQ to and from the memory device 200 via the interconnect vias IVb. In other words, the signal path DP can include the interconnect vias IVb, and the interconnect vias IVb can include through-silicon vias penetrating the interposer substrate IS, mold vias penetrating the molding layer 101, and through-silicon vias penetrating the second substrate SUB2 of the second die DIE2. Alternatively, as described above with reference to FIGS. 4A and 4B, the signal path can also include internal wiring within the interposer substrate IS.

[0073] In some example embodiments, the interface circuit 111 included in the memory controller 110 of the system-on-chip 100 may be formed on the second active layer ACL2 of the second die DIE2. The interconnect via IVb may be formed to extend in a vertical direction from the second active layer ACL2 to the interconnect terminal IM to electrically connect the interface circuit 111 formed on the second active layer ACL2 to the memory device 200. However, the example embodiments are not limited thereto, and the interface circuit 111 may also be formed on the first active layer ACL1 of the first die DIE1, and the signal path DP may also include wiring connected to each of the first active layer ACL1 and the second active layer ACL2 connected to the interconnect via IVb and the second bump BP2. Alternatively, as described above with reference to FIGS. 4A and 4B, the signal path may also include internal wiring inside the interposer substrate IS.

[0074] Referring to FIG. 9, the size of the first die DIE1 disposed relatively close to the system-on-chip package substrate SSUB may be smaller than the size of the second die DIE2. The first active layer ACL1 of the first die DIE1 and the second active layer ACL2 of the second die DIE2 may be disposed face to face. For example, the first active layer ACL1 of the first die DIE1 may be disposed to face the system-on-chip package substrate SSUB, and the second active layer ACL2 of the second die DIE2 may be disposed to face the first die DIE1.

[0075] The system-on-chip 100 may transmit and receive data input / output signals DQ to and from the memory device 200 via the interconnect via IVb. In other words, the signal path DP may include the interconnect via IVb. Alternatively, as described above with reference to FIGS. 4A and 4B, the signal path may also include internal wiring inside the interposer substrate IS.

[0076] In some example embodiments, the interface circuit 111 included in the memory controller 110 of the system-on-chip 100 may be formed on the second active layer ACL2 of the second die DIE2. The interconnect via IVb may be formed to extend in a vertical direction from the second active layer ACL2 to the interconnect terminal IM to electrically connect the interface circuit 111 formed on the second active layer ACL2 to the memory device 200. However, the example embodiments are not limited thereto, and the interface circuit 111 may also be formed on the first active layer ACL1 of the first die DIE1, and the signal path DP may also include wiring connected to each of the first active layer ACL1 and the second active layer ACL2 connected to the interconnect via IVb, through-silicon vias penetrating the first substrate SUB1, and the second bump BP2.

[0077] FIG. 10 is a cross-sectional view of a memory device 200 included in an electronic device according to some example embodiments.

[0078] Referring to FIG. 10, the memory device 200 may include a three-dimensional (3D) stacked memory device. The memory device 200 may include buffer dies 220, and a plurality of memory dies stacked on the buffer dies 220, e.g., a first memory die 230_1 to an nth memory die 230_n. n may include a natural number equal to or greater than 3, such as 4 or 8, or may vary diversely. The buffer dies 220 and the first memory die 230_1 to the nth memory die 230_n may be disposed in a semiconductor package.

[0079] The memory device 200 may include through vias TV penetrating the buffer dies 220 and the first memory die 230_1 to the nth memory die 230_n, and microbumps MBP electrically connecting the through vias TV to each other. The through vias TV and the microbumps MBP may provide a circuit path between the buffer dies 220 and the first memory die 230_1 to the nth memory die 230_n in the memory device 200. The number of the through vias TV and the microbumps MBP is not limited to that shown in FIG. 10 and may vary diversely. The nth memory die 230_n may not include the through via TV, but is not particularly limited thereto.

[0080] Each of the first memory die 230_1 to the nth memory die 230_n may include a dynamic random access memory (RAM) (DRAM) chip. For example, each of the first memory die 230_1 to the nth memory die 230_n may include a general DRAM device such as a double data rate (DDR) synchronous DRAM (DDR SDRAM), a mobile DRAM device such as a low power (LP) DDR (LPDDR) SDRAM, a graphics DRAM device such as a graphics DDR (GDDR) synchronous graphics RAM (SGRAM), a wide input / output (I / O) providing high capacity and high bandwidth, a DRAM device such as a high bandwidth memory (HBM), HBM2, HBM3, and a hybrid memory cube (HMC). However, the example embodiments are not limited thereto, and each of the first memory die 230_1 to the nth memory die 230_n may also include a volatile memory device without a DRAM device, or may also include a non-volatile memory device.

[0081] According to some example embodiments, the first memory die 230_1 to the nth memory die 230_n may have substantially the same die size. In other words, the first memory die 230_1 to the nth memory die 230_n may have substantially the same planar shape and the same planar size.

[0082] The buffer die 220 may perform the following interface operations: providing data input / output signals, commands, addresses, chip select signals, etc. received from a memory controller (e.g., 110 in FIG. 1) to the first memory die 230_1 to the nth memory die 230_n, or providing data input / output signals received from the first memory die 230_1 to the nth memory die 230_n to the memory controller 110. To perform the interface operations, the buffer die 220 may include a physical layer (PHY) 210 or interface circuitry. The physical layer 210 may correspond to the interface circuitry 210 in FIGS. 1 and 2.

[0083] FIG. 11 is a block diagram of a system-on-chip 1000 included in an electronic device according to some example embodiments.

[0084] Referring to FIG. 11, the system-on-chip 1000 may correspond to the above-mentioned system-on-chip (e.g., 100 in FIG. 1 and 100A in FIG. 2). The system-on-chip 1000 may include a processor 1100, a cache memory 1200, a memory controller 1300, and a bus 1500. The bus 1500 may provide a communication path between the processor 1100, the cache memory 1200, and the memory controller 1300. The processor 1100 may execute various software (application programs, operating systems, file systems, device drivers, etc.) loaded on the cache memory 1200.

[0085] Processor 1100 may include multi-cores of the same type or different types. For example, processor 1100 may include any one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU), and the number of processors 1100 may be one or more.

[0086] In cache memory 1200, application programs, operating systems, file systems, device drivers, etc. for driving an electronic device (e.g., 10 in FIG. 1 and 10A in FIG. 2) may be loaded. For example, cache memory 1200 may include an SRAM device having a faster data input / output speed than a memory device (e.g., 200 in FIG. 1).

[0087] Memory controller 1300 may access memory device 200 by a direct memory access (DMA) method. Memory controller 1300 may include a command (CMD) queue 1310, a command (CMD) scheduler 1320, a read data queue 1330, a write data queue 1340, and a physical layer 1400. Memory controller 1300 may correspond to memory controller 110 in FIGS. 1 and 2, and physical layer 1400 may correspond to interface circuit 111 in FIGS. 1 and 2. Components (1310 to 1340 and 1400) of memory controller 1300 may be implemented by using hardware methods, software methods, or a combination thereof in system-on-chip 1000.

[0088] CMD queue 1310 may store commands and addresses issued by processor 1100 or generated under the control of processor 1100. Based on the control of CMD scheduler 1320, the commands and addresses stored in CMD queue 1310 may be provided to physical layer 1400.

[0089] CMD scheduler 1320 may adjust the sequence of commands and addresses stored in CMD queue 1310, the time points at which commands and addresses are input to CMD queue 1310, the time points at which commands and addresses are output from CMD queue 1310, etc.

[0090] The read data queue 1330 can store read data sent by the memory device 200 via the physical layer 1400 by using a read command. The read data stored in the read data queue 1330 can be provided to the cache memory 1200 and can be processed by the processor 1100.

[0091] The write data queue 1340 can store write data to be stored in the memory device 200. The write data stored in the write data queue 1340 can be sent to the memory device 200 via the physical layer 1400 by using a write command.

[0092] The physical layer 1400 may include a clock (CK) generator 1410, a command / address (CMD / ADD) generator 1420, a data receiver 1430, and a data transmitter 1440. The clock generator 1410 can generate a clock CK for output to the memory device 200, and the number of clocks CK can correspond to the number of channels between the system-on-chip 1000 and the memory device 200.

[0093] The CMD / ADD generator 1420 can receive a command CMD or an address ADD from the command queue 1310 and can send the command CMD or the address ADD to the memory device 200. The data receiver 1430 can receive read data of the data input / output signal DQ based on a read data strobe signal (RDQS or DQS) from the memory device 200. The data receiver 1430 can provide the received read data to the read data queue 1330. The data transmitter 1440 can receive write data from the write data queue 1340. The data transmitter 1440 can send the received write data to the memory device 200 based on a write data strobe signal (WDQS or DQS). As described above, the data input / output signal DQ can be provided to the memory device 200 via a data path (e.g., DP in FIG. 1).

[0094] FIG. 12 is a diagram of a system-on-chip 100B having a 3D die structure.

[0095] Referring to FIG. 12, the system-on-chip 100B may have a 3D die structure including a base die BD and a computing die CD stacked on the base die BD. A plurality of functional blocks IP may be disposed on at least one of the base die BD and the computing die CD. In FIG. 12, the plurality of functional blocks IP are shown as being disposed on the computing die CD, but the exemplary embodiments are not limited thereto, and the plurality of functional blocks IP may also be disposed on the base die BD. In some exemplary embodiments, the base die BD may correspond to the first die DIE1 in FIG. 3A etc., and the computing die CD may correspond to the second die DIE2 in FIG. 3A etc.

[0096] In this case, each of the plurality of functional blocks IP may include a die designed to perform a specified specific function. For example, each of the plurality of functional blocks IP may include a CPU die, an input / output interface die, a die in which circuits for artificial intelligence (AI) operations are implemented, a graphics die, a media die, etc. Some of the plurality of functional blocks IP may include dies that perform the same function.

[0097] In the system-on-chip 100B according to the inventive concept, various modifications may be made to the types of the plurality of functional blocks IP disposed on the base die BD and the computing die CD according to the use of the system-on-chip 100B. Therefore, compared with a system-on-chip of a comparative example in which the system-on-chip is implemented as one functional block, the system-on-chip 100B may have improved reusability and scalability.

[0098] The system-on-chip 100B may include a voltage regulator VR, and the voltage regulator VR may be disposed on at least one of the plurality of dies included in the system-on-chip 100B, that is, on one of the base die BD and the computing die CD. The plurality of functional blocks IP of the system-on-chip 100B may receive an output voltage from the voltage regulator VR. Alternatively, in some exemplary embodiments, the voltage regulator VR may be disposed outside the system-on-chip 100B, and the system-on-chip 100B may receive an output voltage from the voltage regulator VR outside.

[0099] A memory die MD may be disposed on the computing die CD of the system-on-chip 100B. The memory die MD may correspond to the memory device 200 in FIG. 3A etc. The memory die MD may be electrically connected to the system-on-chip 100B via an interconnect via hole, and the interconnect via hole may constitute a signal path.

[0100] The electronic device 10 (or other circuit systems, such as system-on-chip 100, voltage regulator VR, memory controller 110, interface circuit 111, memory device 200, interface circuit 210, PMIC 300, its variants, system-on-chip 1000, processor 1100, cache memory 1200, memory controller 1300, its sub-components or other circuit systems discussed herein) may include hardware having logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuit system may more specifically include (but is not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0101] Although the inventive concept has been specifically illustrated and described with reference to its exemplary embodiments, it should be understood that various changes may be made in form and detail without departing from the spirit and scope of the following claims.

[0102] 101: Molded layer 10, 10A: Electronic device 100, 100A, 100B, 1000: System-on-chip 110, 1300: Memory controller 111, 210: Interface circuit 200: Memory device 210, 1400: Physical layer 220: Buffer die 230_1: First memory die 230_2: Second memory die 230_n: nth memory die 300: Power management integrated circuit / PMIC 1100: Processor 1200: Cache memory 1310: Command queue / CMD queue 1320: Command scheduler / CMD scheduler 1330: Read data queue 1340: Write Data Queue 1410: Clock Generator 1420: CMD / ADD Generator 1430: Data Receiver 1440: Data Transmitter 1500: Bus A, B: Region ACL1: First Active Layer ACL2: Second Active Layer ADD: Address BD: Base Die BP: Internal Connection Terminal BP1: First Bump BP2: Second Bump BP3, BP3a: Third Bump CD: Calculation Die Cin: Capacitor CK: Clock CMD: Command CP: Vertical Internal Wiring DIE1: First Die DIE2: Second Die DP, DP': Signal Path DQ: Data Input / Output Signal IM: Interconnection Terminal IP: Functional Block IS: Interposer Substrate IV, IV', IVa, IVb: Interconnection Through-Hole IW: Internal Wiring MBP: Micro Bump MBP MD: Memory Die P1: Upper Pad P2: Lower Pad PSUB: Printed Circuit Board RDQS: Read Data Strobe Signal SB: External Connection Terminal SSUB: System-on-Chip Package Substrate SUB1: First Substrate SUB2: Second Substrate TMV: Mold Perforation TSV: Through-Silicon Via TV: Through-Hole Vin: Input Voltage VIP: Input Voltage Path VOP: Output Voltage Path Vout: Output Voltage VR: Voltage Regulator WDQS: Write Data Strobe

Claims

1. An electronic device comprising: Printed circuit boards; A system-on-a-chip (SoC) is located on the printed circuit board. Memory device on the system chip; Interconnect vias; And an interposer substrate, between the system chip and the memory device, and electrically connecting the system chip to the memory device, wherein the system chip includes a system chip packaging substrate; A first die is on the system chip package substrate and has logic circuitry thereon; and a second die is on the first die and has logic circuitry thereon, wherein the interconnect vias extend perpendicularly from a position within the system chip that contacts the first die to the outer surface of the system chip facing the memory device, and penetrate the interposer substrate.

2. The electronic device of claim 1, wherein the first die includes a first substrate and a first active layer having semiconductor elements on the first substrate, the second die includes a second substrate and a second active layer having semiconductor elements on the second substrate, and the first active layer and the second active layer are disposed face-to-face.

3. The electronic device of claim 1, wherein the first die includes a first substrate and a first active layer having semiconductor elements on the first substrate, the second die includes a second substrate and a second active layer having semiconductor elements on the second substrate, the first active layer facing the system wafer package substrate, and the second active layer facing the first die.

4. The electronic device as claimed in claim 1, wherein the size of the first die is larger than the size of the second die.

5. The electronic device of claim 1, further comprising a voltage regulator configured to receive an input voltage and generate an output voltage for use by the system chip, wherein the voltage regulator is mounted on the system chip package substrate.

6. The electronic device as claimed in claim 5, wherein the voltage regulator is parallel to the first die in the same plane.

7. The electronic device of claim 1, further comprising a voltage regulator configured to receive an input voltage and configured to generate an output voltage for use by the system chip, wherein the voltage regulator is on the first die.

8. The electronic device of claim 1, further comprising a voltage regulator configured to receive an input voltage and generate an output voltage for use by the system chip, wherein the voltage regulator is embedded in one of the first die and the second die.

9. The electronic device as claimed in claim 1, wherein the system chip further comprises: A memory controller configured to send data input / output signals to and receive the data input / output signals from the memory device, and a signal path, electrically connecting the memory controller to the memory device and configuring it to send the data input / output signals, the signal path including the interconnect via.

10. The electronic device as claimed in claim 1, wherein the system chip further comprises: A memory controller configured to send data input / output signals to and receive the data input / output signals from the memory device, and a signal path electrically connecting the memory controller to the memory device and configured to send the data input / output signals, and including the interconnect via.

11. An electronic device comprising: Printed circuit boards; A system on chip (SoC) is placed on the printed circuit board and includes at least one logic die having logic circuitry thereon. A memory device on the system chip; an interposer substrate between the system chip and the memory device, and electrically connecting the system chip to the memory device; And interconnect vias extending vertically from the location within the system wafer that contacts the at least one logic die to the outer surface of the system wafer facing the memory device and through the interposer substrate to electrically connect the at least one logic die to the memory device.

12. The electronic device of claim 11, wherein the at least one logic die comprises a plurality of vertically stacked logic dies, and the interconnect via extends vertically from a first die to the memory device, the first die being the lowest die among the plurality of vertically stacked logic dies.

13. The electronic device of claim 11, wherein the at least one logic die comprises a plurality of vertically stacked logic dies, and the interconnect via extends vertically from a second die to the memory device, the second die being the uppermost die of the plurality of vertically stacked logic dies.

14. The electronic device of claim 11, wherein the system wafer further includes a molding layer surrounding the at least one logic die, and the interconnect vias include through-holes through the molding layer.

15. The electronic device of claim 11, further comprising a voltage regulator configured to receive an input voltage and generate an output voltage for use by the system chip, wherein the voltage regulator is mounted on a system chip package substrate of the system chip and is parallel to the at least one logic die in the same plane.

16. The electronic device of claim 11 further includes a voltage regulator configured to receive an input voltage and generate an output voltage for use by the system chip, wherein the voltage regulator is embedded in the at least one logic die.

17. An electronic device comprising: A System-on-a-Chip (SoC) having a three-dimensional (3D) chiplet structure, the SoC comprising: a SoC package substrate; a first die on the SoC package substrate by means of a first bump and having a first logic circuit thereon; and a second die on the first die and having a second logic circuit thereon; a memory device on the SoC; interconnect vias; and an interposer substrate between the SoC and the memory device, electrically connecting the SoC to the memory device, wherein the first logic circuit and the second logic circuit receive an output voltage from a voltage regulator on the SoC package substrate via an output voltage path, a plurality of functional blocks on at least one of the first die and the second die, and wherein the interconnect vias extend perpendicularly from a position within the SoC that contacts the first die to an outer surface of the SoC facing the memory device and through the interposer substrate.

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