A semiconductor substrate processing apparatus

Abstract

A semiconductor substrate processing apparatus includes a processing chamber, a boat, and a plurality of wafer supports. The boat is configured to accommodate the plurality of wafers and is housed within the processing chamber for depositing a layer on each wafer. The boat includes at least two boat pillars, each boat pillar including a plurality of slots. Each wafer support includes a support region configured to support a circumferential edge of at least one wafer, and a flange circumferentially surrounding the support region. The flange is housed in and supported by the slots and has a width for establishing a distance between the circumferential edge of the wafer and the boat pillars. This distance ensures that the boat pillars do not substantially affect the layer thickness deposited on the wafer during processing.

Description

[Technical Field]

[0001] This disclosure generally relates to a semiconductor substrate processing apparatus. [Previous Technology]

[0002] In semiconductor substrate processing equipment (such as vertical batch furnaces, atomic layer deposition (ALD) equipment, and the like), wafers can be processed in a process chamber by depositing a layer of deposition material on the wafer. Wafers can be loaded into a boat capable of accommodating a plurality of spaced-apart wafers. The boat with the loaded wafers can be placed in the process chamber for processing. Uniform deposition of material on the wafers in the boat can be important for obtaining high-quality wafers. A known problem is the accumulation of deposition material near the outer edge of the wafer, i.e., accumulation in the outer edge region, making the layer in this outer edge region thicker than elsewhere on the wafer. This edge effect can degrade wafer quality and may reduce the effective area of ​​the wafer. Furthermore, the supports of the slotted boat that support the wafer can interfere with the deposition process, causing the layer thickness deposited on the wafer adjacent to the wafer supports to differ from the layer thickness in wafer portions farther from the supports.

[0003] It is known that a shielding ring is placed in a slot in a boat above a wafer, wherein the shielding ring shields the outer edge region of the wafer from excessive deposition. [Summary of the Invention]

[0004] This disclosure is provided to introduce a series of concepts in a simplified form. These concepts will be described in further detail in the embodiments of the examples disclosed below. This disclosure is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0005] It is understood that in known substrate processing equipment using a shielding ring, the deposited material still accumulates and deposits on the outer edge region of the wafer.

[0006] An objective may be to provide a semiconductor processing apparatus in which the accumulation of material deposited on the outer edge region of the wafer is less than that in known semiconductor processing apparatuses.

[0007] To this end, a semiconductor substrate processing apparatus may be provided. This semiconductor substrate processing apparatus may include a processing chamber, a wafer boat, and a plurality of wafer supports. The processing chamber may be configured for batch processing of a plurality of wafers. The processing may include depositing a layer on each of the plurality of wafers. The wafer boat may be configured to accommodate the plurality of wafers and is housed within the processing chamber. The wafer boat may include at least two boat pillars. Each boat pillar may include a plurality of slots. Each of the plurality of wafer supports may include a support region and a flange. The support region may be configured to support a circumferential edge of at least one of the plurality of wafers. The flange may circumferentially surround the support region. The flange may be housed in and supported by the slots. The flange may have a width for establishing a distance between the circumferential edge of the wafer and the boat pillars of the wafer boat. This distance can be such that these ship pillars do not substantially affect the thickness of the layer deposited on the wafer during the processing of the wafer.

[0008] Another semiconductor substrate processing apparatus may also be provided. This semiconductor substrate processing apparatus may include a processing chamber, a boat, and a shielding ring. The processing chamber may be configured for batch processing of a plurality of wafers. The processing may include depositing a layer on each of the plurality of wafers. The boat may be configured to accommodate the plurality of wafers and is housed within the processing chamber. The boat may include at least two boat supports. Each boat support may include a plurality of slots. The shielding ring may be configured to be supported above an associated wafer in the slots of the boat supports. The shielding ring may shield a circumferentially outer edge region on the upper surface of one of the associated wafers. This circumferentially outer edge region may be annular, having a radial width, and extending circumferentially along a circumferential edge of the wafer. A surface portion of the shielding ring may define a nominal surface area, which, if flat, is one surface area of ​​this surface portion. This surface portion has a surface structure that provides an incremental surface area. An incremental surface area ratio can be defined by dividing the incremental surface area of ​​the surface portion having this surface structure by the nominal surface area. This incremental surface area ratio is greater than 1.5.

[0009] For the purpose of summarizing this disclosure and the advantages achieved over the prior art, certain objectives and advantages of this disclosure have been described above. It should be understood, of course, that not all such objectives or advantages may necessarily be achieved according to any particular embodiment of this disclosure. Therefore, those skilled in the art will recognize, for example, that this disclosure may be embodied or practiced in a manner that achieves or optimizes one or more advantages as taught or suggested herein, and may not necessarily achieve other objectives or advantages that may be taught or suggested herein.

[0010] Various embodiments are claimed in the claims of the subsidiary applications, which will be further illustrated with reference to one example shown in the drawings. These embodiments may be combined or applied separately from each other.

[0011] All of these embodiments are intended to fall within the scope of this disclosure. Those skilled in the art will understand these and other embodiments from the following description of certain embodiments with reference to the accompanying drawings. This disclosure is not limited to any particular embodiment disclosed.

Implementation Method

[0013] In this application, similar or corresponding features are marked by similar or corresponding element symbols. The description of various embodiments is not limited to the examples shown in the drawings and the element symbols used in the embodiments, and the scope of the application is not intended to limit the description of the embodiments, but is included to illustrate the embodiments.

[0014] While certain embodiments and examples are disclosed below, those skilled in the art will understand that this disclosure extends beyond the specific embodiments and / or uses disclosed herein, as well as obvious modifications and equivalents thereof. Therefore, it is intended that the scope of this disclosure be not limited to the specific disclosed embodiments described below. The illustrations presented herein are not intended to represent actual views of any particular material, structure, or device, but are merely idealized representations used to describe embodiments of this disclosure.

[0015] As used herein, the term "wafer" may refer to any underlying material on which devices, circuits or films may be formed or formed.

[0016] In the most general terms, this disclosure provides a semiconductor substrate processing apparatus 10. An example of the semiconductor substrate processing apparatus 10 is shown in Figure 1. The semiconductor substrate processing apparatus 10 may include a processing chamber 12, a wafer boat 14, and a plurality of wafer supports 20. An example of a wafer boat 12 having wafer supports 20 and wafers 90 is shown in Figures 4 and 5. The processing chamber 12 may be configured for batch processing of a plurality of wafers 90. The processing may include depositing a layer on each of the plurality of wafers 90. The wafer boat 14 may be configured to accommodate a plurality of wafers 90 and is housed within the processing chamber 12. The wafer boat 14 may include at least two wafer boat pillars 16. Each wafer boat pillar 16 may include a plurality of slots 18. Each of the plurality of wafer supports 20 may include a support region 22 and a flange 24. A support region may be configured to support the circumferential edge 92 of at least one of a plurality of wafers 90. A flange 24 may circumferentially surround the support region 22. The flange 24 may be accommodated in and supported by slots 18. The flange 24 may have a width to establish a distance 28 between the circumferential edge 92 of this wafer 90 and the boat pillar 16 of the boat 14. This distance may be such that the boat pillar 16 does not substantially affect the layer thickness deposited on the wafer 90 during wafer 90 processing.

[0017] During deposition, a precursor gas may be supplied in the processing chamber 12. This precursor gas may be deposited on the wafer 90, forming a layer of deposited material thereon. The deposition of material on the wafer 90 may not always be uniform, meaning that the layer thickness may vary. Figures 2 and 3B show typical layer thickness profiles T1 and T2 above the wafer 90. The dimensions of the layer thicknesses shown in Figures 2 and 3B are not at the same scale as the diameter of the wafer 90 shown. Figure 2 shows a typical layer thickness profile above the wafer 90 being processed in the boat 14 without the shielding ring 62 present. During processing, the outer edge region 94 may have moved away from the boat support 16. As shown in Figure 2, edge effects may cause deposited material to accumulate at or near the wafer edge 92 in the outer edge region 94. Figure 3B shows a typical layer thickness profile above a wafer 90 being processed in boat 14, where two outer edge regions 94 may be adjacent to the pillars 16 of boat 14, in which the wafer 90 is placed during processing, as can be seen in Figure 3A. As shown in Figure 3B, the wafer pillars 16 can cause less material to be deposited near the boat pillars 16 on the wafer 90, resulting in a reduced layer thickness in the region adjacent to the boat pillars relative to other regions of the wafer 90 farther from the boat pillars 16. The combination of these two effects can be superimposed, causing various deviations in the layer thickness in the edge regions 94 and adjacent to the boat pillars 16.

[0018] To combat edge effects, known semiconductor substrate processing equipment may have a boat in which a wafer and a shielding ring are placed. The arrangement of this known boat may be similar to that shown in Figure 6. However, even in this arrangement, the edge effects described above may not be resolved throughout the entire process, and the layer thickness effect of the boat pillars 16 described above is also not resolved.

[0019] In the semiconductor substrate processing apparatus 10 disclosed herein, the flange 24 can establish a distance 28 between the circumferential edge 92 of the wafer 90 and the boat pillar 16. This results in the boat pillar 16 being further away from the circumferential edge 92 of the wafer 90 than in the boats of known semiconductor substrate processing apparatuses. The width can be selected such that a thicker portion of the deposited layer can be formed on the flange 24 of the wafer support 20, rather than on the outer edge region 92 of the wafer 90. Additionally, the undesirable effects of the boat pillar 16 on the thickness of the deposited layer adjacent to the boat pillar 16, as described above, can be reduced. This can lead to a more even distribution of the deposited material on the wafer 90 itself, thereby improving the quality of the wafer 90.

[0020] As shown in Figure 1, the semiconductor substrate processing apparatus 10 may include a wafer carrier chamber 32 located below the processing chamber 12. A wafer carrier 14 may be configured to transfer between the wafer carrier chamber 32 and the processing chamber 12. The wafer carrier chamber 32 may include a wafer handling robot 34 configured to transfer wafers 90 to and from the wafer carrier 14. An end effector 36 of the wafer handling robot 34 may be configured to engage the wafers 90.

[0021] In one embodiment, the width of the flange 24 used to establish a distance between the circumferential edge 92 of the wafer 90 and the boat pillar 16 may be in the range of 5 to 35 mm, preferably between 10 and 25 mm, and more preferably substantially 15 mm. This width of the flange 24 is sufficient to reduce the influence of the boat pillar 16 on the layer thickness.

[0022] In one embodiment, the distance 28 between the circumferential edge 92 of the wafer 90 and the boat pillar 16 can be in the range of 5 to 35 mm, preferably between 10 and 25 mm, and more preferably substantially 10 mm. This distance between the wafer 90 and the boat pillar 16 is sufficient to substantially reduce the influence of the boat pillar 16 on the layer thickness.

[0023] In one embodiment, as shown in Figure 4, the support region 22 may be closed, such that the wafer support 20 is substantially plate-shaped and capable of supporting the entire bottom surface 98 of the wafer 90. The wafer support 20 thus provides complete support for the wafer 90 and simultaneously shields the bottom surface 98 from any deposited material. Particularly in high process temperature applications, a fully supported wafer is preferred to prevent bending in the central block.

[0024] In one embodiment, one example is shown in Figure 5, the support region 22 may include a central opening 30, such that the wafer support 20 may be substantially annular. This wafer support 20 may have less material and may therefore be lighter and cheaper to manufacture than the plate-shaped wafer support 20 discussed above.

[0025] In one embodiment, the wafer support 20 having the wafer 90 may be removable from the boat 14. An end effector 36 or the like may be used to transport the wafer support 20. The end effector 36 may, for example, engage the bottom surface of the wafer support 20 and may transport the wafer support 20 together with the wafer 90.

[0026] In one embodiment, the wafer support 20 may comprise quartz. Quartz ensures that high purity is maintained while withstanding high temperatures, but does not react with the wafer 90 itself or introduce particles that may cause impurities in the deposited layer.

[0027] In one embodiment, the wafer support 20 may comprise silicon carbide (SiC). As quartz, silicon carbide may be a material with high temperature resistance.

[0028] In one embodiment, as shown in Figure 8, the wafer support 20 may include a thickened edge portion 25 forming a wafer capture edge 25'. This wafer capture edge 25' prevents a wafer 90 placed on the wafer support 20 from slipping off the wafer support 20 during handling by the wafer handling robot 34. The thickened portion 25 may be integrally formed with the flange 24 of the wafer support 20, but may also be formed by means of a split ring element attached to the upper surface of the wafer support 20.

[0029] This disclosure also provides another semiconductor substrate processing apparatus 10. The semiconductor substrate processing apparatus 50 may include a processing chamber 12, a boat 54, and a shielding ring 62. An example of the boat 54 in this embodiment is shown in Figures 6 and 7. The processing chamber 12 may be configured for batch processing of a plurality of wafers 90. The processing may include depositing a layer on each of the plurality of wafers 90. The boat 54 may be configured to accommodate a plurality of wafers 90 and is housed within the processing chamber 12. The boat 54 may include at least two boat supports 56. Each boat support 56 may include a plurality of slots 58, 60. The shielding ring 62 may be configured to be supported in the slots 58, 60 of the boat supports 56 above an associated wafer 90. The shielding ring 62 may shield the circumferentially outer edge region 94 at the upper surface 96 of the associated wafer 90. The circumferential outer edge region 94 may be annular, having a radial width, and extending circumferentially along the circumferential edge 92 of the wafer 90. Surface portions 64 and 65 of the shielding ring 62 may define a nominal surface area 66, which, if flat, is the surface area of ​​the surface portions 64 and 65. Surface portions 64 and 65 may have surface structures 70 providing an incremental surface area 68. The incremental surface area ratio may be defined by dividing the incremental surface area 68 of the surface portions 64 and 65 having surface structures 70 by the nominal surface area 66. The incremental surface area ratio may be greater than 1.5.

[0030] A solid surface may have an incremental surface area that differs from the nominal surface area 66. This is illustrated in Figure 7. The nominal surface area 66 may be a perfectly flat theoretical area. At the molecular scale, each solid surface may have a molecular or atomic topology or surface structure that constitutes the material forming the surface. This topology or surface structure determines the incremental surface area 68. This can mean that, for a solid surface, the incremental surface area ratio is greater than one.

[0031] Similar to the previous semiconductor substrate processing apparatus 10, due to edge effects, the thickness of the deposited layer in the outer edge region 94 of the wafer 90 can be thicker than in the more central portion of the wafer 90. Although a known shielding ring can shield the circumferentially outer edge region 94 at the upper surface 96 of the wafer 90, deposited material may still accumulate in this outer edge region 94. With the shielding ring 62 having an incremental surface area 68 and surface portions 64 and / or 65 according to this specification, this accumulation of deposited material can be reduced.

[0032] With the surface portions 64, 65 of the shielding ring 62 having an incremental surface area ratio of more than 1.5, more deposited material can be prevented from being deposited on the circumferential outer edge region 94 of the wafer 90. This can even result in no accumulation of deposited material on the circumferential outer edge region 94 of the wafer 90, and a uniform layer thickness is obtained over at least the entire upper surface of the wafer 90.

[0033] Due to the high incremental surface area ratio, the surface portions 64 and / or 65 having the incremental surface area 68 can have relatively high roughness, which can lead to more deposited material adhering to the surface portions 64 and / or 65 of the shielding ring 62 according to this specification, thus reducing edge effects.

[0034] Continued use of the shielding ring 62 during processing can cause the deposited material to smooth out the incremental surface area. This can result in a smaller incremental surface area ratio. To ensure a certain level of incremental surface area ratio, it may be necessary to periodically treat the surface portions 64, 65 of the shielding ring 64 that have the incremental surface area ratio. The surface portions 64 and / or 65 of the shielding ring 62 may be treated, for example, by an etching process to remove the deposited material from the shielding ring 62.

[0035] In one embodiment, the surface portion of the shielding ring 62 having the incremental surface area 68 may only include the upper surface 64 of the shielding ring 62.

[0036] In an alternative embodiment, the surface portion of the shielding ring 62 having an incremental surface area 68 may comprise only the lower surface 65 of the shielding ring 62.

[0037] In yet another alternative embodiment, the surface portion of the shielding ring 62 having the incremental surface area 68 may include both the upper surface 64 and the lower surface 65 of the shielding ring 62.

[0038] The choice of which of these three embodiments is made depends on the type of deposition process and the materials used. It is clear that the location of the incremental surface area 68 on the upper surface 64, the lower surface 65, or both can affect the edge effect and thus the layer thickness in the outer edge region 94 of the wafer 90.

[0039] In one embodiment, the incremental surface area ratio may be higher than 20, preferably higher than 50. This value of the incremental surface area ratio is sufficient to prevent the accumulation of any deposited material on the outer edge region 94 of the wafer 90.

[0040] In one embodiment, the surface structure 70 may include a coating that provides roughness. The coating may have a thickness between 500 nm and 5000 nm. This coating may provide an incremental surface area 68 having an incremental surface area ratio greater than 1.5, preferably greater than 20, and even more preferably greater than 50.

[0041] In one embodiment, the surface structure 70 may include a coating comprising hemispherical grains.

[0042] In one embodiment, the shielding ring 62 may be made of a construction material. The surface structure 70 may include geometries provided in the construction material to provide an incremental surface area having the incremental surface area ratio disclosed herein. For example, the surface portions 64, 65 of the shielding ring 62 having the incremental surface area 68 may be ground in a coarse grinding operation to provide the incremental surface area.

[0043] In one embodiment, the surface portions 64 and / or 65 having the incremental surface area 68 may include a coating comprising silicon dioxide (SiO2).

[0044] In one embodiment, the surface portions 64 and / or 65 of the shielding ring 62 having at least an incremental surface area 68 may comprise a porous material. The porous material may comprise, for example, porous silicon oxide.

[0045] In one embodiment, the shielding ring 92 may have a radial width selected such that the circumferentially outer edge region 94 shielded by the shielding ring 92 may have a width in the range of 10 mm to 30 mm. This radial width is sufficient to prevent the edge effects described above.

[0046] In one embodiment, as shown in Figure 5, the shielding ring 62 may simultaneously be a wafer support 20 including a support region 22 and a flange 24. The support region 22 may be configured to support the circumferential edge 92 of one of at least a plurality of wafers 90. The support region 22 may have a central opening 30 having a diameter smaller than the diameter of the wafer 90. The flange 24 may circumferentially surround the support region 22. The flange 24 may be receptacle-18 and supported by such receptacles. The flange 24 may have a width to establish a distance 28 between the circumferential edge 92 of this wafer 90 and the boat pillar 16 of the boat 14. The distance 28 may be such that the boat pillar 16 does not substantially affect the layer thickness of the layers deposited on the wafer 90 during the processing of the wafer 90.

[0047] Similar to the prior semiconductor substrate processing apparatus 10, the flange 24 can establish a distance 28 between the circumferential edge 92 of the wafer 90 and the boat support 16. This results in the boat support 16 being further away from the circumferential edge 92 of the wafer 90 than the boat in the known semiconductor substrate processing apparatus. The width can be selected such that a thicker portion of the deposited layer caused by the edge effect can be formed on the flange 24 of the wafer support 20, rather than on the outer edge region 92 of the wafer 90. This can lead to a more even distribution of the deposited material on the wafer 90 itself, thereby improving the quality of the wafer 90. The shielding ring 62 for the associated wafer 90 is also the wafer support 20 of the wafer 90 directly above the associated wafer 90. This shielding ring not only reduces edge effects due to the increased surface area of ​​the shielding ring 62, but also reduces the negative impact of the boat pillar 56 on the uniformity of layer thickness, because the flange 24 of the wafer support 20 / shielding ring 62 provides an increased distance between the circumferential edge 92 of the wafer 90 and the boat pillar 56.

[0048] Similarly, in a further description of this embodiment, one example is shown in Figure 8, where the wafer support 20 may include a thickened edge portion 25 forming a wafer capture edge 25'. This wafer capture edge 25' prevents the wafer 90 placed on the wafer support 20 from slipping off the wafer support 20 during handling by the wafer handling robot 34. The thickened portion 25 may be integrally formed with the flange 24 of the wafer support, but may also be formed by a split ring element connected to the upper surface of the wafer support 20.

[0049] In an alternative embodiment, one example is shown in Figure 6, according to the present disclosure, the shielding ring 62 may have surface portions 64 and / or 65 having an incremental surface area, and the shielding ring may be received in shielding ring slots 58 between wafers 90 in the boat 54, the shielding ring slots being positioned between wafer slots 60 of the boat pillars 56, the wafer slots being configured to receive wafers 90 in the boat 54.

[0050] In this manner, each wafer 90 can be shielded by a shielding ring 62 positioned directly above the wafer 90. In this embodiment, the shielding ring 62 does not function as a wafer support 20.

[0051] The advantage of the embodiment of Figure 5, in which the wafer support 20 also functions as a shielding ring 62 due to its increased surface area, is that more wafers 90 can be placed in the boat 18 with a certain height. This is because the end effector 36 requires a certain distance between subsequent items to be placed in the boat 16. When the wafers 90 are in the boat 56, the shielding ring 62 must be placed by means of the end effector 36, as in the example shown in Figure 6. Due to the increased surface area of ​​this shielding ring having an increased surface area ratio of more than 1.5, the distance between subsequent wafers 90 is inevitably greater than (as can be seen when comparing Figures 6 and 5) in the case where the wafer support 20 also functions as a shielding ring (as in Figure 5).

[0052] Although illustrative embodiments of the present disclosure have been described above in part with reference to the accompanying drawings, it should be understood that the present disclosure is not limited to these embodiments. Variations of the disclosed embodiments can be understood and practiced by those skilled in the art in the course of practicing the claimed invention by studying the drawings, the present disclosure, and the appended claims.

[0053] Throughout this specification, the reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment disclosed herein. Therefore, the appearance of the phrase "in one embodiment" or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment.

[0054] Furthermore, it should be noted that specific features, structures, or characteristics of one or more of the various embodiments described above can be implemented independently of each other and can be combined in any suitable manner to form new embodiments not explicitly described. The element symbols used in the implementation methods and claims do not limit the description of the embodiments or the scope of the claims. Element symbols are used only for clarification. [Simplified Explanation of the Diagram]

[0012] Although this specification concludes with a claim specifically pointed out and explicitly asserted as the right of the embodiments disclosed herein, the advantages of the embodiments disclosed herein can be more readily appreciated from the description of certain examples of the embodiments disclosed when read in conjunction with the accompanying drawings, in which: Figure 1 shows an example of a semiconductor substrate processing apparatus according to this specification; Figure 2 shows a schematic and exaggerated representation of the thickness of a layer deposited on a wafer, specifically at a cross-section through the wafer, which contains two edge regions of the wafer, these regions being remote from the supports of the wafer boat in which the wafer is placed during processing, wherein no shielding ring is present in the wafer boat during processing; Figure 3A shows a schematic cross-sectional view of an example of a known wafer boat in which a wafer is placed, specifically at a cross-section through the wafer supports of the wafer boat; Figure 3B shows a schematic and exaggerated representation of the thickness of the deposited layer on the wafer in the wafer boat when no shielding ring is used during processing, as depicted in Figure 3A along the shown cross-section through the wafer boat supports. Figure 4 shows a schematic cross-sectional view of an example of a wafer carrier with a wafer support and a wafer support placed therein; Figure 5 shows a schematic cross-sectional view of an example of a wafer carrier with a wafer support and a wafer placed therein; Figure 6 shows a schematic cross-sectional view of an example of a wafer carrier with a wafer and a shielding ring placed therein; Figure 7 shows a schematic representation of the nominal and incremental surface area of ​​a surface portion according to the specification, this surface portion having the incremental surface area of ​​the shielding ring; and Figure 8 shows a cross-sectional detail of the right side portion of the wafer support as shown in Figure 5.

Claims

1. A semiconductor substrate processing apparatus (10), comprising: A processing chamber (12) configured for batch processing of a plurality of wafers (90), wherein the processing includes depositing a layer on each of the wafers (90); a crystal boat (14) configured to accommodate the wafers (90) and receptacle within the processing chamber (12), the crystal boat (14) including at least two crystal boat pillars (16), each of the crystal boat pillars (16) including a plurality of slots (18); and a plurality of wafer supports (20), each of the wafer supports (20) including: A support region (22) configured to support a circumferential edge (92) of at least one of the wafers (90); and a flange (24) circumferentially surrounding the support region (22), wherein the flange (24) is receivable in and supported by the slots (18), wherein the flange (24) has a width to establish a distance (28) between the circumferential edge (92) of the wafer (90) and the boat pillars (16) of the boat (14), wherein the distance is such that the boat pillars (16) do not affect the thickness of one layer deposited on the wafer (90) during the processing of the wafer (90), wherein the support region (22) is closed such that the wafer support (20) is plate-shaped and capable of supporting an entire bottom surface (98) of a wafer (90).

2. The semiconductor substrate processing apparatus of claim 1, wherein the width of the flange (24) used to establish the distance between the circumferential edge (92) of the wafer (90) and the carrier pillars (16) is in the range of 5 mm to 35 mm.

3. The semiconductor substrate processing apparatus of claim 1 or 2, wherein the distance (28) between the circumferential edge (92) of the wafer (90) and the carrier pillars (16) is in the range of 5 mm to 35 mm.

4. The semiconductor substrate processing apparatus of claim 1, wherein the support region (22) includes a central opening (30) such that the wafer support (20) is annular.

5. The semiconductor substrate processing apparatus of claim 1, wherein the wafer support (20) having the wafer (90) is removable from the wafer boat (14).

6. The semiconductor substrate processing apparatus of claim 1, wherein the wafer support (20) includes a thickened edge portion (25) that forms a wafer capture edge (25').

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