Display device and method of manufacturing the same

Abstract

The present invention provides a display device comprising: a substrate; a pixel circuit layer located on the substrate; a first connection electrode and a second connection electrode located on the pixel circuit layer; a first bump and a second bump, the first bump being located on the first connection electrode and the second bump being located on the second connection electrode, the first bump and the second bump comprising materials having different elastic moduli; and a light-emitting element comprising a first electrode electrically connected to the first connection electrode and a second electrode electrically connected to the second connection electrode.

Description

Technical Field

[0001] Cross-reference to related applications:

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2021-0148194, filed on November 1, 2021, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

[0003] Aspects of the embodiments disclosed herein relate to a display device and a method of manufacturing the same.

Prior Art

[0004] With the increasing interest in information display and the demand for the use of portable information media, the demand and commercialization of display devices are being actively pursued.

Summary of the Invention

[0005] The present disclosure relates to a display device that exhibits improved bonding strength between a light-emitting element and a substrate, and a method of manufacturing the same.

[0006] A display device according to an embodiment of the present disclosure includes a substrate; a pixel circuit layer disposed on the substrate; a first connection electrode and a second connection electrode disposed on the pixel circuit layer; a first bump and a second bump, the first bump being disposed on the first connection electrode and the second bump being disposed on the second connection electrode; and a light-emitting element including a first electrode electrically connected to the first connection electrode and a second electrode electrically connected to the second connection electrode, wherein the first bump and the second bump include materials having different elastic moduli.

[0007] The elastic modulus of the first bump may be greater than the elastic modulus of the second bump.

[0008] The first bump and the second bump may include an organic material or a metal material.

[0009] The first bump may include a positive photoresist material, and the second bump may include a negative photoresist material.

[0010] A height of the second bump may be lower than a height of the first bump, and a diameter of the second bump may be greater than a diameter of the first bump.

[0011] The light-emitting element may include a semiconductor structure having a surface with different heights, and the semiconductor structure is configured to emit light, and the first electrode may be disposed on the surface of the semiconductor structure, and the second electrode may be disposed on the surface of the semiconductor structure at a position different from the first electrode.

[0012] The first electrode may be located at a lower horizontal height on the surface of the semiconductor structure, and the second electrode may be located at a higher horizontal height on the surface of the semiconductor structure.

[0013] The semiconductor structure may include a first semiconductor layer, an active layer on one side of the first semiconductor layer, and a second semiconductor layer on one side of the active layer, and a type of the second semiconductor layer may be different from that of the first semiconductor layer.

[0014] The pixel circuit layer may include a transistor on the substrate and a plurality of via layers on the transistor. The transistor may include a semiconductor pattern, a first source electrode, a first drain electrode, and a gate electrode, and the first drain electrode of the transistor may be electrically connected to the first connection electrode through a plurality of contact openings in the plurality of via layers.

[0015] The display device may further include a third connection electrode and a fourth connection electrode. The third connection electrode covers the first bump and at least partially overlaps the first connection electrode, and the fourth connection electrode covers the second bump and at least partially overlaps the second connection electrode.

[0016] The display device may further include an insulating film between the light-emitting element and the third connection electrode and the fourth connection electrode.

[0017] A display device according to an embodiment includes: a substrate, a pixel circuit layer located on the substrate, a via layer located on the pixel circuit layer; a first connection electrode and a second connection electrode located on the pixel circuit layer; a first bump located on the first connection electrode; a second bump located on the second connection electrode; and a light-emitting element including a first electrode electrically connected to the first connection electrode and a second electrode electrically connected to the second connection electrode. The first bump and the second bump include materials having different elastic moduli, and the second bump and the via layer include the same material.

[0018] The elastic modulus of the first bump may be greater than the elastic modulus of the second bump.

[0019] The via layer, the first bump, and the second bump may include an organic material.

[0020] A height of the second bump may be lower than a height of the first bump, and a diameter of the second bump may be greater than a diameter of the first bump.

[0021] The light-emitting element may include a semiconductor structure having a surface with different heights, and the semiconductor structure is configured to emit light, and the first electrode may be disposed on the surface of the semiconductor structure, and the second electrode may be disposed on the surface of the semiconductor structure at a position different from the first electrode.

[0022] The first electrode may be located at a lower horizontal height on the surface of the semiconductor structure, and the second electrode may be located at a higher horizontal height on the surface of the semiconductor structure.

[0023] According to an embodiment, a method of manufacturing a display device includes: providing a pixel circuit layer including a transistor on a substrate; providing a first connection electrode, a second connection electrode, a first bump, a second bump, and a via layer on the pixel circuit layer; disposing a light-emitting element including a first electrode and a second electrode on the substrate; and coupling the light-emitting element and the substrate such that the first electrode of the light-emitting element overlaps with the first bump, and the second electrode of the light-emitting element overlaps with the second bump, and the first bump and the second bump include materials having different elastic moduli.

[0024] Before the light-emitting element is coupled to the substrate, a height of the first bump may be the same as a height of the second bump.

[0025] After the light-emitting element and the substrate are coupled, the height of the first bump may be higher than the height of the second bump.

Embodiments

[0027] Although the present disclosure is open to various modifications and alternative embodiments, some of its embodiments will be described and illustrated by way of example in the drawings. However, it should be understood that the present disclosure is not intended to be limited to the embodiments of the present disclosure. On the contrary, the present disclosure covers all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

[0028] Although the terms "first", "second", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and similarly, the second element may also be referred to as the first element. Unless otherwise specified, the singular form of an expression means including multiple elements.

[0029] It can be understood that when an element or layer is referred to as "on", or "connected to", "coupled to" another element or layer, it can be directly on, connected or coupled to another element or layer, or one or more intermediate elements or layers may also exist. When an element or layer is referred to as "directly on" another element or layer, or "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. For example, when the first element is described as "coupled" or "connected" to the second element, the first element can be directly coupled or connected to the second element, or the first element can be indirectly coupled or connected to the second element through one or more intermediate elements.

[0030] In the figures, for clarity of illustration, the sizes of various elements, layers, etc. may be exaggerated. The same reference numerals represent the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. In addition, when describing the embodiments of this disclosure, "may" refers to "one or more embodiments of this disclosure". Expressions such as "at least one of" modify the entire list of elements before the list of elements, rather than modifying a single element in the list. As used herein, the terms "use", "using", and "used" may be respectively regarded as synonyms of the terms "utilize", "utilizing", and "utilized". As used herein, the terms "substantially", "about", and similar terms are used as approximators rather than metrics, and are used to explain inherent errors, measurements, calculations, and / or provide numerical values, and can be recognized by those of ordinary skill in the art to which the present invention pertains.

[0031] The terms used in this disclosure are for describing embodiments of the present disclosure and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are also intended to include the plural forms unless the context clearly indicates otherwise. It will be understood that when the terms "has", "having", "comprises", "comprising", "includes" and / or "including" are used in this specification, they specify the presence of the feature, integer, step, operation, element, component and / or combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0032] A display device according to an embodiment of the present disclosure will be described with reference to the drawings related to the embodiments of the present disclosure.

[0033] FIG. 1 is a schematic plan view showing a display device according to an embodiment, and FIG. 2 is a schematic cross-sectional view showing the display device shown in FIG. 1.

[0034] Referring to FIG. 1, a display device DD according to an embodiment may have a display area DA for displaying an image and a non-display area NDA for not displaying an image. The non-display area NDA may be provided on at least one side of the display area DA and may be provided to surround (for example, surround or extend around a periphery in a plan view) the display area DA. According to a plurality of embodiments, the shape of the display area DA and the position of the non-display area NDA may vary relatively.

[0035] The display device DD may be provided in a rectangular planar shape having angled corners, but according to an embodiment, the display device DD may be a rectangular planar shape having rounded corners. In addition, the present disclosure is not limited thereto, and the display device DD may be implemented in various shapes.

[0036] A display device DD according to an embodiment may be applied to an electronic device, wherein a display surface is applied to at least one of its surfaces, such as a smart phone, a television, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a medical device, a camera or a wearable device.

[0037] In addition, the display device DD of the embodiment may include a self-emitting display panel, for example, any one of a nano-scale or micro-scale light-emitting diode (LED) display panel, a quantum dot organic light-emitting display panel (QD OLED), etc.

[0038] The display device DD may include a substrate SUB and a plurality of pixels PXL disposed on the substrate.

[0039] The substrate SUB may constitute a base member of the display device DD. According to a plurality of embodiments, the substrate SUB may be a rigid or flexible substrate or a film, and there is no particular limitation on its material or its properties. As an example, the substrate SUB may be a rigid substrate made of (or including) glass or tempered glass, a flexible substrate (or film) made of (or including) plastic or metal, or at least one insulating film, but there is no particular limitation on its material and / or its physical properties.

[0040] A plurality of pixels PXL may be positioned in the display area DA, and the lines, pads, and drive circuits connected to the pixels PXL in the display area DA may be selectively positioned in the non-display area NDA. The pads may be provided on the first surface of the substrate SUB, and the side conductors may be provided on the first surface, the second surface opposite to the first surface, and one side surface between the first surface and the second surface of the substrate SUB, and the side conductors are connected to the pads. The first display device DD may further include connection lines and flexible films. The connection lines are provided on the second surface of the substrate SUB, the flexible films are connected to the connection lines through conductive adhesive members, and the side conductors may be connected to the connection lines.

[0041] Although only one pixel PXL is shown in FIG. 1, a plurality of pixels PXL may be substantially dispersed in the display area DA. For example, the pixels PXL may be arranged in an arrangement structure in the display area DA, such as a matrix or a stripe. However, the present disclosure is not limited thereto.

[0042] Referring to FIG. 2, the display device DD may include a pixel circuit layer PCL, a display element layer DPL, and a cover layer CVL, which are sequentially disposed on the substrate SUB.

[0043] The pixel circuit layer PCL may be disposed on the substrate SUB and may include transistors, capacitors, and signal lines connected to the transistors. For example, each transistor may have one of the following forms: a semiconductor pattern, a gate, a source, and a drain are sequentially stacked, and an insulating layer is inserted therebetween.

[0044] The display element layer DPL may be disposed on the pixel circuit layer PCL and may include light-emitting elements. For example, the light-emitting elements may be inorganic light-emitting elements or light-emitting elements that emit light by changing the wavelength of light using quantum dots.

[0045] The cover layer CVL may be disposed on the display element layer DPL. The cover layer CVL may be in the form of a packaging substrate or a packaging film that forms a multi-layer film. When the cover layer CVL is in the form of a packaging film, the cover layer CVL may have a form in which an inorganic film, an organic film, and an inorganic film are stacked in sequence. The cover layer CVL may prevent or substantially prevent external air and moisture from penetrating into the display element layer DPL and the pixel circuit layer PCL.

[0046] According to an embodiment, the cover layer CVL may include (or may be made of) a thermosetting resin and / or a photocurable resin, which is applied in a liquid form on the substrate SUB and then cured by a curing process using heat and / or light. In this embodiment, the cover layer CVL may protect the light-emitting elements and stably fix the light-emitting elements.

[0047] In addition, the CVL cover layer may include an anti-reflection (AR) film.

[0048] FIG. 3 shows a top view of a multi-screen display device that can be implemented using a display device according to an embodiment.

[0049] Referring to FIG. 3, the display device according to an embodiment may be a multi-screen display device TDD including a plurality of display devices.

[0050] The multi-screen display device TDD (also referred to as a tiled display) may include a plurality of display devices DD1, DD2, DD3, and DD4 arranged in a matrix along a first direction DR1 and a second direction DR2. Here, one display device DD1 may be the display device DD described in FIGS. 1 and 2, and each light-emitting element in the display device DD may be a flip chip type micro light-emitting diode.

[0051] The plurality of display devices DD1, DD2, DD3, and DD4 may display a single image or divide and display an image. The plurality of display devices DD1, DD2, DD3, and DD4 may include display panels having the same type, structure, size, or method, and a seam portion may be provided between the plurality of display devices DD1, DD2, DD3, and DD4, but the present disclosure is not limited thereto.

[0052] A plurality of display devices DD1, DD2, DD3, and DD4 can be physically coupled by a housing, which can be located below the plurality of display devices DD1, DD2, DD3, and DD4 to form a multi-screen display device TDD.

[0053] The plurality of display devices DD1, DD2, DD3, and DD4 can be implemented in various shapes. Although the plurality of display devices DD1, DD2, DD3, and DD4 are shown as having a rectangular plate shape in FIG. 3, the present disclosure is not limited thereto. The plurality of display devices DD1, DD2, DD3, and DD4 can have, for example, a circular or oval shape.

[0054] Hereinafter, the pixels included in the display device embodiment will be described with reference to FIG. 4.

[0055] FIG. 4 is a circuit diagram showing the electrical connection relationship of a pixel included in a display device according to an embodiment.

[0056] Referring to FIG. 4, a pixel PXL according to an embodiment may include a light-emitting unit EMU and a pixel circuit PXC. The light-emitting unit EMU is used to generate light having a brightness corresponding to a data signal, and the pixel circuit PXC is used to drive the light-emitting unit EMU.

[0057] The light-emitting unit EMU may include a light-emitting element LD connected between a first power line PL1 and a second power line PL2. The first power line PL1 applies the voltage of a first driving power source VDD, and the second power line PL2 applies the voltage of a second driving power source VSS.

[0058] The light-emitting element LD may include a second electrode EL2 connected to the first driving power source VDD through the first power line PL1 and a first electrode EL1 connected to the second driving power source VSS through the second power line PL2. In one embodiment, the first electrode EL1 may be a cathode, and the second electrode EL2 may be an anode.

[0059] The light-emitting element LD can emit light with a brightness corresponding to the driving current provided through the pixel circuit PXC, which will be described below. For example, within the period of each frame, the pixel circuit PXC can provide a driving current corresponding to the gradation value of the data of the corresponding frame to the light-emitting unit EMU. The driving current provided to the light-emitting unit EMU can flow into (or through) the light-emitting element LD, and the light-emitting element LD can emit light with a brightness corresponding to the driving current.

[0060] The pixel circuit PXC can be connected to the scan line Si and the data line Dj. When it is assumed that the pixel PXL is set in the display area DA at the i-th row and the j-th column (please refer to, for example, FIG. 1) (where i is a natural number and j is a natural number), the pixel circuit PXC can be connected to the i-th scan line Si and the j-th data line Dj in the display area DA.

[0061] In addition, the pixel circuit PXC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0062] The first transistor T1 can be a driving transistor for controlling the driving current applied to the light-emitting unit EMU, and can be connected between the light-emitting unit EMU and the second driving power supply VSS. For example, the first terminal of the first transistor T1 can be connected to the light-emitting unit EMU, the second terminal of the first transistor T1 can be connected to the second driving power supply VSS through the second power line PL2, and the gate of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of driving current flowing from the first driving power supply VDD to the light-emitting unit EMU according to the voltage applied to the first node N1. In one embodiment, the first terminal of the first transistor T1 can be the drain, and the second terminal of the first transistor T1 can be the source.

[0063] The second transistor T2 can be a switching transistor that selects and activates the pixel PXL in response to the scan signal applied to the scan line Si, and can be connected between the data line Dj and the first node N1. The first terminal of the second transistor T2 can be connected to the data line Dj, the second terminal of the second transistor T2 can be connected to the first node N1, and the gate of the second transistor T2 can be connected to the scan line Si.

[0064] When a scan signal having a gate conduction voltage (for example, a high-level voltage) is provided from (or through) the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj and the first node N1. The first node N1 can be the point where the second terminal of the second transistor T2 is connected to the gate of the first transistor T1, and the second transistor T2 can transmit a data signal to the gate of the first transistor T1.

[0065] One electrode of the storage capacitor Cst (e.g., the first storage electrode) STE1 can be connected to the second driving power supply VSS, and the storage capacitor Cst of the other electrode (e.g., the second storage electrode) STE2 can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal provided to the first node N1, and can hold the charging voltage until the data signal of the next frame is provided.

[0066] The present disclosure is not limited to the structure shown in FIG. 4, and the structure of the pixel circuit PXC can be changed differently. According to an embodiment, the pixel circuit PXC can further include a sensor transistor, an emission control transistor, a parasitic capacitor, etc. in addition to the transistors shown in FIG. 4.

[0067] Hereinafter, the light-emitting element described with reference to FIG. 4 will be described in more detail with reference to FIG. 5.

[0068] FIG. 5 shows a cross-sectional view of a light-emitting element in a display device according to an embodiment.

[0069] Referring to FIG. 5, the light-emitting element LD of the embodiment can include a semiconductor structure 10, a first electrode EL1, and a second electrode EL2.

[0070] The semiconductor structure 10 can emit light according to the recombination of electrons and holes of the current flowing between the first electrode EL1 and the second electrode EL2. By controlling the light emission of the light-emitting element LD using such a principle, the light-emitting element LD can be used as a light source (or light-emitting source) of various display devices (or light-emitting devices).

[0071] The first semiconductor layer 11 can include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 can be an n-type semiconductor layer including any one of semiconductor materials selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductivity type dopant (e.g., an n-type dopant), such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting (or forming) the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 can be made of (or can be formed by) various suitable materials. In an embodiment of the present disclosure, the first semiconductor layer 11 can include a gallium nitride (GaN) semiconductor material doped with a first conductivity type dopant (e.g., an n-type dopant).

[0072] The active layer 12 can be disposed on one side of the first semiconductor layer 11 and can form a single or multiple quantum well structures. For example, when the active layer 12 forms a multiple quantum well structure, the barrier layer, strain enhancing layer, and well layer can be periodically and repeatedly stacked as a unit in the active layer 12. The strain enhancing layer can have a smaller lattice constant than the barrier layer to further enhance the compressive strain applied to the well layer. However, the structure of the active layer 12 is not limited to the above embodiments and can vary according to the embodiments.

[0073] The active layer 12 can emit light with a wavelength in the range of about 400 nm to about 900 nm and can have a double heterostructure. In one embodiment, a clad layer doped with a conductivity type dopant can be formed on the upper and / or lower part of the active layer 12. For example, the composite layer can be formed as an AlGaN layer or an InAlGaN layer. According to the embodiments, materials such as AlGaN or InAlGaN can be used to form the active layer 12. In addition, various materials can constitute the active layer 12. The active layer 12 can have a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0074] The second semiconductor layer 13 can include a semiconductor layer having a type different from that of the first semiconductor layer 11. As an example, the second semiconductor layer 13 can include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 can include a p-type semiconductor layer including at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductivity type dopant (e.g., a p-type dopant), such as magnesium (Mg). However, the material constituting the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 can be made of various suitable materials. In one embodiment, the second semiconductor layer 13 can include a gallium nitride (GaN) semiconductor material doped with a second conductivity type dopant (e.g., a p-type dopant).

[0075] The second semiconductor layer 13 can be disposed on one side of the active layer 12 and can have an upper surface in contact with the active layer 12 and an upper surface in contact with the second electrode EL2. The second semiconductor layer 13 can provide holes to the active layer 12.

[0076] To form the semiconductor structure 10, the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be arranged in a structure stacked in sequence on a semiconductor substrate. Here, the semiconductor substrate may include a semiconductor material, such as a sapphire substrate or a silicon substrate. Such a semiconductor substrate may be used as a growth substrate for growing each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and then may be separated from the first semiconductor layer 11 through a substrate separation process. The substrate separation process may be a laser lift-off process, a chemical lift-off process, etc. Thus, since the growth semiconductor substrate 10 is removed from the semiconductor structure 10, the semiconductor structure 10 may have a thin thickness. In one embodiment, the semiconductor structure 10 may have dimensions on a microscopic scale, but the present disclosure is not limited thereto.

[0077] In one embodiment, the semiconductor structure 10 may include a mesa interface formed to have a surface with different heights and an inclined surface extending along at least a part of the surface. The mesa may be formed by performing an etching process to remove a part of each of the second semiconductor layer 13, the active layer 12, and the first semiconductor layer 11. Thus, the side surfaces of the active layer 12 and / or the second semiconductor layer 13 may be exposed to the outside. The etching process may be, for example, a dry etching process.

[0078] The first electrode EL1 may be disposed on one surface of the semiconductor structure 10. The first electrode EL1 may be located at a lower horizontal height on one surface of the semiconductor structure 10. For example, the first electrode EL1 may be positioned on the first semiconductor layer 11 so as to be electrically separated from the active layer 12 and the second semiconductor layer 13. In FIG. 5, the first electrode EL1 is shown as being disposed on a part of the upper surface of the first semiconductor layer 11, but the size of the first electrode EL1 may be modified differently. According to an embodiment, the edge of the first electrode EL1 may be arranged to be collinear with the edge of the first semiconductor layer 11.

[0079] In one embodiment, the first electrode EL1 may overlap a first bump (please refer to, for example, FIG. 7) to bond the light-emitting element LD.

[0080] The second electrode EL2 may be positioned on a surface of the semiconductor structure 10, and the second electrode EL2 may be located at a higher horizontal height on a surface of the semiconductor structure 10. For example, the second electrode EL2 may be located on the second semiconductor layer 13. In FIG. 5, the second electrode EL2 is shown as being disposed on a part of the upper surface of the second semiconductor layer 13, but the size of the second electrode EL2 may be modified differently. According to an embodiment, the position of the second electrode EL2 may completely overlap the upper surface of the second semiconductor layer 13.

[0081] In one embodiment, the second electrode EL2 may overlap the second bump (please refer to, for example, FIG. 7) to bond the light-emitting element LD.

[0082] The first electrode EL1 may be a contact electrode in ohmic contact with the first semiconductor layer 11, and the second electrode EL2 may be a contact electrode in ohmic contact with the second semiconductor layer 13. According to an embodiment, the first and second electrodes EL1 and EL2 may be Schottky contact electrodes.

[0083] The first electrode EL1 and the second electrode EL2 may include a conductive material. For example, the first electrode EL1 and the second electrode EL2 may include an opaque metal, including: chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni) and their oxides or alloys alone or in combination. According to an embodiment, the first electrode EL1 and the second electrode EL2 may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO).

[0084] Hereinafter, the detailed structure of a display device according to an embodiment will be described with reference to FIGS. 6 and 7.

[0085] FIGS. 6 and 7 show schematic cross-sectional views of pixels included in a display device according to an embodiment.

[0086] Please refer to FIGS. 6 and 7. According to an embodiment, a pixel PXL included in a display device may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

[0087] The substrate SUB may be a base layer, or a rigid substrate or a flexible substrate. For example, when the substrate SUB is rigid, the substrate SUB may be implemented as a glass substrate, a quartz substrate, a glass-ceramic substrate, a crystal glass substrate, etc. When the substrate SUB is flexible, the substrate SUB may be implemented as an organic polymer substrate, including: polyimide, polyamide, etc., a plastic substrate, etc.

[0088] The pixel circuit layer PCL is disposed on the substrate SUB.

[0089] The pixel circuit layer PCL may include one or more transistors and a plurality of lines connecting them. In addition, the pixel circuit layer PCL includes: a buffer layer BFL, a plurality of insulating layers GI1, GI2, ILD, INS1, INS2, and INS3, and a plurality of via layers VIA1, VIA2, and VIA3, which are stacked in sequence on one surface of the substrate SUB.

[0090] The buffer layer BFL is located on the substrate SUB to cover the substrate SUB. The buffer layer BFL can prevent or substantially prevent impurities from diffusing into the pixel circuit layer PCL from the outside. The buffer layer BFL may include at least one selected from metal oxides, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). According to an embodiment, the buffer layer BFL may be omitted. In addition, a lower metal layer may be located between the substrate SUB and the buffer layer BFL.

[0091] The transistor TR may include a semiconductor pattern ACT, a gate GAT, a first source TE1, and a first drain TE2.

[0092] The semiconductor pattern ACT is located on the buffer layer BFL. The semiconductor pattern ACT may include a channel region, a source region, and drain regions located on both sides (e.g., opposite sides) of the channel region. The source region of the semiconductor pattern ACT may be electrically connected to the first source TE1, and its drain region may be electrically connected to the first source TE2. For example, the source region and the drain region may be extended to be electrically connected to electrodes of other layers through contact openings (e.g., contact holes).

[0093] The semiconductor pattern ACT may include at least one semiconductor selected from polysilicon, amorphous silicon, and oxides.

[0094] Among the plurality of insulating layers GI1, GI2, ILD, INS1, INS2, and INS3, the first gate insulating layer GI1 is disposed on the semiconductor pattern ACT and the buffer layer BFL, and the first gate insulating layer GI1 covers the semiconductor pattern ACT and the buffer layer BFL.

[0095] The first gate insulating layer GI1 may include an inorganic material. For example, the first gate insulating layer GI1 may include at least one selected from silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiO xN y), and aluminum oxide (AlO x). According to an embodiment, the first gate insulating layer GI1 may include an organic material.

[0096] The gate GAT is located on the first gate insulating layer GI1. The gate GAT may be positioned to overlap with the channel region of the semiconductor pattern ACT.

[0097] The first capacitor electrode CE1 may be positioned on the first gate insulating layer GI1. The first capacitor electrode CE1 may form a capacitor C together with the second capacitor electrode CE2, which will be described below.

[0098] Among the plurality of insulating layers GI1, GI2, ILD, INS1, INS2, and INS3, the second gate insulating layer GI2 is disposed on the gate GAT and the first gate insulating layer GI1, and the second gate insulating layer GI2 covers the gate GAT and the first gate insulating layer GI1.

[0099] The second gate insulating layer GI2 may include the same material as the first gate insulating layer GI1, and may include, for example, at least one selected from silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiO xN y), and aluminum oxide (AlO x).

[0100] The second capacitor electrode CE2 may be positioned on the second gate insulating layer GI2.

[0101] Among the plurality of insulating layers GI1, GI2, ILD, INS1, INS2, and INS3, an interlayer insulating layer ILD is disposed on the second gate insulating layer GI2. The interlayer insulating layer ILD covers the second gate insulating layer GI2 and the second capacitor electrode CE2, and the interlayer insulating layer ILD may include the same material as the second gate insulating layer GI2, and may include an inorganic material or an organic material.

[0102] The first source electrode TE1 and the first drain electrode TE2 are disposed on the interlayer insulating layer ILD. In some specific embodiments, the first source electrode TE1 may be the same component as the second terminal of the first transistor T1 shown in FIG. 4, and the first drain electrode TE2 may be the same component as the first terminal of the first transistor T1.

[0103] The first drain TE2 can be electrically connected to the first electrode EL1 of the light-emitting element LD1 in the first via layer through the first contact opening (e.g., the first contact hole) CH1 of the first via layer VIA1 (e.g., the first contact hole). The first bridge electrode BRD1 and the second contact opening (e.g., the second contact hole) CH2 are in the second via layer VIA2, and the second bridge electrode BRD2, the third contact opening (e.g., the third contact hole) CH3 in the third via layer VIA3, the first connection electrode CNE1, and the third connection electrode CNE3. Therefore, the transistor TR can transfer the voltage of the second driving power supply VSS (please refer to, for example, FIG. 4) to the first electrode EL1.

[0104] Among the multiple via layers VIA1, VIA2, and VIA3, the first via layer 1 is disposed on the first source electrode TE1, the first drain TE2, and the interlayer insulating layer ILD, and the first via layer VIA1 covers the first source electrode TE1, the first drain TE2, and the interlayer insulating layer ILD.

[0105] The first via layer VIA1 may include at least one organic insulating layer. The first via layer VIA1 may be a single-layer or multi-layer structure and may include an inorganic insulating material or an organic insulating material. For example, the first via layer VIA1 may include at least one selected from acrylic resins, epoxy resins, phenolic resins, polyamide resins, and polyimide resins.

[0106] The first drain TE2 and the first bridge electrode BRD1 may be physically and / or electrically connected together through the first contact opening CH1 in the first via layer 1.

[0107] Among the multiple insulating layers GI1, GI2, ILD, INS1, INS2, and INS3, the first insulating layer INS1 is disposed on the first insulating layer through VIA1. The first insulating layer INS1 may include an inorganic material. For example, the first insulating layer INS1 may include at least one selected from silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxy), and aluminum oxide (AlOx). According to an embodiment, the first insulating layer INS1 may include an organic material. The first drain TE2 and the first bridge electrode BRD1 may be physically and / or electrically interconnected through the first contact opening CH1 in the first insulating layer INS1.

[0108] The first bridge electrode BRD1 is located on the first insulating layer INS1.

[0109] Among the multiple via layers VIA1, VIA2, and VIA3, the second via layer VIA2 is disposed on the first insulating layer INS1 and the first bridge electrode BRD1. The second via layer VIA2 can include the same material as the first via layer VIA1. For example: The second via layer VIA2 can include at least one selected from acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0110] The first bridge electrode BRD1 and the second bridge electrode BRD2 can be physically and / or electrically connected to each other through the second contact opening CH2 in the second via layer VIA2.

[0111] Among the multiple insulating layers GI1, GI2, ILD, INS1, INS2, and INS3, the second insulating layer INS2 is disposed on the second via layer VIA2. The second insulating layer INS2 can include the same material as the first insulating layer INS1. For example: The second insulating layer INS2 can include at least one selected from silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). According to an embodiment, the second insulating layer INS2 can include an organic material.

[0112] The first bridge electrode BRD1 and the second bridge electrode BRD2 can be physically and / or electrically connected to each other through the second contact opening CH2 in the second insulating layer INS2.

[0113] The second bridge electrode BRD2 is located on the second insulating layer INS2. In addition, the drive voltage line DVL is located on the second insulating layer INS2.

[0114] Among the multiple via layers VIA1, VIA2, and VIA3, the third via layer VIA3 is disposed on the second insulating layer INS2, the second bridge electrode BRD2, and the drive voltage line DVL. The third via layer VIA3 can include the same material as the second via layer VIA2. For example: The third via layer VIA3 can include at least one selected from acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0115] As described below, the second bridge electrode BRD2 and the first connection electrode CNE1 can be physically and / or electrically connected to each other through the third contact opening CH3 in the third via layer VIA3. In addition, the drive voltage line DVL and the second connection electrode CNE2, which will be described below, can be physically and / or electrically connected to each other through the fourth contact opening (e.g., the fourth contact hole) CH4 through the third layer VIA3.

[0116] Among the multiple insulating layers GI1, GI2, ILD, INS1, INS2, and INS3, the third insulating layer INS3 is disposed on the third layer through VIA3. The third insulating layer INS3 may include the same material as the second insulating layer INS2. For example, the third insulating layer INS3 may include at least one selected from silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). According to an embodiment, the third insulating layer INS3 may include an organic material.

[0117] The display element layer DPL may include connection electrodes CNE1, CNE2, CNE3, and CNE4, a fourth via layer VIA4, a fourth insulating layer INS4, a first bump BUM1, a second bump BUM2, a light-emitting element LD, and an insulating film FIL.

[0118] The connection electrodes CNE1, CNE2, CNE3, and CNE4 may include a first connection electrode CNE1, a second connection electrode CNE2, a third connection electrode CNE3, and a fourth connection electrode CNE4.

[0119] The first connection electrode CNE1 may be positioned on the pixel circuit layer PCL. The first connection electrode CNE1 may be physically and / or electrically connected to the second bridge electrode BRD2 through a third contact opening CH3 in the third insulating layer INS3 and the third via layer VIA3.

[0120] The second connection electrode CNE2 may be located on the pixel circuit layer PCL and may be coplanar with the first connection electrode CNE1. The second connection electrode CNE2 may be physically and / or electrically connected to the driving voltage line DVL through a fourth contact opening CH4 in the third insulating layer INS3 and the third via layer VIA3, and the driving voltage line DVL may correspond to (or may be) a part of the first power line PL1 described with reference to FIG. 4.

[0121] The first connection electrode CNE1 and the second connection electrode CNE2 may be formed to include (or be made of) one of the groups selected from copper (Cu), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), and alloys or mixtures thereof, or may have a bilayer or multilayer structure including copper (Cu), titanium (Ti), aluminum (Al), silver (Ag), or gold (Au) to reduce the line resistance. For example, the first connection electrode CNE1 and the second connection electrode CNE2 may have a three-layer structure in which titanium (Ti), aluminum (Al), and titanium (Ti) are stacked in sequence.

[0122] The third connection electrode CNE3 may be positioned on the first connection electrode CNE1 and the first bump BUM1. The third connection electrode CNE3 may at least partially overlap with the first connection electrode CNE1 and may be positioned to cover the first bump BUM1. The third connection electrode CNE3 may directly contact the first electrode EL1 of the light-emitting element LD and may be physically and / or electrically connected to the first electrode EL1 of the light-emitting element LD. Therefore, the third connection electrode CNE3 may electrically connect the first electrode EL1 and the first connection electrode CNE1, and the first electrode EL1 may receive a driving current of the second driving power supply VSS from the driving transistor of the pixel circuit layer PCL (please refer to, for example, FIG. 4).

[0123] The fourth connection electrode CNE4 may be positioned on the second connection electrode CNE2 and the second bump BUM2. The fourth connection electrode CNE4 may at least partially overlap with the second connection electrode CNE2 and may be positioned to cover the second bump BUM2. The fourth connection electrode CNE4 may directly contact the second electrode EL2 of the light-emitting element LD and may be physically and / or electrically connected to the second electrode EL2 of the light-emitting element LD. Therefore, the fourth connection electrode CNE4 may electrically connect the second electrode EL2 and the second connection electrode CNE2, and the second electrode EL2 may receive a voltage of the first driving power supply VDD from the driving voltage line DVL of the pixel circuit layer PCL (please refer to, for example, FIG. 4).

[0124] The third connection electrode CNE3 and the fourth connection electrode CNE4 may include a transparent conductive oxide, such as: ITO, IZO, ZnO, IGZO, or ITZO. However, the present disclosure is not limited thereto. According to an embodiment, the third connection electrode CNE3 and the fourth connection electrode CNE4 may include an opaque metal, such as magnesium (Mg), aluminum (Al), silver (Ag), gold (Au), copper (Cu), tin (Sn), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and their oxides or alloys alone or in combination.

[0125] The fourth via layer VIA4 (or via layer) may be provided on the pixel circuit layer PCL.

[0126] The fourth via layer VIA4 may be an organic insulating film including an organic material. For example: The fourth via layer VIA4 may include at least one selected from acrylic resins (such as polyacrylate resins), epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, polyphenylene sulfide resins, and benzocyclobutene resins. However, the present disclosure is not limited thereto, and the fourth via layer VIA4 may include an inorganic material.

[0127] In addition, in one embodiment, the fourth via layer VIA4 may be a black pixel definition layer, made of (or comprising) a negative photoresist material. In one embodiment, the fourth via layer VIA4 may include the same organic material as the second bump BUM2, which will be described below.

[0128] The fourth insulating layer INS4 may be positioned on the fourth via layer VIA4 to cover the fourth via layer VIA4. The fourth insulating layer INS4 may include an inorganic material. For example: The fourth insulating layer INS4 may include at least one selected from metal oxides such as silicon oxide (SiO x), silicon nitride (SiN x), silicon oxynitride (SiO xN y), and aluminum oxide (AlO x). However, the present disclosure is not limited thereto, and the fourth insulating layer INS4 may include an organic material.

[0129] The first bump BUM1 may be positioned on the first connection electrode CNE1.

[0130] The second bump BUM2 may be positioned on the second connection electrode CNE2.

[0131] The first bump BUM1 may have a semi - lunar elliptical shape, long (e.g., extending in the third direction DR3) in a cross - sectional view. Thus, the shape of the third connection electrode CNE3 covering the first bump BUM1 may correspond to the shape of the first bump BUM1. For example: In one embodiment, the third connection electrode CNE3 may have a long semi - lunar elliptical shape in a cross - sectional view. However, the present disclosure is not limited thereto, and the shape of the first bump BUM1 may be modified differently. In one embodiment, the height hh1 of the first bump BUM1 may be in the range of about 1.5 μm to about 3 μm, and the diameter dd1 of the first bump BUM1 may correspond to the range of about 3 μm to about 6 μm.

[0132] The second bump BUM2 may have a semi - lunar elliptical shape and is very long in the third direction DR3 in the cross - sectional view. Thus, the shape of the fourth connection electrode CNE4 covering the second bump BUM2 can correspond to the shape of the second bump BUM2. For example, in one embodiment, the fourth connection electrode CNE4 may have a long semi - lunar elliptical shape in the cross - sectional view. However, the present disclosure is not limited thereto, and the shape of the second bump BUM2 can be modified differently. In an embodiment, the height hh2 of the second bump BUM2 coupled to the light - emitting element LD may be less than the height hh1 of the first bump BUM1, but the diameter dd2 of the second bump BUM2 may be greater than the diameter dd1 of the first bump BUM1. In one embodiment, the height hh2 of the second bump BUM2 may be in the range of about 1.5 μm to about 3 μm, and the diameter dd2 of the second bump BUM2 may be in the range of about 3 μm to about 6 μm.

[0133] The first bump BUM1 may include an organic material. For example, the first bump BUM1 may include a positive photoresist material. However, the present disclosure is not limited thereto, and according to an embodiment, the first bump BUM1 may include a metal material.

[0134] The second bump BUM2 may include an organic material different from that of the first bump BUM1. For example, the second bump BUM2 may include a negative photoresist material. However, the present disclosure is not limited thereto, and according to an embodiment, the second bump BUM2 may include a metal material having an elastic modulus less than that of the first bump BUM1. In addition, the second bump BUM2 may include various organic materials having an elastic modulus less than that of the first bump BUM1.

[0135] In one embodiment, the second bump BUM2 may include the same material as the fourth via layer VIA4. However, the present disclosure is not limited thereto, and the second bump BUM2 may include a material different from the fourth via layer VIA4. The materials constituting the first bump BUM1 and the second bump BUM2 will be described in detail below with reference to FIGS. 8 to 17.

[0136] In one embodiment, the first bump BUM1 may include a material having a modulus of elasticity greater than that of the second bump BUM2. Thus, even when the same pressure is applied to the first bump BUM1 and the second bump BUM2, the second bump BUM2 may be more deformed than the first bump BUM1. That is, under the same load or pressure, the amount of deformation of the second bump BUM2 may be greater than that of the first bump BUM1. Therefore, when the light-emitting element LD is coupled to the substrate SUB such that the first electrode EL1 and the second electrode EL2 face downward in the third direction DR3, since the second bump BUM2 in contact with the second electrode EL2 is more deformed than the first bump BUM1, although there is a height difference (or step difference) between the first electrode EL1 and the second electrode EL2, the contact resistance between the light-emitting element LD and the pixel circuit layer PCL (or circuit board or substrate) can be reduced. Therefore, the bonding force between the light-emitting element LD and the substrate can be improved (or strengthened).

[0137] The light-emitting element LD may be positioned on the third connection electrode CNE3 and the fourth connection electrode CNE4. In one embodiment, the light-emitting element LD may be positioned such that the first electrode EL1 and the second electrode EL2 face the third connection electrode CNE3 and the fourth connection electrode CNE4, respectively, in the third direction DR3. Since the semiconductor structure 10 of the light-emitting element LD includes a mesa-type interface, the first electrode EL1 and the second electrode EL2 may have different heights.

[0138] The first electrode EL1 of the light-emitting element LD may be in direct contact with the third connection electrode CNE3 and may overlap with the first bump BUM1.

[0139] The second electrode EL2 of the light-emitting element LD may be in direct contact with the fourth connection electrode CNE4 and may overlap with the second bump BUM2.

[0140] The insulating film FIL may be disposed on the fourth insulating layer INS4, the third connection electrode CNE3, and the fourth connection electrode CNE4.

[0141] The insulating film FIL may be located between the light-emitting element LD and the circuit board. Here, the circuit board may refer to the substrate SUB, the pixel circuit layer PCL, and a part of the display element layer DPL.

[0142] For example, the insulating film FIL may be located between the light-emitting element LD and the third and fourth connection electrodes CNE3 and CNE4. More specifically, the insulating film FIL may be located between the light-emitting element LD and the third connection electrode CNE3 to couple the light-emitting element LD and the circuit board, and may be disposed between the light-emitting element LD and the fourth connection electrode CNE4 to couple the light-emitting element LD and the circuit board.

[0143] In one embodiment, the insulating film FIL may be a non-conductive film (NCF). However, the present disclosure is not limited thereto, and the insulating film FIL may include (or may be made of) an insulating material and may correspond to various materials having adhesiveness.

[0144] In the display device according to an embodiment, the light-emitting element LD may be stably coupled to the circuit board through the first bump BUM1, the second bump BUM2, the third connection electrode CNE3, the fourth connection electrode CNE4, and the insulating film FIL.

[0145] Hereinafter, the materials constituting the first bump BUM1 and the second bump BUM2 will be described in more detail with reference to FIGS. 8 to 17 of FIG. 7.

[0146] FIG. 8 is a diagram illustrating an experiment for determining the physical properties of the materials of the pixels forming the first bump and the second bump according to an embodiment, FIG. 9 is a graph illustrating the experimental results related to FIG. 8, FIG. 10 is a table illustrating the experimental results related to FIG. 8, FIG. 11 is a diagram illustrating an experiment for determining the physical properties of the materials of the pixels forming the first bump and the second bump according to an embodiment, FIG. 12 is a graph illustrating the experimental results related to FIG. 11, FIG. 13 is a table illustrating the experimental results related to FIG. 11, FIG. 14 is a diagram illustrating an experiment for determining the physical properties of the materials of the pixels forming the first bump and the second bump according to an embodiment, FIG. 15 is a graph illustrating the experimental results related to FIG. 14, FIG. 16 is a table illustrating the experimental results related to FIG. 14, and FIG. 17 is a graph illustrating the relationship between the indentation depth and the load of the pixels formed of the materials forming the first bump and the second bump according to an embodiment.

[0147] First, referring to FIGS. 8 to 16, the materials for forming the first bump and the second bump pixels according to an embodiment can be divided into a first embodiment, a second embodiment, and a third embodiment. The materials for each embodiment can be positioned on a base layer BSL (refer to, for example, FIGS. 8, 11, and 14) as a bump layer BUML. For example, in the first experiment, the bump layer BUML can be set as the bump layer of the first embodiment and can be positioned on the base layer BSL. In the second experiment, the bump layer BUML can be set as the bump layer of the second embodiment and can be positioned on the base layer BSL. And in the third experiment, the bump layer BUML can be set as the bump layer of the third embodiment and can be positioned on the BSL base layer. Here, the base layer BSL can be made of glass, and the bump layer BUML can be a single layer.

[0148] Referring to FIG. 8, an object 810 having an inverted triangular shape (or having an inverted triangular cross-sectional shape) in a cross-sectional view is placed on the bump layer BUML. Thereafter, a reference pressure (e.g., a predetermined pressure) can be applied to the object 810 to measure the indentation depth according to the load applied to the bump layer BUML.

[0149] Referring to FIG. 11, an object 1110 having a circular shape in a cross-sectional view is placed on the bump layer BUML. Thereafter, a reference pressure (e.g., a predetermined pressure) can be applied to the object 1110 to measure the indentation depth according to the load applied to the bump layer BUML.

[0150] Referring to FIG. 14, an object 1410 having a cylindrical shape is positioned on the bump layer BUML. Thereafter, a reference pressure (e.g., a predetermined pressure) can be applied to the object 1410 to measure the indentation depth according to the load applied to the BUML bump layer.

[0151] The contact area between the upper surface of the bump layer BUML having an inverted triangular shape and the object 810 having an inverted triangular shape can be smaller than the contact area between the upper surface of the bump layer BUML having a circular shape and the object 1110. The contact area between the upper surface of the bump layer BUML having a circular shape and the object 1110 can be smaller than the contact area between the upper surface of the bump layer BUML having a cylindrical shape and the object 1410.

[0152] The first embodiment can correspond to the material for forming the first bump BUM1. For example, the first embodiment can correspond to a positive photoresist material in a material using polyimide as an adhesive.

[0153] The second and third embodiments may correspond to the materials constituting the second bump BUM2. For example: The second embodiment and the third embodiment may correspond to using cardo acrylate in a negative photoresist material as the material for the binder. The second and third embodiments may correspond to the black pixel defining film, and may correspond to the material that transmits different wavelengths of light (e.g., light of different wavelengths) according to the initiator. The black pixel defining film may refer to a black organic layer. When the organic layer corresponds to the pixel defining film included in the display element layer, the display element layer may include the black pixel defining film.

[0154] The second embodiment may transmit short wavelengths (e.g., about 365 nm), and the third embodiment may transmit short and long wavelengths (e.g., about 400 nm).

[0155] The materials constituting the first, second, and third embodiments in this disclosure are not limited to the above embodiments. According to the embodiment, when the material constituting the first embodiment is an organic material, that is, a material having an elastic modulus greater than that of the materials constituting the second and third embodiments, this material may correspond to the materials constituting the first bump BUM1 and the second bump BUM2.

[0156] Therefore, referring to FIG. 9, when the bump layer of BUML corresponds to the first embodiment, even when the same load (or pressure) is applied, the indentation depth may be shallower compared to the second and third embodiments. For example: Referring to FIG. 10, the hardness and elastic modulus of the first embodiment may be greater than those of the second embodiment, and the hardness and elastic modulus of the second embodiment may be greater than those of the third embodiment. In addition, when a load of 0.2 mN is applied, the first embodiment may have an indentation depth of about 0.14 μm, and when a load of 0.2 mN is applied, the second and third embodiments may have an indentation depth of about 0.16 μm. In the case of the experiment described with respect to FIG. 8, the results of the second embodiment may be similar to those of the third embodiment. In one embodiment, when the bump layer BUML corresponds to the first embodiment, even when the same load is applied, the value of its elastic strain is less than that of the second and third embodiments (e.g., the elastic modulus is greater than that of the second and third embodiments), and with respect to the same pressure, the deformation amount of the second bump BUM2 may be greater than that of the first bump BUM1. Therefore, since the second bump BUM2 in contact with the second electrode EL2 deforms more than the first bump BUM1, the contact resistance between the light-emitting element LD and the pixel circuit layer PCL (or circuit board or substrate) can be reduced. Therefore, the bonding force between the light-emitting element LD and the substrate can be improved (or strengthened).

[0157] Referring to FIG. 12, when the BUML buffer layer corresponds to the first embodiment, even when the same load (or pressure) is applied, the indentation depth may be shallower compared to the second and third embodiments. For example: Referring to FIG. 13, when a load of 0.2 mN is applied, the first embodiment may have an indentation depth of approximately 0.11 μm, and when a load of 0.2 mN is applied, the second and third embodiments may have an indentation depth of approximately 0.13 μm. In the case of the experiment described with respect to FIG. 11, the results of the second and third embodiments may be similar. In one embodiment, when the bump layer BUML corresponds to the first embodiment, even when the same load is applied, its elastic strain value is less than the elastic strain values of the second and third embodiments (for example: the elastic modulus has a value greater than that of the second and third embodiments), and with respect to the same pressure, the deformation amount of the second bump BUM2 may be greater than the deformation amount of the first bump BUM1. Therefore, since the second bump BUM2 in contact with the second electrode EL2 deforms more than the first bump BUM1, even though there is a height difference (or step difference) between the first electrode EL1 and the second electrode EL2, the contact resistance between the light-emitting element LD and the pixel circuit layer PCL (or circuit board or substrate) can be reduced. Therefore, the bonding force between the light-emitting element LD and the substrate can be strengthened.

[0158] Referring to FIG. 15, when the bump layer BUML corresponds to the first embodiment, even when the same load (or pressure) is applied, the indentation depth may be shallower compared to the second and third embodiments. Further, when the bump layer BUML corresponds to the second embodiment, even when the same load (or pressure) is applied, the indentation depth may be shallower compared to the third embodiment. For example: Referring to FIG. 16, when a load of 1 mN is applied, the first embodiment may have an indentation depth of about 0.03 μm, when a load of 1 mN is applied, the second embodiment may have an indentation depth of about 0.06 μm, and when a load of 1 mN is applied, the third embodiment may have an indentation depth of about 0.08 μm. In one embodiment, when the bump layer BUML corresponds to the first embodiment, even when the same load is applied, the elastic strain value is greater than the elastic strain values of the second and third embodiments (e.g., the elastic modulus has a value less than that of the second and third embodiments), and with respect to the same pressure, the deformation amount of the second bump BUM2 may be greater than the deformation amount of the first bump BUM1. Therefore, since the second bump BUM2 in contact with the second electrode EL2 deforms more than the first bump BUM1, the contact resistance between the light-emitting element LD and the pixel circuit layer PCL (or circuit board or substrate) can be reduced despite the height difference (or step difference) between the first electrode EL1 and the second electrode EL2. Therefore, the bonding force between the light-emitting element LD and the substrate can be improved (or strengthened).

[0159] Referring to FIG. 17, the materials for forming the first and second bump pixels according to the embodiments can be classified into a first embodiment, a second embodiment, a third embodiment, and a fourth embodiment. The first, second, and third embodiments can be the same as the above-described first, second, and third embodiments. Refer to FIGS. 8 to 16.

[0160] The fourth embodiment can correspond to the material BUM2 forming the second bump. For example: The fourth embodiment can correspond to a material using cardo acrylate and epoxy resin in a negative photoresist material as an adhesive. The fourth embodiment can correspond to the black pixel defining film and can correspond to a material that transmits different wavelengths according to the initiator. For example: The fourth embodiment can transmit short wavelengths (e.g., about 350 nm).

[0161] When the first bump BUM1 corresponds to the first embodiment, even when the same load is applied, the indentation depth may be shallower compared to the second bump BUM2 corresponding to the fourth embodiment. For example, when a load of 2 mN or less is applied to the first bump BUM1 and the second bump BUM2, the indentation depth of the first embodiment (the first bump BUM1) is shallower than that of the fourth embodiment (the second bump BUM2). Therefore, in one embodiment, when the bump layer BUML corresponds to the first embodiment, even when the same load is applied, the elastic strain value is smaller than that of the fourth embodiment (for example, the elastic modulus value is greater than the elastic strain value of the fourth embodiment), and for the same pressure, the deformation amount of the second bump BUM2 can be greater than that of the first bump BUM1. Therefore, since the second bump BUM2 in contact with the second electrode EL2 deforms more than the first bump BUM1, even though there is a height difference (or step difference) between the first electrode EL1 and the second electrode EL2, the contact resistance between the light-emitting element LD and the pixel circuit layer PCL (or the circuit board or the substrate) can be reduced. Therefore, the bonding force between the light-emitting element LD and the substrate can be improved (or strengthened).

[0162] Hereinafter, a method for manufacturing a display device according to an embodiment will be described with reference to FIGS. 18 to 20.

[0163] FIGS. 18 to 20 are cross-sectional views sequentially showing the steps of a method for manufacturing a display device according to an embodiment.

[0164] Referring to FIG. 18, a display device according to an embodiment may include pixels, where the pixel circuit layer PCL includes forming a transistor TR on a substrate, and first to fourth connection electrodes CNE1, CNE2, CNE3, and CNE4, a first bump BUM1, a second bump BUM2, a fourth via layer VIA4 (or via layer), and a fourth insulating layer INS4 are provided on the pixel circuit layer PCL.

[0165] The first bump BUM1 may be provided on the first connection electrode CNE1, and the third connection electrode CNE3 may be provided to cover the first bump BUM1 and at least partially overlap the first connection electrode CNE1.

[0166] The second bump BUM2 may be provided on the second connection electrode CNE2, and the fourth connection electrode CNE4 may be provided to cover the second bump BUM2 and at least partially overlap the fourth connection electrode CNE4.

[0167] The first bump BUM1 and the second bump BUM2 may include materials having different elastic moduli. For example, the elastic modulus of the first bump BUM1 may be greater than that of the second bump BUM2. In this embodiment, the height hh1 of the first bump BUM1 may be the same as or similar to the height hh2 of the second bump BUM2, and the diameter dd1 of the first bump BUM1 may be the same as or similar to the diameter dd2 of the second bump BUM2. Therefore, before coupling the light-emitting element LD to the substrate SUB, the sizes and / or shapes of the first bump BUM1 and the second bump BUM2 may be the same or similar.

[0168] In an embodiment, the first bump BUM1 and the second bump BUM2 may include an organic material or a metal material. The materials constituting (or forming) the first bump BUM1 and the second bump BUM2 are the same as those described in detail with reference to FIGS. 7 to 17, and therefore, will not be described in detail below.

[0169] In addition, the second bump BUM2 and the fourth via layer 4 may include the same material. For example, the second bump BUM2 and the fourth via layer VIA4 may include a negative photoresist material. In one embodiment, the second bump BUM2 and the fourth via layer VIA4 may include the same material and may be manufactured by the same process. Therefore, the time and cost of manufacturing the display device can be reduced.

[0170] Referring to FIG. 19, in a display device according to an embodiment, a light-emitting element LD including a first electrode EL1 and a second electrode EL2 may be disposed on a substrate SUB.

[0171] The light-emitting element LD may be disposed such that the first electrode EL1 faces the first bump BUM1 and the third connection electrode CNE3 in a third direction DR3, while the second electrode EL2 faces the second bump BUM2 and the fourth connection electrode CNE4.

[0172] Referring to FIG. 20, in a display device according to an embodiment, a reference (or predetermined) pressure may be applied in the third direction DR3 to couple the light-emitting element LD and the substrate SUB. Therefore, the first electrode EL1 may directly contact the third connection electrode CNE3, and the second electrode EL2 may directly contact the fourth connection electrode CNE4.

[0173] Since the elastic modulus of the first bump BUM1 is greater than that of the second bump BUM2, the deformation of the second bump BUM2 may be greater than that of the first bump BUM1. Therefore, since the second bump BUM2 in contact with the second electrode EL2 is more deformed than the first bump BUM1, the light-emitting element LD can be stably coupled to the substrate SUB despite the height difference (or step difference) between the first electrode EL1 and the second electrode EL2. In this embodiment, the height (e.g., final height) hh1 of the first bump BUM1 may be greater than the height (e.g., final height) hh2 of the second bump BUM2, and the diameter (e.g., final diameter) dd1 of the first bump BUM1 may be smaller than the diameter (e.g., final diameter) dd2 of the second bump BUM2. Therefore, after the light-emitting element LD is coupled to the substrate SUB, the size and / or shape of the first bump BUM1 and the second bump BUM2 may change.

[0174] Thereafter, an insulating film FIL including an insulating material may be formed between the light-emitting element LD and the third and fourth connection electrodes CNE3 and CNE4. The insulating film FIL may be located between the light-emitting element LD and the third connection electrode CNE3 to couple the light-emitting element LD and the circuit board, and may be provided between the light-emitting element LD and the fourth connection electrode CNE4 to couple the light-emitting element LD and the circuit board.

[0175] According to an embodiment, a first bump and a second bump having different elastic moduli are provided, thereby strengthening the bonding force between the substrate and the light-emitting element. The light-emitting element includes a first electrode and a second electrode located at different horizontal heights.

[0176] Aspects and features of the present disclosure are not limited to those described above with respect to the embodiments described herein, and more diverse aspects and features are included in this specification.

[0177] Although embodiments of the present disclosure have been described, it is understood that the present disclosure should not be limited to these embodiments, but may be variously changed and modified by those of ordinary skill in the art to which the present invention pertains within the spirit and scope of the following disclosure and their equivalents.

[0178] Therefore, the technical scope of the present disclosure is not limited to the embodiments described herein, but should be determined by the claims and their equivalents.

Brief Description of the Drawings

[0026] FIG. 1 is a schematic plan view of a display device according to an embodiment. FIG. 2 is a schematic cross-sectional view of the display device shown in FIG. 1. FIG. 3 is a top view of a multi-screen display device that can be implemented using the display device according to an embodiment. FIG. 4 is a circuit diagram showing the electrical connection relationship of a pixel included in the display device according to an embodiment. FIG. 5 is a cross-sectional view of a light-emitting element in the display device according to an embodiment. FIGS. 6 and 7 are schematic cross-sectional views of a pixel included in the display device according to an embodiment. FIG. 8 is a diagram depicting an experiment for determining the physical properties of the material of the pixel forming the first bump and the second bump according to an embodiment. FIG. 9 is a graph depicting the experimental results related to FIG. 8. FIG. 10 is a table depicting the experimental results related to FIG. 8. FIG. 11 is a diagram depicting an experiment for determining the physical properties of the material of the pixel forming the first bump and the second bump according to an embodiment. FIG. 12 is a graph depicting the experimental results related to FIG. 11. FIG. 13 is a table depicting the experimental results related to FIG. 11. FIG. 14 is a diagram depicting an experiment for determining the physical properties of the material of the pixel forming the first bump and the second bump according to an embodiment. FIG. 15 is a graph depicting the experimental results related to FIG. 14. FIG. 16 is a table depicting the experimental results related to FIG. 14. FIG. 17 is a graph depicting the relationship between the indentation depth and the load of a pixel formed of the material forming the first bump and the second bump according to an embodiment. FIGS. 18 to 20 are cross-sectional views sequentially showing the steps of a manufacturing method of the display device according to an embodiment.

Claims

1. A display device comprising: One substrate; A pixel circuit layer is located on the substrate; A first connection electrode and a second connection electrode are located on the pixel circuit layer; a first bump and a second bump are located on the first connection electrode and the second bump is located on the second connection electrode, the first bump and the second bump comprising materials with different elastic moduli; and a light-emitting element comprising a first electrode electrically connected to the first connection electrode and a second electrode electrically connected to the second connection electrode.

2. The display device according to claim 1, wherein the elastic modulus of the first bump is greater than the elastic modulus of the second bump.

3. The display device according to claim 2, wherein the first bump and the second bump comprise an organic material or a metallic material.

4. The display device according to claim 1, wherein the first bump includes a positive photoresist material and the second bump includes a negative photoresist material.

5. The display device according to claim 1, wherein a height of the second protrusion is lower than a height of the first protrusion, and a diameter of the second protrusion is greater than a diameter of the first protrusion.

6. The display device according to claim 1, wherein the light-emitting element includes a surface having a semiconductor structure having a different height and the semiconductor structure being configured to emit light, and wherein the first electrode is disposed on the surface of the semiconductor structure, and the second electrode is disposed on the surface of the semiconductor structure at a location different from that of the first electrode.

7. The display device according to claim 6, wherein the first electrode is located at a lower horizontal height on the surface of the semiconductor structure, and wherein the second electrode is located at a higher horizontal height on the surface of the semiconductor structure.

8. The display device according to claim 7, wherein the semiconductor structure includes a first semiconductor layer, an active layer located on one side of the first semiconductor layer, and a second semiconductor layer located on one side of the active layer, and the second semiconductor layer is of a different type from the first semiconductor layer.

9. The display device according to claim 1, wherein the pixel circuit layer includes a transistor on the substrate and a plurality of via layers on the transistor, the transistor including a semiconductor pattern, a first source, a first drain and a gate electrode, and wherein the first drain of the transistor is electrically connected to the first connection electrode through a plurality of contact openings in the plurality of via layers.

10. The display device according to claim 9, further comprising a third connecting electrode and a fourth connecting electrode, the third connecting electrode covering the first bump and at least partially overlapping the first connecting electrode, and the fourth connecting electrode covering the second bump and at least partially overlapping the second connecting electrode.

11. The display device according to claim 10, further comprising an insulating film between the light-emitting element and the third connecting electrode and the fourth connecting electrode.

12. The display device according to claim 9, wherein the second bump and the plurality of via layers comprise the same material.

13. A method of manufacturing a display device, comprising: A pixel circuit layer including a transistor is provided on a substrate; A first connection electrode, a second connection electrode, a first bump, a second bump, and a via layer are provided on the pixel circuit layer. The first bump and the second bump are made of materials with different elastic moduli. A light-emitting element including a first electrode and a second electrode is disposed on the substrate. The light-emitting element and the substrate are coupled such that the first electrode of the light-emitting element overlaps with the first bump, and the second electrode of the light-emitting element overlaps with the second bump.

14. The method according to claim 13, wherein before the light-emitting element and the substrate are coupled, a height of the first bump is the same as a height of the second bump.

15. The method according to claim 14, wherein after coupling the light-emitting element and the substrate, the height of the first bump is higher than the height of the second bump.

16. A splicing display device, comprising: A plurality of display devices and a seam portion disposed between the plurality of display devices, wherein a first display device of the plurality of display devices includes: a substrate; a pixel circuit layer located on the substrate; a first connection electrode and a second connection electrode located on the pixel circuit layer; a first bump and a second bump, the first bump being located on the first connection electrode and the second bump being located on the second connection electrode, the first bump and the second bump comprising materials having different elastic moduli; and a light-emitting element including a first electrode electrically connected to the first connection electrode and a second electrode electrically connected to the second connection electrode.

17. The splicing display device according to claim 16, wherein each of the plurality of light-emitting elements is a flip-chip type micro light-emitting diode.

18. The splicing display device according to claim 16, wherein the substrate is made of glass.

19. The splicing display device according to claim 16, wherein the first display device further comprises: A solder pad is disposed on a first surface of the substrate; And a side conductor is disposed on the first surface of the substrate, a second surface opposite to the first surface, and a side surface between the first surface and the second surface, and the side conductor is connected to the solder pad.

20. The splicing display device according to claim 19, wherein the first display device further comprises: A connecting line is disposed on the second surface of the substrate; And a flexible film, which is connected to the connecting line by a conductive adhesive member, wherein the side conductor is connected to the connecting line.

21. The splicing display device according to claim 16, wherein the plurality of display devices are arranged in a matrix format in M ​​rows and N columns.

22. The splicing display device according to claim 16, wherein the elastic modulus of the first protrusion is greater than the elastic modulus of the second protrusion.

23. The splicing display device according to claim 22, wherein the first bump and the second bump comprise an organic material or a metallic material.

24. The splicing display device according to claim 16, wherein the first bump includes a positive photoresist material and the second bump includes a negative photoresist material.

25. The splicing display device according to claim 16, wherein a height of the second protrusion is lower than a height of the first protrusion, and a diameter of the second protrusion is greater than a diameter of the first protrusion.

26. The splicing display device according to claim 16, wherein the light-emitting element includes a semiconductor structure, the semiconductor structure having a surface with a different height, and the semiconductor structure is configured to emit light, and wherein the first electrode is disposed on a surface of the semiconductor structure, and the second electrode is disposed on the surface of the semiconductor structure at a location different from that of the first electrode.

27. The splicing display device according to claim 26, wherein the first electrode is located at a lower horizontal height on the surface of the semiconductor structure, and wherein the second electrode is located at a higher horizontal height on the surface of the semiconductor structure.

28. The splicing display device according to claim 26, wherein the semiconductor structure includes a first semiconductor layer, an active layer located on one side of the first semiconductor layer, and a second semiconductor layer located on one side of the active layer, and the second semiconductor layer is of a different type from the first semiconductor layer.

29. The splicing display device according to claim 16, wherein the pixel circuit layer includes a transistor located on the substrate and a plurality of via layers located on the transistor, the transistor including a semiconductor pattern, a first source, a first drain and a gate electrode, and wherein the first drain of the transistor is electrically connected to the first connection electrode through a plurality of contact openings in the plurality of via layers.

30. The splicing display device according to claim 16, further comprising a third connecting electrode and a fourth connecting electrode, the third connecting electrode covering the first protrusion and at least partially overlapping the first connecting electrode, and the fourth connecting electrode covering the second protrusion and at least partially overlapping the second connecting electrode.

31. The splicing display device according to claim 30, further comprising an insulating film located between the light-emitting element and the third connecting electrode and the fourth connecting electrode.

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