Methods for polishing semiconductor substrates

Abstract

This invention discloses a method for polishing a semiconductor substrate. The method may involve alternating the use of a first and a second polishing slurry during polishing. Each of the first and second slurries contains silicon dioxide particles, wherein the first slurry contains more silicon dioxide particles than the second slurry particles. By alternating between the first and second polishing slurries, this polishing method can improve wafer flatness.

Description

[Technical Field]

[0001] The field of the present invention relates to a method for polishing a semiconductor substrate, and more particularly to a method for reducing the field total indicator reading (STIR) for polishing a semiconductor substrate. [Previous Technology]

[0002] Semiconductor wafers are used to manufacture semiconductor devices, such as integrated circuit (IC) wafers, silicon-on-insulator (SOI) wafers, and radio frequency SOI (RF-SOI) wafers. Typically, the rough surface of a semiconductor wafer needs further processing to achieve characteristics that meet the stringent parameters required for the production of semiconductor devices such as IC wafers, SOI wafers, and RF-SOI wafers.

[0003] Typically, the surface of a semiconductor wafer is polished to improve surface properties, including polycrystalline roughness and micro-defects. One method of polishing a semiconductor wafer is called chemical mechanical polishing (CMP). CMP processing typically uses a circular polishing pad. When a slurry is applied to the pad, the pad is rotated and the wafer contacts and is pressed against the pad. However, the wafer may contact the pad unevenly, particularly towards the wafer edges. This uneven contact affects the surface properties after polishing, which can cause the wafer to be unsatisfactory or require additional processing. For example, due to uneven contact between the pad and the wafer, the wafer may become thinner at a high rate. The field total indication reading (STIR) is a point-by-point measurement of wafer flatness. Single-sided polishing methods typically result in a poorer STIR towards the wafer edges.

[0004] A method is needed for manufacturing a semiconductor structure with improved wafer flatness.

[0005] This section aims to introduce to the reader various aspects of the technology that may be associated with various aspects of the present invention, which will be described and / or claimed below. It is believed that this discussion will help provide the reader with background information to better understand the various aspects of the present invention. Therefore, it should be understood that these statements are to be understood from this perspective and not as an admission of prior art. [Summary of the Invention]

[0006] One aspect of the present invention relates to a method for polishing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface generally parallel to the front surface. In a first polishing step, in the presence of a first polishing slurry, the front surface of the substrate contacts a polishing pad. In a second polishing step, in the presence of a second polishing slurry, the front surface of the substrate contacts a polishing pad. The second polishing step begins after the first polishing step. In a third polishing step, in the presence of the first polishing slurry, the front surface of the substrate contacts a polishing pad. The third polishing step begins after the second polishing step.

[0007] Various modifications exist to the features associated with the above-described embodiments of the present invention. Other features may also be incorporated into the above-described embodiments of the present invention. These modifications and additional features may exist individually or in any combination. For example, the various features discussed below in conjunction with any illustrated embodiment of the present invention may be incorporated individually or in any combination into any of the above-described embodiments of the present invention.

Implementation Method

[0019] This application claims the rights of U.S. Provisional Patent Application No. 63 / 291,085, filed on December 17, 2021, the entire contents of which are incorporated herein by reference.

[0020] This invention provides a method for polishing a semiconductor substrate. Examples of substrates that can be polished according to the method described herein include silicon substrates, such as single-crystal silicon semiconductor substrates. In some embodiments, the substrate is a layered substrate, such as a substrate having a single-crystal silicon layer. Single-crystal silicon semiconductor substrates can be used to fabricate electronic devices, such as integrated circuit (IC) wafers, silicon-on-insulator (SOI) wafers, and radio frequency SOI (RF-SOI) wafers. In embodiments where the substrate is used to produce SOI wafers, SOI wafers can be manufactured according to the procedures described in U.S. Patent No. 10,128,146. The substrate can be of any diameter suitable for use by those skilled in the art, including, for example, wafers with diameters of 200 mm, 300 mm, greater than 300 mm, or even 450 mm. In some embodiments, the diameter of the substrate being polished is 200 mm.

[0021] Referring now to FIG. 1 of this application, an embodiment of a polishing method 100 of the present invention is shown. Method 100 involves polishing the front surface of a substrate to achieve a desired surface roughness. The polishing step may be a single-sided polishing (i.e., without polishing the back surface), which is typical for processing a 200 mm substrate. Single-sided polishing can reduce the surface roughness of the wafer to less than about 2.0 Å, as measured by atomic force microscopy (AFM) at a scan size of about 10 μm x about 10 μm to about 100 μm x about 100 μm. At a scan size of about 10 μm x about 10 μm to about 100 μm x 100 μm, single-sided polishing can even reduce the surface roughness to less than about 1.5 Å or less than about 1.2 Å. Single-sided polishing can result in the removal of at least about 1 µm of material from the front surface of the substrate, which is typical for processing a 200 mm substrate, wherein a single polishing step is performed.

[0022] Single-sided polishing can be achieved, for example, by chemical mechanical planarization (CMP). CMP typically involves immersing the wafer in an abrasive slurry and polishing the wafer with a polymer pad. By combining chemical and mechanical means, the surface of the wafer can be smoothed. Polishing is typically performed until a chemically and thermally stable state is reached, and until the wafer achieves its target shape and flatness.

[0023] A suitable polisher for unilateral polishing is available from Lapmaster SFT (e.g., LGP-708, Chiyoda-ku, Japan). According to embodiments of the invention, the pad for unilateral polishing is a suede-type pad (also referred to as a polyurethane foam pad), such as a SURFIN pad from Fujimi (Japan), a CIEGAL pad from Chiyoda KK (Japan), or an SPM pad from Rohm and Haas. A polyurethane-impregnated polyethylene pad, such as a SUBA pad available from Rohm and Haas, can also be used.

[0024] The single-sided grinding 100 can be performed for at least 60 seconds, or even at least 120 seconds, at least 180 seconds, or at least 240 seconds or longer. The slurry flow rate can be in the range of about 100 ml / min to about 1000 ml / min, and the pad pressure can be in the range of about 75 g / cm 2 to about 125 g / cm 2; however, it should be understood that other grinding times, pad pressures and slurry flow rates may be used without departing from the scope of the invention.

[0025] Referring to FIG. 1, the polishing method involves a first polishing step 110, wherein, in the presence of a first polishing slurry, the front surface of the substrate contacts a polishing pad. In a second step 120, in the presence of a second polishing slurry, the front surface of the substrate contacts a polishing pad (i.e., the second step begins after the first step, wherein the second polishing step begins after the flow of the first polishing slurry has stopped, or occurs simultaneously therewith). In a third step 130, in a third polishing step (i.e., the third polishing step begins after the second polishing step), in the presence of the first polishing slurry, the front surface of the substrate contacts a polishing pad.

[0026] In some embodiments, each of the first and second grinding slurries is a polydisperse slurry containing colloidal silicon particles. The first slurry contains silicon dioxide particles having a silicon dioxide content of X 1 wt%, and the second slurry contains silicon dioxide particles having a silicon dioxide content of X 2 wt%. X 1 is greater than X 2. The silicon dioxide particles in the first and second slurries may be amorphous silicon dioxide and are generally spherical. The silicon dioxide content of the particles can be varied (i.e., between the first and second slurries) by individually encapsulating the particles of each slurry with a polymer, the degree of encapsulation (i.e., the thickness of the polymer) differing between the two slurries. The polymer reduces the silicon dioxide content within the particle cluster. In some embodiments, the ratio of X1 to X2 is at least about 2:1 or even at least about 3:1, at least about 5:1, at least about 10:1 or even at least about 15:1. The difference between X1 and X2 (i.e., X1 minus X2) may be about 5 wt%, at least about 10 wt%, at least about 25 wt%, or at least about 50 wt%.

[0027] In some embodiments, the silica particles of the first slurry are individually encapsulated with a polymer. The polymer-encapsulated silica particles may include at least about 50 wt% silica or at least about 60 wt%, at least about 70 wt%, about 50 wt% to about 95 wt%, about 60 wt% to about 95 wt%, or about 70 wt% to about 90 wt% silica.

[0028] In some embodiments, the silica particles of the second grinding slurry are also individually encapsulated in a polymer. The silica particles of the second grinding slurry contain less than about 25 wt% silica, or, as in other embodiments, less than about 15 wt%, less than about 10 wt%, about 1 wt% to about 25 wt%, about 1 wt% to about 15 wt%, or about 1 wt% to about 10 wt% silica.

[0029] The polymer used to encapsulate the silicon dioxide particles in the first and / or second polishing slurry may be any polymer known to be used in the field of substrate polishing, and specifically silicon wafer polishing. The polymer may be a water-soluble polymer, such as cellulose, substituted cellulose, modified starch, or xanthan gum.

[0030] The silicon dioxide particles of both the first and second grinding slurries have an average particle size. The average diameter of the particles in the two slurries may be less than about 100 nm, less than about 50 nm, about 10 nm to about 50 nm, about 20 nm to about 40 nm, or about 30 nm to about 40 nm. In some embodiments, the average diameter of the particles in the first grinding slurry is about 30 nm and / or the average diameter of the particles in the second grinding slurry is about 35 nm.

[0031] Each polishing slurry is generally a polydisperse colloid, wherein solid silicon dioxide particles are dispersed in a liquid phase. Suitable liquid phases include aqueous solutions. The slurry may contain typical additional components of polishing slurries used for polishing single-crystal silicon wafers.

[0032] In each of the three grinding steps 110, 120, and 130, a first or second slurry is used without delivering other slurries to the grinding pad (i.e., only the first or second slurry is used). Each slurry may be delivered to the pad together with other fluids (e.g., deionized water, caustic alkali (e.g., KOH)) and / or resins (such as nonionic polyethylene oxide polymers (e.g., POLYOX available from DuPont (Wilmington, DE))).

[0033] After single-sided grinding, the wafer can be rinsed and dried. Furthermore, the wafer can withstand a wet bench or spin cleaning. Wet bench cleaning may involve contacting the wafer with an SC-1 cleaning solution (i.e., ammonium hydroxide and hydrogen peroxide), and, if necessary, at an elevated temperature (e.g., from about 50°C to about 80°C). Spin cleaning involves contact with an HF solution and ozone water, and can be performed at room temperature.

[0034] In some embodiments, an additional polishing step is performed as part of the single-sided polishing. For example, as shown in FIG2, in the fourth polishing step 140, which begins after the third polishing step 130, the front surface of the substrate contacts a polishing pad in the presence of a second polishing slurry.

[0035] Figure 3 shows another embodiment of the polishing method 100. In addition to the first polishing step 110, the second polishing step 120, the third polishing step 130, and the fourth polishing step 140, in a fifth polishing step 150 that begins after the fourth polishing step 140, the front surface of the substrate contacts a polishing pad in the presence of the first polishing slurry. Then, in a sixth polishing step 160 that begins after the fifth polishing step 150, the front surface of the substrate contacts a polishing pad in the presence of the second polishing slurry.

[0036] The above-described grinding steps may generally include an overlap (e.g., the application of a second grinding slurry begins while the first grinding slurry is being shut off). However, generally each step involves a period of time during which the respective slurry is introduced into the grinding pad (e.g., the first slurry in the first grinding step, but not the second slurry).

[0037] The above-described polishing steps are generally performed using the same polishing pad, which is used to contact the surface of the silicon dioxide substrate. The polishing steps are performed on the same polishing apparatus.

[0038] In some embodiments, in addition to the polishing method 100 of the embodiments of the present invention cited above, the semiconductor structure may be processed in additional steps and / or on additional polishing apparatus. For example, the substrate may be polished in a polishing system 200 (FIG. 4) having a first polishing apparatus 202A, a second polishing apparatus 202B, and a third polishing apparatus 202C. Although each apparatus 202A, 202B, and 202C is shown in an integrated system 200, each of apparatus 202A, 202B, and 202C may be an independent unit. Although three apparatuses 202A, 202B, and 202C are shown and described, the polishing system 200 may include more or fewer apparatuses.

[0039] As shown in FIG. 5, each substrate polishing apparatus 202A, 202B, 202C includes a polishing pad 204 mounted on a pivotable stage 206 and a substrate mounting device 208 having a rotatable head 210 for mounting a semiconductor substrate 100 on the polishing pad 204. A ring 211 facilitates positioning the substrate 100 relative to the polishing pad 204. In a suitable embodiment, the substrate polishing apparatus 202 may include any number of polishing pads 204, substrate mounting devices 208, and rings 211. In the illustrated embodiment, each substrate polishing apparatus 202 includes two substrate mounting devices 208. The substrate mounting devices 208 hold the substrate 100 and bring the substrate 100 into contact with the polishing pad 204 when both the substrate 100 and the polishing pad 204 are rotated. The polishing pad 204 polishes one of the front surfaces 212 of the wafer 100 through the abrasive and with an polishing slurry 214, the polishing slurry 214 being applied to one of the surfaces 216 of the polishing pad 204.

[0040] In the illustrated embodiment, each substrate polishing apparatus 202 includes a nozzle 218 for dispensing polishing slurry 214. Each apparatus 202 may include multiple nozzles for dispensing multiple slurries or liquids to polishing pads 204. Additionally or separately, different slurries 214 may be dispensed from any single nozzle 218 during the polishing process.

[0041] During polishing, polishing slurry 214 is present, simultaneously bringing the front surface of the substrate into contact with the polishing pad to aid in polishing the front surface 212 of the substrate 100. When the polishing pad 204 is pressed onto the substrate 100, the polishing pad 204 causes the slurry 214 to work against the front surface 212 of the substrate 100, simultaneously and uniformly removing material from the front surface 212 of the substrate 100 and helping to improve the overall smoothness of the substrate 100. Because the front surface 212 of the substrate 100 is polished, silicon is removed by the polishing action of the slurry 214, and some minor damage is generated on the surface 212.

[0042] FIG. 6 is a flowchart of an example method 20 for polishing a semiconductor substrate using the system 200 shown in FIG. 4 or a similar system. Method 20 generally includes positioning a substrate 100 (FIG. 5) on a first wafer polishing apparatus 202A (FIG. 4) for an initial "coarse" polishing 50. The substrate 100 can be polished on the first wafer polishing apparatus 202A for any amount of time suitable for a portion of the substrate 100 to be polished and / or achieve a desired smoothness. In some embodiments, the substrate 100 is polished on the first wafer polishing apparatus 202A such that the thickness reduction ranges from about 1µm to 10µm, or from 6µm to 7µm. As a result, warpage and / or bending of the substrate 100 are reduced.

[0043] In an exemplary embodiment, the substrate 100 is transferred from the first polishing apparatus 202A to the second polishing apparatus 202B for additional polishing, such as the single-sided polishing method 100 described above (e.g., method 100 of FIG. 1, FIG. 2, or FIG. 3). As described above, in some embodiments of polishing method 100, the substrate 100 is polished on the second wafer polishing apparatus 202B such that the thickness reduction ranges from about 1µm to 10µm, or from about 3µm to about 4µm. The substrate 100 can be polished on the second polishing apparatus 202B for any amount of time suitable for a portion of the substrate 100 to be polished and / or to achieve a desired smoothness.

[0044] In polishing method 20, after polishing is completed on the second apparatus 202B, the substrate 100 is transferred to the third polishing apparatus 202C. On the third polishing apparatus 202C, during a final "contact" or "rapid" polishing of one of the substrates 100, an polishing slurry is applied to the polishing pad 204 to improve submicron roughness and substantially eliminate minor defects remaining on the surface 212 of the substrate 100. The final polishing maintains substrate flatness while imparting a smooth, mirror finish to the surface 212 of the substrate 100, which is typical for polishing wafers and is desired by many device manufacturers. This final polishing substantially removes material smaller than about 1 µm or between about 0.25 µm and about 0.5 µm from the surface 212 of the substrate 100.

[0045] Compared to conventional methods for polishing substrates, the method of the present invention has several advantages. By alternating between a first polishing slurry and a second polishing slurry, the polishing method can improve wafer flatness, such as in STIR measurements. Improved flatness reduces wafer rework and scrap. In some embodiments, each of the first and second slurries contains silicon dioxide particles, wherein the first slurry contains more silicon dioxide particles than the second slurry. This allows the first slurry to be a "coarse slurry," which relatively removes more material, while the second slurry is tailored for controlling edge roll-off. Alternating the use of slurries improves flatness without reducing edge roll-off. Examples

[0046] The following examples further illustrate the procedure of the present invention. These examples should not be considered limiting. Example 1: Effect of grinding slurry sequence

[0047] Figure 7 shows the wafer edge removal profiles (normalized thickness) for two sets of single-crystal silicon wafers (200 mm), and the single-crystal silicon wafer sets were unilaterally polished using different polishing slurries containing polymer-encapsulated colloidal silicon dioxide. Slurry 1 containing colloidal silicon dioxide (Nalco DVSTS029) was diluted with deionized water. The polishing slurry also contained KOH and POLYOX. The polymer-encapsulated silicon dioxide particles contained approximately 80 wt% silicon dioxide (the remainder being polymer) and had an average particle diameter of approximately 30 nm.

[0048] A second set of silicon wafers (200 mm) was also unilaterally polished using a colloidal silicon dioxide slurry (Glanzox-3950) ("Slurry 2") having an average particle size of about 35 nm, diluted with deionized water. The polishing slurry also contained KOH and POLYOX. The polymer-encapsulated silicon dioxide particles contained about 5 wt% silicon dioxide (the remainder being polymer).

[0049] As shown in Figure 7, slurry 1 is more abrasive and removes more material. The second slurry results in improved edge roll-off.

[0050] A third-group silicon wafer (200 mm) is unilaterally polished using a colloidal silicon dioxide slurry according to the following formulation ("POR"): step 1 2 3 4 5 6 7 8 9 time 2 10 42 40 46 twenty three 20 4 13 pressure 0 46 46 46 46 15 15 0 0 DI wat 200 200 200 200 200 600 600 600 600 PolyOx 0 0 0 0 0 0 0 0 600 -Slurry 1- -35- -35- -15- 0 0 0 0 0 0 KOH 0 125 215 100 0 0 0 0 0 -Slurry 2- 0 0 -10- -10- -10- -10- -10- 0 0 Table 1: Grinding Formulation for Slurry 1 followed by Slurry 2

[0051] A fourth group silicon wafer (200 mm) is unilaterally polished using a colloidal silicon dioxide slurry according to the following formulation ("New"): step 1 2 3 4 5 6 7 8 9 10 11 time 2 10 25 10 25 10 25 33 43 4 13 pressure 0 46 46 46 46 46 30 30 15 0 0 DI wat 200 240 100 240 100 240 100 300 600 600 600 PolyOx 0 0 0 0 0 0 0 0 0 0 600 -Slurry 1- -35- -15- 0 -15- 0 -15- 0 0 0 0 0 KOH 0 75 215 75 25 75 215 0 0 0 0 -Slurry 2- 0 0 -10- 0 -10- 0 -10- -10- -10- 0 0 Table 2: Grinding formulations using alternating slurry 1 and slurry 2

[0052] As shown in Figure 8, the method of alternating the use of slurry 1 and slurry 2 results in improved flatness and improved edge roll-off. Figure 9 shows a probability plot of STIR and ecurve (edge ​​roll-off deviation) for the new method ("Experiment") and the method without alternating slurry use ("POR"). As shown in Figure 9, the alternating slurry method exhibits improved STIR. Figure 10 shows a probability plot of STIR and ecurve (edge ​​roll-off deviation). As shown in Figure 10, the alternating slurry method exhibits improved STIR and ecurve.

[0053] As used herein, when used with ranges of size, concentration, temperature or other physical or chemical properties or characteristics, the terms "about," "substantially," "essentially," and "approximately" cover variations that may exist within the upper and / or lower limits of the range of properties or characteristics, including, for example, variations caused by rounding, measurement methods, or other statistical variations.

[0054] In describing elements of the present invention or embodiments thereof, the articles "a," "an," "the," and "said" are intended to indicate the presence of one or more elements. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and mean that additional elements besides those listed may be present. The use of terms indicating a particular direction (e.g., "top," "bottom," "side," etc.) is for ease of description and does not require any particular orientation of the described items.

[0055] Since various changes can be made to the above structure and method without departing from the scope of the invention, all contents contained in the above description and shown in (some) accompanying drawings should be interpreted as illustrative rather than restrictive. [Simplified Explanation of the Diagram]

[0008] Figure 1 is a block diagram of one embodiment of a method for grinding a semiconductor structure;

[0009] Figure 2 is a block diagram of another embodiment of a method for grinding a semiconductor structure;

[0010] Figure 3 is a block diagram of another embodiment of a method for grinding a semiconductor structure;

[0011] Figure 4 is a schematic diagram of one embodiment of a wafer polishing system;

[0012] Figure 5 is a flowchart illustrating one embodiment of a method for processing a semiconductor wafer;

[0013] FIG6 is a block diagram of one embodiment of a method for grinding a semiconductor structure on a plurality of substrate grinding apparatuses;

[0014] Figure 7 is a diagram showing one of the wafer edge removal profiles when using a single paste;

[0015] Figure 8 is a diagram illustrating wafer edge removal by one embodiment of the method of the present invention and a conventional method;

[0016] Figure 9 shows a box diagram of STIR and ECURV used for processing the substrate according to Example 1; and

[0017] Figure 10 shows a probability plot of STIR and ECURV used to process the substrate according to Example 1.

[0018] Widely distributed across the diagram, with corresponding component symbols indicating the corresponding parts.

Claims

1. A method for polishing a semiconductor substrate having a front surface and a back surface substantially parallel to the front surface, the method comprising: In a first polishing step, in the presence of a first polishing slurry, the front surface of the substrate is brought into contact with a polishing pad; In a second polishing step, in the presence of a second polishing slurry, the front surface of the substrate is brought into contact with a polishing pad, and the second polishing step begins after the first polishing step; and in a third polishing step, in the presence of the first polishing slurry, the front surface of the substrate is brought into contact with a polishing pad, and the third polishing step begins after the second polishing step.

2. The method of claim 1, comprising, in a fourth polishing step, bringing the front surface of the substrate into contact with a polishing pad in the presence of the second polishing slurry, and starting the fourth polishing step after the third polishing step.

3. The method of claim 2, comprising, in a fifth polishing step, bringing the front surface of the substrate into contact with a polishing pad in the presence of the first polishing slurry, and starting the fifth polishing step after the fourth polishing step.

4. The method of claim 3, comprising, in a sixth polishing step, bringing the front surface of the substrate into contact with a polishing pad in the presence of the second polishing slurry, and starting the sixth polishing step after the fifth polishing step.

5. The method of claim 1, wherein the polishing pad that contacts the front surface of the substrate in each polishing step is the same polishing pad.

6. The method of claim 1, wherein the first grinding slurry comprises silicon dioxide particles having a silicon dioxide content of X1 wt%, and the second grinding slurry comprises silicon dioxide particles having a silicon dioxide content of X2 wt%, wherein X1 is greater than X2.

7. As in claim 6, wherein the ratio of X1 to X2 is at least about 2:

1.

8. As in claim 6, wherein the ratio of X1 to X2 is at least about 10:

1.

9. The method of claim 6, wherein the ratio of X1 to X2 is at least about 15:

1.

10. The method of claim 6, wherein the difference between X1 and X2 is at least about 5wt%.

11. The method of claim 6, wherein the difference between X1 and X2 is at least about 25 wt%.

12. The method of claim 6, wherein the difference between X1 and X2 is at least about 50 wt%.

13. The method of claim 6, wherein each of the silica particles in the first slurry and each of the silica particles in the second slurry is polymer-encapsulated.

14. The method of claim 1, wherein the back surface is not ground when grinding the front surface, and wherein at least about 1 µm of material is removed from the front surface of the substrate.

15. The method of claim 1, wherein the substrate has a diameter of about 200 mm.

16. The method of claim 1, wherein each grinding slurry is a colloid.

17. The method of claim 1, wherein the first grinding step, the second grinding step and the third grinding step are each performed on the same grinding apparatus.

18. The method of claim 17, wherein the polishing apparatus is a second polishing apparatus, and prior to the first polishing step, the substrate is positioned on a first polishing apparatus, and in the presence of one or more second polishing apparatus slurries, the front surface of the substrate is brought into contact with a first polishing apparatus polishing pad, and the substrate is transferred from the first polishing apparatus to the second polishing apparatus.

19. The method of claim 18, further comprising transferring the substrate from the second polishing apparatus to a third polishing apparatus, the method comprising, in the presence of one or more third polishing apparatus slurries, contacting the front surface of the substrate with a third polishing apparatus polishing pad.

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