Electronic device and repair method thereof

Abstract

An electronic device and a repair method thereof, wherein the repair method includes: providing a panel, wherein the panel includes a substrate, a first conductive layer disposed on the substrate, a transistor disposed on the substrate, and a dielectric layer disposed between the first conductive layer and the transistor, wherein the transistor includes a first electrode and a second electrode; and cutting at least one of the first electrode and the second electrode with a laser beam, wherein the cutting point formed by the laser beam does not overlap with the first conductive layer.

Description

Technical Field

[0001] This invention relates to an electronic device and a method for repairing the same. Prior Technology

[0002] Defects in component arrays are typically repaired using lasers. However, when there are other conductive layers (such as metal layers) between the component array and the substrate, the originally electrically insulating upper and lower conductive layers are prone to short circuits due to high-temperature melting during laser repair. Summary of the Invention

[0003] This invention provides an electronic device and a repair method thereof, which helps to improve the short circuit problem caused by laser repair.

[0004] In one embodiment of the present invention, a method for repairing an electronic device includes: providing a panel, wherein the panel includes a substrate, a first conductive layer disposed on the substrate, a transistor disposed on the substrate, and a dielectric layer disposed between the first conductive layer and the transistor, wherein the transistor includes a first electrode and a second electrode; and cutting at least one of the first electrode and the second electrode with a laser beam, wherein the cutting point formed by the laser beam does not overlap with the first conductive layer.

[0005] In one embodiment of the present invention, the electronic device includes a panel. The panel includes a substrate, a first conductive layer, a transistor, and a dielectric layer. The first conductive layer is disposed on the substrate and has an opening. The transistor is disposed on the substrate, wherein the transistor includes a first electrode and a second electrode, and the transistor at least partially overlaps with the opening. The dielectric layer is disposed between the first conductive layer and the transistor.

[0006] In one embodiment of the present invention, a method for repairing an electronic device includes: providing a panel, wherein the panel includes a substrate, a first conductive layer disposed on the substrate, a dielectric layer disposed on the first conductive layer, a transistor disposed on the dielectric layer, and a reflective layer disposed between the first conductive layer and the transistor, wherein the transistor includes a first electrode and a second electrode; and cutting at least one of the first electrode and the second electrode with a laser beam, wherein the reflective layer is used to reflect the laser beam.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0008] Figures 1, 3, 6, and 8 are partial top views of electronic devices according to some embodiments of the present disclosure. Figures 2, 4, 5, 7, and 9 are partial cross-sectional schematic diagrams of electronic devices according to some embodiments of the present disclosure. Figures 10A and 10B are schematic flowcharts of methods for repairing electronic devices according to some embodiments of the present disclosure. Figures 11A and 11B are schematic flowcharts of methods for repairing electronic devices according to other embodiments of the present disclosure. Implementation

[0009] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0010] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that function identically but have different names. In the following specification and claims, terms such as "containing" and "comprising" are open-ended and should therefore be interpreted as "containing but not limited to...".

[0011] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, the various figures illustrate general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and positions of various films, regions, and / or structures may be reduced or enlarged.

[0012] In this disclosure, the description of one structure (or layer, element, substrate) being located on / above another structure (or layer, element, substrate) can refer to the two structures being adjacent and directly connected, or to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate spacer) between the two structures, with the lower surface of one structure adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single or multiple solid or non-solid structure, without limitation. In this disclosure, when a structure is placed "on" other structures, it may mean that the structure is "directly" on other structures, or that the structure is "indirectly" on other structures, meaning that at least one structure is sandwiched between the structure and other structures.

[0013] The terms “approximately,” “equal to,” “equivalent to,” “same,” “substantially,” or “roughly” are generally interpreted as within 20% of a given value or range, or as within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value. Furthermore, the phrases “range from the first value to the second value” or “range between the first value and the second value” indicate that the range includes the first value, the second value, and other values ​​in between.

[0014] The ordinal numbers used in the specification and claims, such as "first" and "second," to modify elements do not inherently imply or represent any prior ordinal number for that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; therefore, a first component in the specification may be a second component in the claims.

[0015] The electrical connections or couplings described in this disclosure can refer to direct connections or indirect connections. In the case of a direct connection, the endpoints of the components in two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components between the endpoints of the components in two circuits, but not limited to these.

[0016] In this disclosure, the thickness, length, and width can be measured using an optical microscope (OM), while the thickness or width can be measured from cross-sectional images obtained from an electron microscope, but this is not a limitation. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. Additionally, if the first direction is perpendicular to the second direction, the angle between the first and second directions can be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions can be between 0 and 10 degrees.

[0017] It should be understood that the features in the following embodiments can be replaced, recombined, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0018] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0019] Although the electronic device described in this disclosure is an antenna device, it may also include display devices, backlight devices, sensing devices, or splicing devices, but is not limited thereto. The electronic device may be bendable or flexible. The display device may be a non-emissive display device or a self-emissive display device. The electronic device may include, for example, liquid crystal, light-emitting diode, fluorescence, phosphorescence, quantum dot (QD), other suitable display media, or combinations thereof. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device for capacitance, light, heat, or ultrasound, but is not limited thereto. In this disclosure, the electronic device may include electronic units, which may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light-emitting diodes or photodiodes. The light-emitting diode (LED) may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto. Furthermore, the shape of the electronic device may be rectangular, circular, polygonal, with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a drive system, control system, and light source system to support display devices, antenna devices, wearable devices (e.g., augmented reality or virtual reality), automotive devices (e.g., automotive windshields), or splicing devices.

[0020] Figures 1, 3, 6, and 8 are partial top views of electronic devices according to some embodiments of the present disclosure. Figures 2, 4, 5, 7, and 9 are partial cross-sectional views of electronic devices according to some embodiments of the present disclosure. Figures 10A and 10B are flowcharts of methods for repairing electronic devices according to some embodiments of the present disclosure. Figures 11A and 11B are flowcharts of methods for repairing electronic devices according to other embodiments of the present disclosure.

[0021] In the top views of Figures 1, 3, 6, and 8, some films / components in the electronic device are omitted to clearly show the relative arrangement between certain films / components. For films / components not shown in the top views, please refer to the corresponding cross-sectional views (Figures 2, 4, 7, and 9).

[0022] Referring to Figures 1 and 2, the electronic device 1 may include a panel 10. The panel 10 may include a substrate 100, a first conductive layer 101, a dielectric layer 102, and a transistor 103. The first conductive layer 101 is disposed on the substrate 100 and has an opening A. The transistor 103 is disposed on the substrate 100, wherein the transistor 103 includes a first electrode E1 and a second electrode E2, and the transistor 103 at least partially overlaps with the opening A. The dielectric layer 102 is disposed between the first conductive layer 101 and the transistor 103.

[0023] In detail, the substrate 100 can be a rigid substrate or a flexible substrate. The material of the substrate 100 includes, but is not limited to, glass, quartz, ceramic, sapphire, or plastic. Plastics may include, but are not limited to, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), other suitable flexible materials, or combinations of the foregoing materials.

[0024] The first conductive layer 101 is disposed between the substrate 100 and the dielectric layer 102. The material of the first conductive layer 101 may include, for example, copper, aluminum, any conductive metal material, alloy, metal oxide or other conductive non-metallic material or a combination thereof, but is not limited thereto.

[0025] An opening A through the first conductive layer 101 exposes the substrate 100 beneath it; that is, the area where opening A is located is the area where the first conductive layer 101 is removed. Opening A may, for example, correspond to a laser repair / cutting area. For instance, as shown in FIG1, in a top view, opening A may overlap at least one of the first electrode E1 and the second electrode E2. In this document, overlap means at least partial overlap in a direction perpendicular to the surface of the substrate 100 (e.g., the surface of the substrate 100 facing the first conductive layer 101), such as direction Z. In other words, the statement "opening A overlaps at least one of the first electrode E1 and the second electrode E2" means that opening A at least partially overlaps at least one of the first electrode E1 and the second electrode E2 in direction Z. FIG1 schematically illustrates two openings A, with each opening A overlapping the end of the first electrode E1 away from the second electrode E2 and the end of the second electrode E2 away from the first electrode E1, respectively. However, it should be understood that the number of openings A and the relative arrangement of openings A with other elements can be changed as needed and are not limited to what is shown in FIG1.

[0026] The dielectric layer 102 is disposed on the first conductive layer 101 and fills the opening A. The dielectric layer 102 may be a single layer or multiple layers. The material of the dielectric layer 102 includes, for example, inorganic materials such as silicon oxide, silicon nitride, or combinations thereof, but is not limited thereto.

[0027] Transistor 103 is disposed, for example, on dielectric layer 102. In addition to the first electrode E1 and the second electrode E2, transistor 103 may also include a gate GE, which overlaps with the first conductive layer 101. In some embodiments, as shown in FIG2, the gate GE may be located between the first electrode E1 and the first conductive layer 101. In other embodiments, as shown in FIG9, the first electrode E1 may be located between the gate GE and the first conductive layer 101C.

[0028] Transistor 103 may further include a semiconductor pattern CH. The semiconductor pattern CH is disposed between the gate GE and the first electrode E1 and between the gate GE and the second electrode E2, and the semiconductor pattern CH overlaps with the gate GE. The material of the semiconductor pattern CH includes, for example, amorphous silicon, polysilicon, or metal oxide, such as indium gallium zinc oxide (IGZO), but is not limited thereto.

[0029] It should be understood that Figures 1 and 2 use a bottom-gate thin-film transistor as an example of transistor 103, but the type of transistor 103 can be changed as needed and is not limited thereto.

[0030] Depending on the specific requirements, panel 10 may also include other components or film layers. For example, panel 10 may also include a dielectric layer 104. Dielectric layer 104 is disposed on dielectric layer 102 and covers the gate GE. Dielectric layer 104 may be a single layer or multiple layers. The material of dielectric layer 104 may include, for example, inorganic or organic materials, such as silicon oxide, silicon nitride, or combinations thereof, but is not limited thereto.

[0031] Panel 10 may also include scan lines SL and data lines DL. Scan lines SL and data lines DL intersect each other and are electrically insulated from each other through dielectric layer 104. Scan lines SL are electrically connected to the gate GE. Scan lines SL and the gate GE may belong to the same conductive layer (e.g., referred to as the second conductive layer). The second conductive layer may be a single metal layer or a metal stack, and the material of the second conductive layer may include metals such as aluminum, molybdenum, or titanium / aluminum / titanium, but is not limited thereto.

[0032] One of the first electrode E1 and the second electrode E2 is the source electrode, and the other of the first electrode E1 and the second electrode E2 is the drain electrode, and the data line DL is electrically connected to the source electrode. The data line DL, the first electrode E1, and the second electrode E2 may belong to the same conductive layer (e.g., referred to as the third conductive layer). The third conductive layer may be a single metal layer or a multilayer metal stack, such as a single layer of aluminum, a molybdenum / aluminum / molybdenum metal stack, or a titanium / aluminum / titanium metal stack, but is not limited thereto.

[0033] The method of repairing electronic device 1 may include: providing panel 10 (for details of panel 10, please refer to the foregoing, and will not be repeated here); and cutting at least one of first electrode E1 and second electrode E2 with laser beam B, wherein the cutting point P formed by laser beam B does not overlap with the first conductive layer 101.

[0034] For example, when a defect DF falls on the first electrode E1 and the second electrode E2 of transistor 103, causing a short circuit between the first electrode E1 and the second electrode E2, at least one of the first electrode E1 and the second electrode E2 can be cut at the opening A by the laser beam B, thereby disabling transistor 103. Taking Figure 1 as an example, the laser beam B can cut at least one of the first electrode E1 and the second electrode E2 along at least one of the paths L1 and L2. When the first electrode E1 contains multiple branches, the path L1 traverses the multiple branches of the first electrode E1. Therefore, when the laser beam B cuts multiple first electrodes E1 along the path L1, it will sequentially break the multiple branches of the first electrode E1, and form a cutting point P at the break point of each branch of the first electrode E1 (for the simplicity of Figure 1, only the multiple cutting points P of the branches of the second electrode E2 are shown). Similarly, when the second electrode E2 contains multiple branches, the path L2 traverses these branches. Therefore, when the laser beam B cuts the second electrode E2 along the path L2, it sequentially breaks the multiple branches of the second electrode E2, forming a cutting point P at the break point of each branch of the second electrode E2. It should be noted that in some embodiments, the laser beam B may also cut only a portion of the branches of the first electrode E1 and / or the second electrode E2.

[0035] In this embodiment, the opening A of the first conductive layer 101 is designed to correspond to the laser repair / cutting area. That is, the range of the opening A at least covers the laser cutting path (such as path L1 and path L2), and in the top view, the opening A overlaps with the cutting point P. When the laser beam B cuts the third conductive layer (such as the first electrode E1 or the second electrode E2), since there is no first conductive layer 101 below the cutting point P of the third conductive layer, the problem of short circuit caused by high-temperature melting of the upper and lower conductive layers (such as the third conductive layer and the first conductive layer 101) during the laser repair process can be improved. In some embodiments, the electronic device 1 can be an antenna device, and the panel 10 can be a high-frequency single substrate for antennas. The design of the opening A of the first conductive layer 101 can improve the short circuit problem during the laser repair process, while simplifying the circuit design of the first conductive layer 101 in the high-frequency single substrate or meeting the return current (the current generated by the antenna device when receiving signals) at various frequencies.

[0036] In some embodiments, the opening A may be rectangular, but is not limited thereto. Considering the spot size of the laser beam B, the width WA of the opening A is, for example, greater than or equal to 5 micrometers (μm). On the other hand, considering the size of the transistor 103 and electromagnetic wave propagation, the length LA of the opening A may be designed to be less than or equal to the length LGE of the gate GE, while the maximum length ML of the opening A (e.g., diagonal length) is, for example, less than one-fifth of the wavelength of the electromagnetic wave. Generally, the operating frequency of antenna devices used for communication purposes is from 1 GHz to 1 THz. Since the product of the wavelength and frequency of electromagnetic waves used for communication is equal to the speed of light, calculations show that when the operating frequency is 1 GHz, the wavelength of electromagnetic waves used for communication can reach 300 meters (m), therefore the maximum length ML can be, for example, less than 60 meters, and when the operating frequency is 1 THz, the maximum length ML is, for example, less than 60 micrometers. In some embodiments, the maximum length ML of the opening A may be less than or equal to 10 centimeters (cm) to match the actual size of the antenna device.

[0037] Referring to Figures 3 and 4, the main differences between electronic device 1A and electronic device 1 of Figures 1 and 2 are explained below. In electronic device 1A, panel 10A further includes a reflective layer 105 for reflecting the laser beam B. The reflective layer 105 is disposed between the first conductive layer 101A and the transistor 103, and for example, between the first conductive layer 101A and the dielectric layer 102. In some embodiments, the material of the reflective layer 105 includes silicon nitride, but is not limited thereto. In some embodiments, the reflective layer 105 includes a plurality of sublayers (such as sublayer 105-1 and sublayer 105-2, but not limited thereto), and the refractive indices of two adjacent sublayers are different. Taking silicon nitride as an example of the material of the sublayers, the refractive indices of different sublayers can be controlled by changing the ratio of nitrogen to silicon in each sublayer. In other words, for sublayers with different refractive indices formed by this method, when the ratio of silicon-hydrogen bonds (Si-H) to nitrogen-hydrogen bonds (NH) in sublayer 105-1 and sublayer 105-2 is analyzed using Fourier Transform Infrared Spectroscopy (FTIR), the ratio of silicon-hydrogen bonds to nitrogen-hydrogen bonds in sublayer 105-1 differs from that in sublayer 105-2. In some embodiments, the thickness of sublayer 105-1 and sublayer 105-2 can be approximately one-quarter of the wavelength of the laser beam B, for example, in the range of one-third to one-fifth of the wavelength (1 / 5 laser beam wavelength ≤ sublayer thickness ≤ 1 / 3 laser beam wavelength), but is not limited thereto.

[0038] Although Figure 4 only schematically illustrates one sublayer 105-1 and one sublayer 105-2, it should be understood that the number of high and low refractive index sublayers in the reflective layer 105 can be changed as needed, and the reflective layer 105 can be formed by alternating stacking of one or more high refractive index sublayers and one or more low refractive index sublayers.

[0039] The method of repairing electronic device 1A may include: providing panel 10A (details of panel 10A are described above and will not be repeated here); and cutting at least one of first electrode E1 and second electrode E2 with laser beam B, wherein reflective layer 105 is used to reflect laser beam B.

[0040] For example, when a defect DF falls on the first electrode E1 and the second electrode E2 of transistor 103, causing a short circuit between the first electrode E1 and the second electrode E2, at least one of the first electrode E1 and the second electrode E2 can be cut by the laser beam B to disable transistor 103. Taking Figure 3 as an example, the laser beam B can cut at least one of the first electrode E1 and the second electrode E2 along at least one of paths L1 and L2. For example, when the first electrode E1 and / or the second electrode E2 each contain multiple branches, path L1 traverses the multiple branches of the first electrode E1. Therefore, when the laser beam B cuts multiple first electrodes E1 along path L1, it sequentially breaks the multiple branches of the first electrode E1, forming a cutting point P at the point where the branches of the first electrode E1 break (for simplicity, only the cutting points P of the multiple branches of the second electrode E2 are shown in Figure 3). Path L2 traverses multiple branches of the second electrode E2. Therefore, when laser beam B cuts multiple branches of the second electrode E2 along path L2, it sequentially breaks each branch of the second electrode E2, forming a cutting point P at the branch break. It should be noted that in some embodiments, laser beam B may also only cut a portion of the branches of the first electrode E1 and / or the second electrode E2.

[0041] In this embodiment, a reflective layer 105 is disposed between the first conductive layer 101A and the third conductive layer (including the first electrode E1 and the second electrode E2). The reflective layer 105 overlaps the laser repair / cutting area. For example, the reflective layer 105 can completely cover the substrate 100, but is not limited thereto. When the laser beam B cuts the third conductive layer, since there is a reflective layer 105 below the cutting point P of the third conductive layer, the reflective layer 105 reflects the laser beam B, thereby reducing the problem of short circuit between the first conductive layer 101A and the third conductive layer due to high temperature melting. By providing the reflective layer 105, the first conductive layer 101A does not need to form the opening A corresponding to the laser repair / cutting area.

[0042] Please refer to Figure 5. The main differences between electronic device 1B and electronic device 1A in Figures 3 and 4 are explained below. In electronic device 1B, panel 10B also includes a fourth conductive layer 106, a dielectric layer 107, and a dielectric layer 108.

[0043] The fourth conductive layer 106 is disposed on the substrate 100 and located between the substrate 100 and the dielectric layer 107. The material of the fourth conductive layer 106 can be referred to the material of the first conductive layer 101 described above, and will not be repeated here.

[0044] A dielectric layer 107 is disposed on the substrate 100 and the fourth conductive layer 106 and has a plurality of vias TH. The plurality of vias TH expose different regions of the fourth conductive layer 106. The material of the dielectric layer 107 can be referred to the material of the dielectric layer 102 described above, and will not be repeated here.

[0045] A first conductive layer 101B is disposed on the dielectric layer 107 and located between the dielectric layer 107 and the dielectric layer 102. The first conductive layer 101B is, for example, a patterned metal layer and includes a plurality of patterned PTs. At least a portion of the plurality of patterned PTs can be coupled to the fourth conductive layer 106 through a plurality of vias TH. The first conductive layer 101B can be a noise masking structure, for example, an electromagnetic bandgap (EBG) structure, wherein the plurality of patterned PTs can be a periodic structure to control electromagnetic waves or reduce electromagnetic interference.

[0046] A dielectric layer 102 is disposed on the dielectric layer 107 and the first conductive layer 101B and is located between the reflective layer 105 and the first conductive layer 101B. As shown in FIG5, the reflective layer 105 is disposed on the dielectric layer 102 and is located between the dielectric layer 104 and the first conductive layer 102. A second conductive layer (including a gate GE), a dielectric layer 104, a semiconductor layer (including a semiconductor pattern CH), a third conductive layer (including a first electrode E1 and a second electrode E2), and a dielectric layer 108 may be sequentially formed on the reflective layer 105, but are not limited thereto. For example, in some embodiments, the gate GE may be located above the first electrode E1 and the second electrode E2. The material of the dielectric layer 108 may refer to the material of the dielectric layer 102 described above, and will not be repeated here.

[0047] Referring to Figures 6 and 7, the main differences between electronic device 1C and electronic device 1 of Figures 1 and 2 are explained below. In electronic device 1C, the first conductive layer 101C in panel 10C is a grid-like electrode with a plurality of openings A arranged in an array. Panel 10C also includes electrodes E3 and E4. Electrodes E3 and E4 are both disposed on dielectric layer 102, and electrodes E3 and E4 may, for example, but not limited to, belong to the second conductive layer along with scan line SL and gate. Second electrode E2 may penetrate dielectric layer 104 and be electrically connected to electrode E3, while electrode E4 may penetrate dielectric layer 102 and be electrically connected to the first conductive layer 101C, but is not limited thereto.

[0048] Panel 10C may also include one or more modulation elements 109 (Figure 6 only schematically shows one). The modulation element 109 is disposed on substrate 100 and is used to modulate the phase and amplitude of a communication electromagnetic wave having a wavelength, or simultaneously modulates both the phase and amplitude (not shown) of the communication electromagnetic wave having a wavelength. The modulation element 109 is coupled to transistor 103; more specifically, in an electronic device, each modulation element 109 may be coupled to a different transistor 103, but this disclosure is not limited thereto. For example, the two ends of the modulation element 109 may be electrically connected to electrodes E3 and E4 respectively through conductive elements (not shown), and the modulation element 109 may be electrically connected to the second electrode E2 of transistor 103 through electrode E3, but this is not a limitation. As mentioned above, when the antenna device is used for communication purposes, based on considerations of electromagnetic wave transmission, the length of opening A (e.g., the maximum length ML) is, for example, less than one-fifth of the wavelength of the communication electromagnetic wave. Conductive components may include conductive bumps (such as solder balls), conductive adhesives such as anisotropic conductive film (ACF), but are not limited thereto. Modulation element 109 may be, for example, a variable capacitor, a variable inductor, a diode, or a combination thereof.

[0049] Referring to Figures 8 and 9, the main differences between electronic device 1D and electronic device 1C of Figures 6 and 7 are explained below. In electronic device 1D, panel 10D further includes dielectric layer 108 and conductive element CT, and transistor 103, dielectric layer 102, first conductive layer 101C, and dielectric layer 108 are sequentially formed on substrate 100. Furthermore, electrodes E3 and E4 are disposed on dielectric layer 108, wherein electrode E3 penetrates dielectric layer 108 and dielectric layer 102 and is electrically connected to second electrode E2, and electrode E4 penetrates dielectric layer 108 and is electrically connected to first conductive layer 101C. Additionally, modulation element 109 is electrically connected to electrodes E3 and E4 through conductive element CT.

[0050] In some embodiments, when a defect DF falls on the first electrode E1 and / or the second electrode E2 of the transistor 103, causing a short circuit between the first electrode E1 and the second electrode E2, laser repair / cutting can be performed before forming the first conductive layer 101C, after forming the first conductive layer 101C and before bonding the modulation element 109, or after bonding the modulation element 109, to disable the transistor 103. For details regarding paths L1 and L2, cutting point P, etc., please refer to the foregoing and will not be repeated here.

[0051] In other embodiments, when the defect DF falls on the scan line SL, as shown in Figures 10A and 10B, before forming the first conductive layer 101C, the scan line SL can be cut along paths L1 and L2 with a laser beam (not shown), where paths L1 and L2 are located on opposite sides of the defect DF. After the laser beam cuts the scan line SL along paths L1 and L2, the scan line SL is divided into three parts, including a first part P1, a second part P2, and a third part P3, where the third part P3 is connected to the gate GE, the second part P2 is located between the first part P1 and the third part P3, and the defect DF is located on the second part P2. Then, a conductor SL' connecting the first part P1 and the third part P3 can be formed by means such as laser-assisted chemical vapor deposition, so that the first part P1 and the third part P3 are electrically connected. Subsequently, subsequent film layers and components (such as the first conductive layer 101C, electrode E3, electrode E4, and modulation element 109) can be formed to form panel 10D.

[0052] Similarly, when the defect DF falls on the data line DL, as shown in Figures 11A and 11B, before forming the first conductive layer 101C, the data line DL can be cut along paths L1 and L2 with a laser beam (not shown), where paths L1 and L2 are located on opposite sides of the defect DF. After the laser beam cuts the data line DL along paths L1 and L2, the data line DL is divided into three parts, including a first part P1', a second part P2', and a third part P3', where the third part P3' is connected to the first electrode E1, the second part P2' is located between the first part P1' and the third part P3', and the defect DF is located on the second part P2'. Then, a wire DL' connecting the first part P1' and the third part P3' can be formed by means such as laser-assisted chemical vapor deposition, so that the first part P1' and the third part P3' are electrically connected. Subsequently, subsequent film layers and components (such as the first conductive layer 101C, electrode E3, electrode E4, and modulation element 109) can be formed to form panel 10D.

[0053] By performing laser cutting / repair before forming the first conductive layer 101C, short circuits caused by high-temperature melting of the upper and lower metal layers during laser cutting / repair can be avoided.

[0054] In summary, in the embodiments disclosed herein, the short circuit problem caused by laser repair can be improved by forming an opening in the first conductive layer, forming a reflective layer between the first conductive layer and the transistor, or performing laser cutting / repair before forming the first conductive layer.

[0055] The above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein.

[0056] While the embodiments and advantages of this disclosure have been presented above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure, and features of the various embodiments can be arbitrarily mixed and substituted to form other new embodiments. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Anyone skilled in the art can understand from the content of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments. The scope of protection of this disclosure shall be determined by the appended claims.

[0057] 1, 1A, 1B, 1C, 1D: Electronic devices 10, 10A, 10B, 10C, 10D: Panels 100:Substrate 101, 101A, 101B, 101C: First conductive layer 102, 104, 107, 108: Dielectric layers 103: Transistor 105: Reflective layer 105-1, 105-2: Sublayers 106: Fourth conductive layer 109: Modulation element A: Opening B: Laser Beam CH: Semiconductor pattern CT: Conductive component DF: Defect DL: Data Line E1: First electrode E2: Second electrode E3, E4: Electrodes GE: Gate L1, L2: Paths LA, LGE: Length ML: Maximum length P: Cutting point P1, P1': Part 1 P2, P2': Part Two P3, P3': Part Three PT: Pattern SL: Scan line SL', DL': Conductors TH: Through-hole WA:width Z: Direction

Claims

1. A method for repairing an electronic device, comprising: A panel is provided, the panel comprising: a substrate; a first conductive layer disposed on the substrate; a dielectric layer disposed on the first conductive layer; a transistor disposed on the dielectric layer, wherein the transistor includes a first electrode and a second electrode; and a reflective layer disposed between the first conductive layer and the transistor; and laser beam cutting at least one of the first electrode and the second electrode, wherein the reflective layer is used to reflect the laser beam.

2. The method of repairing an electronic device as claimed in claim 1, wherein the material of the reflective layer comprises silicon nitride.

3. The method for repairing an electronic device as claimed in claim 1, wherein the reflective layer comprises a plurality of sublayers, and adjacent sublayers have different refractive indices.

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