Semiconductor packages

Abstract

A semiconductor package includes: a lower substrate and an upper substrate spaced apart from the lower substrate, wherein a gap exists between the lower substrate and the upper substrate; a logic chip and a memory chip mounted side-by-side on the top surface of the lower substrate, wherein the thickness of the logic chip is not less than 125 micrometers; a connection structure disposed between the lower substrate and the upper substrate, wherein the connection structure is located around the logic chip and the memory chip for electrically connecting the lower substrate and the upper substrate; and a sealing resin filling the gap to seal the logic chip, the memory chip, and the connection structure within the gap.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor packaging and more particularly to a thermally enhanced semiconductor package having a thick logic chip. Prior Art

[0002] Package-on-Package (PoP) is an integrated circuit packaging method that vertically combines discrete logic and memory ball grid array (BGA) packages. Two or more packages are mounted on top of each other, or stacked, and signals are routed between them using a standard interface. This allows for higher component density in devices such as mobile phones or digital cameras.

[0003] PoP solutions are commonly used for baseband and application processors in mobile phones. High-end mobile phones are rapidly adopting PoP packaging to meet high input / output (I / O) and performance requirements. The main advantage of PoP is that devices can be fully tested individually before assembly.

[0004] With the development of the semiconductor industry, many studies have been conducted to improve the reliability and durability of semiconductor packaging. Improving the PoP structure to improve heat dissipation efficiency has become very important and imperative. Summary of the Invention

[0005] The present disclosure provides a semiconductor packaging structure that can improve the heat dissipation problem of a PoP structure.

[0006] In one embodiment, a semiconductor package may include: a lower substrate and an upper substrate spaced apart from the lower substrate, wherein a gap is included between the lower substrate and the upper substrate; a logic chip and a memory chip mounted side by side on a top surface of the lower substrate, wherein the thickness of the logic chip is not less than 125 microns; a connecting structure disposed between the lower substrate and the upper substrate, wherein the connecting structure is located around the logic chip and the memory chip and is used to electrically connect the lower substrate and the upper substrate; and a sealing resin filled in the gap to seal the logic chip, the memory chip, and the connecting structure in the gap.

[0007] In one embodiment, a semiconductor package may include: a substrate; a fan-out device mounted on a top surface of the substrate, wherein the fan-out device includes a logic chip and a redistribution layer disposed between the logic chip and the substrate, wherein the thickness of the logic chip is not less than 125 microns; a memory chip mounted on the top surface of the substrate, wherein the fan-out device and the memory chip are disposed side by side; and a sealing resin for sealing the logic chip and the memory chip. Simple diagram description

[0008] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings: FIG1 is a schematic cross-sectional view showing an exemplary package-on-package (PoP) having a thick logic chip; Figure 2 is a schematic cross-sectional view showing an exemplary semiconductor package having a thick logic chip according to an embodiment of the present disclosure; Figure 3 is a schematic diagram showing an exemplary chip arrangement of a semiconductor package having a thick logic chip according to another embodiment of the present disclosure; FIG4 is a schematic cross-sectional view along line II′ of FIG3 . 5 is a schematic diagram illustrating an exemplary chip arrangement of a semiconductor package having a thick logic chip according to yet another embodiment of the present disclosure; and FIG. 6 is a schematic cross-sectional view along line II-II′ of FIG. 5 . Implementation Method

[0009] In the following detailed description of the embodiments of the disclosure, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

[0010] The present disclosure describes these embodiments in sufficient detail to enable one skilled in the art to practice them, and it should be understood that other embodiments may be utilized and mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the embodiments of the present disclosure is limited solely by the appended claims.

[0011] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or other elements or layers may be present between them. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. Like numbers refer to like elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0012] Figure 1 is a schematic cross-sectional view illustrating an exemplary package-on-package (PoP) with a thick logic chip. As shown in Figure 1 , a PoP device 1, such as a high-bandwidth PoP (HBPoP), may include a semiconductor package 10 and a memory package 20, such as a low-power (LP) DDR DRAM package, stacked on semiconductor package 10. According to one embodiment, by way of example, memory package 20 may include a substrate 200, a memory chip 210 mounted on substrate 200, and a molding compound 220 encapsulating memory chip 210. According to one embodiment, by way of example, memory package 20 may be electrically connected to semiconductor package 10 via a plurality of conductive elements 230, such as solder balls or bumps.

[0013] The semiconductor package 10 includes a lower substrate 100 having a top surface 100a and an opposite bottom surface 100b. According to one embodiment, the lower substrate 100 may be a printed wiring board, a redistribution layer (RDL) substrate, or a package substrate, and may include a plurality of conductive interconnect structures 110 and at least one insulating layer 112. According to one embodiment, as an example, the conductive interconnect structures 110 may include a plurality of pad patterns 110a distributed on the top surface 100a and a plurality of pad patterns 110b distributed on the bottom surface 100b.

[0014] According to one embodiment, the logic chip 50 is flip-chip mounted on the top surface 100a of the lower substrate 100. For example, the logic chip 50 may be an application processor (AP) chip or a baseband processor chip, but is not limited thereto. According to one embodiment, for example, the logic chip 50 has a thickness t of no less than 125 microns. For example, the thickness t is between 125 and 350 microns, such as 170 microns, which is thicker than typical logic chips (approximately 80 microns) used in high-end mobile devices such as high-end mobile phones. The increased chip thickness can improve the thermal performance of the semiconductor package and the performance of the XPU.

[0015] According to one embodiment, for example, the logic chip 50 has an active front side 50a and a passive rear side 50b. According to one embodiment, for example, a plurality of input / output (I / O) pads 501 are provided on the active front side 50a. According to one embodiment, for example, the logic chip 50 is electrically connected to the lower substrate 100 via a plurality of conductive elements 502 (e.g., solder bumps, metal bumps, or pillars) formed on the plurality of I / O pads 501. According to one embodiment, an underfill resin 510 may be filled into the space between the logic chip 50 and the top surface 100a of the lower substrate 100. According to one embodiment, the conductive elements 502 are surrounded by the underfill resin 510.

[0016] According to one embodiment, a logic chip 50 is disposed between a lower substrate 100 and an upper substrate 300. According to one embodiment, the upper substrate 300 may be a printed circuit board or a package substrate, having a plurality of conductive interconnect structures 310 and at least one insulating layer 312. According to one embodiment, by way of example, the conductive interconnect structures 310 may include a plurality of pad patterns 310a distributed on the top surface 300a of the upper substrate 300 and a plurality of pad patterns 310b distributed on the bottom surface 300b of the upper substrate 300. According to one embodiment, a plurality of copper-core solder balls 60 or other more ductile metal connections are disposed on the pad patterns 310b on the bottom surface 300b of the upper substrate 300.

[0017] According to one embodiment, the lower substrate 100 is electrically connected to the upper substrate 300 via the copper-core solder balls 60 surrounding the logic chip 50. Sealing resin SM fills the gap h between the bottom of the lower substrate 100 and the upper substrate 300. According to one embodiment, for example, within a ball pitch range of 0.2-0.3 mm, the gap height h may be between 160-450 microns, but is not limited thereto. According to one embodiment, for example, the width w of the pad pattern 110a to which the copper-core solder balls 60 are attached may be between 100-300 microns, but is not limited thereto. According to one embodiment, for example, the aspect ratio of the copper-core solder balls 60 may be between 1.1-2.0. For example, the copper-core solder balls 60 may have an aspect ratio of approximately 1.44. According to one embodiment, for example, the ball pitch P of the copper-core solder balls 60 may be between 0.2-0.3 mm.

[0018] According to one embodiment, the sealing resin SM surrounds the copper core solder balls 60 and covers the passive backside 50b and sidewalls of the logic chip 50. According to one embodiment, the sealing resin SM directly contacts the bottom surface 300b of the upper substrate 300, the side surfaces of the underfill resin 510, and the top surface 100a of the lower substrate 100. The gap between the lower substrate 100 and the upper substrate 300 is sealed with the sealing resin SM. By way of example, the distance d between the passive backside 50b of the logic chip 50 and the bottom surface 300b of the upper substrate 300 can be equal to or greater than 30 microns.

[0019] According to one embodiment, each copper-core solder ball 60 may include a copper core 602 having a diameter of approximately 10 microns, coated with a solder layer 604. The copper-core solder balls 60 are connected to the lower substrate 100 and the upper substrate 300. According to one embodiment, for example, the copper core 602 may be formed of copper or a copper alloy and shaped into a solid sphere. According to one embodiment, for example, the upper substrate 300 having the copper-core solder balls 60 may be mounted on the top surface 100a of the lower substrate 100 using a thermal compression bonding (TCB) method.

[0020] According to one embodiment, external connection terminals 120, such as solder balls or BGA balls, can be respectively bonded to pad patterns 110b on the bottom surface 100b of the lower substrate 100 to further connect to a motherboard or system board. According to one embodiment, surface mount devices 130, such as capacitors or resistors, can be mounted on the bottom surface 100b of the lower substrate 100.

[0021] As mentioned earlier, PoP solutions are commonly used for baseband and application processors in mobile phones. High-end mobile phones are rapidly adopting PoP packaging to meet high I / O and performance requirements. The main advantage of stacked PoP is that devices can be fully tested individually before assembly.

[0022] With the development of the semiconductor industry, many studies have been conducted to improve the reliability and durability of semiconductor packages. It has become very important to improve the PoP structure to improve heat dissipation efficiency.

[0023] Figure 2 is a schematic cross-sectional view illustrating an exemplary semiconductor package having a thick logic chip according to an embodiment of the present disclosure, in which similar layers, regions, or components are designated by similar reference numerals or labels. As shown in Figure 2 , similarly, a semiconductor package 2, such as a high-bandwidth side-by-side (HBSBS) package, includes a lower substrate 100 having a top surface 100a and an opposing bottom surface 100b. According to one embodiment, lower substrate 100 may be a printed wiring board, a redistribution layer (RDL) substrate, or a package substrate, and may include a plurality of conductive interconnect structures 110 and at least one insulating layer 112. According to one embodiment, by way of example, conductive interconnect structure 110 may include a plurality of pad patterns 110a, 110c, and 110d distributed on top surface 100a, and a plurality of pad patterns 110b distributed on bottom surface 100b.

[0024] According to one embodiment, the logic chip 50 is flip-chip mounted on the top surface 100a of the lower substrate 100. According to one embodiment, the logic chip 50 may be, for example, a system-on-chip (SoC) chip (typically including an application processor (AP) and a modem), an application processor chip, or a baseband processor chip, but is not limited thereto. According to one embodiment, the logic chip 50 may have a thickness t of, for example, between 125 and 750 microns, for example, between 125 and 733 microns, which is thicker than typical logic chips used in high-end mobile devices such as high-end mobile phones (having a thickness of approximately 80 microns). According to some embodiments, the logic chip 50 may have a thickness t of, for example, between 250 and 750 microns. According to some embodiments, the logic chip 50 may have a thickness t of, for example, between 250 and 733 microns.

[0025] According to one embodiment, for example, a logic chip 50 has an active front side 50a and a passive back side 50b. According to one embodiment, for example, a plurality of input / output (I / O) pads 501 are provided on the active front side 50a. According to one embodiment, for example, the logic chip 50 is electrically connected to the lower substrate 100 via a plurality of conductive elements 502 (e.g., solder bumps, metal bumps, or pillars) formed on the plurality of I / O pads 501. The conductive elements 502 are electrically connected to the pad pattern 110c of the conductive interconnect structure 110 of the lower substrate 100. According to one embodiment, an underfill resin 510 may be injected into the space between the logic chip 50 and the top surface 100a of the lower substrate 100. According to one embodiment, the conductive elements 502 are surrounded by the underfill resin 510.

[0026] According to one embodiment, for example, the memory chip 70 is mounted on the top surface 100a of the lower substrate 100 and is disposed adjacent to the logic chip 50. The logic chip 50 and the memory chip 70 are disposed on the top surface 100a of the lower substrate 100 in a side-by-side arrangement. According to one embodiment, for example, the memory chip 70 may be mounted on the top surface 100a of the lower substrate 100 in a flip-chip manner, but is not limited thereto.

[0027] According to one embodiment, the memory chip 70 may include, for example, a dynamic random access memory (DRAM). For example, the memory chip 70 is a double data rate (DDR) dynamic random access memory (DRAM) chip, such as a low power (LP) DDR DRAM chip. For example, the LPDDR DRAM chip may be an LPDDR5X DRAM chip, which can operate at a data rate of up to 8533 Mbps. According to one embodiment, for example, the memory chip 70 is electrically connected to the lower substrate 100 via a plurality of conductive elements 702 (e.g., solder bumps, metal bumps, or pillars). The conductive elements 702 are electrically connected to the pad pattern 110d of the conductive interconnect structure 110 of the lower substrate 100.

[0028] According to one embodiment, a logic chip 50 and a memory chip 70 are disposed between a lower substrate 100 and an upper substrate (or bridge substrate) 300. According to one embodiment, the upper substrate 300 may be a printed wiring board, a redistribution layer (RDL) substrate, or a package substrate, and may include a plurality of conductive interconnect structures 310 and at least one insulating layer 312. According to one embodiment, by way of example, the conductive interconnect structures 310 may include a plurality of pad patterns 310a distributed on a top surface 300a and a plurality of pad patterns 310b distributed on a bottom surface 300b. According to one embodiment, a connection structure 90 may be disposed between the lower substrate 100 and the upper substrate 300 to electrically connect the upper substrate 300 and the lower substrate 100. The upper substrate 300 and the connection structure 90 provide a signal path for signal transmission between the far-side DRAM connection circuits of the logic chip 50 and the memory chip 70. According to some embodiments, the connection structure 90 may include a plurality of conductive structures 900 (e.g., metal pillars, solder balls, metal vias) and an insulating layer 901 surrounding the plurality of conductive structures 900. As shown in Figure 2, the conductive structure 900 can be I-shaped, and the insulating layer 901 can be made of a combination of B (bismaleimide) and T (triazine), but is not limited thereto. According to some embodiments, the connection structure 90 can include copper-core solder balls, as shown in Figure 1. According to some embodiments, the aspect ratio of the copper-core solder balls can be, for example, between 1.1 and 2.0, such as 1.44. According to some embodiments, the pitch P of the copper-core solder balls can be, for example, between 0.2 and 0.3 mm. In other embodiments, the connection structure 90 can include other structures, and thus the structure of the connection structure 90 is not limited to the examples provided herein.

[0029] According to one embodiment, the lower substrate 100 can be electrically connected to the upper substrate 300 via the connection structure 90 and the solder balls 902 disposed around the logic chip 50 and the memory chip 70. A sealing resin SM is filled into the gap between the lower substrate 100 and the upper substrate 300, and the gap has a height h. According to one embodiment, the gap height h can be, for example, between 160 and 1000 microns, but is not limited thereto. According to one embodiment, the width w of the pad pattern 110a can be, for example, between 100 and 300 microns, but is not limited thereto.

[0030] According to one embodiment, the sealing resin SM surrounds the connection structure 90 and the solder balls 902. According to one embodiment, the sealing resin SM covers the logic chip 50 and the memory chip 70. According to one embodiment, the sealing resin SM directly contacts the bottom surface 300b of the upper substrate 300, the side surfaces of the underfill resin 510, and the top surface 100a of the lower substrate 100. The gap between the lower substrate 100 and the upper substrate 300 is sealed by the sealing resin SM. The distance d between the passive back surface 50b of the logic chip 50 and the bottom surface 300b of the upper substrate 300 can be equal to or greater than 30 microns.

[0031] Signals, such as high-speed signals, can be transmitted between the memory chip 70 and the proximal DRAM connection circuit region (e.g., DDR connection circuit CN) of the logic chip 50 adjacent to the memory chip 70 via the conductive interconnect structure 110 of the lower substrate 100 (e.g., the first metal layer of the conductive interconnect structure 110). Signals, such as high-speed signals, can be transmitted between the memory chip 70 and the distal DRAM connection circuit region (e.g., DDR connection circuit CF) of the logic chip 50 away from the memory chip 70 via the upper substrate 300 and the conductive structure 900 of the connection structure 90. For illustrative purposes, the signal transmission path between the memory chip 70 and the distal DDR connection circuit region CF of the logic chip 50 is indicated by arrow SP.

[0032] According to one embodiment, external connection terminals 120, such as solder balls or BGA balls, are bonded to pad patterns 110b on the bottom surface 100b of the lower substrate 100 for further connection to a motherboard or system board. According to one embodiment, surface mount devices 130, such as capacitors or resistors, may be mounted on the bottom surface 100b of the lower substrate 100.

[0033] FIG3 is a schematic diagram illustrating an exemplary chip arrangement of a semiconductor package having a thick logic chip according to another embodiment of the present disclosure. FIG4 is a schematic cross-sectional view of FIG3 along line II'. As shown in FIG3 and FIG4, semiconductor package 3 includes a lower substrate 100 having a top surface 100a and an opposing bottom surface 100b. According to one embodiment, lower substrate 100 may be a printed wiring board, a redistribution layer (RDL) substrate, or a package substrate, and may include a plurality of conductive interconnect structures 110 and at least one insulating layer 112. According to one embodiment, by way of example, conductive interconnect structure 110 may include a plurality of pad patterns 110c and 110d distributed on top surface 100a, and a plurality of pad patterns 110b distributed on bottom surface 100b.

[0034] According to one embodiment, a fan-out device 5 including a logic chip 50 is flip-chip mounted on the top surface 100a of the lower substrate 100. For example, the fan-out device 5 may be a fan-out chip package. According to one embodiment, for example, the logic chip 50 may be a system-on-chip chip, an application processor chip, or a baseband processor chip, but is not limited thereto. According to one embodiment, for example, the logic chip 50 is overmolded. According to one embodiment, for example, the logic chip 50 may have a thickness t in the range of 125-750 microns, for example, 125-733 microns, which is thicker than typical logic chips used in high-end mobile devices (such as high-end mobile phones) (having a thickness of approximately 80 microns). According to some embodiments, for example, the logic chip 50 may have a thickness t in the range of 250-750 microns. According to some embodiments, for example, the logic chip 50 may have a thickness t in the range of 250-733 microns.

[0035] According to one embodiment, for example, the fan-out device 5 includes a redistribution layer (RDL) 560 disposed between the logic chip 50 and the lower substrate 100 to redistribute the I / O pads 501 to 502 of the logic chip. The RDL 560 may be formed on the bottom surface of the molding compound 520 and the active front side 50a of the logic chip 50. According to one embodiment, for example, the RDL 560 may include metal traces 561 and an insulating layer 562.

[0036] According to one embodiment, similarly, memory chip 70 is mounted on top surface 100a of lower substrate 100 and disposed near fan-out device 5. Fan-out device 5 and memory chip 70 are arranged side by side on top surface 100a of lower substrate 100. According to one embodiment, for example, memory chip 70 may be mounted on top surface 100a of lower substrate 100 in a flip-chip manner, but is not limited thereto.

[0037] According to one embodiment, the memory chip 70 may include, for example, a dynamic random access memory (DRAM). For example, the memory chip 70 is a double data rate (DDR) dynamic random access memory (DRAM) chip, such as an LPDDR DRAM chip. For example, the LPDDR DRAM chip may be an LPDDR5X DRAM chip, which can operate at a data rate of up to 8533 Mbps. According to one embodiment, for example, the memory chip 70 is electrically connected to the lower substrate 100 via a plurality of conductive elements 702 (e.g., solder bumps, metal bumps, or pillars). The conductive elements 702 are electrically connected to the pad pattern 110d of the conductive interconnect structure 110 of the lower substrate 100.

[0038] As indicated by arrows SPN, signals such as high-speed signals can be transmitted between the memory chip 70 and a proximal DRAM connection circuit region (e.g., DDR connection circuit CN) of the logic chip 50 adjacent to the memory chip 70 via the RDL 560 and the conductive interconnect structure 110 of the lower substrate 100. As indicated by arrows SP, signals such as high-speed signals can be transmitted between the memory chip 70 and a distal DRAM connection circuit region (e.g., DDR connection circuit CF) of the logic chip 50 away from the memory chip 70 via the RDL 560 and the conductive interconnect structure 110 of the lower substrate 100.

[0039] According to one embodiment, sealing resin SM surrounds fan-out device 5 and memory chip 70. According to one embodiment, external connection terminals 120, such as solder balls or BGA balls, are bonded to pad patterns 110b on bottom surface 100b of lower substrate 100 for further connection to a motherboard or system board. According to one embodiment, surface mount devices 130, such as capacitors or resistors, may be mounted on bottom surface 100b of lower substrate 100.

[0040] FIG5 is a schematic diagram illustrating an exemplary chip arrangement of a semiconductor package having a thick logic chip according to yet another embodiment of the present disclosure. FIG6 is a schematic cross-sectional view of FIG5 along line II-II'. Similarly, as shown in FIG5 and FIG6, a semiconductor package 4, such as a high-bandwidth side-by-side (HBSBS) package, includes a lower substrate 100 having a top surface 100a and an opposing bottom surface 100b. According to one embodiment, lower substrate 100 may be a printed wiring board, a redistribution layer (RDL) substrate, or a package substrate, and may include a plurality of conductive interconnect structures 110 and at least one insulating layer 112. According to one embodiment, by way of example, conductive interconnect structure 110 may include a plurality of pad patterns 110c and 110d distributed on top surface 100a, and a plurality of pad patterns 110b distributed on bottom surface 100b.

[0041] According to one embodiment, a fan-out device 5 including a logic chip 50 is flip-chip mounted on the top surface 100a of the lower substrate 100. For example, the fan-out device 5 may be a fan-out chip package. According to one embodiment, for example, the logic chip 50 may be a system-on-chip chip, an application processor chip, or a baseband processor chip, but is not limited thereto. According to one embodiment, for example, the logic chip 50 is overmolded. According to one embodiment, for example, the logic chip 50 may have a thickness t in the range of 125-750 microns, for example, 125-733 microns, which is thicker than typical logic chips used in high-end mobile devices (such as high-end mobile phones) (having a thickness of approximately 80 microns). According to some embodiments, for example, the logic chip 50 may have a thickness t in the range of 250-750 microns. According to some embodiments, for example, the logic chip 50 may have a thickness t in the range of 250-733 microns.

[0042] According to one embodiment, for example, the fan-out device 5 includes a redistribution layer (RDL) 560 disposed between the logic chip 50 and the lower substrate 100 to redistribute the I / O pads 501 to 502 of the logic chip. The RDL 560 may be formed on the bottom surface of the molding compound 520 and the active front side 50a of the logic chip 50. According to one embodiment, for example, the RDL 560 may include metal traces 561 and an insulating layer 562.

[0043] According to one embodiment, similarly, memory chip 70 is mounted on top surface 100a of lower substrate 100 and disposed near fan-out device 5. Fan-out device 5 and memory chip 70 are arranged side by side on top surface 100a of lower substrate 100. According to one embodiment, for example, memory chip 70 may be mounted on top surface 100a of lower substrate 100 in a flip-chip manner, but is not limited thereto.

[0044] According to one embodiment, the memory chip 70 may include, for example, a dynamic random access memory (DRAM). For example, the memory chip 70 is a double data rate (DDR) dynamic random access memory (DRAM) chip, such as an LPDDR DRAM chip. For example, the LPDDR DRAM chip may be an LPDDR5X DRAM chip, which can operate at a data rate of up to 8533 Mbps. According to one embodiment, for example, the memory chip 70 is electrically connected to the lower substrate 100 via a plurality of conductive elements 702 (e.g., solder bumps, metal bumps, or pillars). The conductive elements 702 are electrically connected to the pad pattern 110d of the conductive interconnect structure 110 of the lower substrate 100.

[0045] According to one embodiment, to address package warpage, a reinforcement frame may be mounted on the top surface 100a of the lower substrate 100 using an adhesive layer 810. According to one embodiment, the reinforcement frame may comprise a high modulus material. According to one embodiment, the reinforcement frame may comprise, for example, stainless steel or a metal such as copper or iron, but is not limited thereto. According to one embodiment, the reinforcement frame may comprise at least one first reinforcement column, such as three parallel reinforcement columns 80a, 80b, and 80c disposed near the fan-out device 5 and the memory chip 70. In other embodiments, only one or two of the three parallel reinforcement columns 80a, 80b, and 80c are disposed near the fan-out device 5 and the memory chip 70.

[0046] For example, reinforcing column 80a extends along first direction D1 and is positioned on the left side of fan-out device 5, reinforcing column 80b extends along first direction D1 and is positioned between fan-out device 5 and memory chip 70, and reinforcing column 80c extends along first direction D1 and is positioned on the right side of memory chip 70. Fan-out device 5, memory chip 70, and the three parallel reinforcing columns 80a, 80b, and 80c are all sealed with sealing resin SM.

[0047] Optionally, the reinforcement frame may further include at least one second reinforcement column, such as two parallel reinforcement columns 80d and 80e. As shown in FIG5 , reinforcement columns 80d and 80e extend along a second direction D2. By way of example, first direction D1 is orthogonal to second direction D2. According to one embodiment, reinforcement columns 80a, 80b, 80c, 80d, and 80e surround the fan-out device 5 and the memory chip 70.

[0048] The disclosed high bandwidth side-by-side (HBSBS) package can solve the heat dissipation problem in a PoP structure to improve chip performance and further reduce the package height compared to a traditional PoP.

[0049] Those skilled in the art will readily appreciate that many modifications and variations can be made to the apparatus and method while retaining the teachings of the present disclosure. Therefore, the above disclosure should be interpreted as being limited only by the scope of the appended claims. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0050] 1:HBPoP 10, 2, 3, 4: Semiconductor packaging 310a, 310b, 110c, 110a, 110b, 110d: pad patterns 312, 112, 901, 562: insulation layer 300b: bottom surface of upper substrate 300 100a: top surface of the lower substrate 100 120: External connection terminal 602: Copper core 60: Copper core solder ball 604:Solder layer 50a: Active front 50b: Passive back 100b: bottom surface of the lower substrate 100 50:Logic chip 501: Input / output pad 502, 230, 702: conductive elements 130: Surface Mount Devices 510: bottom filling resin 300a: top surface of upper substrate 300 310, 110: Conductive interconnect structure 300: Upper substrate 100:Lower base plate 20:Memory packaging 210, 70: memory chips 220: Molding compound 200:Substrate 90: Connection structure 900: conductive structure 560: redistribution layer 561:Metal trace 80a, 80b, 80c, 80e, 80d: Reinforcement columns 5: Fan-out device

Claims

1. A semiconductor package, comprising: A lower substrate and an upper substrate spaced apart from the lower substrate, wherein a gap is included between the lower substrate and the upper substrate; a logic chip and a memory chip mounted side-by-side on the top surface of the lower substrate, wherein the thickness of the logic chip is not less than 125 micrometers; a connection structure disposed between the lower substrate and the upper substrate, wherein the connection structure is located around the logic chip and the memory chip, for electrically connecting the lower substrate and the upper substrate; and a sealing resin filling the gap to seal the logic chip, the memory chip, and the connection structure within the gap; wherein the memory chip includes a dynamic random access memory (DRAM) chip; wherein the logic chip includes a proximal DRAM connection circuit region adjacent to the DRAM chip and a distal DRAM connection circuit region disposed away from the DRAM chip, wherein a first high-speed signal is transmitted between the DRAM chip and the proximal DRAM connection circuit region through a conductive interconnect structure of a first portion of the lower substrate, and between the DRAM chip and the distal DRAM connection circuit region through the upper substrate and the connection structure. A second high-speed signal is transmitted between the connection circuit regions. The signal path for transmitting the second high-speed signal between the DRAM chip and the distal DRAM connection circuit region first passes through the second part of the lower substrate located below the logic chip and not overlapping with the first part of the lower substrate, then passes through the first part of the connection structure adjacent to the distal DRAM connection circuit region, then passes through the upper substrate, then passes through the second part of the connection structure away from the distal DRAM connection circuit region, and then passes through the third part of the lower substrate located below the DRAM chip and not overlapping with the first and second parts of the lower substrate.

2. The semiconductor package as described in claim 1, wherein the thickness of the logic chip is 125-750 micrometers.

3. The semiconductor package as claimed in claim 1, wherein the logic chip is mounted on the top surface of the lower substrate in a flip-chip manner.

4. The semiconductor package as claimed in claim 3, wherein the logic chip includes an active front side and a passive back side, wherein a plurality of input / output (I / O) pads are provided on the active front side, and the logic chip is electrically connected to the lower substrate through a plurality of conductive elements respectively formed on the plurality of I / O pads.

5. The semiconductor package as claimed in claim 1, wherein the DRAM chip includes a double data rate (DDR) DRAM chip.

6. The semiconductor package as claimed in claim 5, wherein the DDR DRAM chip includes a low-power (LP) DDR DRAM chip.

7. The semiconductor package as claimed in claim 1, wherein the connection structure includes a plurality of conductive structures and an insulating layer surrounding the plurality of conductive structures.

8. The semiconductor package as claimed in claim 1, wherein the logic chip includes a system-on-a-chip, an application processor chip, or a baseband processor chip.

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