Semiconductor device

Abstract

The present invention provides a semiconductor device comprising: a substrate including a cell array region and a peripheral circuit region, the substrate including a first active region defined in the cell array region and a second active region defined in the peripheral circuit region; a plurality of word lines located in the substrate and extending in a first direction; a bit line located in the cell array region and extending in a second direction perpendicular to the first direction; a plurality of first pad separation patterns respectively located on a corresponding one of the word lines and extending in the first direction; a cell pad structure located on the substrate and between two adjacent first pad separation patterns; and a second pad separation pattern located between two adjacent first pad separation patterns and adjacent to the cell pad structure.

Description

Technical Field

[0001] The present inventive concept relates to a semiconductor device. More particularly, the present inventive concept relates to a semiconductor device including a cell pad structure. [Cross - reference to Related Applications]

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2022 - 0089883, filed with the Korean Intellectual Property Office on July 20, 2022, the disclosure of which is incorporated herein by reference in its entirety. Prior Art

[0003] With the development of the electronics industry, semiconductor devices are gradually shrinking. Accordingly, the size of individual micro - circuit patterns for implementing semiconductor devices is further reduced. In addition, due to the high integration of integrated circuit devices, the line width of bit lines is reduced and the difficulty of the process for forming contacts between bit lines increases. Summary of the Invention

[0004] The present inventive concept provides a semiconductor device capable of reducing the cost of a semiconductor device manufacturing process while improving reliability.

[0005] According to an aspect of the present inventive concept, a semiconductor device includes: a substrate including a cell array region and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region; a plurality of word lines located in the substrate and extending in a first direction; a plurality of bit lines located in the cell array region of the substrate and extending in a second direction perpendicular to the first direction; a plurality of first pad isolation patterns respectively located on corresponding ones of the word lines, the first pad isolation patterns extending in the first direction; a cell pad structure located on the substrate and between two adjacent ones of the first pad isolation patterns; and a second pad isolation pattern located between two adjacent ones of the first pad isolation patterns and adjacent to the cell pad structure, wherein a cross - section of the cell pad structure perpendicular to the first direction has a quadrilateral shape, and two corners of a lower surface thereof are rounded.

[0006] According to another aspect of the inventive concept, a semiconductor device includes: a substrate including a cell array region, a boundary region, and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region; a word line located in the substrate and extending in a first direction; a bit line located in the cell array region of the substrate and extending in a second direction perpendicular to the first direction; a plurality of first pad isolation patterns located on the word line, the first pad isolation patterns extending in the first direction; a cell pad structure located on the substrate and between two adjacent ones of the first pad isolation patterns; a second pad isolation pattern located between two adjacent ones of the first pad isolation patterns, the second pad isolation pattern being adjacent to the cell pad structure; a first insulating layer located on the cell pad structure and extending to the boundary region; and a second insulating layer located on the first insulating layer and extending to the boundary region, wherein a first cross-section of the cell pad structure perpendicular to the first direction has a quadrilateral shape, wherein two corners of a lower surface are rounded, and wherein upper surfaces of the first insulating layer and the second insulating layer are flat.

[0007] According to another aspect of the inventive concept, a semiconductor device includes: a substrate including a cell array region, a boundary region, and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region; a word line located in the substrate and extending in a first direction; a capping insulating film located on the word line; a bit line located in the cell array region of the substrate and extending in a second direction perpendicular to the first direction; a direct contact located between the bit line and a corresponding one of the first active regions; a plurality of cell pad structures respectively contacting the first active regions, the cell pad structures being located on the substrate; a buried contact located on a corresponding one of the cell pad structures; a first pad isolation pattern located on the word line and extending in the first direction; a second pad isolation pattern located between two adjacent ones of the cell pad structures and extending in the second direction; a buffer layer located on the cell pad structures and extending to the boundary region; and a first insulating layer located on the buffer layer and extending to the boundary region, wherein a first cross-section of each of the cell pad structures perpendicular to the first direction has a quadrilateral shape, wherein two corners of a lower surface are rounded, wherein upper surfaces of the buffer layer and the first insulating layer are flat, and wherein a corresponding one of the capping insulating film and the first pad isolation pattern is respectively a part of a single integral structure. Brief Description of the Drawings

[0008] The following detailed description made with reference to the accompanying drawings will enable a clearer understanding of example embodiments of the inventive concept, in which: FIG. 1 is a layout diagram of a semiconductor device showing an exemplary embodiment according to the concept of the present invention. FIG. 2 is an enlarged layout diagram of a portion EX of FIG. 1. FIG. 3A is a cross-sectional view taken along line A-A' of FIG. 2. FIG. 3B is a cross-sectional view taken along line B-B' of FIG. 2. FIG. 4A is a cross-sectional view taken along line A-A' of FIG. 2 of a semiconductor device according to another exemplary embodiment of the concept of the present invention. FIG. 4B is a cross-sectional view taken along line B-B' of FIG. 2 of a semiconductor device according to another exemplary embodiment of the concept of the present invention. FIG. 5A is an enlarged cross-sectional view of a portion PX2 of FIG. 3B. FIG. 5B is an enlarged cross-sectional view of a portion corresponding to portion PX2 of FIG. 3B of a semiconductor device according to another exemplary embodiment of the concept of the present invention. FIGS. 6A to 6H are cross-sectional views showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Embodiments

[0009] Hereinafter, some exemplary embodiments of the technical idea of the concept of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and their repeated description is omitted.

[0010] Although the terms "same", "equal", or "equivalent" are used in the description of the exemplary embodiments, it should be understood that there may be some inaccuracies. Thus, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as another element within the manufacturing or operating tolerance range (e.g., ±10%) of what is to be manufactured or operated.

[0011] When the term "about" or "substantially" is used in this specification in connection with a numerical value, the associated numerical value is intended to include the manufacturing or operating tolerance (e.g., ±10%) with respect to the stated numerical value. In addition, when the phrases "about" and "substantially" are used in connection with a geometric shape, it is intended that the exactness of the geometric shape is not required, but the tolerance of the shape is within the scope of this disclosure. Further, whether a numerical value or a shape is modified by "about" or "substantially", it should be understood that such values and shapes should be interpreted as including the manufacturing or operating tolerance (e.g., ±10%) with respect to the stated numerical value or shape.

[0012] FIG. 1 is a layout diagram of a semiconductor device 100 showing an exemplary embodiment according to the concept of the present invention. FIG. 2 is an enlarged layout diagram of a portion EX of FIG. 1. FIG. 3A is a cross-sectional view taken along line A-A' of FIG. 2. FIG. 3B is a cross-sectional view taken along line B-B' of FIG. 2.

[0013] Referring to FIGS. 1 to 3B, the semiconductor device 100 may include a substrate 110 including a cell array region MCA and a peripheral circuit region PCA. The cell array region MCA may be a memory cell region of a dynamic random access memory (DRAM) device, and the peripheral circuit region PCA may be a core region or a peripheral circuit region of the DRAM device. For example, the cell array region MCA may include cell transistors CTR and a capacitor structure (not shown) connected thereto, and the peripheral circuit region PCA may include peripheral circuit transistors (not shown) for transmitting signals and / or power to the cell transistors (not shown) included in the cell array region MCA. In some exemplary embodiments, the peripheral circuit transistors may configure various circuits, such as a command decoder, control logic, an address buffer, a column decoder, a row decoder, a sense amplifier, and a data input / output circuit.

[0014] A boundary trench 114T may be formed in a boundary area BA between the cell array region MCA and the peripheral circuit region PCA, and a boundary structure 114 may be formed in the boundary trench 114T. In a plan view, the boundary trench 114T may be arranged to surround four surfaces (e.g., four sides) of the cell array region MCA. The boundary structure 114 may include a buried insulating layer 114A, an insulating liner 114B, and a gap-fill insulating layer 114C disposed inside the boundary trench 114T.

[0015] The buried insulating layer 114A may be conformally disposed on the inner wall of the boundary trench 114T. In some exemplary embodiments, the buried insulating layer 114A may include silicon oxide. For example, the buried insulating layer 114A may include silicon oxide formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, a low pressure CVD (LPCVD) process, or the like.

[0016] The insulating liner 114B can be conformally disposed on the inner wall of the boundary trench 114T, and more specifically, on the buried insulating layer 114A. In some example embodiments, the insulating liner 114B can include silicon nitride. For example, the insulating liner 114B can include silicon nitride formed by an ALD process, a CVD process, a PECVD process, an LPCVD process, or the like.

[0017] The gap-fill insulating layer 114C on the insulating liner 114B can fill the interior of the boundary trench 114T. In some example embodiments, the gap-fill insulating layer 114C can include silicon oxide, such as tonen silazene (TOSZ), undoped silicate glass (USG), boro-phospho-silicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma enhanced deposition of tetra-ethyl-ortho-silicate (PE-TEOS), or fluoride silicate glass (FSG).

[0018] A plurality of first active regions ACT1 can be respectively disposed to have a major axis in a diagonal direction with respect to a first horizontal direction X and a second horizontal direction Y. A plurality of word lines WL can extend parallel to each other in the first horizontal direction X across the plurality of first active regions ACT1. A plurality of bit lines BL can extend parallel to each other in the second horizontal direction Y on the plurality of word lines WL. The plurality of bit lines BL can be respectively connected to the plurality of first active regions ACT1 via direct contacts DC.

[0019] A plurality of unit pad structures 130 can be formed between two adjacent bit lines BL among the plurality of bit lines BL. The plurality of unit pad structures 130 can be arranged in rows in the first horizontal direction X and the second horizontal direction Y.

[0020] The substrate 110 can include silicon, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon. In some other example embodiments, the substrate 110 can include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some example embodiments, the substrate 110 can include conductive regions, such as wells doped with impurities or structures doped with impurities.

[0021] An element isolation trench 112T may be formed in a substrate 110, and an element isolation film 112 may be formed in the element isolation trench 112T. The element isolation film 112 may include, for example, an oxide film, a nitride film, or a combination thereof. In a cell array region MCA, a plurality of first active regions ACT1 may be defined on the substrate 110 by the element isolation film 112, and at least one second active region ACT2 may be defined on the substrate 110 in a peripheral circuit region PCA.

[0022] In the cell array region MCA, a plurality of word line trenches 120T extending in a first horizontal direction (X direction) to intersect the plurality of first active regions ACT1 may be disposed in the substrate 110, and a buried gate structure 120 may be disposed in each of the plurality of word line trenches 120T. The buried gate structure 120 may include a gate dielectric film 121, a gate electrode 123, and a capping insulating film 125. The plurality of gate electrodes 123 may respectively correspond to the plurality of word lines WL shown in FIG. 1.

[0023] The gate dielectric film 121 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO) film, or a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film. The gate electrode 123 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. The capping insulating film 125 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

[0024] A plurality of first pad isolation patterns 132 may be respectively disposed on the plurality of buried gate structures 120. Each of the plurality of first pad isolation patterns 132 may extend in a first direction (X direction) and may be spaced apart from each other in a second direction (Y direction). The first pad isolation pattern 132 may include, for example, silicon nitride. In some exemplary embodiments, the first pad isolation pattern 132 may be integrally formed with the capping insulating film 125. In other words, the capping insulating film 125 and the first pad isolation pattern 132 may be parts of a single integral structure, respectively. Accordingly, the length of the first pad isolation pattern 132 in the second direction (Y direction) may be the same as the length of the capping insulating film 125 in the second direction (Y direction). However, the inventive concept is not limited thereto, and if necessary, spacers (not shown) may be additionally formed on two sidewalls of the first pad isolation pattern 132.

[0025] A plurality of unit pad structures 130 can be disposed between two adjacent first pad isolation patterns 132. In some exemplary embodiments, a cross-section of the unit pad structure 130 perpendicular to the first direction (X direction) can have a quadrilateral shape, with two corners of the lower surface being rounded. As will be described later, after forming the first isolation pad pattern 132 without using a separate mask pattern and forming the unit pad structure 130 using the first isolation pad pattern 132 by using a first mask pattern Ox (refer to FIG. 6A) for forming the word line WL, the aforementioned cross-sectional shape of the unit pad structure 130 can be obtained. Since a separate mask pattern is not used to form the first pad isolation pattern 132, the manufacturing process of the semiconductor device 100 can be simplified compared to the case of using two mask patterns to form the pad isolation pattern in the prior art. Therefore, the cost of the manufacturing process of the semiconductor device 100 can be reduced.

[0026] In some exemplary embodiments, as shown in FIGS. 3A and 3B, the upper surface of the unit pad structure 130 can be disposed at a higher vertical level than the upper surface of the second active region ACT2, and the lower surface of the unit pad structure 130 can be disposed at a lower vertical level than the upper surface of the second active region ACT2. For example, the upper surface of the unit pad structure 130 can be disposed at a first vertical level X1, the upper surface of the second active region ACT2 can be disposed at a second vertical level X2 lower than the first vertical level X1, and the lower surface of the unit pad structure 130 can be disposed at a third vertical level X3 lower than the second vertical level X2. As shown in FIGS. 3A and 3B, the unit pad structure 130 is disposed on the first active region ACT1. Therefore, the lower surface of the unit pad structure 130 and the upper surface of the first active region ACT1 can be disposed at the same vertical level. Since the lower surface of the unit pad structure 130 is located at a lower vertical level than the upper surface of the second active region ACT2, the upper surface of the first active region ACT1 can also be located at a lower vertical level than the lower surface of the second active region ACT2. As will be described later with reference to FIGS. 6C and 6D, this is because a process of recessing the upper surface of the first active region ACT1 of the substrate 110 is performed in the manufacturing process of the semiconductor device 100. When such a recessing process is performed, even if the unit pad structure 130 is disposed on the upper surface of the first active region ACT1, the step difference between the unit array region MCA and the peripheral circuit region PCA due to the length of the unit pad structure 130 in the third direction (Z direction) can be minimized. In addition, compared to the case where the recessing process is not performed, the desired length of the first mask pattern Ox for forming the first pad isolation pattern 132 in the third direction (Z direction) can be reduced, thereby reducing the difficulty of the manufacturing process of the semiconductor device 100.

[0027] In some exemplary embodiments, the lower surface of the plurality of unit pad structures 130 may be disposed at a lower vertical level than the lower surface of the first pad isolation pattern 132, and the upper surface of the plurality of unit pad structures 130 may be disposed at the same vertical level as the upper surface of the first pad isolation pattern 132.

[0028] In some exemplary embodiments, the lower surface of the plurality of unit pad structures 130 may be disposed at a higher vertical level than the lower surface of the second pad isolation pattern 134, and the upper surface of the plurality of unit pad structures 130 may be disposed at the same vertical level as the upper surface of the second pad isolation pattern 134.

[0029] In some exemplary embodiments, the plurality of unit pad structures 130 may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0030] The plurality of second pad isolation patterns 134 may be disposed between two adjacent first pad isolation patterns 132. The plurality of second pad isolation patterns 134 may be disposed adjacent to the unit pad structures 130. The plurality of second pad isolation patterns 134 may extend in a second direction. The plurality of second pad isolation patterns 134 may have an island pattern shape in a plan view. The second pad isolation pattern 134 may include, for example, silicon nitride.

[0031] The first insulating layer 151 and the second insulating layer 153 may be sequentially disposed on the unit pad structures 130, the first pad isolation pattern 132, and the second pad isolation pattern 134. In some exemplary embodiments, the first insulating layer 151 and the second insulating layer 153 extend parallel to each other from the unit array region MCA to the boundary region BA on the substrate 110 in a first direction (X direction) and a second direction (Y direction) and may be flat. The first insulating layer 151 may be, for example, silicon oxide, and the second insulating layer 153 may be, for example, silicon nitride.

[0032] The plurality of buried contacts 160 may be disposed on the plurality of unit pad structures 130. The plurality of buried contacts 160 may penetrate through the first insulating layer 151 and the second insulating layer 153. The plurality of buried contacts 160 may be respectively disposed to overlap corresponding portions of the plurality of unit pad structures 130 in a third direction (Z direction). The plurality of unit pad structures 130 and the plurality of buried contacts 160 may connect a capacitor structure (not shown) formed on the plurality of bit lines BL to the first active region ACT1.

[0033] A plurality of buried contacts 160 may be electrically insulated from each other by a second insulating pattern 173 surrounding the plurality of buried contacts 160. The second insulating pattern 173 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0034] A capacitor structure (not shown) may be disposed on the plurality of buried contacts 160.

[0035] A plurality of direct contacts DC may be formed in a plurality of direct contact holes DCH on the substrate 110. The plurality of direct contacts DC may pass through the first insulating layer 151 and the second insulating layer 153. The plurality of direct contacts DC may be connected to the plurality of first active regions ACT1. The plurality of direct contacts DC may include TiN, TiSiN, W, tungsten silicide, doped polysilicon, or a combination thereof.

[0036] Direct contact spacers 171A may be disposed on two sidewalls of the plurality of direct contacts DC. The direct contact spacers 171A may cover the two sidewalls of the direct contacts DC.

[0037] The first insulating pattern 155 is formed on the inner wall of the direct contact hole DCH and may fill the direct contact hole DCH. The upper surface of the first insulating pattern 155 may be disposed at the same vertical level as the upper surface of the direct contacts DC.

[0038] A plurality of bit lines BL may extend in the second horizontal direction Y on the substrate 110 and the plurality of direct contacts DC. Each of the plurality of bit lines BL may be connected to the first active region ACT1 via the direct contact DC. The plurality of bit lines BL may include ruthenium (Ru), tungsten (W), cobalt (Co), titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0039] The plurality of bit lines BL may be respectively covered by a plurality of insulating capping structures 140. The plurality of insulating capping structures 140 may extend in the second horizontal direction Y on the plurality of bit lines BL.

[0040] The bit line spacer 171B can be disposed on two sidewalls of each of the plurality of bit lines BL. The bit line spacer 171B can extend in a second direction (Y direction) on two sidewalls of the plurality of bit lines BL. The bit line spacer 171B can extend in a third direction (Z direction) on two sidewalls of the plurality of bit lines BL to cover two sidewalls of the insulating capping structure 140. Although the bit line spacer 171B is illustrated as a single material layer in FIG. 3B, in some example embodiments, the bit line spacer 171B can be formed as a stacked structure of a plurality of spacer layers (not illustrated), and at least one of the plurality of spacer layers can be an air spacer.

[0041] FIG. 4A is a cross-sectional view taken along line A-A′ of FIG. 2 of the semiconductor device 100a according to another example embodiment of the inventive concept. FIG. 4B is a cross-sectional view taken along line B-B′ of FIG. 2 of the semiconductor device 100a according to another example embodiment of the inventive concept. Since the configurations of the semiconductor device 100a illustrated in FIGS. 4A and 4B are similar to the corresponding configurations of the semiconductor device 100 illustrated in FIGS. 1 to 3B, the differences therebetween will be mainly described hereinafter.

[0042] Referring to FIGS. 4A and 4B, as illustrated by line Y1 shown, the upper surface of the unit pad structure 130a is disposed at the same or substantially similar vertical level as the upper surface of the second active region ACT2, or as illustrated by line Y2 shown, the lower surface of the unit pad structure 130a is disposed at the same or substantially similar vertical level as the lower surface of the second active region ACT2. This can be accomplished by performing a process of recessing the upper surface of the first active region ACT1 of the substrate 110 as described later with reference to FIGS. 6C and 6D. Compared with the manufacturing process of the semiconductor device 100 described with reference to FIGS. 1 to 3B, in the manufacturing process of the semiconductor device 100a shown in FIGS. 4A and 4B, the recessing process described later with reference to FIG. 6D can be performed until the height of the first active region ACT1 is lower than the previous height.

[0043] In some example embodiments, the lower surfaces of the plurality of unit pad structures 130a can be disposed at a lower vertical level than the lower surface of the first pad isolation pattern 132, and the upper surfaces of the plurality of unit pad structures 130a can be disposed at the same vertical level as the upper surface of the first pad isolation pattern 132.

[0044] In some example embodiments, the lower surface of the plurality of unit pad structures 130a may be disposed at a higher vertical level than the lower surface of the second pad isolation pattern 134, and the upper surface of the plurality of unit pad structures 130a may be disposed at the same vertical level as the upper surface of the second pad isolation pattern 134.

[0045] FIG. 5A is an enlarged cross-sectional view of a portion PX2 of FIG. 3B. FIG. 5B is an enlarged cross-sectional view of a portion corresponding to portion PX2 of FIG. 3B of semiconductor device 100b according to another example embodiment of the inventive concept.

[0046] Referring to FIG. 5A, in semiconductor device 100 illustrated in FIGS. 1 to 3B, with respect to a cross-section of unit pad structure 130 perpendicular to the second direction (Y direction), of the two corners of the lower surface of the cross-section, corner 130S1 adjacent to second pad isolation pattern 134 may be circular, and the remaining corner 130S2 of the two corners of the lower surface of the cross-section may be angled. Accordingly, the cross-section of unit pad structure 130 may have a quadrilateral shape including a circular corner. This shape is because after first performing a first patterning process of forming second pad isolation pattern 134, which will be described with reference to FIG. 6B later, a deposition process of forming unit pad structure 130, which will be described with reference to FIG. 6E later, is performed.

[0047] On the other hand, referring to FIG. 5B, in semiconductor device 100b, a cross-section of unit pad structure 130b perpendicular to the second direction (Y direction) may have a quadrilateral shape, where the two corners 130bS1 and 130bS2 of the lower surface of the cross-section are angled. Accordingly, the cross-section of unit pad structure 130 may have a quadrilateral shape having angled corners. This shape is because after first performing a deposition process of forming unit pad structure 130, which will be described with reference to FIG. 6E later, a first patterning process of forming second pad isolation pattern 134, which will be described with reference to FIG. 6B later, is performed.

[0048] FIGS. 6A to 6H are cross-sectional views illustrating a method of manufacturing semiconductor device 100 according to example embodiments of the inventive concept. For example, FIGS. 6A to 6H are enlarged cross-sectional views illustrating portions CX1 and CX2 of FIGS. 3A and 3B.

[0049] Referring to FIG. 6A, a plurality of character line trenches 120T may be formed in the substrate 110, and a gate dielectric film 121, a gate electrode 123, and a capping insulating film 125P may be sequentially formed in the plurality of character line trenches 120T. Thereafter, the first mask pattern Ox for forming the gate dielectric film 121, the gate electrode 123, and the capping insulating film 125P is retained, and a planarization process may be performed such that the upper surface of the capping insulating film 125P is disposed at the same vertical level as the upper surface of the first mask pattern Ox. At this time, through a process to be described later with reference to FIGS. 6B to 6D, the upper portion of the capping insulating film 125P may be the first pad isolation pattern 132 (see FIG. 6D), and the lower portion of the capping insulating film 125P may be the capping insulating film 125 included in the buried gate structure 120 (refer to FIG. 6D). The planarization process may be, for example, a chemical mechanical polishing (CMP) process, but is not limited thereto. Since the retained first mask pattern Ox is used instead of using a separate mask pattern, the semiconductor device manufacturing process can be simplified and the manufacturing process cost can be reduced. In addition, since the first pad isolation pattern 132 (refer to FIG. 6D) can be formed in a self-aligned manner, misalignment of the unit pad structure 130 (refer to FIG. 6F) can be alleviated or avoided, and the reliability of the semiconductor device can be improved.

[0050] Referring to FIG. 6B, a first patterning process for forming the second pad isolation pattern 134 may be performed. For example, a second mask pattern (not shown) having an opening (not shown) is formed on the first mask pattern Ox, and a first patterning process of etching the first mask pattern Ox, the substrate 110, and the element isolation film 112 may be performed using the second mask pattern (not shown) as an etching mask. Thereafter, the second pad isolation pattern 134P may be formed by depositing silicon nitride and performing a planarization process. The planarization process may be, for example, a CMP process.

[0051] Referring to FIG. 6C, the first mask pattern Ox may be recessed. The first mask pattern Ox may be recessed to expose the first active region ACT1 of the substrate 110 and the element isolation film 112.

[0052] Referring to FIG. 6D, the upper surfaces of the base 110 and the device isolation film 112 can be recessed. Accordingly, the upper portion of the second pad isolation pattern 134P (refer to FIG. 6C) can also be partially recessed, thereby forming the second pad isolation pattern 134. At this time, the regions where the base 110, the device isolation film 112, and the first pad isolation pattern 132 intersect can be recessed into a circular shape, and the regions where the base 110, the device isolation film 112, and the second pad isolation pattern 134 intersect can also be recessed into a circular shape. Through the recessing process, the upper surface of the first active region ACT1 is located at a lower vertical level than the upper surface of the second active region ACT2, such that even when the unit pad structure 130 (refer to FIG. 6F) is disposed on the upper surface of the first active region ACT1, the step difference between the unit array region MCA and the peripheral circuit region PCA due to the length of the unit pad structure 130 (refer to FIG. 6F) in the third direction (Z direction) can be reduced or minimized. Additionally, compared with the case where the recessing process is not performed, the desired length of the first mask pattern Ox for forming the first pad isolation pattern 132 in the third direction (Z direction) can be reduced, thereby reducing the difficulty of the manufacturing process of the semiconductor device 100.

[0053] Referring to FIG. 6E, a unit pad structure pattern 130P can be formed. In some exemplary embodiments, the unit pad structure pattern 130P can include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. For example, the unit pad structure pattern 130P can include polysilicon.

[0054] Referring to FIG. 6F, a planarization process can be performed to form the unit pad structure 130. The planarization process can be, for example, a CMP process.

[0055] Referring to FIG. 6G, the first insulating layer 151 and the second insulating layer 153 can be sequentially formed on the unit pad structure 130, the first pad isolation pattern 132, and the second pad isolation pattern 134. The first insulating layer 151 and the second insulating layer 153 can be formed by, for example, a deposition process.

[0056] Referring to FIG. 6H, the direct contact member DC, the bit line BL, and the insulating capping structure 140 may be sequentially formed on the substrate 110. First, a direct contact hole DCH may be formed through a portion of the substrate 110, a portion of the element isolation film 112, the unit pad structure 130, the first insulating layer 151, and the second insulating layer 153, and the direct contact member DC, the bit line BL, and the insulating capping structure 140 may be sequentially formed on the direct contact hole DCH. Thereafter, a mask pattern (not shown) may be formed on the insulating capping structure 140, and the mask pattern may be used to pattern the direct contact member DC, the bit line BL, and the insulating capping structure 140. Thereafter, the direct contact spacer 171A and the bit line spacer 171B may be formed, and the first insulating pattern 155 filling the direct contact hole DCH may be formed. In this case, the first insulating pattern 155 may be formed to have the same height as the upper surface of the second insulating layer 153. After performing the process described with reference to FIG. 6G, the cross-section of the unit pad structure 130 perpendicular to the second direction (Y direction) may have the shape of the cross-section described with reference to FIG. 5A.

[0057] In another exemplary embodiment of the inventive concept, the first patterning process described with reference to FIG. 6B may be performed after the planarization process described with reference to FIG. 6F. For example, after performing the process of forming the buried gate structure 120 and the planarization process described with reference to FIG. 6A, the recess process described with reference to FIGS. 6C and 6D may be performed, and thereafter, the process of forming the unit pad structure 130 described with reference to FIGS. 6E and 6F may be performed, and then the first patterning process described with reference to FIG. 6B may be performed. In this case, in the recess process described with reference to FIGS. 6C and 6D, the region where the substrate 110, the element isolation film 112, and the first pad isolation pattern 132 intersect may be recessed into a circular shape, and the region where the substrate 110, the element isolation film 112, and the second pad isolation pattern 134 intersect may be recessed into an angled shape. Therefore, after the process of forming the direct contact member DC, the bit line BL, and the insulating capping structure 140 described with reference to FIG. 6H, the cross-section of the unit pad structure 130 perpendicular to the second direction (Y direction) may have the shape of the cross-section described with reference to FIG. 5B.

[0058] Although the inventive concept has been specifically illustrated and described with reference to some exemplary embodiments, it should be understood that various changes may be made in form and detail without departing from the spirit and scope of the following claims.

[0059] 100, 100a, 100b: semiconductor device 110: substrate 112: element isolation film 112T: Element isolation trench 114: Boundary structure 114A: Buried insulating layer 114B: Insulating liner 114C: Gap-fill insulating layer 114T: Boundary trench 120: Buried gate structure 120T: Character line trench 121: Gate dielectric film 123: Gate electrode 125, 125P: Capping insulating film 130, 130a, 130b: Unit pad structure 130bS1, 130bS2, 130S1, 130S2: Corners 130P: Unit pad structure pattern 132: First pad isolation pattern 134, 134P: Second pad isolation pattern 140: Insulating capping structure 151: First insulating layer 153: Second insulating layer 155: First insulating pattern 160: Buried contact 171A: Direct contact spacer 171B: Bit line spacer 173: Second insulating pattern A - A', B - B', Y1, Y2: Lines ACT1: First active region ACT2: Second active region BA: Boundary region BL: Bit line CX1, CX2, EX, PX2: Portions DC: Direct contact DCH: Direct contact hole MCA: Memory cell array region Ox: First mask pattern PCA: Peripheral circuit region WL: Word line X: First horizontal direction X1: First vertical - horizontal X2: Second vertical - horizontal X3: Third vertical - horizontal Y: Second horizontal direction Z: Third direction

Claims

1. A semiconductor device, comprising: A substrate comprising a cell array region and a peripheral circuit region, the substrate comprising a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region; Multiple character lines extend in the substrate and in a first direction; Multiple bit lines extend in the cell array region of the substrate and in a second direction perpendicular to the first direction; multiple first pad separation patterns extend in the first direction, respectively on the counterparts of the bit lines. A unit pad structure is located on the substrate and between two adjacent elements of the first pad separation pattern; and a second pad separation pattern is located between two adjacent elements of the first pad separation pattern and adjacent to the unit pad structure, wherein the cross-section of the unit pad structure perpendicular to the first direction has a quadrilateral shape, wherein the two corners of the lower surface of the cross-section are rounded, and the upper surface of the first pad separation pattern, the upper surface of the unit pad structure, and the upper surface of the second pad separation pattern are on the same plane.

2. The semiconductor device of claim 1, wherein the cross-section of the unit pad structure perpendicular to the second direction includes a first corner and a second corner at its lower surface, the first corner being adjacent to the second pad separation pattern and having a circular shape, and the second corner having a square shape.

3. The semiconductor device of claim 1, wherein the cross-section of the unit pad structure perpendicular to the second direction has a quadrilateral shape, wherein two opposite corners of the lower surface of the cross-section are angled.

4. The semiconductor device of claim 1, wherein the upper surface of each of the first active regions is at a lower vertical level than the upper surface of the second active region.

5. The semiconductor device of claim 1, wherein the upper surface of the cell pad structure is at a higher vertical level than the upper surface of the second active region, and the lower surface of the cell pad structure is at a lower vertical level than the upper surface of the second active region.

6. The semiconductor device of claim 1, wherein the upper surface of the cell pad structure is at the same vertical level as the upper surface of the second active region, and the lower surface of the cell pad structure is at a lower vertical level than the upper surface of the second active region.

7. The semiconductor device as claimed in claim 1, further comprising: An insulating film is placed between a corresponding element line and a corresponding element in the first pad separation pattern, wherein the length of the corresponding element in the first pad separation pattern in the second direction is the same as the length of the insulating film in the second direction.

8. The semiconductor device of claim 7, wherein the corresponding one in the first pad separation pattern and the capping insulating film are each part of a single integral structure.

9. The semiconductor device of claim 1, wherein the upper surface of the unit pad structure is at the same vertical level as the upper surface of the second pad separation pattern, and the lower surface of the unit pad structure is at a higher vertical level than the lower surface of the second pad separation pattern.

10. A semiconductor device, comprising: A substrate comprising a cell array region, a boundary region, and a peripheral circuit region, the substrate comprising a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region; a character line extending in the substrate in a first direction; a bit line extending in the cell array region of the substrate in a second direction perpendicular to the first direction; and a plurality of first pad separation patterns extending in the first direction on the character line. A unit pad structure is located on the substrate and between two adjacent elements of the first pad separation pattern; a second pad separation pattern is located between two adjacent elements of the first pad separation pattern and is adjacent to the unit pad structure; a first insulating layer is located on the unit pad structure and extends to the boundary region. And a second insulating layer, on the first insulating layer and extending to the boundary region, wherein the first cross-section of the unit pad structure perpendicular to the first direction has a quadrilateral shape, wherein the two corners of the lower surface are rounded, and wherein the upper surface of the first insulating layer and the upper surface of the second insulating layer are flat, and the upper surface of the first pad separation pattern, the upper surface of the unit pad structure and the upper surface of the second pad separation pattern are on the same plane.

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