Semiconductor device

Abstract

The present invention provides a semiconductor device comprising: a substrate including a first region and a second region planarly surrounding the first region; a lower electrode disposed on the first region of the substrate and extending in a vertical direction; a support member surrounding a sidewall of the lower electrode and supporting the lower electrode; a first upper electrode covering the lower electrode and located on the lower electrode, the first upper electrode including a first portion disposed in the first region and a second portion disposed in the second region; a dielectric layer disposed between the lower electrode and the first upper electrode; and a second upper electrode disposed on the first portion of the first upper electrode, wherein the second upper electrode is not disposed on the second portion of the first upper electrode.

Description

Semiconductor device [Cross-reference to related applications] This application is based on and claims the priority of Korean Patent Application No. 10-2022-0147381, filed on November 7, 2022, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. The present inventive concept relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device including a capacitor and a method of manufacturing a semiconductor device. As semiconductor devices are scaled down, the size of individual fine circuit patterns for implementing semiconductor devices has been further reduced. As the size of individual fine circuit patterns increases, the height of cell capacitors and peripheral circuit contacts increases. Accordingly, misalignment defects may occur in the process of forming peripheral circuit contacts. The present inventive concept provides a semiconductor device having improved reliability. The objectives to be solved by the technical idea are not limited to the above objectives, and other objectives not mentioned can be clearly understood by those of ordinary skill in the art from the following description. According to an embodiment of the present inventive concept, a semiconductor device may be provided. The semiconductor device includes: a substrate including a first region and a second region planar-ly surrounding the first region; a lower electrode disposed on the first region of the substrate and extending in a vertical direction; a support surrounding a sidewall of the lower electrode and supporting the lower electrode; a first upper electrode covering and located on the lower electrode, the first upper electrode including a first portion disposed within the first region and a second portion disposed within the second region; a dielectric layer disposed between the lower electrode and the first upper electrode; and a second upper electrode disposed on the first portion of the first upper electrode, wherein the second upper electrode is not disposed on the second portion of the first upper electrode. According to an embodiment of the present inventive concept, a semiconductor device may be provided. The semiconductor device includes: a substrate including a cell region and a connection region, the cell region including a first region and a second region, the second region being disposed between the first region and the connection region; a plurality of conductive patterns disposed on the cell region of the substrate; a plurality of lower electrodes respectively connected to the plurality of conductive patterns and each extending in a vertical direction; a plurality of supports surrounding respective ones of the plurality of sidewalls of the plurality of lower electrodes and supporting the plurality of lower electrodes; a dielectric layer disposed on the plurality of lower electrodes and the plurality of supports and not disposed within the connection region; a first upper electrode disposed on the dielectric layer; the first upper electrode including a first portion disposed within the first region and a second portion disposed within the second region, and a second upper electrode disposed within the first region and not disposed within the second region and the connection region. According to an embodiment of the inventive concept, a semiconductor device may be provided. The semiconductor device includes: a substrate including a cell region, a connection region, and a peripheral circuit region, the cell region including a first region and a second region, the second region being disposed between the first region and the connection region; cell transistors disposed within the cell region of the substrate; a peripheral circuit disposed within the peripheral circuit region of the substrate; a capacitor disposed within the cell region of the substrate and electrically connected to the cell transistors; and a peripheral circuit contact disposed within the peripheral circuit region of the substrate and electrically connected to the peripheral circuit, wherein the capacitor includes a lower electrode disposed on the first region of the substrate and extending in a vertical direction; a plurality of supports surrounding a sidewall of the lower electrode and supporting the lower electrode; a first upper electrode covering the lower electrode and located on the lower electrode, the first upper electrode including a first portion disposed within the first region and a second portion disposed within the second region; a dielectric layer disposed between the lower electrode and the first upper electrode; and a second upper electrode disposed on the first portion of the first upper electrode, wherein the second upper electrode is not disposed on the second portion of the first upper electrode. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, this element may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present. Other words used to describe the relationship between elements or layers (e.g., "between" and "directly between," "adjacent" and "directly adjacent," "on" and "directly on") should be interpreted in a similar manner. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, the first element, first component, first region, first layer, or first section discussed below may be referred to as a second element, second component, second region, second layer, or second section without departing from the teachings of the example embodiments. For ease of description, spatial relative terms, such as "under", "below", "lower", "above", "upper", and the like, may be used herein to describe the relationship of one element or feature to another (some) element or feature as illustrated in the figures. It should be understood that spatial relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "under" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary term "under" can encompass both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the example embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" are also intended to include the plural forms. It should be further understood that if used herein, the terms "comprises / comprising" and / or "includes / including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Example embodiments of the inventive concept are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the example embodiments. Accordingly, it is expected that the shapes of the illustrations will vary due to, for example, manufacturing techniques and / or tolerances. Thus, example embodiments of the inventive concept should not be construed as limited to the particular shapes of regions illustrated herein, but should include, for example, shape deviations resulting from manufacturing. For example, an implantation region shown as rectangular may have rounded or curved features at its edges and / or an implant concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may create some implantation in the region between the buried region and the surface where the implantation is performed. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the example embodiments. Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. FIG. 1 is a layout diagram of a semiconductor device 100 according to an embodiment of the inventive concept. Referring to FIG. 1, the semiconductor device 100 may include a substrate 110, which includes a cell array region MCA and a peripheral circuit region PCA. For example, the cell array region MCA may be a memory cell region of a dynamic random-access memory (DRAM) device, and the peripheral circuit region PCA may be a core region or a peripheral circuit region of the DRAM device. For example, the cell array region MCA may include cell transistors CTR and capacitors connected to the cell transistors CTR, and the peripheral circuit region PCA may include peripheral circuit transistors PTR for transmitting signals and / or power to the cell transistors CTR included in the cell array region MCA. In an embodiment, the peripheral circuit transistors PTR may configure various circuits, such as a command decoder, control logic, an address buffer, a column decoder, a row decoder, a sense amplifier, data, or input / output circuits. FIG. 2 is a schematic layout diagram of the semiconductor device 100 according to an embodiment of the inventive concept. Specifically, FIG. 2 is a schematic layout diagram of the cell array region MCA of the semiconductor device 100 illustrated in FIG. 1. FIG. 3 is a plan view schematically showing a partial configuration of the semiconductor device 100 according to an embodiment of the inventive concept. Specifically, FIG. 3 is a plan view schematically showing a partial configuration disposed in the first region CR1 of the semiconductor device 100 illustrated in FIG. 2. FIGS. 4 to 8 are cross-sectional views schematically showing partial configurations of semiconductor devices 100A, 100B, 100C, 100D, and 100E according to embodiments of the inventive concept, respectively. Specifically, FIGS. 4 to 8 are cross-sectional views of the semiconductor devices 100A, 100B, 100C, 100D, and 100E corresponding to cross-sections taken along lines I-I' and II-II' in FIG. 2. Referring to FIG. 2, a substrate 110 including a cell region CR and a connection region BR may be provided. Specifically, the cell array region MCA of the semiconductor device 100 may include the cell region CR and the connection region BR, and the cell region CR may include a first region CR1 and a second region CR2. The first region CR1 may be defined by the second region CR2. Specifically, the first region CR1 may be surrounded by the second region CR2. The cell region CR may be surrounded by the connection region BR. The second region CR2 may be disposed between the first region CR1 and the connection region BR. The connection region BR may be a region for connecting structures disposed in the cell region CR to structures of the peripheral circuit region PCA. The first region CR1 may be spaced apart from the connection region BR by the second region CR2 between the first region and the connection region. The second region CR2 may be surrounded by the connection region BR. As shown in FIG. 2, a plurality of lower electrodes LE may be disposed in a first region CR1 of the substrate 110. Specifically, FIG. 2 illustrates an example of a configuration having a substantially rhombic planar shape with vertices respectively formed at four adjacent lower electrodes LE. However, the planar configuration of the plurality of lower electrodes LE is not limited to the example shown in FIG. 2, and various deformations and modifications can be made within the scope of the inventive concept. Referring to FIG. 3, the semiconductor device 100 may include a plurality of cell transistors CTR in a first region CR1 of the substrate 110. Specifically, the semiconductor device 100 may include a plurality of first active regions AC1 configured to horizontally extend in an inclined direction with respect to a first horizontal direction (X direction) and a second horizontal direction (Y direction) in a plan view. A plurality of word lines WL may extend parallel to each other in the first horizontal direction (X direction) across the plurality of first active regions AC1. Above the plurality of word lines WL, a plurality of bit lines BL may each extend parallel to each other in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). The plurality of bit lines BL may be connected to the first active regions AC1 via corresponding direct contacts DC. A plurality of buried contacts BC may be disposed between two adjacent bit lines BL among the plurality of bit lines BL. A plurality of conductive landing pads LP may be disposed on the plurality of buried contacts BC. The plurality of conductive landing pads LP may be configured to at least partially overlap the plurality of buried contacts BC respectively. The plurality of lower electrodes LE may be configured to be spaced apart from each other above the plurality of conductive landing pads LP. The plurality of lower electrodes LE may be connected to the plurality of first active regions AC1 via the plurality of buried contacts BC and the plurality of conductive landing pads LP. Referring to FIG. 4, the semiconductor device 100A may include a substrate 110 including a cell region CR and a connection region BR. Specifically, the semiconductor device 100A may include a substrate 110 including a first region CR1, a second region CR2, and a connection region BR. The substrate 110 may include silicon, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate 110 may include at least one selected from germanium (GE), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate 110 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities. In some embodiments, the device isolation layer 112 that defines multiple active regions may be disposed in the substrate 110. The device isolation layer 112 may include an oxide layer, a nitride layer, or a combination thereof. In some embodiments, the device isolation layer 112 may have various structures, such as a shallow trench isolation (STI) structure. Specifically, within the substrate 110, a first active region AC1 may be formed in a first region CR1, and a second active region AC2 may be formed in a second region CR2. The first active region AC1 may be defined by the device isolation layer 112. The second active region AC2 may be defined by the device isolation layer 112 and a connection isolation layer 113. In some embodiments, the connection isolation layer 113 may be disposed in the substrate 110 of the connection region BR. The connection isolation layer 113 may include an oxide layer, a nitride layer, or a combination thereof. The connection isolation layer 113 may have various structures, such as an STI structure. Although not shown, the connection isolation layer 113 may include multiple layers. For example, the connection isolation layer 113 may include a first connection pad (not shown), a second connection pad (not shown), and a connection buried insulating layer (not shown). In some embodiments, the semiconductor device 100A may include a lower structure 120 and multiple conductive patterns 124 on the substrate 110 of the cell region CR. Specifically, the semiconductor device 100A may include a lower structure 120 and multiple conductive patterns 124 on the substrate 110 of the first region CR1. In the first region CR1, the multiple conductive patterns 124 may be connected to the multiple active regions AC1 by passing through the lower structure 120. In some embodiments, the multiple conductive patterns 124 may not be disposed in the second region CR2 and / or the connection region BR. In some embodiments, the lower structure 120 may include an insulating layer that includes a silicon oxide layer, a silicon nitride layer, or a combination thereof. In some other embodiments, the lower structure 120 may include various conductive regions, such as wiring layers, contact plugs, transistors, etc., and an insulating layer for insulating the conductive regions from each other. The lower structure 120 may include multiple bit lines BL described with reference to FIG. 3. In some embodiments, the multiple conductive patterns 124 may include polysilicon, metal, conductive metal nitride, metal silicide, or a combination thereof. Each of the multiple conductive patterns 124 may include a buried contact BC and a conductive landing pad LP described with reference to FIG. 3. In some embodiments, a first insulating pattern 126P having a plurality of openings 126H overlapping with a plurality of conductive patterns 124 in a horizontal direction (Z direction) may be disposed on a lower structure 120 and the plurality of conductive patterns 124 in a cell region CR. Specifically, the first insulating pattern 126P may include a silicon compound layer, such as a silicon nitride (SiN) layer, a silicon carbonitride (SiCN) layer, a silicon boron nitride (SiBN) layer, or a combination thereof. As used herein, the terms "SiN", "SiCN", and "SiBN" indicate materials containing the elements included in each of the terms and are not chemical formulas representing stoichiometric relationships. In some embodiments, the first insulating pattern 126P may extend to a connection region BR and be disposed on a substrate 110. In some embodiments, a plurality of capacitors CP may be disposed on the plurality of conductive patterns 124 in the cell region CR. Each of the plurality of capacitors CP may include: a lower electrode LE extending in a vertical direction (Z direction) with respect to an upper surface of the substrate 110, supports 142P and 144P surrounding sidewalls of the lower electrode LE and supporting the lower electrode LE, a dielectric layer 160 disposed on the lower electrode LE, the supports 142P, and the supports 144P, a first upper electrode UE1A disposed on the dielectric layer 160 and the lower electrode LE, and a second upper electrode UE2 disposed on the first upper electrode UE1A. The first insulating pattern 126P may be configured to be adjacent to a lower end of each of the plurality of lower electrodes LE. Each of the plurality of lower electrodes LE may have a columnar shape extending through an opening 126H of the first insulating pattern 126P from an upper surface of the conductive pattern 124 in a direction away from the substrate 110 in a vertical direction (Z direction). As described above, the lower electrode LE may be disposed in the first region CR1 and may not be disposed in the second region CR2. Although the case where each of the plurality of lower electrodes LE has a columnar shape is described as an example, the inventive concept is not limited thereto. For example, each of the plurality of lower electrodes LE may have a cup shape with a closed bottom or a cross-sectional structure of a cylindrical shape. In the cell region CR, the plurality of lower electrodes LE may be supported by a lower support 142P and an upper support 144P. The plurality of lower electrodes LE and the first upper electrode UE1A may face each other, with the dielectric layer 160 located between the lower electrode and the first upper electrode. In the cell region CR, the upper support member 144P can extend parallel to the substrate 110 while surrounding the upper ends of each of the plurality of lower electrodes LE. The upper support member 144P can be disposed above the substrate 110 within the first region CR1 and not disposed above the substrate 110 within the second region CR2. A plurality of holes 144H through which the plurality of lower electrodes LE pass can be defined in the upper support member 144P. The inner sidewall of each of the plurality of holes 144H defined in the upper support member 144P can contact the outer sidewall of the lower electrode LE. The upper surface of each of the plurality of lower electrodes LE can be in the same plane as the upper surface of the disposed upper support member 144P. In the cell region CR, the lower support member 142P can extend parallel to the substrate 110 between the substrate 110 and the upper support member 144P and contact the outer sidewalls of the plurality of lower electrodes LE. The lower support member 142P can be disposed above the substrate 110 within the first region CR1 and not disposed above the substrate 110 within the second region CR2. A plurality of holes 142H through which the plurality of lower electrodes LE pass can be defined in the lower support member 142P. Each of the plurality of lower electrodes LE can extend in the horizontal direction (Z direction) through the plurality of holes 144H defined in the upper support member 144P and the plurality of holes 142H defined in the lower support member 142P. Each of the lower support member 142P and the upper support member 144P can include a compound of a metalloid and at least one reactive non-metal, such as a compound including silicon and nitrogen, such as a SiN layer, a SiCN layer, a SiBN layer, or a combination thereof. In an embodiment, the lower support member 142P and the upper support member 144P can include the same material as each other. In other embodiments, the lower support member 142P and the upper support member 144P can include different materials from each other. For example, each of the lower support member 142P and the upper support member 144P can include SiCN. In another example, the lower support member 142P can include SiCN, and the upper support member 144P can include SiBN. However, the inventive concept is not limited to the materials described above. The lower electrode LE may include a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, a conductive metal oxynitride, or a combination thereof, such as where the metal is a pre-transition metal, a late transition metal / post transition metal, or a combination thereof. Also covered are conductive oxide, nitride, or oxynitride compounds where a transition metal and a late transition metal are present or where a transition metal and an alkaline earth metal are present. In an embodiment, the lower electrode LE may include titanium (Ti), Ti oxide, Ti nitride, Ti oxynitride, niobium (Nb), Nb oxide, Nb nitride, Nb oxynitride, cobalt (Co), Co oxide, Co nitride, Co oxynitride, tin (Sn), Sn oxide, Sn nitride, Sn oxynitride, or a combination thereof. For example, the lower electrode LE may include niobium nitride (NbN), titanium nitride (TiN), cobalt nitride (CoN), tin oxide (SnO 2 ), or a combination thereof. In other embodiments, the lower electrode LE may include tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten (W), ruthenium (Ru), ruthenium oxide (RuO 2 ), strontium ruthenate (SrRuO 3 ), iridium (IR), iridium oxide (IrO 2 ), platinum (Pt), platinum oxide (PtO), SrRuO 3 (SRO), (Ba,Sr)RuO 3 (BSRO), CaRuO 3 (CRO), (La,Sr)CoO 3 (LSCO), or a combination thereof. However, the materials included in the lower electrode LE are not limited to those described above. In some embodiments, the dielectric layer 160 may be disposed on the lower electrode LE and the support. For example, a dielectric layer 160 may be provided that conformally covers the lower electrode LE, the lower support 142P, and the upper support 144P. The dielectric layer 160 may be disposed within the first region CR1 and the second region CR2 of the substrate 110. The dielectric layer 160 may include a high-k dielectric layer. As used herein, the term "high-k dielectric layer" refers to a dielectric layer having a dielectric constant higher than that of a silicon oxide layer. In an embodiment, the dielectric layer 160 may include a metal oxide, the metal oxide including at least one metal selected from hafnium (Hf), zirconium (Zr), aluminum (Al), Nb, cerium (Ce), lanthanum (La), tantalum (Ta), and Ti. In some embodiments, the dielectric layer 160 may have a single-layer structure including one high-k dielectric layer. In other embodiments, the dielectric layer 160 may have a multi-layer structure including multiple high-k dielectric layers. The high-k dielectric layer may include hafnium oxide (HfO 2 ), zirconium dioxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum pentoxide (Ta 2 O 3 ), niobium oxide (Nb 2 O 5 ), cerium oxide (CeO 2 ), titanium dioxide (TiO 2 ), germanium dioxide (GeO 2 ), or a combination thereof, but not limited thereto. In some embodiments, the dielectric layer 160 may include at least one of a ferroelectric material layer, an antiferroelectric material layer, and a paraelectric material layer. For example, the dielectric layer 160 may include hafnium zirconium oxide (HfZrO 2 ), ZrO 2 ), lead titanate (PbTiO 3 ), silver niobate (AgNbO 3 ), HfO 2 ), ZrO 2 ), TiO 2 ), Ta 2 O 3 , vanadium dioxide (VO 2 ), aluminate (AlO 2 ), silicon dioxide (SiO 2 ), strontium titanate (SrTiO 3 ), barium titanate (BaTiO 3 ), bismuth ferrite (BiFeO 3 ) or a combination thereof, but not limited thereto. In some embodiments, dielectric layer 160 may include a multilayer stack including a plurality of material layers of different materials from each other. For example, dielectric layer 160 may include a first dielectric layer (not shown) in contact with lower electrode LE and a second dielectric layer (not shown) located on the first dielectric layer. The first dielectric layer may include a ferroelectric material layer, an antiferroelectric material layer, or a combination thereof. In an embodiment, the first dielectric layer may include a single layer in which a ferroelectric material and an antiferroelectric material are unevenly mixed. In other embodiments, the first dielectric layer may include a single layer including a ferroelectric material. In other embodiments, the first dielectric layer may include a single layer including an antiferroelectric material. The second dielectric layer may include a paraelectric material layer. For example, the first dielectric layer may include HfZrO 2 , ZrO 2 , PbTiO 3 , AgNbO 3 or a combination thereof. The second dielectric layer may include HfO 2 , ZrO 2 , TiO 2 , Ta 2 O 3 , VO 2 , AlO 2 , SiO 2 , SrTiO 3 , BaTiO 3 , BiFeO 3 or a combination thereof. In some embodiments, the thickness of the dielectric layer 160 may be greater than about 0 nm and less than about 6 nm. In some embodiments, each of the thickness of the first dielectric layer and the thickness of the second dielectric layer may be greater than about 0 nm and less than about 3 nm. In other embodiments, each of the thickness of the first dielectric layer and the thickness of the second dielectric layer may be from about 3 nm to about 6 nm, but is not limited thereto. The first upper electrode UE1A may be disposed on the lower electrode LE and the dielectric layer 160. The lower electrode LE may be disposed within the first region CR1 of the substrate 110, while the first upper electrode UE1A may be disposed within the first region CR1 and the second region CR2 of the substrate 110. For example, the first upper electrode UE1A may be formed to cover the dielectric layer 160 of the first region CR1 and the second region CR2. The first upper electrode UE1A may include one or more materials selected from SiGe and silicon (Si). In some embodiments, the first upper electrode UE1A may include a first portion UE1_1 within the first region CR1 of the substrate 110 and a second portion UE1_2A within the second region CR2 of the substrate 110. For example, the first upper electrode UE1A may include the first portion UE1_1, which fills between the lower electrode LE within the first region CR1 of the substrate 110 and the supports 142P and 144P and is disposed on the dielectric layer 160. For example, the first upper electrode UE1A may include a second portion UE1_2A that extends in the horizontal direction (Z direction) within the second region CR2 of the substrate 110. In a plan view, the second portion UE1_2A of the first upper electrode UE1A may have a shape that horizontally surrounds the remaining portion of the capacitor CP. In other words, the second portion UE1_2A of the first upper electrode UE1A may horizontally surround the lower electrode LE, the upper support 144P, the lower support 142P, the first portion UE1_1 of the first upper electrode UE1A, and the dielectric layer 160 disposed between the lower electrode LE and the first portion UE1_1 of the first upper electrode UE1A, which are disposed within the first region CR1 of the substrate 110. In some embodiments, the second portion UE1_2A of the first upper electrode UE1A may include a portion of the first upper electrode UE1A adjacent to the connection region BR. In other words, the second portion UE1_2A of the first upper electrode UE1A may include a portion disposed at the boundary between the cell region CR and the connection region BR. The second portion UE1_2A of the first upper electrode UE1A may include a portion disposed between the lower electrode LE of the first region CR1 and the connection region BR. In some embodiments, a first portion UE1_1 of the first upper electrode UE1A may include a portion disposed between a plurality of lower electrodes LE. On the other hand, a second portion UE1_2A of the first upper electrode UE1A may include a portion disposed on a sidewall of the outermost lower electrode LE among the plurality of lower electrodes LE. In some embodiments, an upper surface UE1_1t of the first portion UE1_1 of the first upper electrode UE1A may be located at the same vertical level as an upper surface UE1_2At of the second portion UE1_2A of the first upper electrode UE1A. In other embodiments, different from that shown in FIG. 4, an upper surface UE1_1t of the first portion UE1_1 of the first upper electrode UE1A may be located at a vertical level different from the vertical level of an upper surface UE1_2At of the second portion UE1_2A of the first upper electrode UE1A. The second upper electrode UE2 may be disposed on the first upper electrode UE1A. For example, the second upper electrode UE2 may be disposed on the first portion UE1_1 of the first upper electrode UE1A. In other words, the second upper electrode UE2 may be disposed above the substrate 110 within the first region CR1. For example, the second upper electrode UE2 may not be disposed on the second portion UE1_2A of the first upper electrode UE1A. In other words, the second upper electrode UE2 may not be disposed above the substrate 110 within the second region CR2. In some embodiments, the second upper electrode UE2 may have a plate shape extending in a first horizontal direction (X direction) and a second horizontal direction (Y direction), but the shape of the second upper electrode UE2 is not limited thereto. The second upper electrode UE2 may include one or more materials selected from W, TiN, and combinations thereof. In some embodiments, as described above, the second upper electrode UE2 including one or more materials selected from W, TiN, and combinations thereof may not be disposed within the second region CR2 of the substrate 110. In other words, W, TiN, and combinations thereof may not be disposed within the second region CR2. In other words, the second portion UE1_2A of the first upper electrode UE1A disposed within the second region CR2 may not include W, TiN, and combinations thereof. A protective layer 170 including an insulating material may be disposed on the second upper electrode UE2. For example, the protective layer 170 may be disposed on the second upper electrode UE2 disposed within the first region CR1 of the substrate 110. The protective layer 170 may include one or more materials selected from silicon oxide, silicon nitride, and silicon oxynitride. The protective layer 170 may include multiple layers. Each of the multiple layers of the protective layer 170 may include one or more materials selected from silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, due to the capacitor CP disposed in the cell region CR of the semiconductor device 100A, a step may be formed between the cell region CR and the connection region BR. For example, due to the lower electrode LE disposed in the first region CR1 of the substrate 110, a step may be formed between the cell region CR and the connection region BR, and the first upper electrode UE1A filled between the lower electrodes LE and covering the lower electrodes LE may include a second portion UE1_2A extending in the vertical direction (Z direction) in the second region CR2 between the first region CR1 and the connection region BR. The insulating layer 180A, the first insulating pad 181, and the second insulating pad 182 may be disposed on the connection region BR of the substrate 110. Each of the insulating layer 180A, the first insulating pad 181, and the second insulating pad 182 may include one or more materials selected from silicon oxide, silicon nitride, and silicon oxynitride. For example, the insulating layer 180A that fills the step formed due to the capacitor CP disposed in the cell region CR may be formed. For example, the insulating layer 180A may be formed on the connection region BR by horizontally surrounding the capacitor CP. The insulating layer 180A may be formed to be in contact with the side surface of the second portion UE1_2A of the first upper electrode UE1A. The upper surface of the insulating layer 180A may be located at the same vertical level as the upper surface UE1_2At of the second portion UE1_2A of the first upper electrode UE1A. For example, the first insulating pad 181 surrounding the second upper electrode UE2 of the cell region CR may be formed. For example, the second upper electrode UE2 may be formed in the first region CR1 of the cell region CR, and the first insulating pad 181 surrounding the second upper electrode UE2 may be formed in the second region CR2 and the connection region BR. The upper surface of the first insulating pad 181 may be located at the same vertical level as the upper surface of the second upper electrode UE2. For example, a second insulating pad 182 that forms a protective layer 170 around the cell region CR can be formed. For example, the protective layer 170 can be formed in a first region CR1 of the cell region CR, and the second insulating pad 182 surrounding the protective layer 170 can be formed in a second region CR2 and a connection region BR. The upper surface of the second insulating pad 182 can be located at the same vertical level as the upper surface of the protective layer 170. In some embodiments, the protective layer 170 and the second insulating pad 182 surrounding the protective layer can all comprise insulating materials, but can comprise different materials from each other or can be separated from each other due to differences in the processing order. In some embodiments, the protective layer 170 and the second insulating pad 182 surrounding the protective layer can indicate an insulating layer covering the second upper electrode UE2 and a first insulating pad 181 surrounding the second upper electrode UE2, and the portion disposed within the first region CR1 can be referred to as the protective layer 170, and the portion disposed within the second region CR2 can be referred to as the second insulating pad 182. With the semiconductor device 100A according to an embodiment based on the inventive concept, a second upper electrode UE2 can be provided only on a first portion UE1_1 of a first upper electrode UE1 disposed only within a first region CR1. In the semiconductor device 100A, since the second upper electrode UE2 is disposed only on the first portion UE1_1 of the first region CR1 and not on a second portion UE1_2A of the second region CR2, the horizontal thickness of the capacitor CP portion disposed within the second region CR2 can be reduced. In other words, the size of the cell region CR of the semiconductor device 100A in the horizontal direction can be reduced, and thus the size of the semiconductor device 100A in the horizontal direction can be reduced. With the semiconductor device 100A according to an embodiment based on the inventive concept, the manufacturing difficulty can be reduced. For example, in the semiconductor device 100A, since the second upper electrode UE2 is disposed only within the first region CR1, the thickness of the capacitor CP portion disposed within the second region CR2 in the horizontal direction can be reduced, and thus the manufacturing defects resulting from the larger thickness can be improved. Therefore, a semiconductor device 100A with improved reliability can be provided. With the semiconductor device 100A according to an embodiment based on the inventive concept, a second upper electrode UE2 that is disposed only on a first portion UE1_1 of a first upper electrode UE1 disposed only within a first region CR1 and a protective layer 170 that is disposed only on the second upper electrode UE2 can be provided. In the semiconductor device 100A, since the protective layer 170 is disposed only within the first region CR1, the protective layer 170 can be formed without additionally increasing the size of the cell region CR of the semiconductor device 100A in the horizontal direction. Referring to FIG. 5, a semiconductor device 100B can be provided. The differences from the semiconductor device 100A described with reference to FIG. 4 will be mainly described below. The semiconductor device 100B may include a first upper electrode UE1B, and the first upper electrode includes a second portion UE1_2B. The second portion UE1_2B may include a curved side surface. For example, an upper surface UE1_2Bt of the second portion UE1_2B of the first upper electrode UE1B may include a portion at a vertical level different from that of the upper surface UE1_1t of the first portion UE1_1. In other words, the upper surface UE1_2Bt of the second portion UE1_2B of the first upper electrode UE1B may include a portion in the second region CR2 where the vertical level decreases as the distance from the connection region BR decreases. For example, the thickness of the second portion UE1_2B of the first upper electrode UE1B in the first horizontal direction (X direction) may not be constant in the vertical direction (Z direction). For example, the second portion UE1_2B of the first upper electrode UE1B may include a portion where the thickness in the first horizontal direction (X direction) decreases as the distance from the substrate 110 in the vertical direction (Z direction) increases. In some embodiments, an insulating layer 180B may be formed around the second portion UE1_2B of the first upper electrode UE1B in the connection region BR, and the unfilled portion in the second region CR2 may be filled with the second portion UE1_2B. In other words, the insulating layer 180B may include a portion disposed on the upper surface of the second portion UE1_2B. In other words, the insulating layer 180B may include a portion formed in the second region CR2. The insulating layer 180B may include a curved side surface along the side surface of the second portion UE1_2B. Referring to FIG. 6, a semiconductor device 100C may be provided. The differences from the semiconductor device 100A described with reference to FIG. 4 will be mainly described below. The semiconductor device 100C may include a first upper electrode UE1C, and the first upper electrode includes a second portion UE1_2C. The second portion UE1_2C may include a curved side surface. For example, an upper surface of the second portion UE1_2C of the first upper electrode UE1C may include a portion at a vertical level different from that of the upper surface of the first portion UE1_1. In other words, the upper surface of the second portion UE1_2C of the first upper electrode UE1C may include a portion in the second region CR2 where the vertical level decreases as the distance from the connection region BR decreases. The second part UE1_2C of the first upper electrode UE1C may further include at least one protruding part UE1_21 and a protruding part UE1_22. For example, the second part UE1_2C may further include at least one protruding part UE1_21 and a protruding part UE1_22 that protrude toward the connection region BR in the second region CR2. For example, the second part UE1_2C may further include at least one protruding part UE1_21 and a protruding part UE1_22 that protrude in the first horizontal direction (X direction). At least one protruding part UE1_21 and the protruding part UE1_22 may also protrude in the second horizontal direction (Y direction). At least a portion of at least one protruding part UE1_21 and the protruding part UE1_22 may overlap with the support member 144P and the support member 142P in the first horizontal direction (X direction). For example, at least a portion of the first protruding part UE1_21 may overlap with the upper support member 144P in the first horizontal direction (X direction). In other words, at least a portion of the first protruding part UE1_21 may be located at the same vertical level where the upper support member 144P is positioned. For example, at least a portion of the second protruding part UE1_22 may overlap with the lower support member 142P in the first horizontal direction (X direction). In other words, at least a portion of the second protruding part UE1_22 may be located at the same vertical level where the lower support member 142P is positioned. When at least one protruding part UE1_21 and the protruding part UE1_22 protrude in the second horizontal direction (Y direction), at least a portion of at least one protruding part UE1_21 and the protruding part UE1_22 may overlap with the support member 144P in the second horizontal direction (Y direction). In some embodiments, the first protruding part UE1_21 and the second protruding part UE1_22 may not overlap each other in the horizontal direction. In some other embodiments, the first protruding part UE1_21 and the second protruding part UE1_22 may include portions that overlap each other in the horizontal direction. In some embodiments, an insulating layer 180C may be formed by surrounding the second part UE1_2C of the first upper electrode UE1C within the connection region BR, and the unfilled portion in the second region CR2 may be filled by the second part UE1_2C. In other words, the insulating layer 180C may be formed on the upper surface of the second part UE1_2C and fill the connection region BR between the first protruding part UE1_21 and the second protruding part UE1_22. In other words, the insulating layer 180C may include a portion disposed within the second region CR2. The insulating layer 180C may have a curved side surface along the side surface of the second part UE1_2C. Referring to FIG. 7, a semiconductor device 100D may be provided. The differences from the semiconductor device 100A described with reference to FIG. 4 are mainly described below. The semiconductor device 100D may include a first upper electrode UE1D, and the first upper electrode includes a second portion UE1_2D. The second portion UE1_2D may further include a tail portion UE1_23 protruding toward the connection region BR within the second region CR2. For example, the second portion UE1_2D may further include a tail portion UE1_23 protruding in the first horizontal direction (X direction) within the second region CR2. In other words, the second portion UE1_2D of the first upper electrode UE1D may have an L-shaped cross section. The tail portion UE1_23 may also protrude in the second horizontal direction (Y direction). The tail portion UE1_23 may include a portion of the lower portion of the second portion UE1_2D protruding toward the connection region BR within the second region CR2. In other words, the lower surface of the tail portion UE1_23 may be located at the same vertical level where the lower surface of the second portion UE1_2D is located. The tail portion UE1_23 may include a portion disposed on the dielectric layer 160 in the second region CR2. In other words, the lower surface of the tail portion UE1_23 may be located at the same vertical level where the upper surface of the dielectric layer 160 in the second region CR2 is located. The tail portion UE1_23 may not overlap with the support member 144P and the support member 142P in the first horizontal direction (X direction). In other words, the tail portion UE1_23 may be located at a vertical level different from the vertical levels of the support member 144P and the support member 142P. In some embodiments, an insulating layer 180D may be formed by surrounding the second portion UE1_2D of the first upper electrode UE1D within the connection region BR, and the unfilled portion in the second region CR2 may be filled by the second portion UE1_2D. In other words, since the tail portion UE1_23 of the second portion UE1_2D protrudes toward the connection region BR, the insulating layer 180D may be formed within the second region CR2 by filling the upper portion above the tail portion UE1_23. In other words, the insulating layer 180D may include a portion disposed within the second region CR2. The insulating layer 180D may have a curved side surface along the side surface of the second portion UE1_2D. Referring to FIG. 8, a semiconductor device 100E may be provided. The differences from the semiconductor device 100A described with reference to FIG. 4 will be mainly described below. The semiconductor device 100E may include a first upper electrode UE1E, and the first upper electrode includes a second portion UE1_2E. The second portion UE1_2E may include a curved side surface. For example, the upper surface of the second portion UE1_2E of the first upper electrode UE1E may include a portion at a vertical level different from the vertical level of the upper surface of the first portion UE1_1. In other words, the upper surface of the second portion UE1_2E of the first upper electrode UE1E may include a portion within the second region CR2 where the vertical level decreases as the distance from the connection region BR decreases. The second portion UE1_2E of the first upper electrode UE1E of the semiconductor device 100E may further include at least one protruding portion UE1_21 and a protruding portion UE1_22. For example, the second portion UE1_2E may further include at least one protruding portion UE1_21 and a protruding portion UE1_22 that protrude toward the connection region BR in the second region CR2. The at least one protruding portion UE1_21 and the protruding portion UE1_22 of the second portion UE1_2E are similar to the protruding portions described with reference to FIG. 6. The second portion UE1_2E of the first upper electrode UE1E of the semiconductor device 100E may further include a tail portion UE1_23 that protrudes toward the connection region BR within the second region CR2. For example, the second portion UE1_2E may further include a tail portion UE1_23 that protrudes in the first horizontal direction (X direction) within the second region CR2. The tail portion UE1_23 of the second portion UE1_2E is similar to the tail portion described with reference to FIG. 7. In some embodiments, when the semiconductor device 100E includes both at least one protruding portion UE1_21 and UE1_22 and a tail portion UE1_23, the vertical levels of the at least one protruding portion UE1_21 and the protruding portion UE1_22 and the tail portion UE1_23 may be different from each other. For example, the at least one protruding portion UE1_21 and the protruding portion UE1_22 include at least a portion that overlaps with the support member 144P and the support member 142P in the first horizontal direction (X direction), while the tail portion UE1_23 may not overlap with the support member 144P and the support member 142P in the first horizontal direction (X direction). For example, the tail portion UE1_23 may be disposed on the dielectric layer 160 of the second region CR2 and may include a lower surface at the same vertical level as the lower surface positioned on the second portion UE1_2E. On the other hand, the at least one protruding portion UE1_21 and the protruding portion UE1_22 are located at a vertical level higher than the vertical level of the lower surface of the second portion UE1_2E. In some embodiments, an insulating layer 180E may be formed by surrounding a second portion UE1_2E of a first upper electrode UE1E within a connection region BR, and an unfilled portion in a second region CR2 may be filled by the second portion UE1_2E. In other words, the insulating layer 180E may include a portion disposed on an upper surface of the second portion UE1_2E. In other words, when at least one protruding portion UE1_21 and a protruding portion UE1_22 and a tail portion UE1_23 of the second portion UE1_2E protrude toward the connection region BR, the insulating layer 180E may be formed within the second region CR2 by filling between at least one protruding portion UE1_21 and the protruding portion UE1_22 and between each of at least one protruding portion UE1_21 and UE1_22 and the tail portion UE1_23. In other words, the insulating layer 180E may include a portion disposed within the second region CR2. The insulating layer 180E may have a curved side surface along a side surface of the second portion UE1_2E. With the semiconductor device 100E according to an embodiment in accordance with the inventive concept, a second upper electrode UE2 is disposed only on a first portion UE1_1 of a first region CR1 and not on a second portion UE1_2E of a second region CR2, and thus, a thickness of a capacitor portion CP disposed within the second region CR2 in a horizontal direction may be reduced. For example, a length of a protruding portion and a tail portion of a capacitor CP disposed within the second region CR2 in a horizontal direction may be reduced. FIG. 9 is a cross-sectional view showing a partial configuration of a semiconductor device 200 according to an embodiment in accordance with the inventive concept. The semiconductor device 200 may include a substrate 110 including a cell array region MCA and a peripheral circuit region PCA. The cell array region MCA and the peripheral circuit region PCA may be respectively similar to the cell array region and the peripheral circuit region described with reference to FIG. 1. The cell array region MCA may include a cell region CR including a first region CR1 and a second region CR2, and a connection region BR surrounding the cell region CR. The first region CR1, the second region CR2, and the connection region BR may be respectively similar to the first region, the second region, and the connection region described with reference to FIGS. 2 and 4. The semiconductor device 200 may include a cell transistor CTR disposed within the cell array region MCA of the substrate 110, a capacitor CP electrically connected to the cell transistor, a peripheral circuit transistor PTR disposed within the peripheral circuit region PCA of the substrate 110, and a peripheral circuit contact PCC electrically connected to the peripheral circuit transistor. The cell transistor CTR and the capacitor CP may be respectively similar to the cell transistor CTR and the capacitor CP described with reference to FIGS. 2 to 4. In some embodiments, the peripheral circuit isolation layer 114 and the third active region AC3 defined hereby may be disposed within the substrate 110 of the peripheral circuit area PCA. The peripheral circuit isolation layer 114 may include an oxide layer, a nitride layer, or a combination thereof. In some embodiments, the peripheral circuit isolation layer 114 may have various structures, such as a STI structure. In some embodiments, the peripheral circuit transistor PTR may be disposed on the third active region AC3 in the peripheral circuit area PCA. The peripheral circuit transistor PTR may include a gate dielectric layer 212, a peripheral circuit gate electrode 214, and a gate capping pattern 216 stacked in sequence within the third active region AC3. In some embodiments, the gate dielectric layer 212 may include at least one layer selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer. The peripheral circuit gate electrode 214 may include the same material as the bit line BL disposed in the cell array area MCA described with reference to FIG. 3. The peripheral circuit gate electrode 214 may have a structure including a lower conductive pattern (not shown), an intermediate conductive pattern (not shown), and an upper conductive pattern (not shown). The lower conductive pattern (not shown) may include doped polysilicon. Each of the intermediate conductive pattern (not shown) and the upper conductive pattern (not shown) may include TiN, titanium silicon nitride (TiSiN), W, tungsten silicide, or a combination thereof. The gate capping pattern 216 may include a silicon nitride layer. In some embodiments, two sidewalls of each of the peripheral circuit gate electrode 214 and the gate capping pattern 216 may be covered by an insulating spacer 218. The insulating spacer 218 may include an oxide layer, a nitride layer, or a combination thereof. Although not shown, the peripheral circuit transistor PTR and the insulating spacer 218 may be covered by a peripheral circuit protection layer (not shown), and the first interlayer insulating layer 231 may be disposed on the peripheral circuit protection layer and fill the space between two adjacent peripheral circuit transistors PTR. The interlayer insulating layer 231 may have an upper surface at the same vertical level as the upper surface of the gate capping pattern 216. The second interlayer insulating layer 232 may be disposed on the first interlayer insulating layer 231 and the peripheral circuit transistor PTR. In the peripheral circuit area PCA, a contact plug 240 may be formed vertically through the first interlayer insulating layer 231 and the second interlayer insulating layer 232. A metal silicide layer (not shown) may be located between the third active region AC3 and the contact plug 240. A second insulating pattern 127P covering the contact plug 240 may be disposed on the second interlayer insulating layer 232. The second insulating pattern 127P may be located at the same vertical level as the first insulating pattern 126P disposed in the cell array area MCA. In a peripheral circuit area PCA, a peripheral circuit contact PCC can be configured to extend in a vertical direction (Z direction) through an interlayer insulating layer 250 and a second insulating pattern 127P. The peripheral circuit contact PCC can be electrically connected to a peripheral circuit transistor PTR via a contact plug 240. Although not shown, the peripheral circuit contact PCC can include a contact conductive layer formed on a conductive barrier layer and the conductive barrier layer. According to an embodiment of the inventive concept, a semiconductor device 200 in which a distance between a capacitor CP disposed in a cell array area MCA and a peripheral circuit contact PCC disposed in a peripheral circuit area PCA is reduced. For example, in the semiconductor device 200, since the second upper electrode UE2 is only disposed in the first region CR1, a thickness of a portion of the capacitor CP disposed in the second region CR2 in a horizontal direction can be reduced, and thus, the semiconductor device 200 in which a distance between a lower electrode LE disposed in the first region CR1 and a peripheral circuit contact PCC disposed in the peripheral circuit area PCA is reduced can be provided. FIGS. 10A to 10K are cross-sectional views for describing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. Referring to FIG. 10A, an element isolation layer 112 can be disposed in a cell region CR of a substrate 110 to define a plurality of active regions AC1 and AC2, and a connection isolation layer 113 can be disposed in a connection region BR. A lower structure 120 connected to the active region AC via a lower structure 120 and a conductive pattern 124 can be formed on the substrate 110 in the cell region CR. Thereafter, an insulating layer 126 covering the lower structure 120 and the conductive pattern 124 can be formed in the cell region CR and the connection region BR. The insulating layer 126 can be used as an etch stop layer in a subsequent process. The insulating layer 126 can include an insulating material having an etch selectivity with respect to the lower structure 120. In some embodiments, the insulating layer 126 can include an SiN layer, an SiCN layer, an SiBN layer, or a combination thereof. Referring to FIG. 10B, a mold structure MST can be formed on the insulating layer 126. For example, the mold structure MST can be formed on the insulating layer 126 in the cell region CR and the connection region BR. For example, the mold structure MST can be formed on a plurality of first active regions AC1 in a first region CR1 and a plurality of second active regions AC2 in a second region CR2. For example, the mold structure MST can be formed on the element isolation layer 112 in the cell region CR and the connection isolation layer 113 in the connection region BR. The mold structure MST may include multiple mold layers and multiple support layers. For example, the mold structure MST may include a first mold layer 132, a lower support member layer 142, a second mold layer 134, and an upper support member layer 144 that are sequentially stacked on the insulating layer 126. Since each of the first mold layer 132 and the second mold layer 134 may include a material that has a higher etching rate compared to an etchant containing ammonium fluoride (NH 4 F), hydrofluoric acid (HF), and water, and thus may include a material that can be removed by a lift-off process using the etchant. In some embodiments, each of the first mold layer 132 and the second mold layer 134 may include an oxide layer, a nitride layer, or a combination thereof. For example, the first mold layer 132 may include a borophosphosilicate glass (BPSG) layer. The BPSG layer may include at least one of the following: a first portion in which the concentration of the dopant boron (B) varies in the thickness direction of the BPSG layer; and a second portion in which the concentration of the dopant phosphorus (P) varies in the thickness direction of the BPSG layer. The second mold layer 134 may include a multi-insulating layer in which relatively thin silicon oxide layers and silicon nitride layers are alternately stacked multiple times, or a silicon nitride layer. However, the material of each of the first mold layer 132 and the second mold layer 134 is not limited to the materials described above, and various modifications can be made within the scope of the inventive concept. In addition, the stacking order of the mold structure MST is not limited to the stacking order described with reference to FIG. 10B, and various modifications can be made within the scope of the inventive concept. Each of the lower support member layer 142 and the upper support member layer 144 may include a SiN layer, a SiCN layer, a SiBN layer, or a combination thereof. In an embodiment, the lower support member layer 142 and the upper support member layer 144 may include the same material as each other. In other embodiments, the lower support member layer 142 and the upper support member layer 144 may include different materials from each other. For example, each of the lower support member layer 142 and the upper support member layer 144 may include a SiCN layer. In another example, the lower support member layer 142 may include a SiCN layer, and the upper support member layer 144 may include a boron-containing SiN layer. However, the materials of the lower support member layer 142 and the upper support member layer 144 are not limited to the materials described above, and various modifications can be made within the scope of the inventive concept. Referring to FIG. 10C, in the result of FIG. 10B, the mold structure pattern MSP that defines multiple holes BH can be formed by forming a mask pattern MP on the mold structure MST, and then anisotropically etching the mold structure MST and using the mask pattern MP as an etching mask and using the insulating layer 126 as an etching stop layer. The mold structure pattern MSP may include a first mold pattern 132P, a lower support member 142P, a second mold pattern 134P, and an upper support member 244P. The mask pattern MP may include a nitride layer, an oxide layer, a polysilicon layer, a photoresist layer, or a combination thereof. The process of forming the plurality of holes BH may further include a process of wet-treating the result of the anisotropic etching of the mold structure MST. During the process of anisotropically etching the mold structure MST and wet-treating the result, a portion of the insulating layer 126 is etched together, and a first insulating pattern 126P having a plurality of openings 126H exposing the plurality of conductive patterns 124 can be obtained. In an example of the process of wet-treating the result of the anisotropic etching of the mold structure MST, an etchant including a diluted dithionic acid persulfate (DSP) solution may be used, but is not limited thereto. In the mold structure pattern MSP, a plurality of holes 142H as part of the plurality of holes BH may be formed in the lower support 142P, and a plurality of holes 144H as part of the plurality of holes BH may be formed in the upper support 144P. Referring to FIG. 10D, the mask pattern MP may be removed from the result of FIG. 10C, and a lower electrode LE filling the plurality of holes BH may be formed. In an embodiment, to form the lower electrode LE, a conductive layer covering the upper surface of the upper support 144P and filling the plurality of holes BH may be formed on the result of FIG. 10C. To form the conductive layer, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a metal organic CVD (MOCVD) process, or an atomic layer deposition (ALD) process may be used. Thereafter, a portion of the conductive layer may be removed by using an etch-back process or a chemical mechanical polishing (CMP) process so that the upper surface of the upper support 144P can be exposed. Referring to FIG. 10E, a plurality of upper holes UH can be formed by removing a portion of the upper support 144P within the cell region CR from the result of FIG. 10D, and then, the second mold pattern 134P can be wet-removed through the plurality of upper holes UH. Thereafter, a plurality of lower holes LH can be formed by removing a portion of the lower support 142P within the cell region CR that is exposed through the plurality of upper holes UH, and then, the first mold pattern 132P can be wet-removed through the plurality of lower holes LH, such that the upper surface of the first insulating pattern 126P within the cell region CR can be exposed. In other words, the upper surface of the first insulating pattern 126P within the first region CR1 and the second region CR2 can be exposed. After removing the first mold pattern 132P and the second mold pattern 134P, the sidewalls of the plurality of lower electrodes LE can be exposed. The first mold pattern 132P, the lower support 142P, the second mold pattern 134P, and the upper support 144P within the connection region BR are all removed, and the upper surface of the first insulating pattern 126P can be exposed. In an embodiment, in order to wet-remove the second mold pattern 134P and the first mold pattern 132P, an etchant containing NH 4 F, HF, and water can be used, but is not limited thereto. Referring to FIG. 10F, a process of forming a dielectric layer 160 covering the lower electrode LE exposed in the result of FIG. 10E can be performed. The dielectric layer 160 can be formed to cover not only the sidewalls of the lower electrode LE, but also the exposed surfaces of each of the lower support 142P and the upper support 144P and the exposed surface of the first insulating pattern 126P. To form the dielectric layer 160, a CVD process, a PECVD process, a MOCVD process, or an ALD process can be used. After performing the deposition process for the dielectric layer 160 covering the lower electrode LE, an annealing process can be performed. In an embodiment, the annealing process can be performed at a temperature of about 200°C to about 700°C. The crystallinity of the dielectric layer 160 can be improved by the annealing process, which can be performed in the state of forming the dielectric layer 160. Herein, the dielectric layer 160 is formed within the cell region CR and the connection region BR. However, in other embodiments, the dielectric layer 160 can be formed within the cell region CR, but not within the connection region BR. Referring to FIG. 10G, a first upper electrode UE1 covering the dielectric layer 160 in the result of FIG. 10F can be formed. In the cell region CR, the first upper electrode UE1 can be disposed on the lower electrode LE, with the dielectric layer 160 therebetween. In the cell region CR, the first upper electrode UE1 can be disposed on the upper support 144P, with the dielectric layer 160 therebetween. In the cell region CR, the first upper electrode UE1 can be disposed on the lower support 142P, with the dielectric layer 160 therebetween. For example, in the second region CR2, the second portion UE1_2 of the first upper electrode UE1 can be disposed on the dielectric layer 160. Herein, when the dielectric layer 160 is formed in the cell region CR and the connection region BR, the first upper electrode UE1 is also formed on the dielectric layer 160 formed in the connection region BR. However, in some other embodiments, the first upper electrode UE1 can be formed in the cell region CR but not in the connection region BR. Referring to FIG. 10H, a mask pattern can be formed on the first upper electrode UE1 in the cell region CR of the result of FIG. 10G, and the dielectric layer 160 and the first upper electrode UE1 formed in the connection region BR can be removed. Since the dielectric layer 160 and the first upper electrode UE1 formed in the connection region BR are removed, the dielectric layer 160 and the first upper electrode UE1 can be disposed only in the cell region CR. The cell region CR and the connection region BR can be distinguished from each other by the dielectric layer 160 and the first upper electrode UE1. For example, in the cell array region MCA described with reference to FIGS. 1 and 2, the region of the dielectric layer 160 and the first upper electrode UE1 can include the cell region CR, and the region surrounding the cell region CR where no dielectric layer 160 and first upper electrode UE1 are disposed can include the connection region BR. Referring to FIG. 10I, an insulating layer 180 surrounding the first upper electrode UE1 disposed in the cell region CR can be formed. For example, the insulating layer 180 can be formed in the connection region BR to horizontally surround the first upper electrode UE1. The upper surface of the insulating layer 180 can be at the same vertical level as the upper surface of the second portion UE1_2 of the first upper electrode UE1 is positioned. To form the insulating layer 180, an insulating material can be coated on the cell region CR and the connection region BR by using processes such as CVD, PECVD, MOCVD, and ALD, and then, portions of the insulating material can be removed by using an etch-back process or a CMP process so that the upper surface of the second portion UE1_2 of the first upper electrode UE1 can be exposed. Referring to FIG. 10J, a second upper electrode UE2 can be formed within a first upper electrode UE1 disposed in the cell region CR. For example, the second upper electrode UE2 can be formed on a first portion UE1_1 of the first upper electrode UE1. For example, the second upper electrode UE2 can be formed within a first region CR1. To form the second upper electrode UE2, a mask pattern can be formed within a second region CR2 and a connection region BR, and then, the second upper electrode UE2 can be formed within the first region CR1. Thereafter, the mask pattern formed within the second region CR2 and the connection region BR can be removed, and a first insulating pad 181 can be formed around the second upper electrode UE2. Alternatively, to form the second upper electrode UE2, an insulating material can be coated onto the cell region CR and the connection region BR, and then, the insulating material formed within the first region CR1 can be removed such that the first insulating pad 181 can be formed. Thereafter, the second upper electrode UE2 can be formed within the first region CR1. Referring to FIG. 10K, a protective layer 170 including an insulating material can be formed on the second upper electrode UE2 disposed in the cell region CR. For example, the protective layer 170 can be formed on a first portion UE1_1 of the first upper electrode UE1. For example, the protective layer 170 can be formed within the first region CR1. To form the protective layer 170, a mask pattern can be formed within the second region CR2 and the connection region BR, and then, the protective layer 170 can be formed within the first region CR1. Thereafter, the mask pattern formed within the second region CR2 and the connection region BR can be removed, and a second insulating pad 182 can be formed around the protective layer 170. Alternatively, to form the protective layer 170, an insulating material can be coated onto the cell region CR and the connection region BR, and then, the insulating material formed within the first region CR1 can be removed such that the second insulating pad 182 can be formed. Thereafter, the protective layer 170 can be formed within the first region CR1. By a method of manufacturing a semiconductor device according to the inventive concept, a semiconductor device 100 including a second upper electrode UE2 disposed only on a first portion UE1_1 of a first upper electrode UE1 within a first region CR1 can be provided. Although a method of manufacturing the semiconductor device 100 is described with reference to FIGS. 10A to 10K, those of ordinary skill in the art can manufacture the semiconductor devices 100A, 100B, 100C, 100D, 100E, and 200 described with reference to FIGS. 4 to 9 within the spirit and scope of the inventive concept. Although the inventive concept has been particularly shown and described with reference to its embodiments, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the following claims. 100, 100A, 100B, 100C, 100D, 100E, 200: Semiconductor device 110: Substrate 112: Element isolation layer 113: Connection isolation layer 114: Peripheral circuit isolation layer 120: Lower structure 124: Conductive pattern 126: Insulating layer 126H: Opening 126P: First insulating pattern 127P: Second insulating pattern 132: First mold layer 132P: First mold pattern 134: Second mold layer 134P: Second mold pattern 142: Lower support layer 142H, 144H, BH: Hole 142P: Lower support 144: Upper support layer 144P: Upper support 160: Dielectric layer 170: Protection layer 180A, 180B, 180C, 180D, 180E: Insulating layer 181: First insulating pad 182: Second insulating pad 212: Gate dielectric layer 214: Peripheral circuit gate electrode 216: Gate capping pattern 218: Insulating spacer 231: First interlayer insulating layer 232: Second interlayer insulating layer 240: Contact plug 250: Interlayer insulating layer AC1: First active region AC2: Second active region AC3: Third active region BC: Buried contact BL: Bit line BR: Connection region CP: Capacitor CR: Cell region CR1: First region CR2: Second region CTR: Cell transistor DC: Direct contact I-I', II-II': Line LE: Lower electrode LH: Lower hole LP: Conductive landing pad MCA: Cell array region MP: Mask pattern MSP: Mold structure pattern MST: Mold structure PCA: Peripheral circuit region PCC: Peripheral circuit contact PTR: Peripheral circuit transistor UE1, UE1A, UE1B, UE1C, UE1D, UE1E: First upper electrode UE1_1: First part UE1_1t, UE1_2At, UE1_2Bt: Upper surface UE1_21: First protruding part UE1_22: Second protruding part UE1_23: Tail part UE1_2, UE1_2A, UE1_2B, UE1_2C, UE1_2D, UE1_2E: Second part UE2: Second upper electrode UH: Upper hole WL: Word line X, Y, Z: Directions The following detailed description, taken in conjunction with the accompanying drawings, will more clearly understand the embodiments. In the accompanying drawings: FIG. 1 is a schematic layout diagram of a semiconductor device according to an embodiment of the present invention concept. FIG. 2 is a schematic layout diagram of a semiconductor device according to an embodiment of the present invention concept. FIG. 3 is a plan view schematically showing a partial configuration of a semiconductor device according to an exemplary embodiment of the present invention concept. FIGS. 4 to 8 are cross-sectional views schematically showing a partial configuration of a semiconductor device according to an embodiment of the present invention concept. FIG. 9 is a cross-sectional view showing a partial configuration of a semiconductor device according to an embodiment of the present invention concept. FIGS. 10A to 10K are cross-sectional views for describing a manufacturing method of a semiconductor device according to an embodiment of the present invention concept. 100A: Semiconductor device 110: Substrate 112: Element isolation layer 113: Connection isolation layer 120: Lower structure 124: Conductive pattern 126H: Opening 126P: First insulating pattern 142H, 144H: Hole 142P: Lower support 144P: Upper support 160: Dielectric layer 170: Protection layer 180A: 181: First insulating pad 182: Second insulating pad AC1: First active region AC2: Second active region BR: Connection region CP: Capacitor CR: Cell region CR1: First region CR2: Second region LE: Lower electrode UE1A: First upper electrode UE1_1: First part UE1_1t, UE1_2At: Upper surface UE1_2A: Second part UE2: Second upper electrode X, Y, Z: Directions

Claims

1. A semiconductor device, comprising: The substrate includes a first region and a second region planarly surrounding the first region; An active region is disposed in the first region of the substrate; A lower electrode is disposed on the first region of the substrate and extends in the vertical direction, and the lower electrode is electrically connected to the active region; A support member surrounds the sidewall of the lower electrode and supports the lower electrode; A first upper electrode covers the lower electrode and is located on the lower electrode. The first upper electrode includes a first portion disposed in the first region and a second portion disposed in the second region. A dielectric layer is disposed between the lower electrode and the first upper electrode. And a second upper electrode, disposed on the first portion of the first upper electrode, wherein the second upper electrode is not disposed on the second portion of the first upper electrode.

2. The semiconductor device of claim 1, wherein the first upper electrode comprises one or more selected from silicon germanium (SiGe) and silicon (Si), and the second upper electrode comprises one or more selected from tungsten (W), titanium nitride (TiN), and combinations thereof.

3. The semiconductor device of claim 1, wherein the second portion of the first upper electrode comprises a material substantially different from the material of the second upper electrode.

4. The semiconductor device of claim 1, further comprising a protective layer on the second upper electrode, the protective layer comprising an insulating material.

5. The semiconductor device as claimed in claim 4, wherein the protective layer is not disposed on the second portion of the first upper electrode.

6. The semiconductor device of claim 1, wherein the second portion of the first upper electrode has an L-shaped cross-section.

7. The semiconductor device of claim 1, wherein the second portion of the first upper electrode includes one or more protrusions projecting in a horizontal direction intersecting the vertical direction, and at least a portion of the protrusions overlaps with the support in the horizontal direction.

8. A semiconductor device, comprising: A substrate includes cell regions and connecting regions, the cell regions including a first region and a second region, the second region being disposed between the first region and the connecting region; a plurality of active regions are disposed in the cell regions of the substrate; Multiple conductive patterns are disposed on the cell region of the substrate, and the multiple conductive patterns are disposed on the multiple active regions; multiple lower electrodes extend vertically and are electrically connected to the multiple active regions via the multiple conductive patterns; Multiple support members surround and support each of the multiple sidewalls of the multiple lower electrodes; A dielectric layer is disposed on the plurality of lower electrodes and the plurality of supports but not placed within the connection area; A first upper electrode is disposed on the dielectric layer, the first upper electrode comprising a first portion disposed in the first region and a second portion disposed in the second region; And a second upper electrode, which is placed in the first region but not in the second region and the connection region.

9. The semiconductor device of claim 8, wherein the first upper electrode comprises one or more selected from silicon germanium (SiGe) and silicon (Si), and the second upper electrode comprises one or more selected from tungsten (W), titanium nitride (TiN), and combinations thereof.

10. The semiconductor device of claim 8, wherein the vertical hierarchy of the upper surface of the second portion of the first upper electrode includes a portion of the vertical hierarchy that is different from the vertical hierarchy of the upper surface of the first portion of the first upper electrode.

Images