Reconfigurable circuit chip that can simultaneously process multi-dimensional signals of convolutional neural network

Abstract

This invention relates to a reconfigurable circuit chip capable of simultaneously processing multi-dimensional signals using convolutional neural networks (CNNs). The chip primarily comprises a one-dimensional CNN module and a two-dimensional CNN module, connected to an integrated module. Each one-dimensional CNN module can independently output its identification result, as can each two-dimensional CNN module. The integrated module combines the input one-dimensional and output two-dimensional CNN identification results to output a unified identification result. This allows for application in edge computing of multi-dimensional CNNs for multi-dimensional signal analysis and identification. It can learn and adjust circuit parameters based on input and output signal patterns, directly performing calculations and identification on the input signals using hardware circuitry. This offers advantages in application flexibility and low power consumption, and can also be applied to other single-dimensional or multi-dimensional applications, further enhancing its practicality.

Description

A reconfigurable circuit chip for convolutional neural networks capable of simultaneously processing multi-dimensional signals The present invention relates to a reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multi-dimensional signals. Specifically, the chip can self-learn and adjust circuit parameters based on input and output signal patterns, and directly operate and identify input signals using hardware circuits. The chip has the advantages of flexibility and low power consumption, and further enhances practical performance characteristics in its overall implementation. In recent years, convolutional neural networks (CNNs) have become a key tool in deep learning. Originally designed to mimic the visual neurons in the human cerebral cortex, CNNs are used to recognize images, leading to their widespread application in various image recognition systems. However, because many applications require one-dimensional signals, recent research has modified the 2D CNN architecture into a 1D CNN for use in the recognition or processing of one-dimensional signals. For example, S. Kiranyaz et al. first proposed the 1D CNN in 2016 and applied it to ECG signal arrhythmia detection. Subsequently, T. Ince et al. applied this 1D CNN to motor current signal-based fault diagnosis. L. Eren also applied the 1D CNN to motor bearing fault detection. This demonstrates that the 1D CNN architecture is still a relatively new approach, but it is increasingly being adopted in various fields. In addition, in recent years, 2-D CNN has replaced previous methods such as LBP, NMF and Sparse Learning and become the mainstream method for image emotion recognition. In the past, field programmable gate array (FPGA) chips were primarily used to improve chip computing efficiency. For example, MH Lee, KK Shyu, PL Lee, CM Huang, and YJ Chiu, “Hardware Implementation of EMD Using DSP and FPGA for Online Signal Processing,” IEEE Transactions on Industrial Electronics, Vol. 58, No. 6, pp. 2473–2481, June 2011, presented a hardware implementation of EMD. The authors used a DSP processor to perform EMD calculations and an FPGA to coordinate and control the workflow. However, this approach has the following disadvantages: 1. It requires an additional DSP processor to perform EMD calculations, which is very costly; 2. The system still uses a single-core architecture and lacks parallelization mechanisms, resulting in limited improvement in computing speed. As personal computers evolved from early dual-CPU workstations to multi-CPU servers, Moore's Law, along with advances in process technology, led to a doubling of the number of transistors in a chip of the same size every 18 months. Consequently, performance increased significantly with each successive cycle. However, as computing demands grew, CPU clock speeds struggled to keep pace with the massive computational demands of humanity. This led to the gradual evolution of clock speeds to dual-core, quad-core, and other multi-core processors, which in turn led to the incorporation of parallelization technology into personal computers. In recent years, the capacity of FPGAs has significantly increased, transforming their role from a CPU accelerator peripheral to a device capable of independently performing large amounts of computation. This made it possible to fully implement CNN circuits on FPGAs, which are inherently digital circuits capable of performing parallel computations. This approach significantly reduces wasted waiting time during program execution. Therefore, in view of this, the inventors, drawing on their rich design, development and actual production experience in the related industry over the years, have conducted further research and improvements to provide a reconfigurable circuit chip for a convolutional neural network that can simultaneously process multi-dimensional signals, in order to achieve the goal of better practical value. The primary objective of the present invention is to provide a reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multi-dimensional signals. This chip is primarily applicable to edge computing using multi-dimensional CNNs (MD CNNs) for multi-dimensional signal analysis and identification. The chip can self-learn and adjust circuit parameters based on input and output signal patterns, and directly compute and identify input signals using hardware circuits without the need for an operating system or other software. This chip offers the advantages of flexibility and low power consumption, and can also be applied to other single-dimensional or multi-dimensional applications, such as scene recognition, object recognition, and sleep apnea detection, while also enhancing its overall practicality and performance. The main purpose and function of the present invention's reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multi-dimensional signals are achieved by the following specific technical means: It mainly includes reconfigurable circuit chips, including: The reconfigurable circuit chip is respectively provided with a one-dimensional convolutional neural network [1-D Convolutional Neural Network, 1-D CNN] module and a two-dimensional convolutional neural network [2-D Convolutional Neural Network, 2-D CNN] module, and is provided with an integration module, so that the one-dimensional convolutional neural network module and the two-dimensional convolutional neural network module are connected to the integration module together. The one-dimensional convolutional neural network module can independently output the one-dimensional convolutional neural network module identification result or transmit the one-dimensional convolutional neural network module identification result to the integration module, and the two-dimensional convolutional neural network module can also independently output the two-dimensional convolutional neural network module identification result or transmit the two-dimensional convolutional neural network module identification result to the integration module, so that the integration module can integrate the input one-dimensional convolutional neural network module identification result and the output two-dimensional convolutional neural network module identification result and then output the integrated identification result. The present invention provides a preferred embodiment of a reconfigurable circuit chip for a convolutional neural network that can simultaneously process multi-dimensional signals, wherein the integrated module increases or decreases the number of the one-dimensional convolutional neural network modules and the two-dimensional convolutional neural network modules according to the requirements of the application field. The present invention is a preferred embodiment of a reconfigurable circuit chip for a convolutional neural network that can simultaneously process multi-dimensional signals, wherein the convolution layer circuit of the one-dimensional convolutional neural network module includes a register file connected to the external memory of the field programmable logic gate array, an inverting register file connected to the internal memory of the field programmable logic gate array, a shift circuit connected to the register file, a multiplier / accumulator connected to the shift circuit, and a state control circuit respectively connected to the register file, the shift circuit, and the multiplier / accumulator. In addition, the multiplier / accumulator is connected to an output function. f(·) circuit; and the convolution layer circuit of the two-dimensional convolutional neural network module includes the array [two-dimensional] register file connected to the external memory of the field programmable logic gate array, the rotation register file connected to the internal memory of the field programmable logic gate array, the array shift circuit connected to the array register file, the multiplier / accumulator connected to the array shift circuit, and the state control circuit connected to the array register file, the array shift circuit, and the multiplier / accumulator respectively. In addition, the multiplier / accumulator is connected to the output function f(·) circuit. The present invention provides a preferred embodiment of a reconfigurable circuit chip for a convolutional neural network that can simultaneously process multi-dimensional signals, wherein the pooling layer circuit of the one-dimensional convolutional neural network module is composed of a register file, an accumulator, and a divider connected in sequence; and the pooling layer circuit of the two-dimensional convolutional neural network module is composed of an array register file, an accumulator, and a divider connected in sequence. The preferred embodiment of the present invention is a reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multi-dimensional signals, wherein a neuron circuit architecture in a fully connected layer of the one-dimensional convolutional neural network module is provided with a register file connected to the internal memory of the field programmable logic gate array, a multiplier / accumulator connected to the register file, a register file connected to the multiplier / accumulator, and an output function connected to the multiplier / accumulator. f(·) circuit, and are respectively connected to the register file, the multiplier / accumulator, the output function State control circuit of f(·) circuit. The present invention provides a preferred embodiment of a reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multi-dimensional signals. The reconfigurable circuit chip includes a multiplexer circuit for controlling the selection of three different outputs: the one-dimensional convolutional neural network module recognition result output, the two-dimensional convolutional neural network module recognition result output, and the integrated recognition result output after integrating the multi-dimensional convolutional neural network. In order to make the technical content, inventive objectives and effects achieved by the present invention more complete and clear, they are described in detail below. Please refer to the disclosed drawings and figure numbers: First, referring to FIG. 1 , which shows a schematic diagram of the system architecture of the present invention, the present invention mainly includes a reconfigurable circuit chip (A); wherein: The reconfigurable circuit chip (A) is provided with a one-dimensional convolutional neural network [1-D Convolutional Neural Network, 1-D CNN] module (1) and a two-dimensional convolutional neural network [2-D Convolutional Neural Network, 2-D CNN] module (2), and an integration module (3) so that the one-dimensional convolutional neural network module (1) and the two-dimensional convolutional neural network module (2) are connected to the integration module (3) together. The one-dimensional convolutional neural network module (1) can output the one-dimensional convolutional neural network module recognition result alone or transmit the one-dimensional convolutional neural network module recognition result to the integration module (3), and the two-dimensional convolutional neural network module (2) can also output the two-dimensional convolutional neural network module alone. The network module identification result or the two-dimensional convolutional neural network module identification result is transmitted to the integration module (3), so that the integration module (3) can integrate the input one-dimensional convolutional neural network module identification result and the output two-dimensional convolutional neural network module identification result and output the integrated identification result. In addition, the integration module (3) can also increase or decrease the number of the one-dimensional convolutional neural network module (1) and the two-dimensional convolutional neural network module (2) according to the requirements of the application field. Wherein: Reconfigurable computing one-dimensional convolutional neural network is designed on a field programmable gate array: Please refer to the second figure for a schematic diagram of the structure of a field programmable gate array chip of the present invention and the third figure for a schematic diagram of the structure of a field programmable gate array chip of the present invention. Since the field programmable gate array [FPGA] chip (4) is a programmable chip, its circuit structure and parameters can be repeatedly programmed at any time through the contents stored in the static random-access memory [SRAM] on the chip and by using a lookup table [LUT]. The field programmable gate array chip (4) includes a programmable logic block [logic block] (41), and the internal connection [interconnection] of the logic block (41) is a programmable input / output pin [I / O] (42), which is very suitable for convolutional neural networks. The circuit architecture and parameter repetitive correction requirements of the training process of Convolutional Neural Networks (CNN) make it possible to implement the one-dimensional convolutional neural network module (1) using the field programmable logic gate array chip (4), and to use the Altera FPGA DE2-70 development board as the implementation platform. In order to reduce the amount of calculation, the data representation method of the present invention will adopt a 16-bit fixed point method. The following is an initial planning of the circuit planning of each part of the convolutional neural network. Convolution layer circuit design: Please refer to Figure 4 for the convolution layer circuit architecture of the one-dimensional convolutional neural network module of the present invention. The present invention predicts the speech signal after emotional enhancement and the neuron output calculated at each layer. and pooling output The weight vectors and bias values ​​will be stored in the field programmable logic gate array external memory (11), while the weight vectors and bias values ​​will be stored in the field programmable logic gate array internal memory (12), which can be updated more efficiently during the training process of the convolutional neural network. The convolution layer circuit (13) includes a register file (131) connected to the external memory (11) of the field programmable logic gate array, an inverting register file (132) connected to the internal memory (12) of the field programmable logic gate array, a shift circuit (133) connected to the register file (131), a multiplier / accumulator (134) connected to the shift circuit (133), and a state control circuit (135) connected to the register file (131), the shift circuit (133), and the multiplier / accumulator (134), respectively, wherein the inverting register file (132) is used to implement the following formula: deal with; In addition, the multiplier / accumulator (134) is connected to an output function f(·) circuit (136), the output function The f(·) circuit (136) will be implemented using a look-up table [LUT]. Pooling layer circuit design: Please refer to the fifth figure for the circuit architecture of the pooling layer of the one-dimensional convolutional neural network module of the present invention. In the process of pooling, the present invention anticipates the use of average calculation to make the pooling layer circuit (14) pass through the connected register (141), accumulator (142) and divider (143) in sequence to calculate the average value. The outputs are averaged according to the ratio set by ss. For example, if If ss= 4, every 4 output values ​​will be averaged to get an average value. Fully connected layer neuron circuit design: Please refer to the sixth figure for the neuron circuit architecture in the fully connected layer of the one-dimensional convolutional neural network module of the present invention. The sixth figure is a preliminary design of the architecture of a neuron circuit (15) in the fully connected layer. The neuron circuit (15) is provided with a register file (151) connected to the internal memory (12) of the field programmable logic gate array, a multiplier / accumulator (152) connected to the register file (151), a register file (153) connected to the multiplier / accumulator (152), and an output function connected to the multiplier / accumulator (152). f(·) circuit (154), and are respectively connected to the register file (153), the multiplier / accumulator (152), the output function The state control circuit (155) of the f(·) circuit (154) and the activation function in the neuron circuit (15) are still completed in a table lookup manner, mainly because the calculation speed of the activation function can be improved through the table lookup. Forward transfer [FP] and backward transfer [BP] circuit design of the overall one-dimensional convolutional neural network: Please refer to the seventh figure for the local circuit diagram of the one-dimensional convolutional neural network of the present invention, which is limited to the field programmable logic gate array chip. The above-mentioned convolutional neural network operation layers are integrated into a one-dimensional convolutional neural network module (1). The seventh figure only discloses a convolutional layer circuit (13) connected to the field programmable logic gate array external memory (11), a pooling layer circuit (14) connected to the convolutional layer circuit (13), and a fully connected layer circuit (16) connected to the pooling layer circuit (14). The fully connected layer circuit (16) also only discloses one hidden layer (161) and one output layer (162). The convolutional layer circuit (13), the pooling layer circuit (14) and the fully connected layer circuit (16) are connected to the pooling layer circuit (14). The pooling layer circuit (14) and the fully connected layer circuit (16) are connected to the internal memory (12) of the field programmable logic gate array, and the internal memory (12) of the field programmable logic gate array is respectively connected to the first update circuit (17) [please refer to the eighth figure for the schematic diagram of the first update circuit architecture of the one-dimensional convolutional neural network module of the present invention], the second update circuit (18) [please refer to the ninth figure for the schematic diagram of the second update circuit architecture of the one-dimensional convolutional neural network module of the present invention], and the dimension-increasing circuit (19) [please refer to the tenth figure for the schematic diagram of the dimension-increasing circuit architecture of the one-dimensional convolutional neural network module of the present invention], and the actual one-dimensional convolutional neural network module (1) requires a plurality of these unit circuits, which can be completed by repeatedly replicating these units. The first updating circuit (17) and the second updating circuit (18) both access the output stored in a memory at a certain level. , parameter sensitivity and , the old weight parameters and the old bias weight parameters , update the weight parameters through circuit operation and bias weight parameters , and as a circuit, it does not directly access the memory, but rather performs dimensionality-upgrading on the previous accumulator output. In addition, regarding the design of reconfigurable computational two-dimensional convolutional neural networks and multi-dimensional convolutional neural networks (MD CNN) on field programmable logic gate arrays, since the architecture and processing procedures of two-dimensional convolutional neural networks are the same as those of one-dimensional convolutional neural networks, only the signal dimensions are different. In the calculation of the convolutional layer and pooling layer, the data is changed from one dimension to two dimensions. Therefore, the circuit design of the two-dimensional convolutional neural network will be completed by modifying the one-dimensional convolutional neural network circuit designed in the previous step. The circuits to be modified include the convolution circuit and the pooling circuit, which are described as follows: Two-dimensional convolutional neural network convolutional layer circuit design: Please refer to the convolution circuit architecture diagram of the two-dimensional convolutional neural network module of the present invention in Figure 11. The convolution layer circuit (23) of the two-dimensional convolutional neural network module (2) will be modified by the convolution layer circuit (13) of the one-dimensional convolutional neural network module (1). The main modified circuit is to modify the one-dimensional inversion register file (132) in the convolution layer circuit (13) of the one-dimensional convolutional neural network module (1) into a two-dimensional rotation register file (232). The weights and biases of the memory are used to read the order and position design of the rotation register file (232), rotate the parameter array by 180 degrees, and perform image data shift and multiplication to complete the two-dimensional convolution operation. In addition, a field programmable logic gate array external memory (11) is read. The register file (131) and the shift circuit (133) are also changed into an array [two-dimensional] register file (231) and an array shift circuit (233) to conform to the dimension of the data; so that the convolution layer circuit (23) is composed of the array [two-dimensional] register file (231) connected to the field programmable logic gate array external memory (21), the rotation circuit (233) connected to the field programmable logic gate array internal memory (22) A register file (232), an array shift circuit (233) connected to the array register file (231), a multiplier / accumulator (234) connected to the array shift circuit (233), and a state control circuit (235) connected to the array register file (231), the array shift circuit (233), and the multiplier / accumulator (234), respectively. In addition, the multiplier / accumulator (234) is connected to an output function f(·) circuit (236), the output function The f(·) circuit (236) will be implemented using a look-up table [LUT]. Two-dimensional convolutional neural network pooling [dimensionality reduction] and dimension-increasing circuit design: Similarly, please refer to the twelfth figure for the circuit architecture diagram of the pooling layer of the two-dimensional convolutional neural network module of the present invention. The register file (141) in the pooling layer circuit (14) of the one-dimensional convolutional neural network module (1) is also changed to an array register file (241); so that the pooling layer circuit (24) of the two-dimensional convolutional neural network module (2) is composed of the array register file (241), the accumulator (242) and the divider (243) connected in sequence. Please refer to the thirteenth figure for the circuit architecture diagram of the two-dimensional convolutional neural network module of the present invention. The amplification register file in the dimension-increasing circuit (19) of the one-dimensional convolutional neural network module (1) is also changed to an array amplification register file in the dimension-increasing circuit (25) of the two-dimensional convolutional neural network module (2). Field programmable logic gate array multi-dimensional convolutional neural network chip implementation: After completing the circuit design of the two-dimensional convolutional neural network module (2) and the image emotion recognition test, the integration module (3) of the one-dimensional convolutional neural network module (1) and the two-dimensional convolutional neural network module (2) will be designed, and actual voice and image emotion recognition tests will be carried out to complete the reconfigurable circuit chip (A) of the multi-dimensional convolutional neural network on the field programmable logic gate array chip; the design of the integration module (3) will be completed in a table lookup manner, and the integration matrix [Fusion Matrix] obtained through training will be used. F is built into the memory of the field programmable logic gate array. After obtaining the speech emotion recognition results of the one-dimensional convolutional neural network circuit and the image emotion recognition results of the two-dimensional convolutional neural network circuit, the final emotion recognition result output of the multi-dimensional convolutional neural network [MD CNN] chip can be obtained through a table lookup method. The integrated matrix F is ,in K represents the type of emotion, and each column of the integration matrix is: , in Represents real emotions. represents the result [emotion] identified by the one-dimensional convolutional neural network circuit, Represents the result [emotion] identified by the two-dimensional convolutional neural network circuit, The representative identification result is and , but the actual sentiment is The probability of , According to Bayesian theorem, the following formula can be derived: , Build the integration matrix through the training database F, and in the testing phase, the identification results and According to the trained integration matrix F lookup table, find the largest , corresponding to It is the final identification result [emotion]. As for the chip output circuit, a multiplexer circuit [multiplexer] (5) is designed to control the options of three different outputs, namely the output of the one-dimensional convolutional neural network module identification result, the output of the two-dimensional convolutional neural network module identification result, and the integrated identification result output after the integration of the multi-dimensional convolutional neural network [please also refer to Figure 14 for the multi-dimensional convolutional neural network chip architecture diagram of the field programmable logic gate array of the present invention]. From the above description of the use and implementation of the present invention, it can be seen that compared with the existing technical means, the present invention mainly has the following advantages: 1. This invention is designed to realize the CNN chip required for edge computing, thereby making our country more competitive in this field. 2. The present invention can provide a new direction for the application of chip design, with greater flexibility, variability, and applicable areas than traditional functional chips. 3. The present invention uses 1-D CNN for signal analysis, which is of great help to related industries such as biomedicine and smart machinery applications. 4. The MD CNN chip system implemented in this invention can be applied to other single-dimensional or multi-dimensional fields, such as scene environment recognition, object recognition, and sleep apnea detection. The MD CNN chip utilizes a modular architecture, specifically designing individual 1-D CNN and 2-D CNN circuit modules, along with an integrated circuit module, to integrate these modules into a single chip. Due to this modular design, and given the considerable capacity of current FPGAs, the number of 1-D CNN and 2-D CNN modules can be increased or decreased based on application needs, enabling even wider applications and more effective results for CNN chips. 5. This invention combines voice and image emotion recognition, significantly improving emotion recognition accuracy. Embedding the chip in everyday devices makes home emotional care possible, potentially enabling widespread application in related industries and enhancing product value. However, the aforementioned embodiments or drawings do not limit the product structure or usage of the present invention. Any appropriate changes or modifications made by a person skilled in the art should be considered as not departing from the patent scope of the present invention. In summary, the embodiments of the present invention can indeed achieve the expected use effects. Moreover, the specific structure disclosed therein has not only never been seen in similar products, but has also not been disclosed before the application. It fully complies with the provisions and requirements of the Patent Law. Therefore, an application for an invention patent is filed in accordance with the law. I sincerely request that you review it and grant the patent. I would be truly grateful for your kindness. A: Reconfigurable circuit chip 1: One-dimensional convolutional neural network module 11: Field programmable logic gate array external memory 12: Field programmable logic gate array internal memory 13: Convolution layer circuit 131: Register file 132: Invert register file 133: Shift circuit 134: Multiplier / accumulator 135: State control circuit 136: Output function f(·) circuit 14: pooling layer circuit 141: register file 142: accumulator 143: divider 15: neuron circuit 151: register file 152: multiplier / accumulator 153: register file 154: output function f(·) circuit 155: state control circuit 16: fully connected layer circuit 161: hidden layer 162: output layer 17: first update circuit 18: second update circuit 19: dimension increase circuit 2: two-dimensional convolutional neural network 21: field programmable logic gate array external memory 22: field programmable logic gate array internal memory 23: convolution layer circuit 231: array register file 232: rotation register file 233: array shift circuit 234: multiplier / accumulator 235: state control circuit 236: output function f(·) circuit 24: Pooling layer circuit 241: Array register file 242: Accumulator 243: Divider 25: Dimensional increase circuit 3: Integration module 4: Field programmable logic gate array chip 41: Logic block 42: Input / output pin 5: Multiplexer circuit Figure 1: Schematic diagram of the system architecture of the present invention Figure 2: Schematic diagram of the structure of the field programmable logic gate array chip that can be repeatedly planned Figure 3: Schematic diagram of the architecture of the field programmable logic gate array chip that can be repeatedly planned Figure 4: Circuit architecture diagram of the convolution layer of the one-dimensional convolutional neural network module of the present invention Figure 5: Circuit architecture diagram of the pooling layer of the one-dimensional convolutional neural network module of the present invention Figure 6: Circuit architecture diagram of the neurons in the fully connected layer of the one-dimensional convolutional neural network module of the present invention Figure 7: Schematic diagram of the local circuit of the field programmable logic gate array chip of the one-dimensional convolutional neural network of the present invention Figure 9: Schematic diagram of the first update circuit architecture of the one-dimensional convolutional neural network module of the present invention Figure 10: Schematic diagram of the dimensional upgrade circuit architecture of the one-dimensional convolutional neural network module of the present invention Figure 11: Schematic diagram of the convolution circuit architecture of the two-dimensional convolutional neural network module of the present invention Figure 12: Circuit architecture diagram of the pooling layer of the two-dimensional convolutional neural network module of the present invention Figure 13: Schematic diagram of the dimensional upgrade circuit architecture of the two-dimensional convolutional neural network module of the present invention Figure 14: Architecture diagram of the multi-dimensional convolutional neural network chip with field programmable logic gate array of the present invention A: Reconfigurable circuit chip 1: One-dimensional convolutional neural network module 2: Two-dimensional convolutional neural network 3: Integration module

Claims

1. A reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multi-dimensional signals, mainly comprising a reconfigurable circuit chip; wherein: The reconfigurable circuit chip comprises a 1-D Convolutional Neural Network (1-D CNN) module and a 2-D Convolutional Neural Network (2-D CNN) module, and an integrated module connecting the 1-D and 2-D CNN modules. The 1-D CNN module can independently output its recognition results or transmit them to the integrated module. Similarly, the 2-D CNN module can independently output its recognition results or transmit them to the integrated module. The data is fed to the integration module, which integrates the input recognition result of the one-dimensional convolutional neural network module and the output recognition result of the two-dimensional convolutional neural network module, and outputs the integrated recognition result. The pooling layer circuit of the one-dimensional convolutional neural network module is composed of a register, an accumulator and a divider connected in sequence, and the pooling layer circuit of the two-dimensional convolutional neural network module is composed of an array of registers, an accumulator and a divider connected in sequence.

2. A reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multidimensional signals as described in claim 1, wherein, The number of one-dimensional convolutional neural network modules and two-dimensional convolutional neural network modules can be increased or decreased according to the needs of the application field.

3. A reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multidimensional signals as described in claim 1, wherein, The convolutional layer circuit of the one-dimensional convolutional neural network module includes a register file connected to the external memory of the field-programmable gate array. The array consists of a [file], an inverting register connected to the internal memory of the field-programmable gate array (FPGA), a shift circuit connected to the register, a multiplier / accumulator connected to the shift circuit, and state control circuits connected to the register, the shift circuit, and the multiplier / accumulator, respectively. The multiplier / accumulator is also connected to an output function f(·) circuit. The convolutional layer circuit of the two-dimensional convolutional neural network module includes the array [two-dimensional] register connected to the external memory of the FPGA, the rotating register connected to the internal memory of the FPGA, the array shift circuit connected to the register, the multiplier / accumulator connected to the shift circuit, and state control circuits connected to the array register, the array shift circuit, and the multiplier / accumulator, respectively. The multiplier / accumulator is also connected to an output function f(·) circuit.

4. A reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multidimensional signals as described in claim 1, wherein, The circuit architecture of a neuron in the fully connected layer of the one-dimensional convolutional neural network module includes a temporary register connected to the internal memory of the field-programmable gate array, a multiplier / accumulator connected to the temporary register, a temporary register connected to the multiplier / accumulator, an output function f(·) circuit connected to the multiplier / accumulator, and state control circuits connected to the temporary register, the multiplier / accumulator, and the output function f(·) circuit respectively.

5. A reconfigurable circuit chip for a convolutional neural network capable of simultaneously processing multidimensional signals as described in claim 1, wherein, The reconfigurable circuit chip includes a multiplexer circuit for controlling three different output options: the one-dimensional convolutional neural network module identification result output, the two-dimensional convolutional neural network module identification result output, and the integrated identification result output after the multi-dimensional convolutional neural network is integrated.

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