Transistor structure with higher junction breakdown voltage and forming method of the same

Abstract

Transistors with strained source and drain structures are suitable for high-voltage applications. A gate stack is present on the substrate, and the gate stack has a gate dielectric layer and a gate structure. Gate spacers exist on the sidewalls of the gate stack. Two lightly doped drain regions extend from below the gate stack to the opposite side of the gate stack. Multiple strained source and drain structures exist within each lightly doped drain region. The strained source and drain structures do not extend below the gate spacers. The transistor can be used in high-voltage devices and still avoids junction collapse.

Description

Transistor structure with higher junction breakdown voltage Integrated circuits are formed on semiconductor wafers. A lithographic patterning process uses ultraviolet light to transfer the desired mask pattern to a photoresist layer on the semiconductor wafer. An etching process is then used to transfer the pattern to the layer beneath the photoresist. This process is repeated multiple times with different patterns to build up different layers on the wafer substrate and create useful devices. Integrated circuits are made up of numerous transistors. Field-effect transistors typically consist of a substrate, on which a conductive gate electrode controls the current between source and drain electrodes. An insulating gate dielectric layer electrically separates the gate from the source and drain electrodes. A semiconductor layer bridges the source and drain electrodes and contacts the gate dielectric layer. The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature over or on a second feature may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purposes of brevity and clarity and does not itself represent a relationship between the various embodiments and / or configurations discussed. Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. The numerical values ​​in the specification and claims of this application should be understood to include the same numerical values ​​when reduced to the same number of significant digits, as well as numerical values ​​that differ from the stated values ​​by less than the experimental error of routine measurement techniques of the type described in this application to determine the numerical values. All ranges disclosed herein include the recited endpoints. The term "about" can be used to include any value that can vary without changing the basic function of the value. When used in conjunction with a range, "about" also discloses the range defined by the absolute values ​​of the two endpoints, for example, "about 2 to about 4" also discloses a range of "from 2 to 4". The term "about" can include plus or minus 10% of the indicated value. The present disclosure relates to a structure composed of different layers. When the terms "on" or "above" are used to describe two different layers (including a substrate), they simply mean that one layer is on or above another layer. These terms do not limit the two layers to being in direct contact with each other and allow other layers to be located between the two layers. For example, all layers of a structure can be considered to be located "on" a substrate, even if they are not all in direct contact with the substrate. The term "directly" can be used to indicate that two layers are in direct contact without any layers between them. In addition, when it is mentioned that a process step is performed on or above a substrate, depending on the context, it should be interpreted as performing these process steps on any layer that may be present on the substrate. The present disclosure relates to transistor structures with higher source / drain (S / D) junction breakdown voltages, methods for fabricating such transistor structures, and methods for using such structures. Stress / strain techniques are used to increase carrier mobility in the transistor channel and improve device performance. Strain applied parallel to the length and width of the transistor channel is called in-plane strain. Biaxial in-plane tensile strain is known to improve the performance of N-type metal oxide semiconductors (NMOS), while compressive strain applied parallel to the channel length can improve the performance of P-type metal oxide semiconductors (PMOS). However, such stress / strain techniques are not typically used in high-voltage devices because they result in lower junction breakdown voltages, which are particularly undesirable at high voltages (greater than 9 volts). The present disclosure describes structures that can include strain-engineered source / drain regions and still maintain high junction breakdown voltages. Figure 1A is a Y-axis cross-sectional view of a transistor structure 101 according to a first exemplary embodiment of some embodiments of the present disclosure, and Figure 1A illustrates some features. Figure 1B is a plan view close to the upper surface of the substrate in the first exemplary embodiment. Referring to FIG. 1A and FIG. 1B , transistor 101 is formed on substrate 110 . For example, the two isolation regions 114 and 116 shown may be shallow trench isolation (STI) regions or deep trench isolation (DTI) regions. The region between the two isolation regions 114 and 116 is defined as an active region 118 . It is worth noting that isolation regions (not shown) may also be provided along the X-axis, such that the active region is surrounded on all sides. Alternatively, isolation regions 114 and 116 may be considered as one isolation region because they are formed in the same step and are physically connected together. Two lightly doped drain (LDD) regions 120 and 130 are present on the substrate and located on opposite sides of the active region 118. The LDD region 120 extends from the isolation region 114 toward the center of the active region 118, and the LDD region 130 extends from the isolation region 116 toward the center of the active region. The two LDD regions 120 and 130 do not contact each other and are spaced apart from each other. A gate stack 160 is also present on the substrate and within the active region 118. The gate stack 160 includes a gate dielectric layer 140 and a gate structure 150 disposed on the gate dielectric layer 140. The gate stack 160 overlaps the lightly doped drain regions 120 and 130, or in other words, a portion of the gate stack 160 is vertically disposed above each of the lightly doped drain regions 120 and 130. The lightly doped drain regions 120 and 130 can also be described as extending away from the gate stack 160 toward opposite sides of the active region 118. The optional first sealing layer 170 is located above the sidewalls 162 of the gate stack 160 and is oriented vertically. The optional second sealing layer 180 is in contact with the first sealing layer 170 and is also oriented vertically. The gate spacer 190 is in contact with the second sealing layer 180 and is also oriented vertically. The optional first sealing layer 170, the optional second sealing layer 180, and the gate spacer 190 can all be described as being formed above the sidewalls 162 of the gate stack 160. As can be better seen in the plan view of FIG. 1B , the optional first sealing layer 170, the optional second sealing layer 180, and the gate spacer 190 surround the gate stack 160. The optional first sealing layer 170, the optional second sealing layer 180, and the gate spacer 190 are typically composed of a dielectric material. A plurality of source / drain (S / D) trenches 200 are present in each lightly doped drain region 120, 130. Three S / D trenches 200 are depicted in each lightly doped drain region 120, 130. The S / D trenches 200 are spaced apart from one another. Each S / D trench 200 includes a strained source and drain (SSD) structure 210. A cap portion 212 of the SSD structure 210 is positioned above the substrate 110. It is important to note that the SSD structure 210 does not extend below the gate spacer 190. The dotted line indicates the location of the semiconductor channel 230, which is spaced apart from the SSD structure 210. An interlayer dielectric (ILD) region 240 is present above the S / D trenches 200. Generally, the SSD structure 210 is formed by introducing dopants into silicon to increase the distance between atoms and change the lattice structure. This causes strain or stress in the semiconductor channel 230. The dopant concentration in the SSD structure 210 is in a gradient form, with the highest dopant concentration existing along the periphery or wall of the SSD structure 210 and the lowest dopant concentration existing near the center of the SSD structure 210. As shown in the figure, the low dopant concentration area is indicated by the number 214 and the high dopant concentration area is indicated by the number 216. In a specific embodiment, the dopant concentration in the low dopant concentration area can be about 1x10 19 (1E19) to approximately 5x10 20 (5E20) atoms / cc. In high dopant concentration areas, the dopant concentration can be about 5x10 20 (5E20) to approximately 5x10 21 (5E21) atoms / cc. The dopant concentration generally changes smoothly from the periphery to the center. Each lightly doped drain region 120, 130 has a width 125, 135 and a depth 127, 137, respectively. In a specific embodiment, the widths 125, 135 are approximately 200 nm to approximately 1000 nm, respectively. In a specific embodiment, the depths 127, 137 are approximately 50 nm to approximately 300 nm, respectively. Combinations of widths and depths are also contemplated. Other ranges and values ​​for each of these properties are also within the scope of the present disclosure. The gate dielectric layer 140 has a width 145 and a depth 147. In a specific embodiment, the width 145 is from about 300 nm to about 1000 nm. In a specific embodiment, the depth 147 is from about 10 nm to about 30 nm. Combinations of widths and depths are also contemplated. Other ranges and values ​​for each of these properties are also within the scope of the present disclosure. Gate structure 150 has a width 155 and a depth 157. In a specific embodiment, width 155 is from about 300 nm to about 1000 nm. In a specific embodiment, depth 157 is from about 10 nm to about 100 nm. Combinations of widths and depths are also contemplated. Other ranges and values ​​for each of these properties are also within the scope of the present disclosure. First sealing layer 170 has a width 175 and a depth 177. In a specific embodiment, width 175 is from about 10 nm to about 30 nm. In a specific embodiment, depth 177 is from about 30 nm to about 100 nm. Combinations of widths and depths are also contemplated. Other ranges and values ​​for each of these properties are also within the scope of the present disclosure. Second sealing layer 180 has a width 185 and a depth 187. In a specific embodiment, width 185 is from about 10 nm to about 30 nm. In a specific embodiment, depth 187 is from about 30 nm to about 100 nm. Combinations of widths and depths are also contemplated. Other ranges and values ​​for each of these properties are also within the scope of the present disclosure. Gate spacer 190 has a width 195 and a depth 197. In a specific embodiment, width 195 is from about 10 nm to about 30 nm. In a specific embodiment, depth 197 is from about 30 nm to about 100 nm. Combinations of widths and depths are also contemplated. Other ranges and values ​​for each of these properties are also within the scope of the present disclosure. The dimensions of the S / D trenches 200 and the SSD structures 210 can be discussed together. Each SSD structure 210 has a width 215 and a depth 217. In a specific embodiment, the width 215 is from about 10 nm to about 100 nm. In a specific embodiment, the depth 217 is from about 30 nm to about 100 nm. Combinations of widths and depths are also contemplated. Other ranges and values ​​for each of these properties are also within the scope of the present disclosure. Adjacent S / D trenches 200 and SSD structures 210 are separated from each other by a spacing width 232. In a specific embodiment, width 232 is about 10 nm to about 100 nm. Other ranges and values ​​are also within the scope of the present disclosure. FIG2 is a flow chart illustrating a first method 300 for forming a transistor structure according to some embodiments. FIG3 through FIG16 illustrate certain steps of this method. These figures provide different perspectives for better understanding the present disclosure. Although the following method steps are discussed from the perspective of forming a single transistor structure, this discussion should be broadly interpreted as applicable to the simultaneous formation of multiple transistors. FIG3 is a cross-sectional view of substrate 110 on which the transistor will be formed. For example, substrate 110 can be a wafer made of a semiconductor material. The semiconductor material can include silicon, such as crystalline silicon. In alternative embodiments, substrate 110 can be made of other elemental semiconductors, such as germanium, or can include compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, gallium arsenide (InAs), indium phosphide (InP), silicon germanium (SiGe), silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In a specific embodiment, substrate 110 is silicon. Substrate 110 includes an upper surface 112. In step 305 of FIG. 2 and as shown in FIG. 4 , one or more isolation regions are formed in substrate 110 to define an active region 118 of substrate 110. As shown here, two shallow trench isolation (STI) regions 114 and 116 are formed in substrate 110. Active region 118 is located in the region between the two shallow trench isolation regions 114 and 116. As previously mentioned, when considering three-dimensional dimensions, the two shallow trench isolation regions 114 and 116 can be connected to each other and can be considered as one isolation region. The isolation regions 114 and 116 are formed by patterning the substrate, etching trenches, and filling the trenches with dielectric material. The dielectric material in the shallow trench isolation regions 114 and 116 is typically silicon dioxide, but other dielectric materials such as undoped polysilicon, silicon oxide (e.g., SiO 2) Silicon nitride, silicon oxynitride, fluoride-doped silicate glass, or other low-k dielectric materials. Deposition can be accomplished using physical vapor deposition (PVD), chemical vapor deposition (CVD), or spin-on processes known in the art, or grown by oxidation. If desired, the dielectric material can be deposited to a level above the upper surface 112 of the substrate and then recessed back down to the desired height. In step 310 of FIG. 2 and as shown in FIG. 5 , two lightly doped drain (LDD) regions 120 and 130 are formed in the substrate 110 on opposite sides of the active region 118. The LDD regions 120 and 130 reduce the hot carrier effect that can occur in the saturation region of the transistor. As shown here, the first LDD region 120 extends from the shallow trench isolation region 114 to the center or middle of the active region 118. Similarly, the second LDD region 130 extends from the other shallow trench isolation region 116 to the center or middle of the active region 118. However, the two LDD regions 120 and 130 do not contact each other. In other words, there is a gap 234 between the two LDD regions 120 and 130. The lightly doped drain regions 120 and 130 can be made by ion implantation or other suitable methods. In short, in ion implantation, an ion implanter is used to implant atoms into the silicon lattice, thereby modifying the conductivity of the lattice in the implantation location. An ion implanter generally includes an ion source, a beam line, and a process chamber. The ion source produces the required ions. The beam line organizes the ions into a beam with high purity in terms of ion mass, energy, and matter. A mask, such as a patterned photoresist layer or a hard mask layer, is used to expose the required area of ​​the substrate. The semiconductor wafer substrate in the process chamber is then irradiated with an ion beam. The ion beam strikes the exposed area on the wafer substrate, and the ions can be implanted into the substrate at the required depth as dopants. Alternatively, the substrate can be partially etched, followed by a blanket deposition of dopants, and finally an annealing process, during which the dopants react with the exposed silicon underneath. Next, in step 315 of FIG. 2 and as shown in FIG. 6 , a gate dielectric layer 140 is formed on the substrate 110 . Similarly, the gate dielectric layer 140 can be formed using CVD, PVD, atomic layer deposition (ALD), or other suitable deposition processes. Thermal oxidation can also be used to form the gate dielectric layer 140 . Then, in step 320 of FIG. 2 , a dummy gate 168 is formed on the gate dielectric layer 140 . The dummy gate 168 is typically made of polysilicon. The dummy gate 168 can be formed using a suitable process, such as CVD, PVD, ALD, or other deposition techniques. The resulting structure is illustrated in FIG. 6 . The gate dielectric layer 140 and the dummy gate 168 can be collectively referred to as a gate stack 160 . As shown, the gate stack 160 bridges the gap between the two lightly doped drain regions 120 and 130 . In other words, the gate stack 160 overlaps the two lightly doped drain regions 120 and 130 . The gate stack 160 has sidewalls 162 . Next, in optional step 325 of FIG. 2 and as shown in FIG. 7 , a first sealing layer 170 may be optionally formed on the sidewalls 162 of the gate stack 160. The first sealing layer 170 is vertically oriented and has a relatively narrow width. The first sealing layer 170 is made of a dielectric material to electrically isolate the final gate. In certain embodiments, the first sealing layer 170 is silicon nitride (SiN) or silicon dioxide (SiO2). The first sealing layer 170 may be fabricated using CVD, PVD, ALD, or other deposition techniques. Referring now to FIG. 8 , similarly, in optional step 330 of FIG. 2 , a second sealing layer 180 may be selectively formed on the sidewalls 162 of the gate stack 160 and over the first sealing layer 170 . Then, in step 335 of FIG. 2 , a gate spacer 190 is formed on the sidewalls of the gate stack 160 . In certain embodiments, the gate spacer 190 is silicon nitride (SiN) or silicon dioxide (SiO 2 ). The gate spacer 190 may be formed by CVD, PVD, ALD, or other deposition techniques. As shown, the gate spacer 190 is formed over the lightly doped drain regions 120 and 130 . Next, in step 340 of FIG. 2 and as shown in FIG. 9A , a plurality of S / D trenches 200 are etched in each lightly doped drain region 120 , 130 to form source / drain regions 220 . Each S / D trench 200 penetrates the lightly doped drain region 120 , 130 and extends into the substrate 110 . This etching step is typically performed by dry etching and requires an anisotropic etch profile. In a more specific embodiment, the etching gas may be a mixture of HBr / O 2 / H 2 in the desired ratio to achieve the desired trench shape. As shown here, three spaced-apart trenches are formed in each lightly doped drain region 120 , 130 . Of particular note, the S / D trenches 200 do not extend below the gate spacer 190 . Therefore, for the semiconductor channel 230 , the distance 236 between the S / D trenches 200 and the channel 230 can be as little as 10 nanometers, depending on the dimensions of the selective first sealing layer 170 , the selective second sealing layer 180 , and the gate spacer 190 . FIG9B illustrates a set of etched cross-sectional profiles of source / drain trenches that may be formed, depending on the concentration of the secondary etchant in the etching gas. In this regard, trench 200 is formed by removing substrate 110 material. Byproducts of the etching process may form a protective layer on the exposed substrate and within the trench, resulting in a higher etch rate at the bottom of the trench than near the upper surface of the substrate (i.e., near the trench surface covered by the protective layer). The secondary etchant is more selective for the protective layer, thereby removing the protective layer from the trench surface. When the secondary etchant concentration is "low," the resulting trench 200 has a trapezoidal cross-section, wherein the width 205 of the trench 200 at its bottom is greater than the width 207 of the trench 200 at its top. When the secondary etchant concentration is "medium," the resulting trench 200 has substantially vertical sidewalls, such that the width 205 of the trench 200 at its bottom is substantially equal to the width 207 of the trench 200 at its top. When the concentration of the secondary etchant is "high," the resulting trench 200 has a trapezoidal profile, where the width 205 of the trench 200 at its bottom is smaller than the width 207 of the trench 200 at its top. This etch profile can be referred to as a "necking" profile. It is worth noting that the surface at the bottom of the trench 200 can be curved rather than linear. In certain embodiments, the S / D trench 200 has a necking profile. 2 and as shown in FIG10, a strained source and drain (SSD) structure 210 is formed within each S / D trench 200. Again, the SSD structure 210 does not extend below the gate spacer 190. In some embodiments, the SSD structure 210 is formed by an epitaxial process. Examples of such processes include selective epitaxy growth (SEG) processes, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), and some CVD deposition techniques. Typically, gaseous precursors are used that can interact with each other and / or with the substrate 110. Dopants can be introduced during the epitaxial process by introducing dopants. Dopants can include p-type dopants, such as germanium (Ge) or boron (B); or n-type dopants, such as phosphorus (P) or arsenic (As). Alternatively, an ion implantation process can be used to dope the SSD structure 210. The SSD structure 210 can be grown on the surface of the S / D trench 200, ultimately filling the trench and also forming a cap portion 212. As previously described, the dopant concentration can increase from the periphery / walls 211 of the SSD structure 210 toward the center 213 of the SSD structure 210. In other words, the dopant concentration increases with distance from the trench walls. The lower dopant concentration adjacent to the undoped silicon substrate helps lower the Schottky barrier. The higher dopant concentration near the center of the SSD structure 210 can reduce the source / drain contact resistance. The dopant concentration can be varied by changing the ratio of gaseous precursors. In some specific embodiments, the SSD structure 210 is formed from SiP (for NMOS) or silicon germanium (for PMOS). In some embodiments, an annealing process can be performed to activate the dopants in the SSD structure 210. Thus, the semiconductor channel 230 is strained or stressed to increase carrier mobility within the channel. As discussed in step 350 of FIG. 2 and as discussed in FIG. 11 , an interlayer dielectric (ILD) material may be applied over the source / drain regions 220 to form ILD regions 240. The ILD regions 240 electrically isolate the source / drain regions 220 from the final gate structure or electrode. The ILD regions 240 may be formed of any dielectric material and need not be a high-k dielectric material. The ILD material may be deposited using any suitable method, such as CVD. Continuing, in step 355 of FIG. 2 and as shown in FIG. 12 , the dummy gate 168 is removed to form a gate portion 169 . This can be accomplished by etching or other suitable processes. Then, in step 360 of FIG. 2 , a conductive gate material is deposited to fill the gate portion 169 and form the gate structure 150 . Suitable gate materials may include, for example, metals such as W, titanium nitride, TiAl, Pt, Co, Rh, Pd, Ti, Ta, and the like, or doped polysilicon. The resulting structure is illustrated in FIG. 1A and FIG. 1B , discussed above. Further processing may be performed to encapsulate the transistor. For example, in step 365 of FIG. 2 and as shown in FIG. 13 , a first insulating layer 250 is formed over the active region 118 including the source / drain regions 220 and the gate structure 150. This layer may be formed using a deposition process such as PVD, CVD, sub-atmospheric pressure chemical vapor deposition, or other suitable deposition process. The material of the first insulating layer 250 may be silicon or another suitable dielectric material (e.g., silicon dioxide). Then, in step 370 of FIG. 2 and as shown in FIG. 14 , an etch is performed to form openings that penetrate the first insulating layer 250 and the ILD region 240 and extend to the SSD structure 210 and the gate structure 150 in the source / drain region 220. In step 375, the openings are then filled with a conductive material to form source / drain vias 256 and gate vias 258. Note that, as shown here, the vias 256 are formed in each of the SSD structures 210. The vias 256, 258 themselves may be sufficient to serve as electrodes (i.e., source, drain, and gate) for further processing steps. These steps may be repeated if a larger contact footprint is desired. For example, in step 380 of FIG. 2 and as shown in FIG. 15A , a second insulating layer 260 is formed on the first insulating layer 250 and over the active region 118 including the source / drain regions 220 and the gate structure 150. Then, in step 385 of FIG. 2 , an etching step is performed to form openings through the second insulating layer 260 and extending to the vias 256 and 258 in the first insulating layer 250. In step 390 , the openings are then filled with a conductive material to form source / drain pads 266 and gate pads 268. Note that, as shown, the S / D pads 266 contact the vias 256 and the SSD structures 210, electrically connecting the SSD structures in each lightly doped drain region. In this embodiment, the source / drain electrodes 272 are formed by the combination of the S / D vias 256 and the S / D pads 266. The gate electrode 274 is formed by the combination of the gate vias 258 and the gate pads 268. FIG15B is a perspective view of another embodiment of a packaged transistor 102. In this embodiment, only the first insulating layer 250 is applied. Source / drain vias 256 are formed through the ILD region 240. S / D pads 272 are then formed in the first insulating layer 250 to connect the S / D vias together and form source / drain electrodes 272. Gate electrodes 274 are also formed in the first insulating layer 250. 16 is a perspective view of another embodiment of the packaged transistor 103. It should be noted that the gate electrode 274 can be separated from the source / drain electrodes 272 in the direction of the X-axis. The transistors and methods disclosed herein include several different dielectric structures. Such dielectric structures can generally be made of any suitable combination of dielectric materials, although the properties of any particular layer may be further defined. Examples of dielectric materials may include silicon dioxide (SiO 2) Silicon nitride (Si 3N 4) Silicon carbide (SiC), Hafnium dioxide (HfO 2) Zirconium dioxide (ZrO 2) Alumina (Al 2O 3) Silicon oxynitride (SiO x N y ), Hafnium Oxynitride (HfO x N y ) or zirconium oxynitride (ZrO x N y )), or hafnium silicate (ZrSi x O y ) or zirconium silicate (ZrSi x O y ) or silicon carbonitride (SiC x O y N z ), or hexagonal boron nitride (hBN). Other dielectric materials may include tantalum oxide (Ta 2O 5) Nitrides such as silicon nitride, polysilicon, phosphorus silicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-pressure undoped silicate glass (HSUSG), and borosilicate glass (BSG). It should also be noted that certain conventional steps are not explicitly described in the above discussion. For example, a pattern / structure may be formed in a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching. Typically, the photoresist layer can be applied by methods such as spin coating, spraying, roller coating, dip coating, or extrusion coating. Typically, during spin coating, the substrate is placed on a rotating platform that may include a vacuum chuck to hold the plate-shaped substrate. The photoresist composition is then applied to the center of the substrate. The speed of the rotating platform is then increased to evenly distribute the photoresist from the center of the substrate to the periphery of the substrate. The platform's rotational speed is then fixed to control the thickness of the final photoresist layer. Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking is performed at a temperature of about 90°C to about 110°C. Baking can be performed using a hot plate, an oven, or similar equipment. Thus, a photoresist layer is formed on the substrate. The photoresist layer is then patterned by exposing it to radiation. The radiation can be any wavelength of light that carries the desired mask pattern. In a particular embodiment, EUV light with a wavelength of approximately 13.5 nanometers is used for patterning because it allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to the radiation and some portions not being exposed. This exposure can cause some portions of the photoresist to become soluble in the developer, while other portions of the photoresist become insoluble in the developer. After exposure to radiation, an additional resist bake step (i.e., a post-exposure bake, PEB) can be performed. This can, for example, help release acid leaving groups (ALGs) or other molecules of interest in chemical amplification photoresists. The photoresist layer is then developed using a developer. The developer can be an aqueous or organic solution. The soluble portion of the photoresist layer dissolves and washes away during the development step, leaving behind the photoresist pattern. A common example of a developer is aqueous tetramethylammonium hydroxide (TMAH). In general, any suitable developer can be used. Sometimes, a post-development bake or "hard bake" is performed to stabilize the developed photoresist pattern for optimal performance in subsequent steps. Continuing, portions of the layer below the patterned photoresist layer are exposed. Etching transfers the photoresist pattern to the layer below the patterned photoresist layer. After use, the patterned photoresist layer can be removed using, for example, various solvents, such as N-methyl-pyrrolidone (NMP) or alkaline media or other strippers at elevated temperatures, or by dry etching using oxygen plasma. In general, any etching step described herein may be performed using a wet etch, dry etch, or plasma etch process, such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or a combination thereof, as appropriate. The etch may be anisotropic. Depending on the material, the etchant may include carbon tetrafluoride (CF 4) Hexafluoroethane (C 2F 6) Octafluoropropane (C 3F 8) Trifluoromethane (CHF 3) Difluoromethane (CH 2F 2) Fluoromethane (CH 3F), fluorocarbons, nitrogen (N 2) Hydrogen (H 2) Oxygen (O 2) Argon (Ar), Xenon (Xe), Xenon difluoride (XeF 2), helium (He), carbon monoxide (CO), carbon dioxide (CO 2) Fluorine (F 2) Chlorine (Cl 2), hydrobromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF 3) Sulfur hexafluoride (SF 6) Boron trichloride (BCl 3) Ammonia (NH 3) Bromine (Br 2) Nitrogen trifluoride (NF 3), or the like or combinations of various ratios of the foregoing materials. For example, silicon dioxide can be wet etched using hydrofluoric acid and ammonium fluoride. Alternatively, CHF 3. O 2. CF 4 and / or H 2 various mixtures to etch silicon dioxide. For example, a chemical mechanical polishing (CMP) process can be used to planarize a surface. Typically, CMP is performed using a rotating platform with an attached polishing pad. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pad or wafer substrate. During polishing, both the polishing pad and the carrier rotate, which causes mechanical and chemical effects on the surface of the wafer substrate and / or its top layer, removing unwanted material and creating a highly flat surface. A post-CMP cleaning step is then performed using a rotating scrubber and a cleaning fluid to clean one or both sides of the wafer substrate. Some deviations in the transistor structure can be taken into account. Figure 17 is a Y-axis cross-sectional view of transistor 104 in another embodiment. In this embodiment, the gate dielectric layer 140 is formed in a recess in the substrate, or in other words, the gate dielectric layer 140 exists below the upper surface 112 of the substrate 110. The gate dielectric layer 140 fills the recess. Figure 18 is a Y-axis cross-sectional view of transistor 105 in another embodiment. Here, both the gate dielectric layer 140 and the gate structure 150 extend into the recess in the substrate 110. The gate dielectric layer 140 can be considered to cover the surface of the recess. This can help to better control the thickness of the gate dielectric layer 140 and avoid impact on the bottommost interconnect layer (M1). FIG19 is a perspective view of another transistor according to some embodiments of the present disclosure. Here, transistor 106 is a three-dimensional FinFET structure, in which fin 280 is higher than substrate 110. FIG20 is a Y-axis cross-sectional view taken along line AA in FIG19 , and FIG21 is a Y-axis cross-sectional view taken along line BB in FIG19 . Referring first to Figures 19 and 20 , the gate dielectric layer 140 and the gate structure 150 form a gate stack 160, which exists on three sides of the fin 280. The lightly doped drain regions 120 and 130 are visible. Here, the source / drain regions 220 are depicted as part of the fin, although they can also be separate structures connected to multiple ends of multiple fins. The first and second sealing layers 170 and 180 and the gate spacers 190 electrically isolate the SSD structure 210 from the gate stack 160. As shown in Figures 19 and 21 , the SSD structure 210 extends into the source / drain regions 220 and through the lightly doped drain region 120. The top cap portion 212 of the SSD structure 210 is located above the upper surface 282 of the fin. FIG. 22 is a flow chart of a method 400 for forming the FinFET structure of FIG. 19 - FIG. 21 , according to some embodiments. Initially, in step 402, the substrate 110 is shaped to form one or more fins 280. Typically, one or more hard mask layers are applied to the substrate. Mandrels are then formed on the hard mask layer above the substrate. A mandrel pattern can be formed by depositing a mandrel material layer, forming a photoresist layer on the mandrel material layer, exposing the photoresist to radiation, and developing the photoresist layer, and then etching the mandrel material layer to form the mandrels. If desired, the mandrels are then used as a mask, and etching is performed through the hard mask layer and into the substrate to form multiple fins. Alternatively, in a process called self-aligned double patterning (SADP), spacers are formed on the sidewalls of the mandrels, and the mandrels are then removed. The spacers are then used as a mask, and etching is performed through the hard mask layer and into the substrate to form multiple fins. Self-aligned quadruple patterning (SAQP) is a similar process that can also be used to form multiple fins. Many of the following steps are similar to those in the method of FIG. 2 , with appropriate modifications for FinFETs. In step 405 , a plurality of isolation regions, such as STI regions, are formed between adjacent fins to define an active region. In step 410 , two lightly doped drain (LDD) regions are formed on opposite sides of the active region 118 . In step 415 , a gate dielectric layer 140 is formed on three sides of the fin. Similarly, the gate dielectric layer overlaps the two lightly doped drain regions. In step 420 , a dummy gate 168 is formed on the gate dielectric layer 140 to form a gate stack 160 . The dummy gate also overlaps the two lightly doped drain regions. In optional steps 425 and 430 , a first sealing layer 170 and a second sealing layer 180 may be formed on the sidewalls of the gate stack 160 . In step 435 , gate spacers 190 are formed on the sidewalls of the gate stack. The gate spacers are also located above the lightly doped drain regions. In step 440, multiple S / D trenches are etched in each of the lightly doped drain regions to form source / drain regions 450. In step 445, an SSD structure is formed in each of the S / D trenches. In step 450, multiple ILD regions are formed above the source / drain regions (note that this step is not shown in Figures 19 to 21). In step 455, the dummy gate is removed to form a gate portion. In step 460, a conductive gate material is deposited to fill the gate portion and form the gate structure 150 in the form of a gate layer. The resulting structure is shown in Figures 19 to 21, which does not have an ILD region. Process steps 365 to 390 of Figure 2 can also be performed to package the FinFET. The combination of a lightly doped drain region and an SSD structure increases the S / D junction breakdown voltage and also allows for a relatively uniform electric field at the transistor's surface. This achieves the same result as a reduced surface field (RESURF) structure, in which a PN junction is constructed beneath the drain in the transistor, allowing the depletion layer extending from the PN junction to reach the device surface, but without requiring additional processing steps. Furthermore, the dopant concentration in the SSD structure can be increased to reduce the surface electric field without reducing the S / D junction breakdown voltage. The transistors disclosed herein can be used in high-voltage, medium-voltage, and low-voltage devices on a chip. High-voltage devices typically operate in a voltage range of approximately 12V to approximately 28V. Medium-voltage devices typically operate in a voltage range of approximately 3V to approximately 9V. Low-voltage devices typically operate at voltages below 1V. Additional processing steps may be performed to produce semiconductor devices or integrated circuits having additional structures. Examples of such steps may include ion implantation, deposition of other materials, etching, etc. Semiconductor devices can be used in a variety of applications, such as bipolar-CMOS-DMOS (BCD) circuits for driving discrete high-voltage components; drivers for LCD, OLED, AMOLED, or QLED display panels; image sensors for mobile phones, facial recognition systems, or motion sensors for automotive applications, security applications, energy efficiency, etc.; power management devices that control the flow and direction of power; and / or image signal processors (ISPs). Therefore, some embodiments of the present disclosure relate to a method for forming a transistor. A plurality of lightly doped drain (LDD) regions are formed in a substrate and on opposite sides of an active region. A gate stack is formed on the substrate overlapping the lightly doped drain regions. The gate stack includes a gate dielectric layer and a dummy gate located above the gate dielectric layer. A gate spacer is formed on the sidewalls of the gate stack on the lightly doped drain regions. A plurality of source / drain trenches are etched in each lightly doped drain region to form a plurality of source / drain regions. A strained source and drain (SSD) structure is formed in each source / drain trench. The SSD structure does not extend below the gate spacer. Other embodiments disclosed herein relate to a transistor comprising a substrate, a gate stack, a lightly doped drain region, a gate spacer, and an SSD structure. The gate stack is located on the substrate and includes a gate dielectric layer and a gate structure located above the gate dielectric layer. A first lightly doped drain (LDD) region and a second lightly doped drain region extend from below the gate stack to opposite sides of the gate stack. The gate spacer is located on the sidewalls of the gate stack and is located on the first lightly doped drain region and the second lightly doped drain region. A plurality of strained source and drain (SSD) structures are present in each lightly doped drain region, wherein the SSD structure does not extend below the gate spacer. Some other embodiments disclosed herein relate to a transistor including a substrate. The substrate includes a fin extending between two source / drain regions. A gate dielectric layer is present on at least three sides of the fin between the two source / drain regions. A gate layer is located above the gate dielectric layer. Gate spacers are present on sidewalls of the gate layer; a lightly doped drain (LDD) region extends from each source / drain region to below the gate dielectric layer. A plurality of strained source and drain (SSD) structures are present in each lightly doped drain region, wherein the SSD structures do not extend below the gate spacers. The present disclosure also discloses a semiconductor device including one or more transistors having the above structure. For example, the transistors can be packaged with the aforementioned ILD region, the insulating layer, and the electrodes extending through the insulating layer. The methods, systems, and components of the present disclosure will be further described in the following non-limiting examples. It should be understood that these are for illustration only, and the present disclosure is not intended to be limited to the described materials, conditions, process parameters, and the like. example: Transistors according to the present disclosure were tested at three different temperatures (-40°C, 25°C, and 125°C). Figure 23 shows the relationship between drain leakage current and drain voltage under the three temperature conditions. As shown, the leakage current does not increase significantly until the drain voltage exceeds 8V. The above overview of features and embodiments is intended to enable those skilled in the art to better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure. 101: transistor structure 102, 103: packaged transistor 104, 105, 106: transistor 110: substrate 112, 282: upper surface 114, 116: isolation region 118: active region 120, 130, 240: region 125, 135, 145, 155, 175, 185, 195, 205, 207, 215, 232: width 127, 13 7, 147, 157, 177, 187, 197, 217: Depth 140: Gate dielectric layer 150: Gate structure 160: Gate stack 162: Sidewall 168: Dummy gate 169: Gate portion 170: First sealing layer 180: Second sealing layer 190: Gate spacer 200: Trench 210: Structure 211: Periphery / wall 212: Top cover 213: Center 2 14: Low dopant concentration portion 216: High dopant concentration portion 220, 450: Source / drain region 230: Semiconductor channel 234: Gap 236: Distance 250: First insulating layer 256: Via 258: Gate via 260: Second insulating layer 266: Source / drain pad 268: Gate pad 272: Source / drain electrode 274: Gate electrode 280: Fin 300, 400: Methods 305, 310, 315, 320, 335, 340, 345, 350, 355, 360, 365, 370, 375, 380, 385, 390, 402, 405, 410, 415, 420, 425, 430, 435, 440, 445, 455, 460: Steps 325, 330: Optional Steps AA, BB: Sectioning Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1A is a Y-axis cross-sectional view showing a transistor structure according to a first exemplary embodiment of some embodiments of the present disclosure. FIG. 1B is a plan view of the first exemplary embodiment. Figure 2 is a flow chart illustrating a method for forming a transistor structure according to some embodiments. Figures 3 to 16 illustrate various steps of the method. FIG. 3 is a Y-axis cross-sectional view of the substrate before the method of FIG. 2 begins. 4 is a Y-axis cross-sectional view of the substrate after forming one or more isolation regions to define an active region. 5 is a Y-axis cross-sectional view of the substrate after forming a light-doped drain (LDD) region on opposite sides of the active region. 6 is a Y-axis cross-sectional view of the substrate after forming a gate stack including a gate dielectric layer and a dummy gate. The gate stack overlaps with two lightly doped drain regions. FIG. 7 is a Y-axis cross-sectional view of the substrate after a sealing layer is formed on the sidewalls of the gate stack. FIG8 is a Y-axis cross-sectional view of the substrate after forming two sealing layers and gate spacers on the sidewalls of the gate stack. 9A is a Y-axis cross-sectional view of the substrate after etching a plurality of source / drain recesses or trenches into each of the exposed lightly doped drain (LDD) regions on both sides of the gate stack. FIG. 9B illustrates a set of etch profiles of source / drain trenches that may be formed, depending on the concentration of the retardant present in the etching gas. FIG. 10 is a Y-axis cross-sectional view of the substrate after epitaxial growth is performed in the source / drain recesses to obtain a strained source and drain (SSD) structure. FIG. 11 is a Y-axis cross-sectional view of the substrate after forming an interlayer dielectric (ILD) on the source / drain regions. FIG12 is a Y-axis cross-sectional view of the substrate after the dummy gate is removed. FIG13 is a Y-axis cross-sectional view of the substrate after applying a first insulating layer on the transistor. FIG. 14 is a Y-axis cross-sectional view of the substrate after forming a through hole passing through the first insulating layer and extending to the gate structure and the SSD structure. 15A is a Y-axis cross-sectional view of the substrate after applying a second insulating layer on the first insulating layer and forming pads in the second insulating layer to form source electrodes, drain electrodes, and gate electrodes to form a transistor package. 15B is a Y-axis cross-sectional view of a transistor package according to another embodiment of the present disclosure, wherein only one insulating layer is provided. 16 is a perspective view of another embodiment of a transistor package showing that the gate is offset from the source and drain electrodes along the X-axis. FIG17 is a Y-axis cross-sectional view of a transistor according to another embodiment of the present disclosure, wherein the gate dielectric layer is formed in a recess of the substrate. FIG18 is a Y-axis cross-sectional view of a transistor according to another embodiment of the present disclosure, wherein the gate dielectric layer and the gate structure extend into a recess in the substrate. FIG19 is a perspective view of a transistor according to another embodiment of the present disclosure, wherein the transistor is in the form of a FinFET having a three-dimensional structure. FIG20 is a Y-axis cross-sectional view of the gate stack structure taken along line AA in FIG19 . FIG. 21 is a Y-axis cross-sectional view of the SSD structure depicted along the section line BB in FIG. 19 . FIG. 22 is a flow chart of a method for forming the FinFET structure of FIG. 19 through FIG. 21 , according to some embodiments. Figure 23 is a graph showing the relationship between drain leakage current and drain voltage. The y-axis is logarithmic, while the x-axis is linear. 101: Transistor Structure 110: Base 114, 116: Isolation Area 118: Active Zone 120, 130: District 125, 135, 145: Width 127, 137, 147, 157, 177, 187, 197, 217: Depth 140: Gate dielectric layer 150: Gate structure 160: Gate stack 162: Sidewall 170: first sealing layer 180: Second sealing layer 190: Gate spacer 200: Ditch 210:Structure 212: Top cover 214: Low dopant concentration area 216: High dopant concentration area 230:Semiconductor Channel 240: District

Claims

1. A method for forming a transistor, comprising: Lightly doped drain regions are formed in the substrate and on the opposite side of the active region; A gate stack is formed on the substrate, the gate dielectric layer overlapping the lightly doped drain region, the gate stack including the gate dielectric layer and a dummy gate located on the gate dielectric layer; a gate spacer is formed on the sidewall of the gate stack above the lightly doped drain region; multiple source / drain trenches are etched in each lightly doped drain region to form multiple source / drain regions; And forming strain source and drain structures in each source / drain channel, wherein the strain source and drain structures do not extend below the gate gap wall.

2. The method as claimed in claim 1, wherein each strain source and drain structure has a dopant gradient concentration that increases from the periphery of the strain source and drain structure to the center.

3. The method as described in claim 1, wherein each source / drain trench has a trapezoidal profile and a smaller width at the bottom of each source / drain trench.

4. The method as described in claim 1, further comprising: Before forming the lightly doped drain region, an isolation region is formed in the substrate to define the active region.

5. The method as described in claim 1, further comprising: Before forming the gate gap wall, at least one sealing layer is formed on the sidewall of the gate stack.

6. The method as described in claim 1, further comprising, after forming the strain source and drain structures: Remove the dummy gate to form the gate portion; Deposit gate material in the gate portion to form a gate structure; An intermediate dielectric material is applied to the source / drain region; A first insulating layer is formed on the active region; a plurality of openings are etched through the first insulating layer to the source / drain region and the gate structure; and the plurality of openings are filled with a conductive material to form at least one source via, at least one drain via and a gate via.

7. A transistor, comprising: Base; A gate stack is located on the substrate, the gate stack includes a gate dielectric layer and a gate structure located on the gate dielectric layer; A first lightly doped drain region and a second lightly doped drain region, the first lightly doped drain region and the second lightly doped drain region extending from the bottom of the gate stack toward the opposite side of the gate stack; a gate gap wall, located on the sidewall of the gate stack above the first lightly doped drain region and the second lightly doped drain region. And strain source and drain structures, passing through the first lightly doped drain region and the second lightly doped drain region, wherein the strain source and drain structures do not extend below the gate gap wall.

8. The transistor of claim 7, wherein the strain source and drain structures are in the form of trenches, wherein the width at the bottom of the trench is less than the width at the top of the trench.

9. The transistor as claimed in claim 7, wherein each strain source and drain structure has a dopant gradient concentration increasing from the periphery of the strain source and drain structure toward the center of the strain source and drain structure.

10. A transistor, comprising: The substrate includes multiple fins extending between the two source / drain regions; A gate dielectric layer is located on at least three sides of the fin between the two source / drain regions; a gate layer is located above the gate dielectric layer; a gate spacer is located on the sidewall of the gate layer; a lightly doped drain region extends from each source / drain region to below the gate dielectric layer; and strained source and drain structures extend into the two source / drain regions and through the lightly doped drain region, wherein the strained source and drain structures do not extend below the gate spacer.

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