Manufacturing method of printed circuit board

Abstract

This invention provides a method for manufacturing a printed circuit board (PCB) that more effectively suppresses pattern defects and also exhibits excellent high-frequency characteristics. The method includes the following steps: preparing an insulating substrate with a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer with a thickness of less than 1.0 μm, wherein the electroless plating layer has a peak density Sds of 0.90 μm. -2 and above 1.30 μm The value is below -2 and the peak curvature Ssc is 1.00 μm. -1 or higher 4.00 μm A surface below -1; a photoresist layer is applied to the surface of the electroless plating layer; the photoresist is exposed and developed to form a photoresist pattern; the electroless plating layer is electroplated through the photoresist pattern; the photoresist pattern is peeled off; and the useless parts of the electroless plating layer exposed by the peeling off of the photoresist pattern are removed by etching to form a wiring pattern.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a printed circuit board. Prior Art

[0002] In recent years, with the miniaturization and high density required for printed circuit boards, there has been a need for miniaturized circuits (finer pitch). The semi-additive process (SAP) is widely used as a manufacturing process for printed circuit boards suitable for miniaturized circuits. The SAP method is suitable for forming extremely fine circuits. As one example, it is performed using a roughened copper foil with a carrier. For example, as shown in Figures 8 and 9, a prepreg 112 and a primer 113 are used to press the roughened copper foil 110 onto an insulating resin substrate 111 having a lower layer circuit 111b on a base substrate 111a (step (a)). After the carrier (not shown) is peeled off, a guide hole 114 is formed by laser drilling as needed (step (b)). The roughened copper foil 110 is then removed by etching, exposing the primer 113 with a roughened surface profile (step (c)). After electroless copper plating 115 is applied to the roughened surface (step (d)), masking is performed in a predetermined pattern by exposing and developing a dry film 116 (step (e)), and electrolytic copper plating 117 is performed (step (f)). After dry film 116 is removed to form wiring portions 117a (step (g)), unnecessary electroless copper plating 115 between adjacent wiring portions 117a is removed by etching (step (h)), resulting in wiring 118 formed in a predetermined pattern.

[0003] In the SAP method using this type of roughened copper foil, the roughened copper foil itself is removed by etching after laser drilling (step (c)). Furthermore, the roughened copper foil's roughened surface is transferred to the laminate surface after the roughened copper foil is removed. This ensures the adhesion between the insulating layer (e.g., primer layer 113, or prepreg 112 if primer layer 113 is absent) and the plated circuit (e.g., wiring 118) in subsequent steps. However, the surface profile that is most suitable for improving adhesion to the plated circuit tends to be rough and uneven, which reduces the etching resistance of the electroless copper plating in step (h). In other words, the more the electroless copper plating is encroached into the roughened surface, the more etching is required to remove the residual copper.

[0004] Therefore, a method has been disclosed that reduces the size of roughened particles and gives them a constricted shape, thereby ensuring the required adhesion of plated circuits and achieving good etching properties when used in the SAP method. For example, Patent Document 1 (International Publication No. 2016 / 158775) discloses a roughened copper foil having a roughened surface on at least one side, wherein the roughened surface has a plurality of generally spherical protrusions composed of copper particles, and the average height of the generally spherical protrusions is 2.60 μm or less. Furthermore, Patent Document 2 (International Publication No. 2018 / 211951) discloses a low-roughness roughened copper foil having a roughened surface on at least one side, wherein the roughened surface comprises primary roughened particles with constricted portions and secondary roughened particles on the surfaces of the primary roughened particles, and the ten-point average roughness Rz of the roughened surface is 1.7 μm or less.

[0005] Furthermore, in order to make the circuit more miniaturized, it is conceivable to use a copper foil with a smooth surface and smaller roughened particles in the SAP method, and to perform electroless plating relatively thinly to form the circuit. However, in the circuit formed in this way, problems such as short circuits or pattern defects such as protrusions may occur. A method for manufacturing a printed circuit board that addresses this problem has been disclosed. For example, Patent Document 3 (International Publication No. 2020 / 196105) discloses a method for manufacturing a printed circuit board, which includes the following steps: performing electroless plating on an insulating substrate having a roughened surface to form an electroless plating layer with a thickness of less than 1.0 μm, which has a surface with an arithmetic mean undulation Wa of not less than 0.10 μm and not more than 0.25 μm and a peak value Sku of not less than 2.0 and not more than 3.5. Furthermore, Patent Document 4 (International Publication No. 2020 / 196106) discloses an electroless plating layer that forms a surface having an arithmetic mean waviness Wa of 0.10 μm to 0.25 μm, and a concave void volume Vvv of 0.010 μm³ / μm² to 0.028 μm³ / μm². The methods disclosed in Patent Documents 3 and 4 enable the production of printed circuit boards that effectively suppress pattern defects and exhibit excellent fine circuit formability. [Prior Art Literature] [Patent Document]

[0006] [Patent Document 1] International Publication No. 2016 / 158775 [Patent Document 2] International Publication No. 2018 / 211951 [Patent Document 3] International Publication No. 2020 / 196105 [Patent Document 4] International Publication No. 2020 / 196106 Summary of the Invention

[0007] When manufacturing printed circuit boards using the methods disclosed in Patent Documents 3 and 4, the problem of pattern defects can be eliminated to a certain extent. However, further reduction of pattern defects is desired. Furthermore, with the recent advancement in the functionality of portable electronic devices, the need for higher signal frequencies to process large amounts of information at high speeds has led to a demand for printed circuit boards suitable for high-frequency applications such as 5G (fifth generation mobile communication technology), millimeter waves, and base station antennas. However, achieving both reduced pattern defects and excellent high-frequency characteristics is not easy.

[0008] The present inventors have come to the following conclusion: by performing electroless plating on an insulating substrate having a roughened surface to form an electroless plated layer having a surface with a peak density Sds and a peak curvature Ssc controlled within predetermined ranges, it is possible to manufacture a printed circuit board that more effectively suppresses pattern defects and also has excellent high-frequency characteristics.

[0009] Therefore, an object of the present invention is to provide a method for manufacturing a printed circuit board that more effectively suppresses pattern defects and has excellent high-frequency characteristics.

[0010] According to the present invention, the following aspects are provided. [Aspect 1] A method for manufacturing a printed circuit board comprises the following steps: (a) Preparing an insulating substrate with a roughened surface; (b) performing electroless plating on the roughened surface of the insulating substrate to form an electroless plated layer having a thickness of 1.0 μm or less, the electroless plated layer having a peak density Sds of 0.90 μm −2 or more and 1.30 μm −2 or less as measured in accordance with EUR 15178N and a peak curvature Ssc of 1.00 μm −1 or more and 4.00 μm −1 or less as measured in accordance with EUR 15178N; (c) laminating a photoresist on the surface of the electroless plating layer; (d) exposing and developing the photoresist to form a photoresist pattern; (e) electroplating the electroless plating layer through the photoresist pattern; (f) peeling off the photoresist pattern; and (g) removing the useless portion of the electroless plating layer exposed by peeling off the photoresist pattern by etching to form a wiring pattern. [Aspect 2] The method for manufacturing a printed circuit board as described in aspect 1, wherein the surface of the electroless plating layer has an interface development area ratio Sdr of 5.00% or more and 10.00% or less as measured in accordance with EUR 15178N. [Aspect 3] In the method for manufacturing a printed circuit board as described in aspect 1 or 2, the peak curvature Ssc of the surface of the electroless plating layer is not less than 2.30 μm −1 and not more than 3.50 μm −1 . [Aspect 4] The method for manufacturing a printed circuit board according to any one of aspects 1 to 3, wherein the step (a) comprises: (a-1) preparing a surface-treated copper foil having a treated surface having a peak density Sds of 1.00 μm −2 or more and 1.50 μm −2 or less as measured in accordance with EUR 15178N, a peak curvature Ssc of 4.00 μm −1 or more and 6.00 μm −1 or less as measured in accordance with EUR 15178N, and an interface developed area ratio Sdr of 20.00% or more and 40.00% or less as measured in accordance with EUR 15178N, (a-2) laminating an insulating substrate on the treated surface of the surface-treated copper foil, and transferring the surface shape of the treated surface to the surface of the insulating substrate, and then, (a-3) The surface-treated copper foil is removed by etching to obtain an insulating substrate having the roughened surface. [Aspect 5] The method for manufacturing a printed circuit board as described in any one of aspects 1 to 4, wherein the thickness of the electroless plating layer is not less than 0.3 μm and not more than 1.0 μm. [Aspect 6] In the method for manufacturing a printed circuit board as described in any one of aspects 1 to 5, the photoresist comprises a dry film photoresist. [Aspect 7] In the method for manufacturing a printed circuit board as described in aspect 6, the thickness of the dry film photoresist is not less than 2 μm and not more than 35 μm. [Aspect 8] The method for manufacturing a printed circuit board as described in any one of aspects 1 to 7, wherein the thickness of the wiring pattern is not less than 2 μm and not more than 30 μm. Simple diagram description

[0011] FIG1 is a flow chart showing the first half of the steps (steps (a) to (c)) in one example of the manufacturing method of the present invention. FIG2 is a flow chart showing the second half of the steps (steps (d) to (g)) in one example of the manufacturing method of the present invention. 3(a-1) to (a-3) are flowcharts showing an example of a procedure for preparing an insulating substrate having a roughened surface. 4(i) to (iv) are diagrams for explaining the influence of surface foreign matter during exposure and development when the surface after electroless plating does not have a sufficient concavo-convex shape. 5(i) to (iv) are diagrams for explaining the influence of surface foreign matter during exposure and development when the surface after electroless plating has a sufficient concavo-convex shape. Figures 6 (i) and (ii) are diagrams used to illustrate the order of evaluating the number of dirt detections in the embodiment. FIG7A is a diagram for explaining the peak density Sds measured according to EUR15178N, and is a diagram showing an example of a surface and a peak when Sds = 5 μm −2 . FIG7B is a diagram for explaining the peak density Sds measured according to EUR15178N, and is a diagram showing an example of a surface and a peak when Sds = 1 μm −2 . FIG8 is a flowchart illustrating the steps of the SAP method, and is a diagram showing the first half of the steps (steps (a) to (d)). FIG9 is a flowchart illustrating the steps of the SAP method, and is a diagram showing the second half of the steps (steps (e) to (h)). Implementation Method

[0012] [definition] [] The following are definitions of parameters used to specify the present invention.

[0013] In this specification, "peak density Sds" or "Sds" is a parameter indicating the number of peaks per unit area, measured according to EUR 15178N. As shown in Figures 7A and 7B , in the calculation of Sds, a point that is higher than eight adjacent points N is considered a peak S. A larger value indicates a denser presence of protrusions (see Figure 7A ). On the other hand, a smaller value indicates a sparser presence of protrusions (see Figure 7B ).

[0014] In this specification, "peak curvature Ssc" or "Ssc" is a parameter that represents the average value of the principal curvature at the peak point of the surface, measured according to EUR15178N. The smaller the value, the more rounded the point of contact with other objects. On the other hand, the larger the value, the sharper the point of contact with other objects. Furthermore, the parameters measured in ISO25178 only consider the obvious peaks remaining after segmentation and discrimination. In contrast, the parameters specified in EUR15178N do not distinguish between local peaks and obvious peaks for detection. Therefore, when the surface shape is the same, the value of Ssc specified in EUR15178N is greater than the value of Spc (Spc) specified in ISO25178. <Ssc)。

[0015] In this specification, "interface development ratio Sdr" or "Sdr" is a parameter measured in accordance with EUR 15178N that indicates the increase in the development area (surface area) of a defined region relative to the area of ​​the defined region. In this specification, the interface development ratio Sdr is expressed as the increase in surface area (%). A smaller value indicates a more flat surface; a completely flat surface has an Sdr of 0%. On the other hand, a larger value indicates a more uneven surface. For example, if the Sdr of a surface is 10%, it means that the surface area of ​​that surface has increased by 10% compared to a completely flat surface.

[0016] Sds, Ssc, and Sdr can be calculated by measuring the surface profile of a specified measurement area (e.g., a two-dimensional area of ​​64.397 μm x 64.463 μm) on the roughened surface using a commercially available laser microscope. In this specification, Sds, Ssc, and Sdr are measured without using an S filter or an L filter for cutoff. Optimized measurement and analysis conditions for the surface profile using a laser microscope are described in the following examples.

[0017] [Manufacturing method of printed circuit board] [] The present invention relates to a method for manufacturing a printed circuit board. The method includes the following steps: (a) preparing an insulating substrate, (b) forming an electroless plating layer, (c) laminating a photoresist, (d) forming a photoresist pattern, (e) forming an electroplating layer, (f) stripping the photoresist pattern, and (g) forming a wiring pattern.

[0018] Hereinafter, each of steps (a) to (g) will be described with reference to Figures 1 to 5.

[0019] (a) Preparation of insulating substrate As shown in Figure 1(a), an insulating substrate 20 having a roughened surface 20a is prepared. The insulating substrate 20 may have the roughened surface 20a on both sides or only on one side. The insulating substrate 20 preferably contains an insulating resin. Furthermore, the insulating substrate 20 is preferably a prepreg and / or a resin sheet. Prepreg is a general term for composite materials formed by impregnating a substrate such as a synthetic resin plate, glass plate, glass woven fabric, glass non-woven fabric, or paper with a synthetic resin. Preferred examples of insulating resins impregnated in prepregs include epoxy resins, isocyanate resins, bismaleimide triazine resins (BT resins), polyphenylene ether resins, and phenolic resins. Furthermore, examples of insulating resins constituting the resin sheet include epoxy resins, polyimide resins, polyester resins, and the like. To improve insulation properties, the insulating substrate 20 may also contain filler particles such as various inorganic particles such as silicon oxide and aluminum oxide. The thickness of the insulating substrate 20 is not particularly limited, but is preferably 1 μm to 1000 μm, more preferably 2 μm to 400 μm, and even more preferably 3 μm to 200 μm. The insulating substrate 20 may include a plurality of layers.

[0020] The roughened surface 20a of the insulating substrate 20 can be formed by any method, but typically, it is formed by transferring the uneven surface of the treated copper foil to the surface of the insulating substrate 20. According to a preferred embodiment of the present invention, the roughened surface 20a is formed using the surface-treated copper foil by (a-1) preparing a surface-treated copper foil having a predetermined surface treatment; (a-2) laminating the insulating substrate on the treated surface of the surface-treated copper foil to transfer the surface shape of the treated surface to the surface of the insulating substrate; and then (a-3) removing the surface-treated copper foil by etching to obtain the insulating substrate having a roughened surface. The specific order of each step is as follows.

[0021] (a-1) Preparation of surface-treated copper foil As shown in Figure 3(a-1), a surface-treated copper foil 10 having a treated surface 10a on at least one side is prepared. The treated surface 10a is a surface that has undergone some type of surface treatment, typically a roughened surface. The treated surface 10a typically has a plurality of protrusions (e.g., roughened particles). In summary, the surface-treated copper foil 10 may have treated surfaces 10a on both sides or only on one side. In the case of having treated surfaces 10a on both sides, when used in the SAP method, the surface on the laser-irradiated side (the side opposite to the surface in close contact with the insulating substrate) is also surface-treated, thereby improving laser absorption and, as a result, laser perforation performance. Furthermore, the surface-treated copper foil 10 may be in the form of a copper foil with a carrier attached. In this case, the copper foil with a carrier attached typically comprises a carrier, a release layer disposed on the carrier, and the surface-treated copper foil 10 disposed on the release layer with the treated surface 10a facing outward. However, the copper foil with a carrier may have a known layer structure other than the surface-treated copper foil 10 .

[0022] The peak density Sds of the treated surface 10a of the surface-treated copper foil 10 is preferably 1.00 μm-2 or more and 1.50 μm-2 or less, more preferably 1.00 μm-2 or more and 1.40 μm-2 or less, further preferably 1.10 μm-2 or more and 1.40 μm-2 or less, and even more preferably 1.20 μm-2 or more and 1.40 μm-2 or less. Furthermore, the peak curvature Ssc of the treated surface 10a of the surface-treated copper foil 10 is preferably 4.00 μm-1 or more and 6.00 μm-1 or less, more preferably 4.50 μm-1 or more and 6.00 μm-1 or less, and further preferably 4.50 μm-1 or more and 5.00 μm-1 or less. Furthermore, the interfacial developed area ratio Sdr of the treated surface 10a of the surface-treated copper foil 10 is preferably 20.00% to 40.00%, more preferably 20.00% to 25.00%. By using the surface-treated copper foil 10 having the treated surface 10a with Sds, Ssc, and Sdr within these ranges to impart a concave-convex shape to the insulating substrate 20, it is easy to form the electroless plating layer 22 having the following specific surface parameters on the roughened surface 20a of the insulating substrate 20. The treated surface 10a having the above-described surface parameters can be formed by subjecting the copper foil surface to a surface treatment (typically, a roughening treatment) under known or desired conditions. Furthermore, commercially available copper foil having a treated surface 10a that satisfies the above-described conditions can also be selectively obtained.

[0023] (a-2) Transfer of Concavo-convex Shapes onto Insulating Substrates As shown in Figure 3(a-2), an insulating substrate 20' (i.e., an insulating substrate 20 that has not yet formed a roughened surface 20a) is laminated onto the treated surface 10a of the surface-treated copper foil 10 to produce a copper foil laminate 12. This allows the surface profile of the treated surface 10a to be transferred to the surface of the insulating substrate 20'. Lamination of the insulating substrate 20' is preferably performed by hot pressing or hot lamination. The processing temperature and time for the hot pressing or hot lamination process can be appropriately determined based on known conditions, such as the type of insulating substrate 20' being laminated. Preferred types of insulating substrate 20' are as described above for the insulating substrate 20. Furthermore, the insulating substrate 20' can also be laminated onto the surface-treated copper foil 10 via a primer layer (not shown) pre-applied to the treated surface 10a of the surface-treated copper foil 10. In this case, the primer layer is considered to constitute part of the insulating substrate. The base coat preferably comprises a resin, which preferably comprises an insulating resin. Alternatively, prior to the next step of removing the surface-treated copper foil 10, a guide hole (not shown) may be formed in the copper foil laminate 12 by laser perforation.

[0024] (a-3) Removal of surface treated copper foil As shown in FIG3(a-3), the surface-treated copper foil 10 of the copper-clad laminate 12 is removed by etching, thereby obtaining an insulating substrate 20 having a roughened surface 20a. The etching method for the surface-treated copper foil 10 is not particularly limited and can be performed using, for example, a sulfuric acid-hydrogen peroxide-based etching solution, according to etching methods and conditions commonly used in the manufacture of printed circuit boards.

[0025] (b) Formation of electroless plating As shown in FIG1(b), the roughened surface 20a of the insulating substrate 20 is subjected to electroless plating (e.g., electroless copper plating) to form an electroless plating layer 22 having a thickness of 1.0 μm or less. The electroless plating method is not particularly limited and can be performed using a commercially available electroless plating solution according to methods and conditions commonly used in the manufacture of printed circuit boards. The peak density Sds of the surface of the electroless plating layer 22 is not less than 0.90 μm-2 and not more than 1.30 μm-2, and the peak curvature Ssc is not less than 1.00 μm-1 and not more than 4.00 μm-1. In this way, by electrolessly plating the insulating substrate 20 having the roughened surface 20a to form the electroless plating layer 22 having a surface with a peak density Sds and a peak curvature Ssc controlled within a specified range, it is possible to manufacture a printed circuit board that more effectively suppresses pattern defects and has excellent high-frequency characteristics.

[0026] As mentioned above, with the recent trend toward miniaturization of circuits required by the SAP method, the idea of ​​using a copper foil with a smooth surface and small roughening particles to roughen the insulating substrate surface has emerged to achieve superior etching properties. Furthermore, if a thin layer (e.g., less than 1.0 μm) of electroless plating can be applied to the surface of the insulating substrate with a roughened surface, this is advantageous because it reduces the amount of etching required, allowing for further miniaturization of the circuits. However, when attempting to form circuits using a copper foil with a smooth surface and small roughening particles and electroless plating at a thin layer in the SAP method, there is a risk of short circuits or pattern defects such as protrusions in the resulting circuits. The mechanism for these pattern defects is not entirely clear, but the following is a hypothesis.

[0027] That is, when using a surface-treated copper foil to transfer a surface profile to an insulating substrate, the roughened surface of the insulating substrate generally reflects the surface profile of the surface-treated copper foil. Furthermore, when electroless plating is applied to the roughened surface of the insulating substrate at a thickness of 1.0 μm or less, the surface profile of the electroless plated layer generally reflects the surface profile of the roughened surface of the insulating substrate. Therefore, it is believed that if a copper foil with a smooth surface and small roughened particles (in other words, a copper foil with fine unevenness) is used as the copper foil for transferring the surface profile to the insulating substrate, it is difficult to impart sufficient unevenness to the surface of the electroless plated layer. Furthermore, in the manufacturing process of a typical printed circuit board, in order to form a circuit in a predetermined pattern, the following operations are performed as shown in Figures 4(i) to (iv): a photoresist 24 (e.g., comprising a dry film photoresist 24a and a support film 24b) is further layered on the surface of the electroless plated layer 22 laminated on the insulating substrate 20, and exposure and development are performed to form a photoresist pattern 26. Here, as shown in FIG4(i), during the lamination or exposure of the photoresist 24, foreign matter F (e.g., dirt or flaws on the photoresist surface, or air trapped during lamination) may adhere to or enter the surface of the photoresist 24. For example, in a printed circuit board manufacturing plant, clean rooms operate at cleanliness levels of approximately Class 100 to Class 1000, making it difficult to completely eliminate foreign matter from the environment. Furthermore, it is difficult to detect minute flaws on the surface of the photoresist 24. In this regard, if the photoresist 24 is exposed after being laminated on the surface of the electroless plating layer 22 that has not been given a sufficiently concave and convex shape, then, as shown in FIG4(ii), the exposure light I incident perpendicular to the main surface of the laminate will be directly reflected by the electroless plating layer 22 and emitted as exposure reflected light R in a direction 180° opposite to the exposure light I. Therefore, the portion of the photoresist 24 (e.g., dry film photoresist 24a) that should have been exposed, directly below the foreign matter F, remains unexposed (see FIG4(iii)). After development, a hole H is formed (see FIG4(iv)). This is believed to result in electroplating where a circuit should not have been formed. This unnecessary electroplating causes short circuits or protrusions in the circuit, resulting in pattern defects.

[0028] Furthermore, polyethylene terephthalate (PET) film is commonly used as the support film 24b of the photoresist 24. A lubricant is added to the PET film to improve fluidity and release properties during thermoforming. This lubricant typically has uneven particle sizes, with a certain proportion of oversized particles (e.g., diameters of 10 μm or greater). Consequently, the inevitable presence of oversized foreign matter in such PET film can cause areas that should be exposed to remain unexposed, as described above, resulting in pattern defects. Furthermore, it is also assumed that exposure is performed after peeling off the PET film to expose the dry film. However, in this case, oxygen can cause deformation of the dry film. In other words, the aforementioned pattern defects are unavoidable due to the lubricant contained in the PET film. In this regard, existing printed circuit board manufacturing methods, such as those disclosed in Patent Document 3 (International Publication No. 2020 / 196105) and Patent Document 4 (International Publication No. 2020 / 196106), still have room for improvement in eliminating pattern defects caused by oversized foreign matter. Alternatively, one approach might involve using surface-treated copper foil with a high surface roughness to transfer the surface shape to the insulating substrate, thereby excessively increasing the surface roughness of the electroless plating layer. However, this approach can lead to deterioration in high-frequency characteristics. Thus, achieving both pattern defect suppression and good high-frequency characteristics is difficult.

[0029] In this regard, the method of the present invention can achieve both further suppression of pattern defects and excellent high-frequency characteristics. The mechanism is not necessarily clear, but it is believed to be as follows. Specifically, by setting the peak density Sds on the surface of the electroless plating layer 22 to between 0.90 μm-2 and 1.30 μm-2, and the peak curvature Ssc to between 1.00 μm-1 and 4.00 μm-1, the surface of the electroless plating layer 22 has a moderately uneven shape (see FIG5(i)). Therefore, when exposure light I, incident perpendicularly to the main surface of the laminate, reaches the surface of the electroless plating layer 22 during exposure, it is diffusely reflected from the uneven portions of the surface of the electroless plating layer 22 (see FIG5(ii)). As a result, the reflected exposure light R can expose the portion of the photoresist 24 (e.g., dry film photoresist 24a) directly beneath the foreign matter F (see FIG5(iii)). Here, the wavelength of light used to expose the photoresist 24 is typically absorbed by the electroless plating layer 22, which is composed of copper or the like, at approximately 60-70% absorption. Therefore, for example, if the angle formed by the incident exposure light I and the reflected exposure light R is too large, the reflected exposure light R is absorbed by the electroless plating layer 22 (e.g., the concave and convex portions near the reflection position), potentially failing to eliminate pattern defects caused by foreign matter F. In this regard, by controlling the surface shape of the electroless plating layer 22 by combining the peak density Sds and the peak curvature Ssc within the aforementioned range, it is easier to control the angle formed by the incident exposure light I and the reflected exposure light R within the desired range. As a result, the portion of the photoresist 24 (e.g., the dry film photoresist 24a) directly beneath the foreign matter F can be very effectively exposed. This allows even very large foreign matter F present on the surface and / or within the photoresist 24 to be eliminated. This effectively prevents the formation of unexposed areas of the photoresist 24 due to foreign matter F and suppresses the formation of unnecessary holes H due to development (see Figure 5(iv)). This is believed to reduce the likelihood of circuit shorts or pattern defects such as protrusions. Furthermore, it is believed that the surface of the electroless plating layer 22 with a peak density Sds and peak curvature Ssc within the above ranges has a low-roughness surface shape that effectively reduces the skin effect, thereby achieving excellent high-frequency characteristics.

[0030] From the above viewpoint, the peak density Sds of the surface of the electroless plating layer 22 is 0.90 μm −2 or more and 1.30 μm −2 or less, preferably 0.90 μm −2 or more and 1.20 μm −2 or less, and more preferably 1.10 μm −2 or more and 1.20 μm −2 or less.

[0031] Furthermore, the peak curvature Ssc of the surface of the electroless plating layer 22 is not less than 1.00 μm −1 and not more than 4.00 μm −1, preferably not less than 2.30 μm −1 and not more than 3.50 μm −1, and more preferably not less than 2.30 μm −1 and not more than 3.00 μm −1.

[0032] The surface interface development area ratio Sdr of the electroless plating layer 22 is preferably 5.00% to 10.00%, and more preferably 5.00% to 6.00%. Within these ranges, excellent high-frequency characteristics can be achieved while further suppressing pattern defects caused by larger foreign matter F.

[0033] The electroless plated layer 22 having the above-described unique surface parameters can be formed by electroless plating at a thickness of 1.0 μm or less on the roughened surface 20a of the insulating substrate 20. As described above, the surface shape of the electroless plated layer 22 can be considered to substantially reflect the surface shape of the roughened surface 20a of the insulating substrate 20. Furthermore, the roughened surface 20a can be preferably formed by transferring the surface shape of the surface-treated copper foil 10 having the surface parameters described in (a) above to the insulating substrate 20.

[0034] The thickness of the electroless plating layer 22 is 1.0 μm or less, preferably 0.3 μm or more and 1.0 μm or less. Such a thickness can reduce the amount of etching during wiring pattern formation, making it very suitable for forming fine circuits.

[0035] (c) Photoresist layer As shown in FIG1(c), a photoresist 24 is laminated on the surface of the electroless plating layer 22. The lamination speed when laminating the photoresist 24 is not particularly limited, but is typically between 1.0 m / min and 2.0 m / min. The photoresist 24 can be made of a known material commonly used in the manufacture of printed circuit boards. The photoresist 24 can be either negative or positive, and can be either a film or liquid. Preferably, the photoresist 24 comprises a dry film photoresist 24a. Furthermore, the photoresist 24 is preferably a photosensitive film, such as a photosensitive dry film. As shown in FIG1(c), the photoresist 24 can also be formed by further laminating a support film 24b such as a polyethylene terephthalate (PET) film on the dry film photoresist 24a serving as a photosensitive layer. To improve fluidity and release properties during thermoforming, the support film 24b such as a PET film typically contains a lubricant. In this regard, according to the present invention, as described above, pattern defects caused by lubricants can be effectively suppressed. The thickness of the photoresist 24 or dry film photoresist 24a is preferably 2 μm to 35 μm, more preferably 5 μm to 24 μm.

[0036] (d) Formation of photoresist pattern As shown in FIG2(d), the photoresist 24 is exposed and developed to form a photoresist pattern 26. Exposure and development are not particularly limited and can be performed according to known methods and conditions commonly used in the manufacture of printed circuit boards. For example, in addition to mask exposure using a negative or positive mask pattern, direct writing exposure methods such as laser direct imaging (LDI) exposure or digital light processing (DLP) exposure can also be used as the exposure method. The exposure dose during exposure is preferably not less than 5 mJ / cm2 and not more than 150 mJ / cm2. On the other hand, the development method can be either wet development or dry development. In the case of wet development, the developer used can be sodium carbonate, sodium hydroxide, an amine aqueous solution, or the like. Furthermore, when the photoresist 24 includes a support film 24b, it is preferred to remove the support film 24b before performing development.

[0037] (e) Formation of electroplating layer Electroplating (e.g., copper plating) is performed on the electroless plating layer 22 through the photoresist pattern 26. This allows the formation of an electroplated layer 28 between the photoresist patterns 26, as shown in FIG2(e). The electroplating method is not particularly limited and can be performed using various pattern plating methods and conditions commonly used in the manufacture of printed circuit boards, such as a copper sulfate plating solution or a copper pyrophosphate plating solution.

[0038] (f) Stripping of photoresist pattern In this step, the photoresist pattern 26 is stripped. As a result, as shown in FIG2(f), the electroplated layer 28 remains in the form of a wiring pattern, and the unused portion of the electrolytic plating layer 22 where no wiring pattern is formed is exposed. The stripping method for the photoresist pattern 26 is not particularly limited and can be performed using various stripping methods and conditions commonly used for printed circuit boards, such as sodium hydroxide aqueous solution, amine solution, or aqueous solution thereof.

[0039] (g) Formation of wiring pattern The unused portions of the electroless plating layer 22 (i.e., portions where no wiring pattern is formed) exposed by stripping the photoresist pattern 26 are removed by etching to form the wiring pattern 30. Etching of the unused portions of the electroless plating layer 22 is not particularly limited and can be performed using, for example, a sulfuric acid-hydrogen peroxide-based etching solution, according to etching methods and conditions commonly used in the manufacture of printed circuit boards. The thickness of the wiring pattern 30 (i.e., circuit height) is preferably between 2 μm and 30 μm. The wiring pitch of the wiring pattern 30 is preferably between 10 μm (e.g., line / space = 5 μm / 5 μm) and 20 μm (e.g., line / space = 10 μm / 10 μm). By forming circuits on the electroless plating layer 22 having a thickness of 1.0 μm or less and having the specified surface parameters, such a highly miniaturized wiring pattern can be formed. Furthermore, it is considered that the wiring pattern with a wiring pitch within the above range is prone to problems such as short circuits or protrusions, but as described above, the method of the present invention can effectively eliminate these problems.

[0040] Alternatively, a multilayer circuit board can be fabricated by alternately forming an insulating layer and an nth wiring pattern (n is an integer greater than or equal to 2) on the wiring pattern 30. Regarding the wiring patterns that comprise the multilayer circuit board, the wiring pattern 30 can be the first wiring pattern, followed by the second wiring pattern, the third wiring pattern, and so on. The sequentially stacked structure comprising the first wiring pattern, the nth wiring pattern, and the insulating layer is generally referred to as a stacked layer or a stacked wiring layer. The processes used to form the stacked layers after the second wiring pattern are not particularly limited. In addition to the aforementioned SAP method, a modified semi-additive process (MSAP), a fully additive process, a subtractive process, and the like can also be used. Furthermore, solder resist or mounting bumps such as studs can be formed on the outermost wiring pattern of the stacked layer as needed. In short, conventionally known processes used in printed circuit boards can be appropriately supplemented without particular limitation. [Example]

[0041] The present invention will be described more specifically using the following examples.

[0042] [example] [1] [~]

[15] Fifteen types of surface-treated copper foil were prepared and used to transfer the surface profile onto an insulating substrate. The roughened surface of the resulting insulating substrate was electrolessly plated to create a laminate for evaluation, and various evaluations were performed as follows.

[0043] (1) Preparation of surface treated copper foil Fifteen types of surface-treated copper foils 10 were prepared, each having a treated surface 10a on at least one side having the parameters shown in Table 2. Some of these surface-treated copper foils 10 were commercially available, while others were manufactured using conventional methods. The parameters of the treated surface 10a of the prepared surface-treated copper foils 10 were measured or calculated as follows.

[0044] The surface roughness of the treated surface 10a of the surface-treated copper foil 10 was measured using a laser microscope according to EUR 15178 N. Specific measurement conditions are shown in Table 1.

[0045] [Table 1] Table 1 Measurement conditions Measuring device Olympus Corporation, OLS5000 (Version 1.3.4.5425) Objective magnification 100 times Digital zoom ratio 1.0 times Scan Mode 3D Standard + Color Shooting Mode Auto Measurement area 128.750 μm×129.196 μm

[0046] The measurement data acquired using the laser microscope were read using analysis software ("OLS5100 LEXT (Version 2.1.2.215)" manufactured by Olympus Corporation). The unprocessed data was converted intact into a LEXT file format and output. This LEXT file was then read using separate analysis software ("MountainsMap (Version 9.0.9878)" manufactured by Digital Surf Corporation) and analyzed (analysis area: 64.397 μm × 64.463 μm). Specifically, from the Analysis Target tab, select "Parameter Table" and then "Default Settings" to display the parameter analysis screen. On the parameter analysis screen, select "EUR15178N" as the specification, "Linear Surface" as the wavelength processing, "Least Squares" as the F operation (F Run) for shape removal, and "Sds," "Ssc," and "Sdr" as the parameters. On the other hand, in this screen, the S filter and L filter are not selected (i.e., there is no cutoff using the S filter and L filter). Then, select "Output Analysis Results" and save the analysis results. From these analysis results, the peak density Sds, peak curvature Ssc, and interface spread area ratio Sdr are read. For each example, the above parameters are calculated using five different fields of view. The average values ​​across all fields of view are used as the Sds, Ssc, and Sdr of the treated surface 10a of the surface-treated copper foil 10. The results are shown in Table 2.

[0047] (2) Preparation of evaluation laminates After laminating two prepregs (manufactured by Mitsubishi Gas Chemical Co., Ltd., GHPL-830NSF, thickness 100 μm), as shown in FIG3 , the surface-treated copper foil 10 prepared in (1) above was laminated on the insulating substrate 20′ in such a manner that the treated surface 10a was in contact, and the laminate was pressed under the conditions of a pressing temperature of 220°C, a pressing time of 90 minutes, and a pressing pressure of 40 kgf / cm 2 to obtain a copper foil laminate 12. The surface-treated copper foil 10 of the copper foil laminate 12 was completely removed using a sulfuric acid-hydrogen peroxide etching solution to obtain an insulating substrate 20 having a roughened surface 20a with a surface shape transferred from the treated surface 10a. The insulating substrate 20 was electrolessly plated with copper using an electroless copper plating solution (manufactured by Atotech, Atotech MV+) to form an electroless plating layer 22 on the roughened surface 20a side. The thickness of the electroless plating layer 22 is shown in Table 2. In this manner, a laminated body immediately before lamination of the photoresist in the SAP method (hereinafter referred to as a laminated body for evaluation) was obtained.

[0048] (3) Surface profile measurement of the evaluation layer The peak density Sds, peak curvature Ssc, and interface area ratio Sdr of the surface of the electroless plated layer 22 of the evaluation laminate obtained above were measured using surface roughness analysis using a laser microscope in accordance with EUR15178N. The measurement and analysis conditions for each parameter were the same as those for the surface-treated copper foil described in (1) above. The results are shown in Table 2.

[0049] (4) Various assessments The obtained evaluation laminate or circuit board was evaluated for various characteristics as follows.

[0050] <Number of dirt detected> The number of contaminant detections was evaluated as follows. First, a 19 μm-thick negative-type photoresist 24 (RY-5319 manufactured by Hitachi Chemical Co., Ltd.) was laminated onto the surface of the electroless-plated layer 22 of the evaluation laminate obtained above at a lamination rate of 1.5 m / min. Then, as shown in FIG6(i), a glass mask 25 was laminated onto the surface of the photoresist 24. Furthermore, circular light-shielding portions B (diameters 8 μm to 15 μm (8 levels at 1 μm intervals, totaling 25 × 12 fields) were provided on the glass mask 25 at the center of each 100 μm × 100 μm area, assuming the presence of foreign matter such as contaminants. Therefore, the portion of the glass mask 25 without the light-shielding portions B was transparent, while the portion of the glass mask 25 with the light-shielding portions B was opaque. After laminating the glass mask 25, the evaluation laminate was exposed (70 mJ / cm²) and developed to form a photoresist pattern 26. The surface of the developed evaluation laminate on the photoresist pattern 26 side was observed at 700x magnification using a digital microscope (VHX-7000, manufactured by KEYENCE Corporation), and the number of holes H formed in the photoresist pattern 26 was counted, as shown in Figure 6(ii). The average number of holes detected per field of view (i.e., a maximum of 25 holes per size) was calculated based on the size of the light-shielding portion B, and this was used as the number of contamination detections. Furthermore, it is believed that a higher number of contamination detections (i.e., better resolution) indicates a higher likelihood of unnecessary plating in locations where circuits should not be formed, leading to a higher likelihood of pattern defects. Therefore, for each sample, the diameter of the largest light-shielding portion B with a contamination detection number of 13 or fewer was considered the maximum contamination size that could eliminate pattern defects. The results are shown in Table 2.

[0051] <Evaluation of high-frequency characteristics> A high-frequency substrate (manufactured by Panasonic Co., Ltd., MEGTRON7, thickness 68 μm × 2 sheets) was prepared as an insulating resin substrate. On both sides of the insulating resin substrate, a copper foil with a carrier having the surface-treated copper foil 10 prepared in (1) was laminated in such a manner that the treated surface 10a of the surface-treated copper foil 10 abutted against the insulating resin substrate. After pressing with a vacuum press under the conditions of a pressure of 3 MPa, a temperature of 190°C, and a pressing time of 90 minutes, the carrier and the peeling layer were peeled off together. The surface-treated copper foil 10 was completely removed using a sulfuric acid-hydrogen peroxide etching solution to obtain an insulating substrate 20 having a roughened surface 20a to which the surface shape of the treated surface 10a was transferred. Subsequently, the insulating substrate 20 was electrolessly copper-plated using an electroless copper plating solution (manufactured by Atotech Co., Ltd., Atotech MV+), and an electroless plating layer 22 with a thickness of 0.5 μm was formed on the roughened surface side. Subsequently, copper plating was performed until the copper layer thickness reached 18 μm to produce a copper-clad laminate. Circuits were then formed on this copper-clad laminate using a subtractive method with a cupric chloride etchant (circuit height: 18 μm, circuit width: 320 μm, circuit length: 300 mm). This produced a substrate for transmission loss measurement, on which a microstrip line was formed to achieve a characteristic impedance of 50 Ω ± 2 Ω. The transmission loss (dB) of the resulting transmission loss measurement substrate was measured at 50 GHz using a network analyzer (Keysight Technologies, Inc., N5225B) under the following conditions. (Setting conditions) -IF Bandwidth: 100 Hz -Frequency: 10 MHz~50 GHz -Data points: 501 points -Average: Off -Calibration method: SOLT (Short-Open-Load-Thru) (e-cal)

[0052] The transmission loss (absolute value) at 50 GHz obtained was graded and evaluated according to the following criteria. The results are shown in Table 2. <High-Frequency Characteristics Evaluation Criteria> - Evaluation A (Best): Transmission loss (absolute value) is less than 13.5 dB - Evaluation B (Good): Transmission loss (absolute value) is 13.5 dB or more and less than 15.0 dB - Evaluation C (poor): Transmission loss (absolute value) is 15.0 or more

[0053] [Table 2] Table 2 Surface treated copper foil Electroless plating Evaluate Number of dirt detections High frequency characteristics Surface parameters thickness (μm) Surface parameters Diameter of light shielding part B (μm) total Maximum dirt size Transmission loss (dB) and its evaluation Sds(μm-2) Ssc (μm-1) Sdr(%) Sds(μm-2) Ssc (μm-1) Sdr(%) 15 14 13 12 11 10 9 8 Example 1 1.18 5.63 38.21 0.7 1.15 2.97 8.51 twenty four 19 11 3 0 0 0 0 57 13 μm 14.7 B Example 2 1.18 5.63 38.21 0.8 1.01 2.55 7.09 25 twenty two 13 4 2 0 0 0 64 13 μm 14.7 B Example 3 1.18 5.61 34.68 0.8 1.17 3.21 9.66 25 19 9 2 0 0 0 0 54 13 μm 14.6 B Example 4 1.33 4.86 22.24 0.8 1.15 2.55 5.98 25 twenty three 11 1 0 0 0 0 60 13 μm 13.4 A Example 5 1.18 5.63 38.21 1.0 0.96 2.34 6.44 25 twenty three 13 3 0 0 0 0 64 13 μm 14.7 B Example 6 1.18 5.61 34.68 0.7 1.24 3.60 11.54 25 twenty three 16 5 1 0 0 0 70 12 μm 14.6 B Example 7 1.27 5.30 29.25 0.65 1.29 2.24 4.09 25 twenty three 18 9 1 0 0 0 76 12 μm 14.5 B Example 8 1.27 5.30 29.25 0.8 1.13 1.92 3.47 25 25 twenty three 11 0 0 0 0 85 12 μm 14.5 B Example 9 1.27 5.30 29.25 1.0 1.16 1.88 3.37 25 25 18 8 1 0 0 0 76 12 μm 14.5 B Example 10* 1.36 4.24 15.98 0.65 0.89 1.40 3.55 25 25 twenty three 15 3 1 0 0 92 11 μm 12.8 A Example 11* 1.14 5.85 44.13 0.4 1.38 4.17 13.54 25 25 25 twenty three 5 2 0 0 105 11 μm 14.8 B Example 12* 0.86 5.19 37.47 0.4 0.81 1.52 2.90 25 25 twenty four 18 6 0 0 0 99 11 μm 14.6 B Example 13* 1.58 4.08 12.36 0.4 1.26 0.73 0.63 25 25 25 25 25 twenty four 8 0 157 9 μm 12.9 A Example 14* 1.58 4.08 12.36 0.8 1.28 0.78 0.75 25 25 25 25 25 15 0 0 140 9 μm 12.9 A Example 15* 0.66 3.15 19.40 0.7 0.52 3.31 2019.17 25 13 2 0 0 0 0 0 40 14 μm 15.4 C *Indicates comparative example.

[0054] 10: Surface treated copper foil 10a: Surface treatment 12: Copper foil laminate 20: Insulation substrate 20': Insulation substrate 20a: Roughened surface 22: Electroless plating 24: Photoresist 24a: Dry film photoresist 24b: Support membrane 26: Photoresist pattern 28: Electroplating layer 30: Wiring pattern 110: Roughened copper foil 111: Insulating resin substrate 111a: Base material 111b: Lower layer circuit 112: Prepreg 113: Base coating 114: Guide hole 115:Electroless copper plating 116:Dry film 117:Electroplated copper 117a: Wiring part 118: Wiring B: Light-shielding part F: Foreign matter H: hole I: Exposure incident light N: neighboring points R: Exposure reflected light S: Peak

Claims

1. A method for manufacturing a printed circuit board, comprising the steps of: (a) preparing an insulating substrate having a roughened surface; (b) electroless plating the roughened surface of the insulating substrate to form an electroless plating layer with a thickness of 1.0 μm or less, the electroless plating layer having a surface with a peak density Sds of 0.90 μm-2 or more and 1.30 μm-2 or less as measured by EUR15178N and a peak curvature Ssc of 1.00 μm-1 or more and 4.00 μm-1 or less as measured by EUR15178N; (c) applying a photoresist to the surface of the electroless plating layer; (d) exposing and developing the photoresist to form a photoresist pattern; (e) electroplating the electroless plating layer through the photoresist pattern; (f) peeling off the photoresist pattern; and (g) using etching to remove the useless portions of the electroless plating layer exposed by the peeling off of the photoresist pattern to form a wiring pattern.

2. The method for manufacturing a printed circuit board as claimed in claim 1, wherein the surface of the aforementioned electroless plating layer has an interfacial unfolded area ratio (Sdr) of 5.00% to 10.00% as measured according to EUR15178N.

3. The method for manufacturing a printed circuit board as claimed in claim 1 or 2, wherein the peak curvature Ssc of the surface of the electroless plating layer is above 2.30 μm-1 and below 3.50 μm-1.

4. A method for manufacturing a printed circuit board as claimed in claim 1 or 2, wherein step (a) above includes: (a-1) Prepare a surface-treated copper foil having a peak density Sds of 1.00 μm-2 to 1.50 μm-2 as measured by EUR15178N, a peak curvature Ssc of 4.00 μm-1 to 6.00 μm-1 as measured by EUR15178N, and an interface unfolded area ratio Sdr of 20.00% to 40.00% as measured by EUR15178N. (a-2) Apply an insulating substrate to the surface of the surface-treated copper foil to transfer the surface shape of the surface treated to the surface of the insulating substrate. Then, (a-3) Remove the surface-treated copper foil by etching to obtain an insulating substrate having the roughened surface.

5. The method for manufacturing a printed circuit board as claimed in claim 1 or 2, wherein the thickness of the electroless plating layer is 0.3 μm or more and 1.0 μm or less.

6. A method for manufacturing a printed circuit board as claimed in claim 1 or 2, wherein the photoresist includes dry film photoresist.

7. The method for manufacturing a printed circuit board as claimed in claim 6, wherein the thickness of the aforementioned dry film photoresist is 2 μm or more and 35 μm or less.

8. The method for manufacturing a printed circuit board as claimed in claim 1 or 2, wherein the thickness of the aforementioned wiring pattern is more than 2 μm and less than 30 μm.

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