Semiconductor structure, semiconductor device, and forming method thereof

Abstract

This disclosure describes a semiconductor device having a source / drain structure with a doped cluster. The semiconductor device includes a channel structure on a substrate and a source / drain structure on the substrate and adjacent to the channel structure. The source / drain structure includes a first epitaxial layer on the substrate, a second epitaxial layer on the first epitaxial layer and the sidewalls of the channel structure, and a third epitaxial layer on the second epitaxial layer. The second epitaxial layer includes a cluster of dopant extending along a direction of the channel structure.

Description

Technical Field

[0001] None Prior Art

[0002] With the advancement of semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs is increasing. To meet these demands, the semiconductor industry continuously shrinks the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This miniaturization increases the complexity of the semiconductor manufacturing process and the difficulty of process control in semiconductor devices. Summary of the Invention

[0003] None Brief Description of the Drawings

[0004] The various aspects of the present disclosure can be best understood when reading the following detailed description in conjunction with the accompanying drawings. FIG. 1 illustrates an isometric view of a semiconductor device having a source / drain structure with doped clusters according to some embodiments. FIGS. 2A and 2B illustrate cross-sectional views of a semiconductor device having a source / drain structure with doped clusters according to some embodiments. FIG. 3 illustrates a cross-sectional view of a semiconductor device having a source / drain structure with horizontal and inclined doped clusters according to some embodiments. FIGS. 4A to 4D illustrate various shapes of doped clusters in a source / drain structure according to some embodiments. FIGS. 5A to 5C illustrate various shapes of channel structures in a semiconductor device according to some embodiments. FIG. 6 is a flowchart of a method for manufacturing a semiconductor device having a source / drain structure with doped clusters according to some embodiments. FIGS. 7 to 22B illustrate isometric views and cross-sectional views of a semiconductor device having a source / drain structure with doped clusters at various manufacturing stages according to some embodiments. Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally denote like, functionally similar, and / or structurally similar elements. Embodiments

[0005] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. As used herein, forming a first feature over a second feature means that the first feature is formed in direct contact with the second feature. In addition, this disclosure may repeat element symbols and / or letters in various examples. This repetition itself does not indicate a relationship between the various embodiments and / or configurations described.

[0006] In addition, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] It should be noted that references in the specification to "an embodiment", "embodiment", "exemplary embodiment", "illustrative", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include the particular feature, structure, or characteristic. In addition, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not explicitly described, influencing such feature, structure, or characteristic in connection with other embodiments will be within the knowledge of those skilled in the art.

[0008] It should be understood that the terminology or phraseology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of this specification will be interpreted by those skilled in the relevant art in light of the teachings herein.

[0009] In some embodiments, the terms "about" and "substantially" may indicate a given value that varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of the value as interpreted by one skilled in the relevant art in view of the teachings herein.

[0010] As the demand for lower power consumption, higher performance, and smaller semiconductor devices grows, the size of semiconductor devices is continuously scaled down. The continuous scaling down of device size and the increasing demand for device performance may require various process and material improvements, which can pose multiple challenges. For example, nanostructured transistors can utilize channels in a stacked nanosheet / nanowire configuration to provide improved device performance. Nanostructured transistors can include finFETs, gate-all-around field effect transistors (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and transistors of other similar structures. However, during the nanosheet formation process of the channel, the source / drain (S / D) structure of the nanostructured transistor can also be etched, and then gate-S / D short circuit defects can be formed. Gate-S / D short circuit defects can lead to device failures and yield losses.

[0011] Various embodiments in the present disclosure provide exemplary methods for forming S / D structures with dopant clusters in semiconductor devices (such as nanostructured transistors) and / or other semiconductor devices in an integrated circuit (IC). In some embodiments, a channel structure can be formed on a substrate. The S / D structure can be formed on the substrate and adjacent to the channel structure. In some embodiments, the S / D structure can include a first epitaxial layer on the substrate, a second epitaxial layer on the sidewalls of the first epitaxial layer and the channel structure, and a third epitaxial layer on the second epitaxial layer. In some embodiments, the second epitaxial layer can include clusters of dopants extending in the direction of the channel structure. In some embodiments, the first concentration of dopants in the clusters can be more than about ten times greater than the concentration of dopants in the second epitaxial layer. In some embodiments, the clusters of dopants can extend along the intersection of the (111) growth planes of the second epitaxial layer. In some embodiments, the second epitaxial layer can include additional clusters of dopants along the (111) growth plane of the second epitaxial layer. The clusters of dopants can reduce the etching damage to the S / D structure, reduce gate-S / D short circuit defects, and improve device performance and yield.

[0012] FIG. 1 illustrates an isometric view of a semiconductor device 100 having source / drain structures with dopant clusters according to some embodiments. FIGS. 2A and 2B illustrate partial cross-sectional views of the semiconductor device 100 according to some embodiments taken along lines A-A and B-B shown in FIG. 1, respectively. FIG. 3 illustrates a partial cross-sectional view of a semiconductor device 100 having source / drain structures with horizontal and tilted dopant clusters according to some embodiments. FIGS. 4A to 4D illustrate various shapes of dopant clusters in the source / drain structures according to some embodiments. FIGS. 5A to 5C illustrate various shapes of channel structures in the semiconductor device 100 according to some embodiments.

[0013] In some embodiments, the semiconductor device 100 may include transistors 102A to 102C as shown in FIG. 1. In some embodiments, the transistors 102A to 102C may include nanostructure transistors. The nanostructure transistors may include finFETs, GAA FETs, nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and transistors of other similar structures. The nanostructure transistors may provide channels in a stacked nanosheet / nanowire configuration. In some embodiments, the transistors 102A to 102C may be n-type field-effect transistors (NFETs). In some embodiments, the transistors 102A to 102C may be p-type field-effect transistors (PFETs). In some embodiments, any one of the transistors 102A to 102C may be an NFET or a PFET. In some embodiments, the transistor 102A may be an NFET, while the transistors 102B and 102C may be PFETs. Although FIG. 1 shows three transistors, the semiconductor device 100 may have any number of transistors. In addition, the semiconductor device 100 may be incorporated into an IC via the use of other structural components such as conductive vias, conductive lines, dielectric layers, passivation layers, and interconnects, which are not shown for simplicity. Unless otherwise mentioned, the descriptions of the elements of the transistors 102A to 102C with the same reference symbols apply to each other. Moreover, the same reference symbols generally indicate the same, functionally similar, and / or structurally similar elements.

[0014] Referring to FIGS. 1 to 5C, a semiconductor device 100 having transistors 102A to 102C can be formed on a substrate 104 and isolated by shallow trench isolation (STI) regions 106. Each of the transistors 102A to 102C can include a fin structure 108, sidewall spacers 109, a gate dielectric layer 124, a gate structure 112, gate spacers 114, internal spacers 121, S / D structures 110, an etch stop layer (ESL) 116, and an interlayer dielectric (ILD) layer 118. In some embodiments, as shown in FIGS. 2A to 2B, the transistors 102A to 102C can have nanostructures 122-1, 122-2, and 122-3 (collectively referred to as "nanostructures 122") on the fin structure 108.

[0015] Referring to FIGS. 1 to 3, the substrate 104 can include a semiconductor material, such as silicon. In some embodiments, the substrate 104 includes a crystalline silicon substrate (e.g., a silicon wafer). In some embodiments, the substrate 104 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, and / or aluminum gallium arsenide; or (iv) a combination thereof. Additionally, the substrate 104 can be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 can be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0016] The STI regions 106 can provide electrical isolation between the transistors 102A to 102C and are formed adjacent to transistors (not shown) on the substrate 104 and / or adjacent active and passive components (not shown) integrated with or deposited on the substrate 104. The STI regions 106 can be made of a dielectric material. In some embodiments, the STI regions 106 can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the STI regions 106 can include a multi-layer structure.

[0017] Referring to FIGS. 1 to 3, the nanostructure 122 and the fin structure 108 can be formed on the patterned portion of the substrate 104. The embodiments of the nanostructures and fin structures disclosed herein can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multi-patterning processes) can be used to pattern the nanostructures and fin structures. The double patterning or multi-patterning process can combine photolithography and self-alignment processes to form a pattern having a pitch smaller than, for example, the pitch that can be obtained using a single direct photolithography process. For example, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a photolithography process. A spacer can be formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern the nanostructures and fin structures.

[0018] As shown in FIGS. 1 to 3, the nanostructure 122 and the fin structure 108 can extend along the X-axis of the transistors 102A to 102C. In some embodiments, the nanostructure 122 and the fin structure 108 can be disposed on the substrate 104. The nanostructure 122 can include a stack of nanostructures 122-1, 122-2, and 122-3 that can be in the form of nanosheets, nanowires, or nanobelts. Each of the nanostructures 122 can serve as a channel structure and form a channel region under the gate structure 112 of the transistors 102A to 102C. In some embodiments, the nanostructure 122 and the fin structure 108 can include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructure 122 and the fin structure 108 can include silicon. In some embodiments, the nanostructure 122 and the fin structure 108 can include silicon germanium. The semiconductor materials of the nanostructure 122 and the fin structure 108 can be undoped or can be doped in-situ during their formation process. In some embodiments, as shown in FIGS. 2A and 3, the nanostructure 122 under the gate structure 112 can form the channel region of the semiconductor device 100 and represent the current-carrying channel structure of the semiconductor device 100. Although three layers of nanostructures 122 are shown in FIGS. 2A and 3, the transistors 102A to 102C can have any number of nanostructures 122.

[0019] In some embodiments, the nanostructure 122 may have a thickness ranging from about 5 nm to about 8 nm along the Z-axis. In some embodiments, the nanostructure 122 may have a width ranging from about 15 nm to about 50 nm along the Y-axis. In some embodiments, the spacing between adjacent nanostructures 122 along the Z-axis may range from about 8 nm to about 12 nm. In some embodiments, as shown in FIG. 5A, the nanostructure 122 may have a square end portion. In some embodiments, as shown in FIG. 5B, the nanostructure 122 may have a convex end portion. In some embodiments, as shown in FIG. 5C, the nanostructure 122 may have a concave end portion.

[0020] Referring to FIGS. 1 to 3, the gate dielectric layer 124 may be formed on the nanostructure 122, the fin structure 108, and the STI region 106. In some embodiments, the gate dielectric layer 124 may be a multi-layer structure and may include an interface layer and a high-k dielectric layer. In some embodiments, the gate dielectric layer 124 may not include an interface layer and a high-k dielectric layer in direct contact with the nanostructure 122. In some embodiments, the interface layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the interface layer may have a thickness ranging from about 0.1 nm to about 1.5 nm. In some embodiments, the high-k dielectric layer may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials.

[0021] In some embodiments, as shown in FIGS. 1 to 3, the gate structure 112 may be disposed on the gate dielectric layer 124. In some embodiments, the gate structure 112 may include one or more work function metal layers and a metal filler. The one or more work function metal layers may include work function metals to adjust the threshold voltage (Vt) of the transistors 102A to 102C. In some embodiments, the gate structures 112 of the NFET and PFET devices may have substantially the same work function metal. In some embodiments, the gate structures 112 of the NFET and PFET devices may have different work function metals. In some embodiments, as shown in FIGS. 2A and 3, each of the nanostructures 122 may be surrounded by the gate structure 112, in which case the gate structure 112 may be referred to as a "gate-all-around (GAA) structure", and the transistors 102A to 102C may also be referred to as "GAA FETs 102A to 102C". The one or more work function metal layers may surround the nanostructure 122 and may include work function metals to adjust the Vt of the transistors 102A to 102C. In some embodiments, the transistors 102A to 102C may include any number of work function metal layers for Vt adjustment (e.g., ultra-low Vt, low Vt, and standard Vt).

[0022] In some embodiments, NFETs 102A - 102C may include an n-type work function metal layer. The n-type work function metal layer may include aluminum, titanium aluminum, titanium aluminum carbon, tantalum aluminum, tantalum aluminum carbon, tantalum silicon carbide, hafnium carbide, silicon, titanium nitride, titanium nitride silicon, or other suitable work function metals. In some embodiments, PFETs 102A - 102C may include a p-type work function metal layer. The p-type work function metal layer may include titanium nitride, titanium nitride silicon, tantalum nitride, tungsten carbon nitride, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a stack of metal layers. The stack of metal layers may include work function metals having work function values equal to or different from each other. In some embodiments, the metal fill may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0023] Referring to FIGS. 1 to 3, according to some embodiments, the gate spacer 114 may be disposed on the sidewalls of the gate structure 112 and in contact with the gate dielectric layer 124. The sidewall spacer 109 may be disposed on the sidewalls of the fin structure 108. The internal spacer 121 may be arranged adjacent to the end portion of the nanostructure 122 and disposed between the S / D structure 110 and the gate structure 112. The gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, low-k materials, and combinations thereof. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include the same insulating material. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include different insulating materials. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include a single layer of insulating layer or a stack of insulating layers. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may have a low-k material with a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8).

[0024] The S / D structure 110 can be deposited on the fin structure 108 and on opposite sides of the gate structure 112. The S / D structure 110 can be used as the S / D regions of the transistors 102A - 102C. In some embodiments, the S / D structure 110 can have any geometric shape, such as polygonal, conical, rhombic, elliptical, or circular. In some embodiments, the S / D structure 110 can comprise an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the S / D structure 110 can comprise an epitaxially grown semiconductor material different from the material of the substrate 104, such as silicon germanium, and strain can be applied to the channel region under the gate structure 112. Since the lattice constant of this epitaxially grown semiconductor material is different from the material of the substrate 104, the channel region is strained to increase the carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material can comprise: (i) semiconductor materials, such as germanium and silicon; (ii) compound semiconductor materials, such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys, such as silicon germanium and gallium phosphide arsenide.

[0025] In some embodiments, the S / D structure 110 can comprise silicon and can be in-situ doped with n-type dopants (such as phosphorus and arsenic) during the epitaxial growth process. For n-type in-situ doping, n-type dopant precursors, such as phosphine, arsine, and other n-type dopant precursors, can be used. In some embodiments, the S / D structure 110 can comprise silicon, silicon germanium, germanium, or III-V materials (such as indium antimonide, gallium antimonide, or indium gallium antimonide) and can be in-situ doped with p-type dopants (such as boron, indium, and gallium) during the epitaxial growth process. For p-type in-situ doping, p-type dopant precursors, such as diborane (B2H6), boron trifluoride (BF3), and other p-type dopant precursors, can be used.

[0026] In some embodiments, the S / D structure 110 can comprise one or more epitaxial layers, where each epitaxial layer can have a different composition. In some embodiments, as shown in FIGS. 1 to 3, the S / D structure 110 can comprise an epitaxially grown first epitaxial layer 110-1, a second epitaxial layer 110-2, and a third epitaxial layer 110-3. The first epitaxial layer 110-1 can be epitaxially grown on a partially recessed portion of the substrate 104, the second epitaxial layer 110-2 can be epitaxially grown on the sidewalls of the first epitaxial layer 110-1 and the nanostructure 122, and the third epitaxial layer 110-3 can be epitaxially grown on the second epitaxial layer 110-2. Although FIGS. 1 to 3 illustrate three epitaxial layers of the S / D structure 110, the S / D structure 110 can have one or more epitaxial layers, and each epitaxial layer can have a different composition.

[0027] In some embodiments, each of the first epitaxial layer 110-1, the second epitaxial layer 110-2, and the third epitaxial layer 110-3 may comprise Si and be different from each other based on, for example, doping concentration and / or epitaxial growth process conditions. In some embodiments, each of the first epitaxial layer 110-1, the second epitaxial layer 110-2, and the third epitaxial layer 110-3 may comprise silicon germanium and be different from each other based on, for example, doping concentration, epitaxial growth process conditions, and / or the relative concentration of germanium to silicon. For example, the percentage of germanium atoms in the first epitaxial layer 110-1 may be less than the percentage of germanium atoms in the second epitaxial layer 110-2 and the third epitaxial layer 110-3. In some embodiments, the first epitaxial layer 110-1 may comprise silicon without germanium. In some embodiments, the second epitaxial layer 110-2 may comprise germanium in the range of from about 0 atomic percent to about 50 atomic percent, while the third epitaxial layer 110-3 may comprise germanium in the range of from about 50 atomic percent to about 80 atomic percent, where any remaining atomic percent is Si.

[0028] In some embodiments, the first epitaxial layer 110-1, the second epitaxial layer 110-2, and the third epitaxial layer 110-3 may have different dopant concentrations from each other. For example, the dopant concentration of the first epitaxial layer 110-1 may be lower than the dopant concentrations of the second epitaxial layer 110-2 and the third epitaxial layer 110-3. The dopant concentration of the second epitaxial layer 110-2 may be lower than the dopant concentration of the third epitaxial layer 110-3. In some embodiments, the first epitaxial layer 110-1 may be undoped. The second epitaxial layer 110-2 may be doped with boron having a concentration of less than about 5×10²⁰ atoms / cm³ (e.g., from about 1×10²⁰ atoms / cm³ to about 5×10²⁰ atoms / cm³). The third epitaxial layer 110-3 may be doped with boron having a concentration in the range of from about 5×10²⁰ atoms / cm³ to about 2×10²¹ atoms / cm³. The higher dopant concentration in the third epitaxial layer 110-3 may reduce the contact resistance between the S / D structure 110 and the S / D contact structure 130.

[0029] In some embodiments, the second epitaxial layer 110-2 may include one or more dopant clusters. For example, as shown in FIG. 2A, the second epitaxial layer 110-2 may include horizontal dopant clusters 113h1, 113h2, and 113h (collectively referred to as "horizontal dopant clusters 113h"). The horizontal dopant clusters 113h may extend between adjacent stacks of the nanostructure 122 along the direction of the nanostructure 122. In some embodiments, the horizontal dopant clusters 113h may extend from the nanostructure 122 to the third epitaxial layer 110-3. In some embodiments, the dopants in the second epitaxial layer 110-2 may aggregate on the (111) growth surface of the second epitaxial layer 110-2, and the horizontal dopant clusters 113h may be formed along the intersection of the (111) growth surfaces. In some embodiments, the range of the angle 100α between the (111) growth surface and the horizontal direction along the nanostructure 110 may be between about 40 degrees and about 70 degrees.

[0030] In some embodiments, the concentration of the dopants in the horizontal dopant clusters 113h may be more than ten times greater than the concentration of the dopants in the second epitaxial layer 110-2 and the concentration of the dopants on other surfaces (such as the (001) surface) of the second epitaxial layer 110-2. For example, the horizontal dopant clusters 113h may include aggregates of boron dopants having a concentration of about 5×10²⁰ atoms / cm³ to about 5×10²¹ atoms / cm³. In some embodiments, during the process of forming the sheet of the nanostructure 122, the high dopant concentration in the horizontal dopant clusters 113h may increase the etching resistance of the S / D structure 110 and / or the internal spacer 121. Therefore, the horizontal dopant clusters 113h may reduce the etching damage to the S / D structure 110, reduce the gate-S / D short circuit defects, and improve the device performance and yield of the semiconductor device 100. If the dopant concentration in the horizontal dopant clusters 113h is less than about 5×10²⁰ atoms / cm³, the etching damage to the S / D structure 110 may not be reduced. If the dopant concentration in the horizontal dopant clusters 113h is greater than about 5×10²¹ atoms / cm³, more dopants may diffuse into the nanostructure 122 and may increase the device leakage current.

[0031] Referring to FIGS. 4A to 4D, the horizontal dopant clusters 113h may have different shapes. In some embodiments, as shown in FIG. 4A, the horizontal dopant cluster 113h may have an elliptical shape, with its length 113l ranging from about 0 nm to about 10 nm and its width 113w ranging from about 0 nm to about 4 nm. In some embodiments, as shown in FIG. 4B, the horizontal dopant cluster 113h may have a square shape, with its length 113l ranging from about 0 nm to about 10 nm and its width 113w ranging from about 0 nm to about 4 nm. In some embodiments, as shown in FIG. 4C, the horizontal dopant cluster 113h may have a fan shape, with its length 113l ranging from about 0 nm to about 10 nm and its angle 113α ranging from about 0 degrees to about 60 degrees. In some embodiments, as shown in FIG. 4D, the horizontal dopant cluster 113h may include a plurality of circles along a line, with its length 113l ranging from about 0 nm to about 10 nm and the diameter 113d of the circles ranging from about 0 nm to about 2 nm.

[0032] In some embodiments, the horizontal dopant clusters 113h adjacent to the top nanostructure 122-1, the middle nanostructure 122-2, and the bottom nanostructure 122-3 may have different sizes. In some embodiments, the horizontal dopant cluster 113h1 adjacent to the top nanostructure 122-1 may have a larger size (e.g., width 113w and / or length 113l) than the horizontal dopant cluster 113h2 adjacent to the middle nanostructure 122-2. In some embodiments, the horizontal dopant cluster 113h2 adjacent to the middle nanostructure 122-2 may have a larger size (e.g., width 113w and / or length 113l) than the horizontal dopant cluster 113h3 adjacent to the bottom nanostructure 122-3.

[0033] In some embodiments, as shown in FIG. 3, the second epitaxial layer 110-2 may include horizontal dopant clusters 113h and inclined dopant clusters 113s1, 113s2, and 113s3 (collectively referred to as "inclined dopant clusters 113s"). In some embodiments, the dopants in the second epitaxial layer 110-2 may aggregate on the (111) growth surface of the second epitaxial layer 110-2 and form inclined dopant clusters 113s. In some embodiments, the inclined dopant clusters 113s may extend along the (111) growth surface of the second epitaxial layer 110-2 and intersect the horizontal dopant clusters 113h. In some embodiments, the (111) growth surface of the second epitaxial layer 110-2 may contact the third epitaxial layer 110-3. Therefore, the inclined dopant clusters 113s may extend along the interface between the second epitaxial layer 110-2 and the third epitaxial layer 110-3. In some embodiments, the angle between the inclined dopant clusters 113s and the horizontal dopant clusters 113h may be substantially the same as the angle 110α, and the range of this angle may be between about 40 degrees and about 70 degrees. In some embodiments, the inclined dopant clusters 113s may extend along the (111) growth surface to the internal spacer 121 and may contact the internal spacer 121.

[0034] In some embodiments, the concentration of the dopants in the inclined dopant clusters 113s may be more than ten times greater than the concentration of the dopants in the second epitaxial layer 110-2 and the concentration of the dopants on other surfaces of the second epitaxial layer 110-2 (e.g., the (001) surface). For example, the inclined dopant clusters 113s may include aggregates of boron dopants having a concentration of about 5×10^20 atoms / cm^3 to about 5×10^21 atoms / cm^3. In some embodiments, the dopant concentration in the horizontal dopant clusters 113h may be greater than the dopant concentration in the inclined dopant clusters 113s. In some embodiments, during the formation process of the nanosheet structure 122, the high dopant concentrations in both the horizontal dopant clusters 113h and the inclined dopant clusters 113s may further increase the etching resistance of the S / D structure 110 and / or the internal spacer 121. Therefore, the horizontal dopant clusters 113h and the inclined dopant clusters 113s may further reduce the etching damage to the S / D structure 110, reduce the gate-S / D short circuit defects, and improve the device performance and yield of the semiconductor device 100.

[0035] In some embodiments, similar to the horizontal dopant cluster 113h described above, the tilted dopant cluster 113s may have different shapes and sizes, as shown in FIGS. 4A to 4D. In some embodiments, similar to the horizontal dopant cluster 113h, the tilted dopant clusters 113s adjacent to the top nanostructure 122-1, the middle nanostructure 122-2, and the bottom nanostructure 122-3 may have different sizes. In some embodiments, the tilted dopant cluster 113s1 adjacent to the top nanostructure 122-1 may have a larger size (e.g., width 113w and / or length 113l) than the tilted dopant cluster 113s2 adjacent to the middle nanostructure 122-2. In some embodiments, the tilted dopant cluster 113s2 adjacent to the middle nanostructure 122-2 may have a larger size (e.g., width 113w and / or length 113l) than the tilted dopant cluster 113s3 adjacent to the bottom nanostructure 122-3.

[0036] The ESL 116 may be disposed on the STI region 106, on the S / D structure 110, and on the sidewalls of the gate spacer 114 and the sidewall spacer 109. The ESL 116 can be used to protect the STI region 106, the S / D structure 110, and the gate structure 112 during the formation of the S / D contact structure 130 on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon boron nitride, silicon carbon boron nitride, or combinations thereof.

[0037] The ILD layer 118 may be disposed on the ESL 116 above the S / D structure 110 and the STI region 106. The ILD layer 118 may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material. For example, flowable silicon oxide can be deposited using flowable chemical vapor deposition (FCVD). In some embodiments, the dielectric material may include silicon oxide.

[0038] In some embodiments, as shown in FIGS. 1 to 3, the semiconductor device 100 may further include an S / D contact structure 130. In some embodiments, the S / D contact structure 130 may be disposed on the S / D structure 110. In some embodiments, the S / D contact structure 130 may include a silicide layer and a metal contact structure. In some embodiments, the silicide layer may include a metal silicide and may provide a lower resistance interface between the metal contact structure and the S / D structure 110. Examples of metals used to form the metal silicide include cobalt, titanium, and nickel. In some embodiments, the metal contact structure may include a conductive material such as tungsten, aluminum, and cobalt. In some embodiments, as shown in FIGS. 1 to 3, the S / D contact structure 130 may extend into the S / D structure 110 and may contact the horizontal dopant clusters 113h and / or the tilted dopant clusters 113s. In some embodiments, the high dopant concentration in the horizontal dopant clusters 113h and the tilted dopant clusters 113s may further reduce the contact resistance between the S / D contact structure 130 and the S / D structure 110.

[0039] In some embodiments, the horizontal dopant clusters 113h and the tilted dopant clusters 113s may include hydrogen, chlorine, carbon, fluorine, oxygen, and / or titanium due to the materials used during the process flow. For example, during the epitaxial growth of the S / D structure using a hydrogen chloride-containing gas, hydrogen and chlorine may diffuse into the horizontal dopant clusters 113h and the tilted dopant clusters 113s. During the deposition process of the ESL 116 and / or the ILD layer 118, carbon and oxygen in the dielectric material may diffuse into the horizontal dopant clusters 113h and the tilted dopant clusters 113s. During the patterning process of the nanostructure 122, fluorine in the fluorine-based etchant may diffuse into the horizontal dopant clusters 113h and the tilted dopant clusters 113s. During the formation of the S / D contact structure, titanium in the silicide layer may diffuse into the horizontal dopant clusters 113h and the tilted dopant clusters 113s.

[0040] FIG. 6 is a flowchart of a method 600 for manufacturing a semiconductor device 100 having an S / D structure with dopant clusters according to some embodiments. The method 600 is not limited to nanostructure transistor devices and can be applied to other devices that would benefit from an S / D structure with dopant clusters. Additional manufacturing operations can be performed between the various operations of the method 600, and these additional manufacturing operations are omitted for clarity and simplicity of description only. Additional processes can be provided before, during, and / or after the method 600; one or more of these additional processes are briefly described herein. Further, not all operations may be required to practice the disclosure provided herein. Additionally, some operations can be performed simultaneously or in an order different from that shown in FIG. 6. In some embodiments, one or more other operations can be performed in addition to or in place of the currently described operations.

[0041] For illustrative purposes, the operations illustrated in FIG. 6 will be described with reference to an exemplary manufacturing process for manufacturing the semiconductor device 100 illustrated in FIGS. 7 to 22B. FIGS. 7 to 22B illustrate partial isometric views and partial cross-sectional views of the semiconductor device 100 having an S / D structure with dopant clusters at various manufacturing stages according to some embodiments. FIGS. 7, 9, 11, 13, 15, 17, 19, and 21 illustrate partial isometric views of the semiconductor device 100 at various manufacturing stages according to some embodiments. FIGS. 8A, 10A, 12A, 14A, 16A, 18A, 20A, and 22A illustrate partial cross-sectional views of the semiconductor device 100 along line A-A as shown in FIG. 1 at various manufacturing stages according to some embodiments. FIGS. 8B, 10B, 12B, 14B, 16B, 18B, 20B, and 22B illustrate partial cross-sectional views of the semiconductor device 100 along line B-B as shown in FIG. 1 at various manufacturing stages according to some embodiments. Elements having the same element symbols as those in FIGS. 1 to 5C are described above in FIGS. 7 to 22B.

[0042] Referring to FIG. 6, method 600 begins with operation 610 and a process of forming a channel structure on a substrate. For example, as shown in FIGS. 7, 8A, and 8B, nanostructures 122 and 822 may be formed on substrate 104. In some embodiments, nanostructures 122 and 822 may be stacked in an alternating configuration. In some embodiments, nanostructures 122 and 822 may be epitaxially grown on substrate 104 and then patterned to form a stack of nanostructures 122 and 822. In some embodiments, nanostructures 122 and 822 may be in the form of nanosheets, nanowires, or nanoribbons. In some embodiments, nanostructures 122 and 822 may comprise a semiconductor material similar to or different from substrate 104. In some embodiments, nanostructures 122 and 822 may comprise different semiconductor materials. For example, nanostructure 122 may comprise silicon, while nanostructure 822 may comprise silicon germanium having a germanium atomic percentage of about 10% to about 40%.

[0043] Embodiments of nanostructures 122 and 822 disclosed herein may be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multi-patterning processes) may be used to pattern the nanostructures. Double patterning or multi-patterning processes may combine photolithography and self-alignment processes to form patterns having, for example, a smaller pitch than can be obtained using a single direct photolithography process. For example, a sacrificial layer is formed above the substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process may be used to form spacers beside the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the nanostructures.

[0044] After forming nanostructure 122, the following steps may be performed: forming STI region 106 between adjacent stacks of nanostructures 122 and 822; forming a sacrificial gate structure 712 on nanostructure 122; forming gate spacers 114 and 718 on the sidewalls of sacrificial gate structure 712; recessing nanostructures 122 and 822; and depositing an internal spacer layer 721 in the grooves, as shown in FIGS. 7, 8A, and 8B. For clarity, these processes are not described in detail.

[0045] In some embodiments, an etching process may be performed after depositing internal spacer layer 721 to form internal spacers 121, as shown in FIGS. 9, 10A, and 10B. In some embodiments, the etching process may be a directional etching process for removing internal spacer layer 721 on the sidewalls of nanostructure 122 and the top surface of fin structure 108.

[0046] Referring to FIG. 6, in operation 620, a first epitaxial layer is formed on a substrate adjacent to the channel structure. For example, as shown in FIGS. 11, 12A, and 12B, the first epitaxial layer 110-1 can be formed on the substrate 104 adjacent to the nanostructure 122. In some embodiments, the first epitaxial layer 110-1 can be epitaxially grown on the fin structure 108 above the substrate 104 using a bottom-up growth method. In some embodiments, the first epitaxial layer 110-1 can comprise intrinsic silicon without dopants. In some embodiments, the first epitaxial layer 110-1 can be formed on the fin structures 108 of the transistors 102A to 102C. In some embodiments, the first epitaxial layer 110-1 can be formed on an n-type transistor, where the p-type transistor is blocked by a hard mask layer.

[0047] In some embodiments, an n-type S / D structure (e.g., S / D structure 110A) can be formed before a p-type S / D structure (e.g., S / D structure 110B). For example, as shown in FIGS. 13, 14A, and 14B, the n-type S / D structure 110A can be formed on the fin structure 108 covered with the dielectric layer 1316. The hard mask layers 1332 and 1334 can be formed on the sacrificial gate structure 712. The hard mask layer 1336 can be formed on the transistor 102A and patterned to expose the transistor 102B for epitaxial growth of the S / D structure 110B. In some embodiments, the dielectric layer 1316 on the transistor 102B can be removed by an etching process. A pre-cleaning process can clean any residual dielectric material on the first epitaxial layer 110-1. After the etching and pre-cleaning processes, the first epitaxial layer 110-1 of the transistor 102B can be exposed for epitaxial growth of additional layers, as shown in FIGS. 15, 16A, and 16B.

[0048] Referring to FIG. 6, in operation 630, a second epitaxial layer is formed on the sidewalls of the first epitaxial layer and the channel structure. The second epitaxial layer comprises clusters of dopants extending in the direction of the channel structure. For example, as shown in FIGS. 17, 18A, and 18B, the second epitaxial layer 110-2 can be formed on the sidewalls of the first epitaxial layer 110-1 and the nanostructure 122. In some embodiments, the second epitaxial layer 110-2 can comprise horizontal dopant clusters 113h in the direction of the nanostructure 122, as shown in FIG. 2A. In some embodiments, the second epitaxial layer 110-2 can comprise horizontal dopant clusters 113h in the direction of the nanostructure 122 and inclined dopant clusters 113s along the (111) growth plane of the second epitaxial layer 110-2, as shown in FIG. 3. In some embodiments, the horizontal dopant clusters 113h and the inclined dopant clusters 113s in the second epitaxial layer 110-2 can comprise aggregates of boron.

[0049] In some embodiments, during the epitaxial growth of the second epitaxial layer 110-2, the dopant-containing precursor can be controlled at a substantially constant flow rate to form a peak dopant concentration greater than about 5×10²⁰ atoms / cm³. In some embodiments, horizontal dopant clusters 113h and / or inclined dopant clusters 113s can be formed in the second epitaxial layer 110-2 during epitaxial growth. In some embodiments, the dopants in the second epitaxial layer 110-2 can aggregate on the (111) growth surface of the second epitaxial layer 110-2, and the horizontal dopant clusters 113h can be formed along the intersection of the (111) growth surfaces. In some embodiments, the dopants in the second epitaxial layer 110-2 can aggregate on the (111) growth surface of the second epitaxial layer 110-2 and form inclined dopant clusters 113s. In some embodiments, the angle between the inclined dopant clusters 113s and the horizontal dopant clusters 113h can range from about 40 degrees to about 70 degrees. In some embodiments, the inclined dopant clusters 113s can extend along the (111) growth surface to the internal spacer 121 and can contact the internal spacer 121.

[0050] In some embodiments, the second epitaxial layer 110-2 can comprise a silicon-germanium having a germanium concentration of about 0 atomic percent to about 50 atomic percent, where any remaining atomic percent is Si. In some embodiments, the horizontal dopant clusters 113h and the inclined dopant clusters 113s can comprise aggregates of boron having a concentration of about 5×10²⁰ atoms / cm³ to about 5×10²¹ atoms / cm³. In some embodiments, the second epitaxial layer 110-2 can be doped with boron having a concentration less than about 5×10²⁰ atoms / cm³ (e.g., from about 1×10²⁰ atoms / cm³ to about 5×10²⁰ atoms / cm³) during epitaxial growth. In some embodiments, the concentration of the dopants in the horizontal dopant clusters 113h and / or the inclined dopant clusters 113s can be more than ten times greater than the concentration of the dopants in the second epitaxial layer 110-2 and the concentration of the dopants on other surfaces (e.g., the (001) surface) of the second epitaxial layer 110-2. In some embodiments, the concentration of the dopants in the horizontal dopant clusters 113h can be greater than the concentration of the dopants in the inclined dopant clusters 113s.

[0051] In some embodiments, during the formation process of the nanosheets of the nanostructure 122, the high dopant concentration in the horizontal dopant clusters 113h and / or the tilted dopant clusters 113s can increase the etching resistance of the S / D structure 110 and / or the internal spacer 121. Accordingly, the horizontal dopant clusters 113h and the tilted dopant clusters 113s can reduce the etching damage to the S / D structure 110, reduce gate-S / D short circuit defects and improve the device performance and yield of the semiconductor device 100. If the dopant concentration in the horizontal dopant clusters 113h and / or the tilted dopant clusters 113s is less than about 5×10²⁰ atoms / cm³, the etching damage to the S / D structure 110 may not be reduced. If the dopant concentration in the horizontal dopant clusters 113h and / or the tilted dopant clusters 113s is greater than about 5×10²¹ atoms / cm³, more dopants can diffuse into the nanostructure 122 and increase the device leakage current.

[0052] Referring to FIG. 6, in operation 640, a third epitaxial layer is formed on the second epitaxial layer. For example, as shown in FIGS. 19, 20A, and 20B, the third epitaxial layer 110-3 can be formed on the second epitaxial layer 110-2. In some embodiments, the third epitaxial layer 110-3 can be epitaxially grown on the (111) growth surface of the second epitaxial layer 110-2. Accordingly, the tilted dopant clusters 113s can extend along the interface between the second epitaxial layer 110-2 and the third epitaxial layer 110-3. In some embodiments, the third epitaxial layer 110-3 can comprise silicon germanium having a germanium concentration of about 50 atomic percent to about 80 atomic percent, with any remaining atomic percent being Si. In some embodiments, the germanium concentration in the third epitaxial layer 110-3 can be greater than the germanium concentration in the second epitaxial layer 110-2. In some embodiments, the third epitaxial layer 110-3 can be doped with boron having a concentration in the range of about 5×10²⁰ atoms / cm³ to about 2×10²¹ atoms / cm³ during epitaxial growth. In some embodiments, the dopant concentration in the third epitaxial layer 110-3 can be greater than the dopant concentration in the second epitaxial layer 110-2 to reduce the contact resistance between the S / D structure 110 and the subsequently formed S / D contact structure 130. In some embodiments, an annealing process can be performed after the formation of the third epitaxial layer 110-3. In some embodiments, the horizontal dopant clusters 113h and the tilted dopant clusters 113s in the second epitaxial layer 110-2 can be retained after the annealing process.

[0053] After forming the third epitaxial layer 110-3, the dielectric layer 1316 can be removed, as shown in FIGS. 21, 22A, and 22B. After removing the dielectric layer 1316, the following steps can be performed: forming an ESL 116; forming an ILD layer 118; replacing the sacrificial gate structure 712 with a metal gate structure 112; and forming an S / D contact structure 130 to form the semiconductor device 100 as shown in FIGS. 1 to 3. For the sake of brevity, these processes are not described in detail. In some embodiments, as shown in FIGS. 1 to 3, the S / D contact structure 130 can extend into the S / D structure 110 and can contact the horizontal dopant clusters 113h and / or the tilted dopant clusters 113s. In some embodiments, the high dopant concentration in the horizontal dopant clusters 113h and the tilted dopant clusters 113s can further reduce the contact resistance between the S / D contact structure 130 and the S / D structure 110.

[0054] Various embodiments in the present disclosure provide exemplary methods for forming an S / D structure 110 having horizontal dopant clusters 113h in a semiconductor device 100. In some embodiments, a nanostructure 122 can be formed on a substrate 104. The S / D structure 110 can be formed on the substrate 104 and adjacent to the nanostructure 122. In some embodiments, the S / D structure 110 can include a first epitaxial layer 110-1 on the substrate 104, a second epitaxial layer 110-2 on the sidewalls of the first epitaxial layer 110-1 and the nanostructure 122, and a third epitaxial layer 110-3 on the second epitaxial layer 110-2. In some embodiments, the second epitaxial layer 110-2 can include horizontal dopant clusters 113h extending along the direction of the nanostructure 122. In some embodiments, a first concentration of dopants in the horizontal dopant clusters 113h can be more than about ten times greater than the concentration of dopants in the second epitaxial layer 110-2. In some embodiments, the horizontal dopant clusters 113h can extend along the intersection of the (111) growth planes of the second epitaxial layer. In some embodiments, the second epitaxial layer 110-2 can include tilted dopant clusters 113s along the (111) growth plane of the second epitaxial layer 110-2. The horizontal dopant clusters 113h and the tilted dopant clusters 113s can reduce the etching damage to the S / D structure 110, reduce gate-S / D short circuit defects, and improve device performance and yield.

[0055] In some embodiments, the semiconductor structure includes a channel structure on a substrate and an epitaxial structure on the substrate and adjacent to the channel structure. The epitaxial structure includes a first epitaxial layer on the sidewalls of the channel structure and a second epitaxial layer on the first epitaxial layer. The first epitaxial layer includes clusters of dopants extending along the direction of the channel structure.

[0056] In some embodiments, a semiconductor device includes a first channel structure and a second channel structure located on a substrate, and a source / drain (S / D) structure located between the first channel structure and the second channel structure. The S / D structure includes a first epitaxial layer located on sidewalls of the first channel structure and the second channel structure, and a second epitaxial layer located on the first epitaxial layer. The first epitaxial layer includes a first cluster of dopants extending from the first channel structure toward the second channel structure.

[0057] In some embodiments, a method includes: forming a channel structure on a substrate; forming a first epitaxial layer on sidewalls of the substrate and the channel structure; and forming a second epitaxial layer on the first epitaxial layer. The first epitaxial layer includes a cluster of dopants extending along a direction of the channel structure.

[0058] It should be understood that the detailed description section, rather than the abstract section of the disclosure, is intended to interpret the scope of the patent application. The abstract of the disclosure section may set forth one or more but not all possible embodiments as contemplated by the inventor, and thus is not intended to limit the scope of the appended patent application in any way.

[0059] The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

[0060] 100: Semiconductor device 100α, 113α: Angles 102A~102C: Transistors 104: Substrate 106: STI region 108: Fin structure 109: Sidewall spacer 110, 110A, 110B: S / D structures 110-1: First epitaxial layer 110-2: Second epitaxial layer 110-3: Third epitaxial layer 112: Gate structure 113d: Circular diameter 113h, 113h1, 113h2, 113h3: Horizontal dopant clusters 113l: Length 113s, 113s1, 113s2, 113s3: Inclined dopant clusters 113w: Width 114, 718: Gate spacers 116: ESL 118: ILD layer 121: Inner spacer 122, 122 - 1, 122 - 2, 122 - 3, 822: Nanostructures 124: Gate dielectric layer 130: S / D contact structure 600: Method 610, 620, 630, 640: Operations 712: Sacrificial gate structure 721: Inner spacer layer 1316: Dielectric layer 1332, 1334, 1336: Hard mask layers A - A, B - B: Lines

[0061] Domestic deposit information (Please note in the order of deposit institution, date, and number) None Foreign deposit information (Please note in the order of deposit country, institution, date, and number) None

Claims

1. A semiconductor structure, comprising: A channel structure located on a substrate; An epitaxial structure is located on the substrate and adjacent to the channel structure, wherein the epitaxial structure includes: a first epitaxial layer located on a plurality of sidewalls of the channel structure, wherein the first epitaxial layer includes a cluster of dopants extending along a direction of the channel structure; a second epitaxial layer located on the first epitaxial layer; and an additional epitaxial layer located between the first epitaxial layer and the substrate, wherein the germanium concentration in the first epitaxial layer is greater than the germanium concentration in the additional epitaxial layer and less than the germanium concentration in the second epitaxial layer.

2. The semiconductor structure as claimed in claim 1, wherein a first concentration of the dopant in the cluster is greater than a second concentration of the dopant in the first epitaxial layer.

3. The semiconductor structure as claimed in claim 1, wherein the first epitaxial layer further includes an additional cluster of the dopant extending along an interface between the first epitaxial layer and the second epitaxial layer.

4. The semiconductor structure as claimed in claim 1, further comprising a contact structure extending into the epitaxial structure, wherein the cluster is in contact with the contact structure.

5. The semiconductor structure as described in claim 1, further comprising an internal spacer between the channel structure and the epitaxial structure.

6. A semiconductor device, comprising: The first channel structure and the second channel structure are located on a substrate; and a source / drain structure located between the first channel structure and the second channel structure, wherein the source / drain structure includes: a first epitaxial layer located on a plurality of sidewalls of the first channel structure and the second channel structure, wherein the first epitaxial layer includes a first cluster of dopant extending from the first channel structure toward the second channel structure; a second epitaxial layer located on the first epitaxial layer; and an additional epitaxial layer located between the first epitaxial layer and the substrate, wherein the germanium concentration in the first epitaxial layer is greater than the germanium concentration in the additional epitaxial layer and less than the germanium concentration in the second epitaxial layer.

7. The semiconductor device as claimed in claim 6, wherein a first concentration of the dopant in the first cluster is greater than a second concentration of the dopant in the first epitaxial layer.

8. The semiconductor device as claimed in claim 6, wherein the first epitaxial layer further includes a second cluster of the dopant located at an interface between the first epitaxial layer and the second epitaxial layer, and wherein a first concentration of the dopant in the first cluster is greater than a second concentration of the dopant in the second cluster.

9. A method for forming a semiconductor device, comprising: A channel structure is formed on a substrate; A first epitaxial layer is formed on the substrate and multiple sidewalls of the channel structure, wherein the first epitaxial layer includes a cluster of dopants extending along a direction of the channel structure; a second epitaxial layer is formed on the first epitaxial layer; and an additional epitaxial layer is formed before the formation of the first epitaxial layer, wherein after the formation of the first epitaxial layer, the additional epitaxial layer is located between the first epitaxial layer and the substrate, wherein the germanium concentration in the first epitaxial layer is greater than the germanium concentration in the additional epitaxial layer and less than the germanium concentration in the second epitaxial layer.

10. The method as described in claim 9, further comprising: A contact structure is formed, wherein the cluster is in contact with the contact structure.

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