Method and apparatus for processing substrates

Abstract

This paper presents a method and system for reducing the roughness of EUV photoresist and improving post-etched features. The method may involve depositing a thin film on a patterned EUV photoresist having a stress level that is less compressed than the stress level of the patterned EUV photoresist. The resulting composite stress can reduce bending and / or protrusion of the patterned EUV photoresist.

Description

Substrate Processing Method and Equipment The present invention relates to reducing the roughness of extreme ultraviolet (EUV) photoresist. In the manufacture of micron- and nanoscale components, such as in semiconductor processing for manufacturing semiconductor components, patterning of thin films is typically a critical step. Patterning involves lithography. In conventional optical lithography techniques (e.g., 193 nm optical lithography), patterns are printed by emitting photons from a photon source onto a mask and transferring the pattern onto a photosensitive photoresist, thereby causing a chemical reaction in the photoresist that removes certain portions of the photoresist after development to form the pattern. Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include 22 nm, 16 nm, and other nodes. In the 16 nm node, for example, the width of a typical via or line in an interlayer structure is usually no greater than about 30 nm. The scaling of features on advanced semiconductor integrated circuits (ICs) and other components is driving the improvement of lithography resolution. Extreme ultraviolet (EUV) lithography operates at the 30 nm level with different light sources and photoresist materials. EUV lithography can cause two types of roughness in the photoresist: high-frequency roughness caused by the probability effect of secondary electrons, and low-frequency roughness (also referred to as "wiggling") caused by the interaction between the size, geometry, and mechanical properties of the photoresist material. Both types of roughness are undesirable. Methods and equipment for reducing the roughness of EUV photoresist are disclosed herein. The roughness is reduced by reducing the compressive stress of the photoresist layer. This can be achieved by depositing a conformal film that has less compressive stress, or even tensile stress, compared to the photoresist. The resulting composite stress reduces bending and / or bulging, thereby reducing low-frequency roughness. In one aspect of the embodiments disclosed herein, a method for reducing the roughness of EUV photoresist is provided. The method includes: providing a substrate to a processing chamber, the substrate including a patterned EUV photoresist having a first stress level; and depositing a conformal film on the patterned EUV photoresist, the conformal film having a second stress level that is less compressive than the first stress level, such that a third stress level of the patterned EUV photoresist resulting from the deposition of the conformal film is less compressive than the first stress level. In various implementations, the substrate includes a semiconductor wafer of a semiconductor component in a semi-finished state. In some embodiments, the conformal film has a thickness of no greater than 2 nm. In other embodiments, the conformal film has a thickness of about 1 nm. In some embodiments, the second stress level of the conformal film is tensile. In other embodiments, the second stress level of the conformal film is compressive. In various embodiments, the patterned EUV photoresist is characterized in that, after the deposition, the line roughness is reduced. In some embodiments, the line roughness includes one or more of line edge roughness (LER) and line width roughness (LWR). In various embodiments, the line roughness is a low-frequency line roughness. In some embodiments, the low-frequency line roughness has a spatial frequency of less than 0.05 nm -1 In some embodiments, the line roughness is a high-frequency line roughness. In various embodiments, the high-frequency line roughness has a spatial frequency of greater than 0.05 nm -1 In some embodiments, the line roughness is a high-frequency line roughness. In various embodiments, the high-frequency line roughness has a spatial frequency of greater than 0.05 nm In some embodiments, the conformal film includes a Si-based dielectric. In various embodiments, the dielectric is SiO 2 . In certain embodiments, the conformal film is deposited by ALD. In some embodiments, the ALD includes plasma-enhanced ALD, where one cycle includes flowing a mono-oxygen plasma having a power between 10 W and 2500 W and a duty cycle between 25% and 50%. In some embodiments, the EUV photoresist includes a chemically amplified resist (CAR), an organometal, or an organometal oxide. In various embodiments, the organometal oxide is an organotin oxide. In some embodiments, the line edge roughness is reduced from about 0.1 to 1 nm 4 In certain embodiments, the method also includes: after the deposition of the conformal film, etching the substrate layer in the processing chamber. In another aspect of the embodiments herein, a substrate processing apparatus is provided, the apparatus comprising: one or more processing chambers, each processing chamber comprising a substrate support; one or more gas inlets into the processing chambers and associated flow control hardware; one or more substrate transfer devices; and a controller having at least one processor and a memory, wherein the at least one processor and the memory are communicatively coupled to each other, the at least one processor is at least operatively coupled to the one or more substrate transfer devices and the flow control hardware, the memory stores a plurality of computer-executable instructions for controlling the at least one processor to at least control the one or more substrate transfer devices and the flow control hardware to: provide a substrate to a processing chamber, the substrate comprising a patterned EUV photoresist on a substrate layer to be etched, the patterned EUV photoresist having a first stress level; and deposit a conformal film on the patterned EUV photoresist, the conformal film having a second stress level, the second stress level being less compressive than the first stress level, such that a third stress level of the patterned EUV photoresist resulting from the deposition of the conformal film is less compressive than the first stress level. These and other features of the disclosed embodiments will be described in detail below with reference to the related drawings. In the following description, several specific details are set forth to provide a thorough understanding of the described embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known processing operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. Although specific embodiments will be used to illustrate the disclosed embodiments, it should be understood that it is not intended to limit the disclosed embodiments. Extreme ultraviolet (EUV) lithography can be used in semiconductor manufacturing for technology nodes of 30 nm and below. At increasingly smaller critical dimensions, reducing (e.g., minimizing) the roughness of the photoresist and the resulting etch can improve process yield and device performance. The roughness can be measured by the line edge roughness (LER) and line width roughness (LWR) of the photoresist and the resulting etch. Reducing (e.g., minimizing) both the LER and LWR can improve the results of the EUV lithography etch process. The roughness can have high-frequency and low-frequency components, and these components can be represented using a power spectral density (PSD) curve. FIG. 4 shows a representative PSD curve 402. PSD curves are typically plotted on a log-log graph. The horizontal axis represents the spatial frequency of the roughness (which is also the reciprocal of the wavelength of the roughness, i.e., 0.01 nm -1(= 100 nm), where the vertical axis is the PSD value, which is linearly related to LER or LWR. The area under the PSD curve represents the total variance, which should be minimized for any etching process under ideal conditions. Post-exposure of EUV photoresist has two major types of roughness: low-frequency and high-frequency. High-frequency roughness is characterized by short variations in the photoresist and may be caused by various factors, including secondary electrons inherently emitted during the EUV lithography process. This is the region to the right of the PSD curve 402, at approximately 0.1 nm -1 or higher. Low-frequency roughness is the longer wavelength variation in the photoresist and is shown in the left portion of the PSD curve 402, at approximately 0.01 nm -1 or less. One cause of low-frequency roughness is the compressive stress within the photoresist. The compressive stress within the photoresist causes it to bend and / or bulge, thereby generating low-frequency roughness, sometimes referred to as "wiggling". Some solutions to reduce photoresist roughness include plasma treatment, carbon-based deposition, silicon oxide-based deposition, and etching by-product deposition. Each of these treatments has various drawbacks. Plasma treatment can reduce roughness by reflowing the photoresist, but it also reduces the height and selectivity of the photoresist. Carbon-based deposition may cause clogging at the top of the mask, thereby interfering with the etching process. Conventional silicon oxide-based deposition is selective at high aspect ratios, thereby affecting critical dimensions and potentially leading to line breaks or merges. Etching by-products may reduce the selectivity of the etching process and prevent successful transfer of the photoresist pattern. In addition to the various drawbacks of each solution, they can only address high-frequency roughness. An alternative to reducing roughness is to reduce the compressive stress within the photoresist layer. This can be accomplished by depositing a conformal thin film, and the stress of the conformal thin film is less compressive or even tensile compared to the photoresist. The resulting composite stress reduces bending and / or bulging, thereby reducing low-frequency roughness. The conformal thin film can be deposited by plasma-enhanced atomic layer deposition (ALD) process. By modulating O during the ALD process 2 plasma, the internal stress of the conformal thin film can be changed to be less compressive / more tensile. The resulting composite stress of the resulting composite photoresist / oxide layer is less compressive and reduces bending and / or bulging. In some embodiments, the conformal thin film can be 1-2 nm thick but still improves low-frequency roughness. According to the disclosed embodiments, FIG. 1 provides a flowchart of operations for performing a method. The operations in FIG. 1 can be performed, for example, at a chamber pressure between about 1 mTorr and about 100 Torr, such as between about 1 mTorr and about 1 Torr. The method shown in FIG. 1 generally involves deposition on a semiconductor substrate. Specifically, in operation 102, a semiconductor substrate is provided to a processing chamber, and the semiconductor substrate is composed of or includes a plurality of different substrate materials (including a patterned EUV photoresist layer). The patterned EUV photoresist layer can be composed of various materials. In some embodiments, the patterned EUV photoresist layer can be composed of an organic or inorganic metal-containing oxide film, such as an organotin oxide available from Inpria Corp., or a conventional chemically amplified photoresist available from Dow / Rohm, Fujifilm, and Shin-Etsu Polymer. The patterned EUV photoresist can also include a chemically amplified photoresist. The patterned EUV photoresist layer can be, for example, 30 - 40 nm thick. Referring to the chamber that receives the semiconductor substrate in operation 102, the chamber can be in a multi-chamber device or a single-chamber device. The semiconductor substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a wafer having one or more material layers (e.g., dielectric, conductive, or semiconductor materials) deposited thereon. In some embodiments, the semiconductor substrate includes a covering layer of silicon (e.g., amorphous silicon) or a covering layer of germanium. In some embodiments, the layers on the substrate can be patterned. The substrate can have "features", such as vias or contact vias, and the features can be one or more of narrow and / or recessed openings, fillings within the features, or high aspect ratios. The features can be formed in one or more of the above layers. An example of a feature is a hole or via in a semiconductor substrate or a layer on the substrate. Another example is a trench in the substrate or layer. In various embodiments, the feature can have an underlying layer, such as a barrier layer or an adhesion layer. Non-limiting examples of the underlying layer include dielectric layers and conductive layers, such as silicon oxide, silicon nitride, silicon carbide, metal oxides, metal nitrides, metal carbides, and metal layers. At operation 104, a conformal film is deposited onto a semiconductor substrate. The conformal film can include a variety of materials. In some embodiments, the conformal film is silicon oxide. In other embodiments, the conformal film can be silicon nitride. The conformal film can also be composed of carbon-based oxides. In various embodiments, the conformal film is composed of a material that is not removed during subsequent substrate etching. The conformal film can be less than 3 nm thick, less than 2 nm thick, 1-2 nm thick, or about 2 nm thick. This thickness is not sufficient to adversely affect the critical dimensions of the fabricated features. By varying the deposition conditions, the conformal film can be designed to have different levels of internal stress. In some embodiments, the conformal film has internal tensile stress. In other embodiments, the conformal film has a lower compressive stress compared to the patterned EUV photoresist. In some embodiments, the conformal film can be deposited by plasma-enhanced ALD. Generally, ALD is a technique for depositing thin layers of material using sequential self-limiting reactions. Any suitable technique can be used to implement ALD. In various embodiments, ALD can be implemented using plasma, or can be implemented using heat. Additionally, operation 104 can be implemented in a cyclic manner, i.e., what is referred to herein as an "ALD cycle". Referring to FIG. 2, a schematic diagram showing the deposition of a film on a substrate by ALD is shown. In various embodiments, a silicon-containing film is deposited, such as silicon oxide (e.g., SiO 2 ), silicon oxynitride, or silicon nitride. ALD is a technique for depositing thin layers of material using sequential self-limiting reactions. Any suitable technique can be used to implement ALD. In various embodiments, ALD can be implemented using plasma, or can be implemented using heat, and can be implemented in a cyclic manner. The concept of an "ALD cycle" is relevant to the discussion of various embodiments herein. Generally, an ALD cycle is the minimum set of operations used to perform a surface deposition reaction once. For example, as a result of one cycle, at least a portion of a silicon-containing film layer is produced on the substrate surface, such as on the semiconductor substrate material of operation 104. Generally, an ALD cycle includes the operation of transporting and adsorbing at least one reactant to the substrate surface, followed by reacting the adsorbed reactant with one or more reactants to form a partial film layer. The cycle can include certain auxiliary operations, such as purging one of the reactants or by-products, and / or treating the deposited partial film. Generally, a cycle encompasses a situation of a unique series of operations. As an example, an ALD cycle can include the following operations: (i) transporting / adsorbing a silicon-containing precursor, (ii) purging the silicon-containing precursor from the chamber, (iii) transporting a second reactant (e.g., an oxidant) and plasma, and (iv) purging the plasma from the chamber. According to the present disclosure, batch intermediate purge can be used at appropriate intervals between ALD cycles to increase the batch size. According to various embodiments, deposition / purge cycles can be repeated throughout the batch until a maximum accumulation limit is reached. Figure 2 shows an exemplary schematic diagram of an ALD cycle for depositing silicon oxide (SiO 2 ). Figures 282a - 282e show a general ALD cycle. In 282a, a silicon substrate is provided, which includes many silicon atoms. In 282b, a silicon-containing precursor or silicon source is introduced to the substrate, and some silicon atoms are adsorbed on the substrate. In 282c, the unadsorbed silicon-containing precursor or silicon source is purged from the chamber. In 282d, oxygen is introduced as oxygen radicals, and the adsorbed silicon reacts with the oxygen radicals on the substrate surface to form SiO 2 film. In 282e, the chamber is purged and by-products are removed, leaving SiO 2 deposition layer. In some embodiments, the film deposited by ALD can be highly conformal. The conformality of the film can be measured by the step coverage. The step coverage can be calculated by comparing the average thickness of the deposited film at the bottom, sidewall, or top of the feature with the average thickness of the deposited film at the bottom, sidewall, or top of the feature. For example, the step coverage can be calculated by dividing the average thickness of the deposited film on the sidewall by the average thickness of the deposited film on the top and multiplying the result by 100 to obtain a percentage. Unlike chemical vapor deposition (CVD) techniques, ALD processing uses surface-mediated deposition reactions to deposit films layer by layer. In one example of ALD processing, a substrate surface containing a group of surface-active sites is exposed to a gas-phase distribution region of a first precursor (e.g., a silicon-containing precursor), and the first precursor is provided in an injection manner to a processing chamber containing the substrate. Molecules of this first precursor are adsorbed onto the substrate surface, including chemisorbed species containing the first precursor and / or physically adsorbed molecules. It should be understood that when a compound is adsorbed onto the substrate surface (as described herein), the adsorption layer may include the compound and derivatives of the compound. For example, the adsorption layer of a silicon-containing precursor may include the silicon-containing precursor and derivatives of the silicon-containing precursor. In certain embodiments, the injection of the ALD precursor partially saturates the substrate surface. In some embodiments, the injection stage of the ALD cycle ends before the precursor contacts the substrate and evenly saturates the surface. Generally, at this time, the precursor flow is turned off or diverted, and only the purge gas flows. By operating in a sub-saturated state, ALD processing reduces the cycle time and increases the throughput. However, because the precursor adsorption is not saturation-limited, the concentration of the adsorbed precursor may vary slightly across the substrate surface. An example of ALD processing operating in a sub-saturated state is provided in U.S. Patent Application No. 14 / 061,587, filed on October 23, 2013, and entitled "SUB-SATURATED ATOMIC LAYER DEPOSITION AND CONFORMAL FILM DEPOSITION", the entire content of which is incorporated herein by reference. After the first precursor injection, the reactor is then evacuated to remove any first precursor maintained in the gas phase, leaving only the adsorbed species. A second reactant (e.g., an oxygen- or nitrogen-containing gas) is introduced into the reactor so that some of these molecules react with the first precursor adsorbed on the surface. In some processes, the second precursor immediately reacts with the adsorbed first precursor. In other embodiments, the second precursor reacts only after a activation source is temporarily applied. The reactor can then be evacuated again to remove the unreacted second precursor molecules. Additional ALD cycles can be used to increase the film thickness. In some embodiments, the ALD process includes plasma activation, such as when the second reactant is delivered to the chamber. As described herein, the ALD processes and apparatuses described herein can be conformal film deposition (CFD) processes, which are generally described in: U.S. Patent Application No. 13 / 084,399 (now U.S. Patent No. 8,728,956), filed on April 11, 2011 and entitled "PLASMA ACTIVATED CONFORMAL FILM DEPOSITION"; and U.S. Patent Application No. 13 / 084,305, filed on April 11, 2011 and entitled "SILICON NITRIDE FILMS AND METHODS", the entire contents of which are incorporated herein by reference. Additional examples of ALD processing are described in Puurunen's "Surface chemistry of atomic layer deposition: for the trimethylaluminum / water process, 97 J. Applied Physics 12301 (2005)", which is incorporated herein by reference for providing a description of suitable ALD processing. In some embodiments, a carrier gas (such as N 2 , Ar, Ne, He, and combinations thereof) can flow continuously. The carrier gas can be used as a purge gas. An inert gas can be provided to assist in the pressure and / or temperature control of the processing chamber, the evaporation of liquid reactants, the more rapid delivery of reactants, and / or as a sweep gas for removing process gases from the processing chamber and / or the processing chamber piping. During the adsorption operation of the ALD cycle, the substrate can be exposed to a film precursor, such as silicon tetrachloride (SiCl 4 ), or an aminosilane, to adsorb onto the substrate surface. In some embodiments, the film precursor can be a silicon-containing precursor. In some embodiments, the film precursor is bis(tert-butyl-amino)silane (BTBAS). In some embodiments, the film precursor (e.g., SiCl 4 ) can adsorb onto about 60% of the substrate surface. In various embodiments, when the film precursor flows into the chamber, the film precursor adsorbs onto the active sites on the substrate surface, forming a thin layer of the film precursor on the surface. In various embodiments, this layer can be less than a monolayer. After adsorption, the chamber can optionally be purged to remove the excess precursor in the gas phase that has not adsorbed onto the substrate surface. Purging can involve a sweep gas, which can be the carrier gas used in other operations or a different gas. In some embodiments, purging can involve evacuating the chamber. In the second reactant delivery operation of the ALD cycle, the substrate can be exposed to the second reactant and an optional plasma. In various embodiments, the second reactant is oxygen (O 2 ), nitrogen (N 2 ), or a combination thereof. In some embodiments of depositing a silicon oxide layer, oxygen is used as the second reactant. In some embodiments, both the second reactant flow and the plasma are turned on. In some embodiments, the second reactant flow is turned on before the plasma is turned on, for example, to stabilize the second reactant flow. In some embodiments, the optional plasma is an in-situ plasma such that the plasma is directly formed above the substrate surface in the chamber. In various embodiments, the plasma can be an inductively coupled plasma or a capacitively coupled plasma. The inductively coupled plasma can be set to a plasma between about 50 W and about 2000 W. In some embodiments, the plasma can be turned on and off according to a duty cycle (DC), where the plasma power is cyclically turned on and off. In some embodiments, the duty cycle can vary between 25% and 50%, indicating that the plasma is turned on for the operation time between 25% and 50%. In some embodiments, a bias voltage between about 0 V and about 500 V can be applied. During the delivery of the second reactant, the film precursor (e.g., SiCl 4 ) is turned off. The duration for which the substrate can be exposed to the second reactant and the optional plasma can exceed the time for the plasma to interact with all the precursors adsorbed on the substrate surface, thereby forming a continuous film on the substrate surface. After the second reactant delivery operation, the chamber can be purged, for example, by introducing a carrier gas or an inert gas. The conditions for this operation can be any of the conditions described above for the purge process. In various embodiments, the ALD cycle can be repeated. For example, the operations for ALD can be performed about 5 to about 70 cycles. Any suitable number of deposition cycles can be included to deposit a deposited film of the desired film thickness. In some embodiments, each ALD cycle can deposit about 1 Å. Depending on the exposure time of the operation, each cycle can deposit a film with a thickness between about 0.05 Å and about 5 Å, such as a silicon oxide or silicon oxynitride film. In some embodiments, about two to about three ALD cycles can be performed per minute. In some embodiments, such as in a chamber where the inlet is closer to the substrate, more than about three cycles can be performed per minute. Returning to FIG. 1, at operation 106, the substrate is optionally etched. In some embodiments, as described above, after EUV photoresist patterning, the substrate beneath the patterned EUV photoresist is etched. The etching can be performed immediately after EUV photoresist patterning, in the same chamber, and without breaking the vacuum. The patterned EUV photoresist and the conformal film act as a mask for the substrate such that the areas covered by the patterned EUV photoresist are not etched. The conformal film can have an etching rate lower than that of the substrate material to ensure that it remains on the patterned EUV photoresist throughout the etching process. Due to the more tensile stress of the conformal film, the patterned EUV photoresist and the conformal film layer have reduced LER and / or LWR, which also reduces the LER and LWR of the underlying etched substrate. The following table provides exemplary processing conditions for depositing the conformal film as shown in FIG. 1: FIGS. 3A and 3B are diagrams of the roughness with and without a conformal film layer as described herein. In FIG. 3A, photoresist 302a is a diagram of a portion of the photoresist that can be developed on a semiconductor substrate. Photoresist 302a has internal compressive stress, which causes the photoresist to bend and thus increases LER and LWR. Photoresist 302a can be represented by low-frequency roughness 303-1 and high-frequency roughness 303-2, which represent the two types of roughness of photoresist 302a, respectively. The low-frequency roughness 303-1 is partially caused by the compressive stress of photoresist 302a, which causes bending and / or bulging. FIG. 3B is a diagram of an EUV photoresist according to an embodiment disclosed herein. Photoresist 302b has a conformal film 305 deposited thereon. Conformal film 305 is characterized by a tensile stress or less compressive stress compared to photoresist 302b, and the addition of conformal film 305 produces a composite photoresist 306, which has less compressive stress than photoresist 302b. Due to the reduced compressive stress, the composite photoresist 306 has a reduced low-frequency roughness. In some embodiments, conformal film 305 is a silicon oxide deposited using plasma-enhanced ALD. Variations in the plasma-enhanced ALD process can deposit films with various levels of internal stress (from compressive to tensile). By depositing a film with less compressive stress than the photoresist, the film cancels out the compressive stress of the photoresist and reduces the bending and / or bulging that may occur, resulting in less low-frequency roughness. In other embodiments, different dielectric materials can be used as long as they have less compressive stress than the photoresist. According to an example of the present disclosure, FIG. 4 shows graphs and charts of the effects of conformal films deposited on EUV photoresist under different ALD conditions. Graph 402 shows the power spectral density (PSD) curves for four different deposition conditions. Since the PSD value is directly related to the line edge roughness (LER), a lower PSD value also means a smaller LER. Line 404 is the PSD of the EUV photoresist without any treatment. Line 405 is the PSD of the EUV photoresist after depositing a conformal film composed of silicon oxide under 300W 50% DC. Line 406 is the PSD of the EUV photoresist after depositing a conformal film composed of silicon oxide under 75W 3% DC. Line 407 is the PSD of the EUV photoresist after depositing a conformal film composed of silicon oxide under 75W 50% DC. As shown in graph 402, line 404 does not have a conformal film and has the largest PSD value, while lines 405 - 407 show improved PSD values. The following table shows the treatment conditions of the reactants in the ALD cycles of each conformal film in this example. The treatment conditions of the first reactant of each conformal film are the same for all conformal films, while the treatment conditions of the second reactant are different. Chart 412 provides additional information related to graph 402. Rows 414 - 417 show the correlation between the treatment conditions, the in - film stress, and the PSD value at a spatial frequency of 0.01 nm -1 . The roughness at a spatial frequency of 0.01 nm -1 is considered low - frequency roughness, so a lower PSD value at this spatial frequency is generally associated with reduced low - frequency roughness. Row 414 is related to line 404, showing the data of the EUV photoresist without any conformal film, with a PSD value of 13.4 nm 4 . Row 415 is related to line 405, showing the data of the conformal film deposited on the EUV photoresist under 75W 50% DC, with an in - film stress of +25 MPa (positive for tensile stress and negative for compressive stress), and the resulting PSD value of 5.4 nm 4 , which is a 60% improvement over the PSD value of the EUV photoresist without a conformal film. Row 416 is related to line 406, showing the data of the conformal film deposited on the EUV photoresist under 300W 50% DC, with an in - film stress of -25 MPa, and the resulting PSD value of 8.12 nm 4, an improvement of 40%. Finally, row 417 is related to line 407, showing data of a conformal film deposited on EUV photoresist at 75W 3% DC, with an internal stress of -46 MPa and a PSD value of 11.5 nm 4 , an improvement of 14% compared to the original PSD value of the EUV photoresist without the conformal film. It can be clearly seen from the graphs and charts that the EUV photoresist with the conformal film having the maximum tensile stress has the lowest PSD value and thus the lowest LER. The EUV photoresist without any conformal film or with a conformal film having less tensile stress has a larger PSD value and thus a larger LER. FIG. 5 is a schematic diagram of an application of EUV photoresist. Stack 502 is a series of substrate layers with EUV photoresist 503 on top. The EUV photoresist is patterned such that features are formed in the substrate layers during an etching process. The features are etched to a depth 504, which is approximately 185 nm in this example, but the feature depth may be greater or less. When the features are etched through the layers, the roughness of the EUV photoresist will affect the roughness of the etched layers. Image 506 represents an image of the etched features in the substrate, where each feature has a deformation. By improving the roughness of the EUV photoresist, the roughness of the etched features will also be improved. FIG. 6 is a graph and table showing the effect of films deposited under different ALD conditions on the LER of the target layer. Graph 602 shows the PSD curves under four different conditions. Since the PSD value is directly related to the LER, a lower PSD value also means a smaller LER. Line 604 is the PSD of the EUV photoresist layer without the conformal film before etching the substrate. Line 605 is the PSD of the target layer after etching using the EUV photoresist without the conformal film. Line 606 is the PSD of the target layer after etching using the EUV photoresist with a conformal film (composed of silicon oxide at 75W 50% DC). Line 607 is the PSD of the target layer after etching the substrate using the EUV photoresist with a conformal film (composed of silicon oxide at 75W 3% DC). As shown in the figure, line 604 does not have a conformal film and has the largest PSD value, while lines 605 - 607 show improved PSD values. The two conformal films are deposited under the same or similar processing conditions as shown in FIG. 4 above. Table 612 provides additional information related to graph 602. Rows 614 - 617 provide stress, the PSD value at a spatial frequency of 0.01 nm -1 of the spatial frequency, the percentage improvement of the PSD value before etching, and the percentage improvement of the PSD value after etching. The spatial frequency is 0.01 nm -1 The roughness is considered low-frequency roughness, so lower PSD values at this spatial frequency are generally associated with reduced low-frequency roughness. Line 614 shows data of the EUV photoresist layer before etching and without a conformal film. Line 615 shows data of the target layer after etching using the EUV photoresist layer without a conformal film. Line 616 shows data with a conformal film (75W 50% DC) deposited on the EUV photoresist, with an internal stress of +25 MPa (positive is associated with tensile stress, and negative indicates compressive stress). Finally, line 617 shows data with a conformal film (75W 3% DC) deposited on the EUV photoresist, with an internal stress of -46 MPa. Columns 618 and 619 show the improvement using the conformal films disclosed herein. The values in column 618 represent the improvement in the PSD value of the EUV photoresist with a conformal film (compared to the EUV photoresist without a conformal film). For the same processing conditions, these numbers are the same as those shown in the figure. The values in column 619 represent the improvement in the PSD value after etching the target layer with and without a conformal film. By the etching process, the roughness can be slightly reduced by 10%. However, adding a conformal film can significantly reduce the roughness. Depositing the conformal film at 75W and 50% DC will result in a 60% reduction in roughness before etching and a 72% reduction in roughness after etching. Depositing the conformal film at 75W and 3% DC will result in a relatively low 14% reduction in roughness before etching, but the etching process results in a 37% reduction in roughness after etching. It can be clearly seen from the graphs and charts that the EUV photoresist with a conformal film having a larger tensile stress has a smaller PSD value and thus a smaller LER compared to the EUV photoresist without a conformal film or with a smaller tensile stress of the conformal film. Then, the reduction in the LER of the EUV photoresist can be transferred to the target layer during subsequent etching processes, thus reducing the LER and LWR of the etched features. Equipment FIG. 7A is a schematic cross-sectional view showing a plasma processing system that can be used for etching operations according to various embodiments. The system includes a chamber 732, and the chamber 732 includes a chamber body 714, a chuck 716, and a dielectric window 706. The chamber 732 includes a processing region, and the dielectric window 706 is disposed above the processing region. The chuck 716 can be an electrostatic chuck for supporting a substrate 712 and is disposed below the processing region in the chamber. In some embodiments, an internal Faraday shield (not shown) is disposed inside the chamber 732 below the dielectric window 706. The TCP coil 734 is disposed above the dielectric window 706 and is connected to a matching circuit 702. The system includes a bias RF generator 720, which can be defined by one or more generators. If multiple generators are provided, different frequencies can be used to achieve various tuning characteristics. The bias matcher 718 is coupled between the RF generator 720 and the conductive plate of the component that defines the chuck 716. The chuck 716 also includes electrostatic electrodes to allow for the clamping and unclamping of the wafer. Broadly, filters and a DC clamping power supply can be provided. Other control systems can also be provided for lifting the wafer from the chuck 716. The first gas injector 704 provides two different channels to inject two separate flows of a processing gas or liquid precursor (in vapor form) from the top of the chamber into the chamber. It should be understood that multiple gas suppliers can be provided to supply different gases to the chamber for various types of operations, such as processing operations on the wafer, waferless automatic cleaning (WAC) operations, and other operations. The second gas injector 710 provides another gas flow that enters the chamber through the side rather than from the top. In the embodiment of FIG. 7A, independent gas flows can be delivered into the chamber. One flow can be injected through the center of the injector 704. A second flow can also be injected through the injector 704 but through a different path surrounding the center of the injector 704. A third flow can be injected into the side of the chamber through the side injector 710. In one embodiment, the gas injector 704 also provides optical access into the processing chamber, for example, along an axial path from a diagnostic endpoint outside the processing chamber through an optical access window. For more details on the optical access into the chamber, reference can be made to U.S. Patent No. 7,928,366, entitled "Methods of and Apparatus for Accessing a Process Chamber Using a Dual Zone Gas Injector with Improved Optical Access", issued on April 19, 2011, the disclosure of which is incorporated herein by reference. Various ways of injecting gas into the chamber have been described to illustrate that etching gases and / or liquid precursors can be provided to the chamber from various locations. In some examples, only the injector 704 is used. In other examples, only the side injector 710 is used. In other examples, both the injector 704 and the side injector 710 can be used. In one configuration, the manifold 722 controls which gas is supplied to each of the three different gas lines. The manifold 722 allows any type of gas (reactant, conditioning, precursor, etc.) to be provided to any of the three different gas lines. In some embodiments, the conditioning gas can include, for example, a gas such as oxygen (O 2 2) or helium (He). The gas can be delivered to the chamber without mixing or after being mixed with other gases before being introduced into the chamber. The vacuum pump 730 is connected to the chamber 732 to allow for vacuum pressure control and removal of gas by-products from the chamber during operation of the plasma process. The valve 726 is disposed between the exhaust portion 724 and the vacuum pump 730 to control the amount of vacuum suction applied to the chamber. The dielectric window 706 can be defined by a ceramic material or a ceramic-like material. Other dielectric materials are also possible as long as they can withstand the conditions of the semiconductor etch chamber. Typically, the chamber operates at an elevated temperature, in the range between zero degrees Celsius and approximately 200 degrees Celsius. The temperature will depend on the etch process operation and the specific recipe. The chamber 732 will also operate under vacuum conditions, in the range between about 1 millitorr (mT) and about 500 millitorr (mT). As used herein, the terms "about" and "approximately" mean that the specified parameter can vary within reasonable tolerances (e.g., ± 20%). Although not all are specifically shown, when installed in a clean room or processing facility, the chamber 732 is typically coupled to a plurality of facilities. The facilities include plumbing systems that provide process gases, vacuum, temperature control, and environmental particle control, among others. These facilities are coupled to the chamber 732 when the chamber 732 is installed in the target processing facility. In addition, the chamber 732 can be coupled to a transfer chamber that allows a robotic arm to transfer semiconductor wafers into and out of the chamber 732 using automated operations. The programmable controller 708 is provided for controlling the operation of the chamber 732 and its associated components. Broadly speaking, the controller 708 can be programmed to perform chamber operations defined by a recipe. A given recipe can specify various parameters for operation, such as power application to the TCP coil, gas flow into the chamber, and application of vacuum. It should be understood that timing, duration, magnitude, or any other adjustable parameter or controllable feature can be defined by the recipe and executed by the controller to control the operation of the chamber 732 and its associated components. In addition, a series of recipes can be programmed into the controller 708. In one embodiment, the recipe is for processing an etch operation and includes one or more cycles of atomic layer deposition (ALD) processing performed between each of the etch operations. FIG. 7B is a schematic cross-sectional view of a plasma processing system that can be used for an etching operation according to various embodiments. As shown in FIG. 7B, a chuck 716 is disposed in a chamber 714, and the chamber 714 is provided with a dielectric window 706. In one embodiment, the chuck 716 is an electrostatic chuck for supporting a substrate 712. A TCP coil 734 is disposed above the dielectric window 706 and connected to a matching circuit 702, and the matching circuit 702 is coupled to an RF generator 721. In the embodiment of FIG. 7B, a delivery system 728 includes an etching gas delivery system 727 and a liquid delivery system 729. The etching gas delivery system 727 delivers an etchant gas to a manifold 722 via a conduit 703. The liquid delivery system 729 delivers a liquid precursor (in vapor form) to the manifold 722 via a conduit 701, as described in more detail below with reference to FIG. 7C. The manifold 722, in response to control from a controller 708, selects, switches, and / or mixes the outputs by using, for example, a plurality of valves for switching between gases and / or vapors, enabling the outputs from the respective delivery systems to flow to the chamber 714 via a conduit 705 at an appropriate time. The outputs from the respective delivery systems flow from the conduit 705 into the chamber 714 via a gas injector 704, which is located at the top of the chamber. To assist in purging the chamber, the base of the chamber 714 is provided with an outlet 715, which is fluidly connected to a pump 717. In one embodiment, the pump 717 is a turbopump. Those skilled in the art will appreciate that the base of the chamber 714 may be provided with a plurality of outlets, each of which is connected to a suitable pump. FIG. 7C is a schematic diagram depicting additional details of a liquid delivery system according to various embodiments. As shown in FIG. 7C, the liquid delivery system 729 includes a liquid precursor source 758, a liquid flow controller 760, and a vaporizer 762. The liquid precursor source 758 is fluidly coupled to a facility that provides a suitable liquid precursor. As described above, any liquid precursor capable of forming a conformal atomic monolayer can be used. The liquid precursor flows from the source 758 to the liquid flow controller 760, which adjusts the flow rate based on instructions received from the controller 708 (see, for example, FIG. 7B). In one embodiment, the amount of the liquid precursor is in the range of about 50 microliters to about 1,000 microliters. The liquid precursor flows from the liquid flow controller 760 to the vaporizer 762, which converts the liquid precursor from a liquid state to a gaseous state. The vaporized precursor flows to the manifold 722, which supplies the vaporized precursor to the gas injector 704 at an appropriate time based on control received from the controller 708 (see, for example, FIG. 7A). The vaporized precursor flows into a chamber 732 defined by the chamber 714 via the gas injector 704 (see, for example, FIG. 7A). As described above, one or more processing workstations may be included in a multi-workstation processing tool. FIG. 8 shows a schematic diagram of an embodiment of a multi-workstation processing tool 800, having an inbound load chamber 802 and an outbound load chamber 804, either or both of the inbound load chamber 802 and the outbound load chamber 804 may include a remote plasma source (not shown in FIG. 8). A robot 806 at atmospheric pressure is used to move wafers from a cassette (loaded through pod 808) through an atmospheric port 810 into the inbound load chamber 802. The wafers (not shown in FIG. 8) are placed on a pedestal 812 in the inbound load chamber 802 by the robot 806, the atmospheric port 810 is closed, and the inbound load chamber 802 is evacuated. In the case where the inbound load chamber 802 includes a remote plasma source, the wafers can be exposed to remote plasma processing in the inbound load chamber 802 before being introduced into the processing chamber 814. Additionally, the wafers can also be heated in the inbound load chamber 802, for example, to remove moisture and adsorbed gases. Then, the chamber transfer port 816 leading to the processing chamber 814 is opened, and another robot (not shown) places the wafers on a pedestal in the reactor and in the first workstation (shown in the reactor for processing) for processing. Although the embodiment depicted in FIG. 8 includes load chambers, it should be understood that in some embodiments, the wafers can enter the processing workstation directly. In the embodiment shown in FIG. 8, the depicted processing chamber 814 includes four processing workstations, numbered 1 to 4. Each workstation has a heated pedestal (shown as 818 in workstation 1), and a gas pipeline inlet. It should be understood that in some embodiments, each processing workstation may have different or multiple purposes. For example, in some embodiments, the processing workstation can switch between ALC, ALD, and plasma-enhanced ALD processing modes. In some embodiments, exposure to deposition precursors and exposure to a second reactant and plasma are implemented in the same workstation. Additionally or alternatively, in some embodiments, the processing chamber 814 may include one or more pairs of matched ALD and plasma-enhanced ALD processing workstations. Although the depicted processing chamber 814 includes four workstations, it should be understood that a processing chamber according to the present disclosure can have any suitable number of workstations. For example, in some embodiments, the processing chamber can have five or more workstations, while in other embodiments, the processing chamber can have three or fewer workstations. FIG. 8 depicts an embodiment of a wafer transfer system 890 for transferring wafers in a processing chamber 814. In some embodiments, the wafer transfer system 890 can transfer wafers between various processing workstations and / or between a processing workstation and a loading chamber. It should be understood that any suitable wafer transfer system can be employed. Non-limiting examples include a wafer rotator and a wafer transfer robot arm. FIG. 8 also depicts an embodiment of a system controller 850 for controlling the processing conditions and hardware states of the processing tool 800. The system controller 850 can include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 can include a CPU or a computer, analog and / or digital input / output connections, a stepper motor controller board, etc. In some embodiments, the system controller 850 controls all activities of the processing tool 800. The system controller 850 executes system control software 858, which is stored in the mass storage device 854, loaded into the memory device 856, and executed on the processor 852. Alternatively, the control logic can be hard-coded in the controller 850. For these purposes, application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays, or FPGAs), and the like can be used. In the following discussion, in any case where "software" or "coding" is used, functionally comparable hard-coded logic can be used appropriately. The system control software 858 can include instructions for controlling the following: timing, gas mixing, gas flow rate, chamber and / or workstation pressure, chamber and / or workstation temperature, wafer temperature, target power level, RF power level, substrate pedestal, chuck, and / or susceptor position, and other parameters of a specific process performed by the processing tool 800. The system control software 858 can be configured in any suitable manner. For example, various processing tool component subroutines or control objects can be written to control the operation of the processing tool components used to perform various processing tool processes. The system control software 858 can be coded in any suitable computer-readable programming language. In some embodiments, the system control software 858 can include input / output control (IOC) sequence instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on the mass storage device 854 and / or the memory device 856 associated with the system controller 850 can be employed. Examples of programs or program segments for this purpose include a substrate positioning program, a processing gas control program, a pressure control program, a heater control program, and a plasma control program. The substrate positioning program can include code for a processing tool component for loading a substrate onto the pedestal 818 and controlling the spacing between the substrate and other parts of the processing tool 800. The process gas control program may include encoding for controlling gas composition (e.g., silicon-containing gas, oxygen-containing gas, and purge gas as described herein) and flow rate, and optionally, encoding for flowing the gas to one or more processing workstations prior to deposition to stabilize the processing workstation pressure. The pressure control program may include encoding for controlling the pressure within the processing workstation, by adjusting, for example, a throttle valve in the exhaust system of the processing workstation, the gas flow into the processing workstation, etc. The heater control program may include encoding for controlling the current to a heating unit for heating a substrate. Alternatively, the heater control program may control the transfer of a heat transfer gas (e.g., helium) to the substrate. According to embodiments herein, the plasma control program may include encoding for setting the RF power level applied to a processing electrode in one or more processing workstations. According to embodiments herein, the pressure control program may include encoding for maintaining the pressure in a reaction chamber. In some embodiments, there may be a user interface associated with the system controller 850. The user interface may include a display screen, a graphical software display of the equipment and / or processing conditions, and user input devices such as pointing devices, keyboards, touchscreens, microphones, etc. In some embodiments, the parameters adjusted by the system controller 850 may be related to the processing conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), etc. These parameters may be provided to the user in the form of recipes, which can be input using the user interface. Via the analog and / or digital input connections of the system controller 850, signals for monitoring the process may be provided from various process tool sensors. Signals for controlling the process may be output on the analog and digital output connections of the process tool 800. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (e.g., pressure gauges), thermocouples, etc. Appropriate programmed feedback and control algorithms may be used with the data from these sensors to maintain the processing conditions. The system controller 850 may provide program instructions for implementing the deposition process described above. The program instructions may control various processing parameters, such as DC power level, RF bias power level, pressure, temperature, etc. According to various embodiments described herein, the instructions may control the parameters to operate the in-situ deposition of the film stack. Typically, the system controller 850 will include one or more memory devices, and one or more processors for executing the instructions, such that the equipment will perform the methods according to the disclosed embodiments. A machine-readable medium may be coupled to the system controller 850, the machine-readable medium including instructions for controlling the processing operations according to the disclosed embodiments. In some embodiments, system controller 850 is part of a system, which can be part of the above examples. Such systems can include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for performing processing, and / or specific processing components (wafer chucks, gas flow systems, etc.). These systems can be integrated with electronic components used to control their operations before, during, and after the processing of semiconductor wafers or substrates. The electronic components can be referred to as "controllers", and the controller can control various components or sub-parts of one or more systems. Depending on the processing conditions and / or system type, system controller 850 can be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positioning and operation settings, wafer transfer into and out of tools connected to or engaged with a specific system and other transfer tools and / or load locks. Broadly speaking, system controller 850 is an electronic component related to various integrated circuits, logic, memory, and / or software having the ability to receive instructions, issue instructions, control operations, enable cleaning operations to be performed, enable endpoint measurements to be performed, and achieve similar functions. The integrated circuit can include a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions can be instructions communicated to system controller 850 in the form of various individual settings (or program files), defining the operating parameters for performing a specific process on or to a semiconductor wafer or to a system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer. In some implementations, system controller 850 can be part of a computer or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, system controller 850 can be in the "cloud" or in all or part of a fab host computer system to enable remote control of wafer processing. The computer can enable remote control of the system to monitor the current processing of manufacturing operations, examine the historical records of past manufacturing operations, examine trends or performance evaluations of multiple manufacturing operations, change the parameters of the current processing, set the processing steps after the current processing, or initiate a new processing. In some examples, a remote computer (such as a server) can provide a processing recipe to the system via a network, which can include a local area network or the Internet. The remote computer can include a user interface that enables the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, system controller 850 receives instructions in the form of data, and the instructions specify parameters for each of the processing steps to be executed during one or more operation periods. It should be understood that the parameters can be for the type of processing to be performed and the type of tool with which system controller 850 interfaces or controls. Thus, as described above, system controller 850 can be distributed, for example, by including one or more independent controllers that are networked together and work towards a common goal (such as the processing and control described herein). An example of a distributed controller for such a goal would be one or more integrated circuits in a chamber that are in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) to combine to control the processing in the chamber. Non-limitingly, exemplary systems can include a plasma etch chamber or module, a deposition chamber or module, a spin clean chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer clean (ALC) chamber or module, an ion implantation chamber or module, an orbit chamber or module, and any other semiconductor processing system related to or for the processing and / or manufacturing of semiconductor wafers. As described above, depending on the processing steps to be performed by the tool, system controller 850 can communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, the host computer, another controller, or a material transfer tool that moves a wafer container into and out of a tool location and / or a load port in a semiconductor manufacturing factory. Suitable equipment for implementing the methods disclosed herein is further discussed and described in U.S. Patent Application No. 13 / 084,399, filed Apr. 11, 2011, and entitled "PLASMA ACTIVATED CONFORMAL FILM DEPOSITION," now U.S. Patent No. 8,728,956, and U.S. Patent Application No. 13 / 084,305, filed Apr. 11, 2011, and entitled "SILICON NITRIDE FILMS AND METHODS," the entire contents of each of which are incorporated herein by reference. The equipment / processing described herein can be used in conjunction with, for example, lithographic patterning tools or processes for fabricating or manufacturing semiconductor components, displays, LEDs, photovoltaic panels, etc. Generally, although not necessarily, such tools / processes are used or performed together in a common manufacturing facility. Lithographic patterning of a film typically includes some or all of the following operations, each provided by several possible tools: (1) coating a photoresist on a workpiece (i.e., a substrate), using a spin coater or spray coater; (2) curing the photoresist, using a hot plate or oven or UV curing tool; (3) exposing the photoresist to visible light or UV light or x-ray light with a tool (e.g., a wafer stepper); (4) developing the photoresist in order to selectively remove the photoresist and thereby pattern it, using a tool (e.g., a wet bench); (5) transferring the photoresist pattern into the underlying film or workpiece, using a dry or plasma-assisted etch tool; and (6) removing the photoresist, using a tool (e.g., an RF or microwave plasma resist stripper). Conclusion Although the above embodiments have been described in detail for purposes of clarity of understanding, it is obvious that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways to implement the processes, systems, and equipment of the embodiments of the present case. Accordingly, the embodiments of the present case should be regarded as illustrative rather than restrictive, and the embodiments of the present case should not be limited to the details presented herein. 1 - 4: Processing Stations 102, 104, 106: Operations 282a - 282e: Figures 302a, 302b: Photoresist 303 - 1: Low - Frequency Roughness 303 - 2: High - Frequency Roughness 305: Conformal Film 306: Composite Photoresist 402: Curve 404, 405, 406, 407: Lines 412: Chart 414, 415, 416, 417: Rows 502: Stack 503: EUV Photoresist 504: Depth 506: Image 602: Curve 604, 605, 606, 607: Lines 612: Chart 614, 615, 616, 617: Rows 618, 619: Columns 701: Conduit 702: Matching Circuit 703: Conduit 704: Gas Injector 705: Conduit 706: Dielectric Window 708: Controller 710: Gas Injector 712: Substrate 714: Chamber 715: Outlet 716: Chuck 717: Pump 718: Bias Matching Component 720: Bias RF Generator 721: RF Generator 722: Manifold 724: Exhaust Section 726: Valve 727: Etch Gas Delivery System 728: Delivery System 729: Liquid Delivery System 730: Vacuum Pump 732: Chamber 734: TCP Coil 758: Liquid Precursor Source 760: Liquid Flow Controller 762: Vaporizer 800: Multi - Workstation Processing Tool 802: In - Station Loading Chamber 804: Out - Station Loading Chamber 806: Robot Arm 808: Cassette 810: Atmospheric Port 812: Base 814: Processing Chamber 816: Chamber Transfer Port 818: Base 850: System Controller 852: Processor 854: Mass Storage Device 856: Memory Device 858: System Control Software 890: Wafer Transfer System According to the disclosed embodiments, FIG. 1 depicts a process flow diagram of the operations of the method. FIG. 2 is a schematic diagram of an embodiment of atomic layer deposition. FIG. 3A is a diagram of high - frequency and low - frequency roughness. FIG. 3B is a diagram of using the embodiments disclosed herein to reduce high - frequency roughness. FIG. 4 is a data graph showing the influence of various conformal films on LER. FIG. 5 is a diagram showing a plurality of layers etched using the embodiments herein. FIG. 6 is a data graph showing the influence of various conformal films on LER after etching. FIGS. 7A, 7B, and 7C are schematic diagrams of an exemplary processing chamber for implementing the disclosed embodiments. FIG. 8 is a schematic diagram of an exemplary processing apparatus for implementing the disclosed embodiments. 102,104,106: Operation

Claims

1. A substrate processing method, the method comprising: providing a substrate to a processing chamber, the substrate including a patterned EUV photoresist having a first stress level; and depositing a film on the patterned EUV photoresist having a second stress level such that a third stress level of the patterned EUV photoresist resulting from the deposition of the film is less compressed than the first stress level, wherein the patterned EUV photoresist is characterized in that: after the deposition, the line roughness is reduced.

2. The substrate processing method of claim 1, wherein the substrate comprises a semiconductor wafer, which is a semiconductor device semi-finished product.

3. The substrate processing method of claim 1, wherein the film has a thickness of not more than 2 nm.

4. The substrate processing method of claim 1, wherein the film has a thickness of about 1 nm.

5. The substrate processing method of claim 1, wherein the second stress level is tensile.

6. The substrate processing method of claim 1, wherein the second stress level is compressive.

7. The substrate processing method of any one of claims 1-6, wherein the line roughness includes one or more of line edge roughness (LER) and line width roughness (LWR).

8. The substrate processing method of claim 7, wherein the line roughness is a low-frequency line roughness.

9. The substrate processing method of claim 8, wherein the low-frequency line roughness has a spatial frequency of less than 0.05 nm-1.

10. The substrate processing method of claim 7, wherein the line roughness is a high-frequency line roughness.

11. The substrate processing method of claim 10, wherein the high-frequency line roughness has a spatial frequency greater than 0.05 nm-1.

12. The substrate processing method of claim 7, wherein the roughness of the line edge is reduced by an amount from about 0.1 to 1 nm4 (PSD).

13. A substrate processing method according to any one of claims 1-6, wherein the film comprises a Si-based dielectric.

14. The substrate processing method of claim 13, wherein the dielectric is SiO2.

15. The substrate processing method of any one of claims 1-6, wherein the film is deposited by ALD.

16. The substrate processing method of claim 15, wherein the ALD includes a plasma-enhanced ALD, wherein a cycle includes an oxygen plasma flow having a power between 10W and 2500W and a duty cycle between 25% and 50%.

17. The substrate processing method of claim 16, wherein the EUV photoresist comprises a chemically amplified photoresist (CAR), an organometallic material, or an organometallic oxide.

18. The substrate processing method of claim 17, wherein the organometallic oxide is an organotin oxide.

19. The substrate processing method of any one of claims 1-6 further comprises: etching the substrate layer in the processing chamber after the deposition of the film.

20. A substrate processing apparatus, the apparatus comprising: a processing chamber; and a controller having at least one processor and a memory, wherein the memory stores a plurality of computer-executable instructions for controlling the at least one processor to: provide a substrate to the processing chamber, the substrate comprising a patterned EUV photoresist having a first stress level; and deposit a film on the patterned EUV photoresist having a second stress level such that a third stress level of the patterned EUV photoresist resulting from the deposition of the film is less compressed than the first stress level, wherein the patterned EUV photoresist is characterized in that: after the deposition, the line roughness is reduced.

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