Integrated circuit and method for manufacturing integrated circuit

Abstract

An integrated circuit includes a first transistor, a second transistor, a dummy structure, a back feedthrough, and a first metal line. The first transistor includes a gate metal; the second transistor includes the gate metal; the dummy structure is located between the first transistor and the second transistor, and includes a plurality of semiconductor nanostructures and a dummy gate metal surrounding the semiconductor nanostructures; the back feedthrough is in contact with a bottom of the dummy gate metal; the first metal line is on the dummy gate metal and electrically connected to the back feedthrough.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit, and more particularly to a method for manufacturing the integrated circuit. Prior Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in IC materials and design have produced successive generations of ICs, each smaller and more complex than the previous one. Throughout the evolution of ICs, functional density (the number of interconnected devices per chip area) has generally increased, while geometry size (the smallest component (or circuit) that can be manufactured using a process) has decreased. This process of downsizing generally improves production efficiency and reduces associated costs. However, this process of downsizing also increases the complexity of the process and manufacturing of ICs. Summary of the Invention

[0003] The present disclosure provides a method for manufacturing an integrated circuit, including forming a first transistor, forming a second transistor, forming a dummy structure, and forming a feedthrough. The first transistor includes a gate metal wrapped around a plurality of stacked first channels; the second transistor is separated from the first transistor in a first lateral direction and includes a gate metal wrapped around a plurality of stacked second channels; the dummy structure is between the first transistor and the second transistor, wherein the dummy structure includes a dummy gate metal; and the feedthrough extends from below the dummy structure to contact the dummy gate metal.

[0004] Another embodiment provides an integrated circuit comprising a substrate, a dummy structure, and a feedthrough. The dummy structure comprises a dummy gate metal, a first dummy source / drain contact, and a second dummy source / drain contact. The feedthrough extends through the substrate and contacts the dummy gate metal, the first dummy source / drain contact, and the second dummy source / drain contact.

[0005] Another embodiment provides an integrated circuit comprising a first transistor, a second transistor, a dummy structure, a backside feedthrough, and a first metal line. The first transistor comprises a gate metal; the second transistor comprises a gate metal; the dummy structure is located between the first and second transistors and comprises a plurality of semiconductor nanostructures and a dummy gate metal. The dummy gate metal surrounds the plurality of semiconductor nanostructures; the backside feedthrough contacts a bottom portion of the dummy gate metal; and the first metal line is located above the dummy gate metal and electrically connected to the backside feedthrough. Simple diagram description

[0006] The following detailed description, when read in conjunction with the accompanying drawings, may provide a better understanding of various aspects of the present disclosure. It should be noted that, in accordance with standard practice in the art, various features are not drawn to scale. In fact, for ease of discussion, the dimensions of various features may be arbitrarily increased or decreased. FIG. 1 is a perspective view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 2A is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 2B is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG3 is a cross-section of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG4 is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG5 is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG6 is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG. 7A is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 7B is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 8A is a perspective view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG8B is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG8C is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG. 9A is a perspective view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 9B is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG. 9C is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 10A is a perspective view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 10B is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG. 10C is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 11A is a perspective view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 11B is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 11C is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 12A is a perspective view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 12B is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 12C is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 13A is a perspective view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 13B is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 13C is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 14A is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 14B is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 15A is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 15B is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG. 16A is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 16B is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 17 is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG. 18 is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG. 19A is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 19B is a top view of an integrated circuit at different stages of the manufacturing process according to certain embodiments. picture. FIG. 20A is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 20B is a perspective view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 21A is a top view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 21B is a perspective view of an integrated circuit at different stages of fabrication according to certain embodiments. picture. FIG. 22 is a flow chart of a method of operating an integrated circuit according to certain embodiments. Implementation Method

[0007] The following disclosure provides many different implementations or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments in which the first and second features are directly in contact, as well as embodiments in which an additional feature is formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, the disclosure may repeat reference numerals and / or letters throughout various embodiments. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0008] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature depicted in the figures. Spatially relative terms encompass different orientations of the device in use or operation, in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0009] Terms expressing relative degrees, such as "approximately", "substantially", etc., should be interpreted in accordance with the understanding of current technical specifications by those skilled in the art.

[0010] The present disclosure generally relates to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured devices. Examples of nanostructured devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), and nanowire FETs (NWFETs). In advanced technology nodes, nanostructured devices typically have uniform active region spacing, symmetrical source / drain epitaxial structures, and metal gates surrounding all four sides of the nanostructure (e.g., nanosheet).

[0011] Embodiments disclosed herein provide an integrated circuit having a feedthrough via structure that provides an electrical connection between backside metal lines and frontside metal lines of the integrated circuit. The feedthrough via structure incorporates dummy source / drain contacts, dummy metal, and source / drain conductive vias. The dummy metal is formed on the gate metal of a wraparound gate transistor structure between two continuous poly diffusion edge (CPODE) structures. This creates a feedthrough unit with low area loss and low resistance, thereby increasing processing speed and reducing power consumption.

[0012] Feedthrough structures can be provided between transistors. The transistors may be referred to as "nanostructure transistors," and the channels may be referred to as "semiconductor nanostructures." The structure of the nanostructure transistor can be patterned using any suitable method. For example, the structure can be patterned using one or more lithography processes, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine lithography and self-aligned processes to produce patterns with finer pitch than can be achieved using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the nanotransistor structure.

[0013] 1 through 14B are cross-sectional, top, and perspective views of an integrated circuit 100 fabricated according to some embodiments of the present disclosure. As will be described in further detail below, this process produces a plurality of transistors 101.

[0014] FIG1 is a perspective view of an integrated circuit 100 at an intermediate stage in the fabrication process. Integrated circuit 100 includes a substrate 102. Substrate 102 can be a semiconductor substrate, such as a bulk semiconductor or the like, and can be doped (e.g., using p-type or n-type dopants) or undoped. The semiconductor material of substrate 102 can include silicon; germanium; compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide); or combinations thereof. Other substrates, such as single-layer, multi-layer, or gradient substrates, can also be used.

[0015] Integrated circuit 100 includes a semiconductor stack 103 comprising a plurality of alternating semiconductor layers 104 and sacrificial semiconductor layers 106. As described in further detail below, semiconductor layers 104 are patterned to form stacked channels for multiple transistors. As described below, sacrificial semiconductor layers 106 are ultimately removed to form gate metal and other structures surrounding the semiconductor nanostructure. FIG1 illustrates three semiconductor layers 104 and three sacrificial semiconductor layers 106. In some embodiments, semiconductor stack 103 may include fewer or more layers than shown in FIG1.

[0016] In some embodiments, the semiconductor layer 104 can be formed of a suitable first semiconductor material, such as silicon, silicon carbide, or the like, while the sacrificial semiconductor layer 106 can be formed of a second semiconductor material, such as silicon germanium, or the like. The layers of the semiconductor stack 103 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), and molecular beam epitaxy (MBE).

[0017] Due to the high etch selectivity between the materials of the semiconductor layer 104 and the semiconductor sacrificial layer 106, the semiconductor sacrificial layer 106 of the second semiconductor material can be removed without significantly etching the semiconductor layer 104 of the first semiconductor material, thereby allowing the semiconductor layer 104 to be released to form the stacked channel region of the transistor, which will be explained in detail below.

[0018] In FIG. 2A , trenches 110 have been formed in semiconductor stack 103 and substrate 102. Although not shown in FIG. 1 , a hard mask layer is first formed and patterned on semiconductor stack 103. Trenches 110 can be formed using an anisotropic etching process, which etches downward in the presence of the patterned hard mask. This etching process defines semiconductor fins 112 by forming trenches 110 through sacrificial semiconductor layer 106, semiconductor layer 104, and substrate 102.

[0019] In some embodiments, FIG. 2B is a top view of the integrated circuit 100 in FIG. 2A . The top view in FIG. 2B shows semiconductor fins 112 extending along the X direction and trenches 110 between the semiconductor fins 112. The substrate 102 is visible in the trenches 110. The topmost semiconductor layer 106 is visible on top of the semiconductor fins 112. As previously mentioned, in practical applications, a hard mask layer may be located on top of the topmost semiconductor layer 106. FIG. 2B also shows cut line X and cut line Y. The cross-sectional view along cut line Y may be referred to as the "Y view." The cross-sectional view along cut line X may be referred to as the "X view."

[0020] FIG3 is a cross-sectional Y view according to certain embodiments. In FIG3 , shallow trench isolation regions 116 are formed by depositing a dielectric material in trenches 110 between semiconductor fins 112. The shell dielectric layer can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In one exemplary embodiment, the dielectric material comprises silicon oxide. However, the dielectric material may also comprise silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), or other dielectric materials without departing from the scope of the present disclosure. After the dielectric material is deposited, an etch-back process is performed to recess the top of the shallow trench isolation regions 116 below the underlying sacrificial semiconductor layer 106.

[0021] FIG4 is an X-axis view of integrated circuit 100 according to certain embodiments. In FIG4 , sacrificial gate structures 118 are formed on semiconductor fins 112. The sacrificial gate structures 118 extend in the Y direction, perpendicular to the semiconductor fins 112. Each sacrificial gate structure 118 spans across multiple semiconductor fins 112. The sacrificial gate structures 118 are also formed in trenches 110.

[0022] Sacrificial gate structure 118 includes a dielectric layer 126. In one exemplary embodiment, dielectric layer 126 comprises silicon oxide. However, dielectric layer 126 may also comprise silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), or other dielectric materials without departing from the scope of the present disclosure. In some embodiments, dielectric layer 126 comprises a low-K dielectric material. Dielectric layer 126 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0023] The sacrificial gate structure includes a sacrificial gate layer 128 on the dielectric layer 126. The sacrificial gate layer 128 may include a material having a high etch selectivity relative to the shallow trench isolation region 116. In one exemplary embodiment, the sacrificial gate layer 128 includes polysilicon. However, the sacrificial gate layer 128 may be a conductive, semiconducting, or non-conductive material, and may include amorphous silicon, polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 128 may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or other techniques for depositing the selected material.

[0024] The sacrificial gate structure 118 includes a dielectric layer 130 on the sacrificial gate layer 128 and a dielectric layer 132 on the dielectric layer 130. The dielectric layer 130 and the dielectric layer 132 may correspond to the first mask layer and the second mask layer. The dielectric layer 130 may include silicon nitride, silicon oxynitride, or other suitable dielectric materials. The dielectric layer 132 may include silicon nitride, silicon oxynitride, or other suitable dielectric materials. The dielectric layer 130 and the dielectric layer 132 are different materials from each other and can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. The dielectric layer 130 and the dielectric layer 132 may also use other materials and deposition processes without departing from the scope of the present disclosure.

[0025] The gate spacer layer 134 is formed on the sidewalls of the dielectric layer 126, the sacrificial gate layer 128, the dielectric layer 130, and the dielectric layer 132. The gate spacer layer 134 may also be formed on other exposed surfaces of the integrated circuit. The gate spacer layer 134 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition processes. After the gate spacer layer 134 is formed, the horizontal portion of the gate spacer layer 134 (e.g., the X to Y plane) may be removed by an anisotropic etching process to expose the upper surface of the semiconductor fin 112 and the dielectric layer 132. After the gate spacer layer is patterned, the vertically thicker portion of the gate spacer layer 134 remains, as shown in FIG. 4 . The gate spacer layer 134 may include one or more of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), or other suitable dielectric materials.

[0026] After the gate spacer layer 134 is patterned, an etching process is performed to form source / drain trenches 120 in the semiconductor fins 112. One or more etching processes are performed to form the source / drain trenches 120 in the semiconductor fins 112. Forming the source / drain trenches 120 includes etching through each semiconductor layer 104, each sacrificial semiconductor layer 106, and a portion of the substrate 102. Therefore, the removal operation may include an appropriate etching operation for removing material of the semiconductor layers 104, the sacrificial semiconductor layers 106, and the substrate 102. The etching process may include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), or the like.

[0027] The formation of the source / drain trenches 120 results in the formation of a stack of channels 105. Specifically, after forming the source / drain trenches 120, a portion of the semiconductor layer 104 now corresponds to a channel of a transistor. The formation of the source / drain trenches 120 also results in the formation of a plurality of sacrificial semiconductor nanostructures 107 from the sacrificial semiconductor layer 106.

[0028] A large number of source / drain trenches 120 are formed in the semiconductor fins 112. Between each source / drain layer is a stack 122 consisting of a plurality of channels 105. The channels 105 of each stack 122 correspond to the channels 105 of a transistor stack.

[0029] In FIG. 5 , inner spacers 136 are formed. A selective etching process is performed to recess the exposed ends of the semiconductor sacrificial nanostructure 107 without substantially etching the semiconductor sacrificial nanostructure 107. Next, a dielectric material is deposited to fill the recesses formed between the channels 105 in the semiconductor sacrificial nanostructure 107 by the previous selective etching process, thereby forming inner spacers 136. The inner spacers 136 can be made of a suitable dielectric material, such as silicon carbide nitride (SiCN) or silicon oxycarbonitride (SiOCN), and can be formed by a suitable deposition method, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). An etching process, such as an anisotropic etching process, can be performed to remove the portion of the inner spacers 136 outside the recesses of the semiconductor sacrificial nanostructure 107. The remaining portion of the dielectric layer corresponds to the inner spacers 136 shown in FIG. 5 .

[0030] FIG6 shows the formation of source / drain regions 140. In the illustrated embodiment, source / drain regions 140 are epitaxially grown from the channels 105. Source / drain regions 140 are grown on exposed portions of the semiconductor fins 112 and contact the channels 105. Each stack 122 of channels 105 has two source / drain regions 140. Some stacks 122 of channels 105 may share a source / drain region 140 with the channels 105 of adjacent stacks 122 in the X direction.

[0031] Although not shown, dielectric support elements corresponding to the remaining portions of the gate spacer layer 134 above the shallow trench isolation regions 116 can laterally constrain the growth of the source / drain regions 140. In some embodiments, the source / drain regions 140 exert stress in their respective channels 105, thereby improving performance. The source / drain regions 140 are formed so that each sacrificial gate structure 118 is located between a respective pair of adjacent source / drain regions 140. In some embodiments, the gate spacer layer 134 and the inner spacer 136 separate the source / drain regions 140 from the sacrificial gate layer 128 by an appropriate lateral distance (e.g., in the X-axis direction) to prevent electrical bridging to the gate of a subsequently formed device.

[0032] The source / drain regions 140 may comprise any acceptable material, such as materials suitable for n-type or p-type devices. For n-type devices, in some embodiments, the source / drain regions 140 include a material that applies a tensile strain in the channel region, such as silicon, silicon carbide (SiC), silicon carbide phosphide (SiCP), silicon phosphide (SiP), or the like. When forming a p-type device, in some embodiments, the source / drain regions 140 include a material that applies a compressive strain in the channel region, such as silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium (Ge), germanium tin (GeSn), or the like. The source / drain regions 140 may have surfaces that protrude from the respective surfaces of the fins and may also have facets. In some embodiments, adjacent source / drain regions 140 may merge to form a single source / drain region 140 on two adjacent fins of the semiconductor fin 112.

[0033] The source / drain regions 140 may be implanted with dopants and then annealed. The impurity concentration in the source / drain regions 140 may be between approximately 10 19 cm −3 and approximately 10 21 cm −3 . The N-type and / or P-type impurities in the source / drain regions 140 may be any of the impurities discussed above. In some embodiments, the source / drain regions 140 are doped in situ during the growth process.

[0034] In FIG6 , a contact etch stop layer (CESL) 144 and an interlayer dielectric (ILD) 146 are formed above the source / drain regions 140 and between the adjacent sacrificial gate structures. The CESL 144 may comprise a thin dielectric layer conformally deposited on the exposed surfaces of the source / drain regions 140 and other exposed surfaces. The CESL 144 may comprise silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. The CESL 144 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0035] An interlayer dielectric layer 146 covers the contact etch stop layer 144. The interlayer dielectric layer 146 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. The interlayer dielectric layer 146 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0036] In FIG6 , a chemical mechanical polishing (CMP) process is performed to reduce the height of the sacrificial gate structure 118. As a result of the CMP process, the dielectric layers 130 and 132 are completely removed. The heights of the sacrificial gate layer 128, gate spacer layer 134, contact etch stop layer 144, and interlayer dielectric layer 146 are reduced, and their top surfaces are planarized.

[0037] FIG7A is an X-ray view of the integrated circuit 100 according to some embodiments. In FIG7A , the sacrificial gate structure 118 has been removed from between the gate spacer layers 134. In particular, the dielectric layer 126 and the sacrificial gate layer 128 have been completely removed from between the gate spacer layers 134.

[0038] In some embodiments, the sacrificial gate layer 128 is removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process that uses a reactive gas to selectively etch the sacrificial gate layer 128 without etching the gate spacer layer 134. When the sacrificial gate layer 128 is etched, the dielectric layer 126 (if present) may serve as an etch stop layer. Subsequently, after removing the sacrificial gate layer 128, the dielectric layer 126 may be removed.

[0039] After the sacrificial gate layer 128 and the dielectric layer 126 are removed, a cavity is formed between the gate spacer layer 134 above the channel 105. As will be described in detail below, the upper portion of the gate metal or gate electrode will be formed in the cavity. Therefore, the sacrificial gate layer 128 is sacrificial because the upper portion of the gate metal will eventually be formed in its place.

[0040] In FIG. 7A , channel 105 is released by removing semiconductor sacrificial nanostructure 107. Semiconductor sacrificial nanostructure 107 can be removed through a selective etching process using an etchant that is selective for the material of semiconductor sacrificial nanostructure 107, thereby removing semiconductor sacrificial nanostructure 107 without substantially etching channel 105. In some embodiments, this etching process is an isotropic etching process using an etching gas including fluorine (F2) and hydrogen fluoride (HF) and an optional carrier gas. The carrier gas can be an inert gas such as argon (Ar), helium (He), nitrogen (N2), combinations thereof, or the like. In certain embodiments, semiconductor sacrificial nanostructure 107 is removed and channel 105 is patterned to form channel regions for P-type field-effect transistors (PFETs) and N-type field-effect transistors (NFETs). After removing semiconductor sacrificial nanostructure 107, voids are formed between channel 105.

[0041] After the channel 105 is released, an interfacial gate dielectric layer 151 is deposited. The interfacial gate dielectric layer 151 is deposited on all exposed surfaces of the channel 105. The interfacial gate dielectric layer 151 wraps around the channel 105. The interfacial gate dielectric layer 151 may include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interfacial gate dielectric layer 151 may include a low-K dielectric relative to a high-K dielectric, such as hafnium oxide or other high-K dielectric materials that can be used as transistor gate dielectrics. High-K dielectric materials include dielectric materials with a higher dielectric constant than silicon oxide. The interfacial gate dielectric layer 151 may be formed using a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The thickness of the interfacial gate dielectric layer 151 may be between 0.5 nm and 2 nm. The interface gate dielectric layer 151 may also use other materials, deposition processes, and thicknesses without departing from the scope of the present disclosure.

[0042] A high-k gate dielectric layer 153 has been deposited. The high-k gate dielectric layer 153 is deposited in a compliant deposition process. The compliant deposition process deposits the high-k gate dielectric layer 153 over the interfacial gate dielectric layer 151, the hard mask structure, the substrate 102, the shallow trench isolation region 116, and the gate spacer layer 134. The high-k gate dielectric layer 153 wraps around the channel 105. The thickness of the high-k gate dielectric layer 153 is between 1 nm and 3 nm. The high-K dielectric layer includes one or more layers of dielectric materials, such as hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, aluminum oxide, titanium oxide, a hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The high-K gate dielectric layer 153 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable method. Other thicknesses, deposition processes, and materials may also be used for the high-K gate dielectric layer 153 without departing from the scope of the present disclosure.

[0043] Gate metal 155 has been deposited. Gate metal 155 is deposited on all exposed surfaces of high-K gate dielectric layer 153. Gate metal 155 wraps around channel 105. Although gate metal 155 is shown as a single layer in FIG. 7 , in reality, gate metal 155 may include one or more conductive pad layers, work function layers, and gate fill layers, which together constitute the gate metal. The gate metal may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), gold (Au), or other suitable conductive materials. Gate metal 155 may be deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD). Other configurations, materials, and deposition processes for gate metal 155 may also be used without departing from the scope of this disclosure. Gate metal 155 serves as the gate electrode surrounding channel 105.

[0044] At the processing stage shown in Figures 7A and 7B, transistors 101 are substantially complete. Each transistor 101 includes a stack 122 of channels 105 extending between source / drain regions 140 and serving as the channel for the stack of transistors 101. As described below, source / drain contacts and cut metal gate structures have not yet been formed.

[0045] FIG7B is a Y-view of integrated circuit 100 according to certain embodiments, taken along cut line 7B at the process stage of FIG7A . FIG7B shows that at this process stage, the gate metal 155 between adjacent transistors 101 in the Y direction is not broken. Therefore, the gate electrodes of adjacent transistors 101 in the Y direction are shorted together.

[0046] FIG8A is a perspective view of an integrated circuit 100 according to certain embodiments. In FIG8A , gate isolation structures 157a and 157b have been formed. In some instances herein, reference numbers may include a suffix "a," "b," "c," or "d." Gate isolation structures 157a and 157b are examples of such suffixes. Throughout this specification, when a reference is not relevant to a particular structure, the suffix "a," "b," "c," or "d" may be omitted. For example, when a description applies to both gate isolation structures 157a and 157b, the description may refer only to gate isolation structure 157 without using the suffix "a" or "b." This also applies to other reference numbers with suffixes. Gate isolation structure 157 may also be referred to as a "cut metal gate" (CMG) structure. Gate isolation structure 157 electrically isolates the gate electrodes of adjacent transistors 101 in the Y direction.

[0047] Gate isolation structure 157 includes a dielectric layer 159. Dielectric layer 159 serves as a dielectric liner layer and may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 159 may be deposited via chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0048] The gate isolation structure includes a dielectric layer 161. Dielectric layer 161 fills the gap between adjacent portions of dielectric layer 159. Dielectric layer 161 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 161 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In one exemplary embodiment, dielectric layer 159 includes silicon nitride, and dielectric layer 161 includes silicon oxide.

[0049] The gate isolation structure 157 can be formed by forming trenches in the integrated circuit 100 at locations where the gate isolation structure 157 is to be formed. These trenches extend to the shallow trench isolation region 116 and completely etch through the gate metal 155, thereby electrically isolating the gate metals 155 of adjacent transistors in the Y direction from each other. After the trenches are formed, the dielectric layers 159 and 161 can be formed as described above, thereby forming the gate isolation structure 157.

[0050] FIG8A illustrates a transistor 101a according to certain embodiments. Transistor 101a includes multiple channels 105a, each extending along the X-direction between a source / drain region 140a and a source / drain region 140b. A gate metal 155 wraps around each channel 105a. FIG8A does not show the interfacial gate dielectric layer 15 (although it is still present). FIG8A and subsequent figures illustrate only the high-K gate dielectric layer 153. Internal spacers 136 electrically isolate the gate metal 155 from the source / drain region 140. The high-K gate dielectric layer 153 is a gate dielectric layer.

[0051] In FIG8A , a continuous poly on diffusion edge (CPODE) structure 163 is formed at certain locations between adjacent gate isolation structures 157 a and 157 b to replace the gate metal 155. The CPODE structure 163 includes a polysilicon layer 165 and a dielectric layer 167. The dielectric layer 167 is a dielectric pad located on the sidewalls of the gate spacer layer 134. The dielectric layer 167 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxynitride carbon (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. The dielectric layer 167 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. The top surface of the integrated circuit 100 has been planarized using a chemical mechanical polishing process.

[0052] FIG8A shows a cutting line 8B extending along the X direction. FIG8A also shows a cutting line 8C extending along the Y direction. In subsequent figures, the X view is drawn along the cutting line 8B. The Y view is drawn along the cutting line 8C.

[0053] FIG8B is a cross-sectional X-view of the integrated circuit 100 of FIG8A according to some embodiments. FIG8B shows the continuous polysilicon diffusion edge structure 163, the contact etch stop layer 144, the interlayer dielectric layer 146, and the gate metal 155 according to some embodiments.

[0054] FIG8C is a cross-sectional Y-view of the integrated circuit 100 of FIG8A according to certain embodiments. FIG8C shows four stacks of channels 105a through 105d of four transistors 101a through 101d. Transistor 101a includes channel 105a, which is surrounded by gate metal 155 on the left side of gate isolation structure 157a. Transistor 101b includes channel 105b, which is surrounded by gate metal 155 on the right side of gate isolation structure 157a. Transistor 101c includes channel 105c, which is surrounded by gate metal 155 on the left side of gate isolation structure 157b. Transistor 101d includes channel 105d, which is surrounded by gate metal 155 on the right side of gate isolation structure 157b.

[0055] FIG8C shows that the gate metal 155 of transistors 101b and 101c are shorted. Gate isolation structure 157a electrically isolates the gate metal 155 of transistor 101a from the gate metal 155 of transistors 101b and 101c. Gate isolation structure 157b electrically isolates the gate metal 155 of transistor 101d from the gate metal 155 of transistors 101b and 101c.

[0056] FIG9A is a perspective view of an integrated circuit 100 according to some embodiments. In FIG9A , a dielectric layer 168 is deposited on the top surface of the integrated circuit 100 shown in FIG8A according to some embodiments. Dielectric layer 168 functions as a hard mask layer. Dielectric layer 168 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 168 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0057] In FIG. 9A , a dielectric layer 169 is formed on dielectric layer 168. Dielectric layer 169 serves as an interlayer dielectric. Dielectric layer 169 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 169 may be deposited via chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0058] In FIG9A , a lithography process and a corresponding etching process are performed to form a trench 171 in dielectric layer 168 and dielectric layer 169. Although not apparent in FIG9A , trench 171 exposes gate metal 155 between gate isolation structure 157 a and gate isolation structure 157 b. In particular, trench 171 exposes gate metal 155 surrounding channel 105 b and channel 105 c.

[0059] In FIG. 9A , although not readily apparent, an etching process has been performed to remove the gate metal 155 at the exposed locations. The etching process selectively etches the material of the gate metal 155 relative to the material of the exposed dielectric structure.

[0060] FIG9B is an X-view of the integrated circuit 100 at the processing stage of FIG9A according to certain embodiments. FIG9C is a Y-view of the integrated circuit 100 at the processing stage of FIG9A according to certain embodiments. FIG9B and FIG9C show that the gate metal 155 has been removed at the locations exposed by the trench 171. The high-K gate dielectric layer 153 remains above the gate spacer layer 134 and the channels 105b and 105c. The gate metal 155 between the gate isolation structures 157a and 157b has been removed. The gate metal 155 still surrounds the channel 105a of the transistor 101a and the channel 105d of the transistor 101d.

[0061] FIG10A is a perspective view of an integrated circuit 100 according to certain embodiments. In FIG10A , a dummy gate metal 156 has been deposited to replace the removed gate metal 155. The dummy gate metal 156 is a different material than the gate metal 155. In certain embodiments, the dummy gate metal 156 has a lower resistivity than the gate metal 155. The dummy gate metal 156 can be deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or other suitable deposition processes. The dummy gate metal can include tungsten, titanium, aluminum, tantalum, or other suitable conductive materials. In one example, the gate metal 155 includes titanium nitride, which has a relatively high resistivity, while the dummy gate metal 156 includes tungsten, which has a significantly lower resistivity than the titanium nitride gate metal. Other metal combinations may also be used for the gate metal 155 and the dummy gate metal 156 without departing from the scope of the present disclosure. Since transistors 101b and 101c will be dummy transistors with no functional function, a work function metal is not required. This allows the use of a metal with a lower resistance for dummy gate metal 156. Dummy gate metal 156 can be referred to as filler metal, secondary gate metal, or replacement gate metal. Transistors 101b and 101c can be referred to as dummy structures, having the appearance of transistors but without any function.

[0062] FIG10B is an X-view of the integrated circuit 100 of FIG10A according to certain embodiments. FIG10C is a Y-view of the integrated circuit 100 of FIG10A according to certain embodiments. FIG10B shows the dummy gate metal 156 located on the high-K gate dielectric layer 153 between the gate spacer layers 134. FIG10C shows the dummy gate metal 156 between the gate isolation structures 157a and 157b and wrapped around the channels 105b and 105c.

[0063] FIG11A is a perspective view of integrated circuit 100 according to certain embodiments. In FIG11A , source / drain contacts 173 have been formed. Prior to forming source / drain contacts 173, a photolithography process and a corresponding etching process were performed. The photolithography and etching processes form trenches to expose source / drain regions 140 at selected locations.

[0064] After forming the trenches for the source / drain contacts 173, a silicide 174 is formed on the source / drain region 140. The silicide 174 can be formed after depositing the material for the source / drain contacts 173. In particular, a thermal annealing process can be performed after depositing the material for the source / drain contacts 173. The thermal annealing process forms the silicide 174 at the interface between the semiconductor material of the source / drain region 140 and the metal of the source / drain contacts 173.

[0065] In some embodiments, the source / drain contacts 173 may include tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum ruthenium, selenium, or other suitable conductive materials. The source / drain contacts 173 may be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or other suitable deposition processes.

[0066] In some embodiments, a dielectric layer 175 is formed in the trench before the material for the source / drain contacts 173 is deposited. The dielectric layer 175 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. The dielectric layer 175 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0067] FIG11B is an X-view of the integrated circuit 100 of FIG11A according to certain embodiments. FIG11C is a Y-view of the integrated circuit 100 of FIG11A according to certain embodiments. FIG11B shows the source / drain contacts 142 extending into the interlayer dielectric layer 146. The source / drain contacts 173 are not shown in FIG11C.

[0068] FIG12A is a perspective view of integrated circuit 100 according to certain embodiments. In FIG12A , according to certain embodiments, as shown in FIG11A , a dielectric layer 176 is deposited on the top surface of integrated circuit 100. Dielectric layer 176 functions as a hard mask layer. Dielectric layer 176 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 176 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0069] In FIG. 12A , dielectric layer 178 is formed on dielectric layer 176. Dielectric layer 178 serves as an interlayer dielectric. Dielectric layer 178 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 178 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0070] Although not visible in FIG. 12A , a lithography process and a corresponding etching process have been performed to form trenches in dielectric layers 176 and 178. These trenches expose source / drain contacts 173 and dummy gate metal 156 for conductive vias 183 at selected locations. After forming the trenches for conductive vias 183, conductive vias 183 are formed by depositing a conductive material in the trenches. The conductive material may include tungsten, titanium, aluminum, titanium nitride, tantalum nitride, tantalum, ruthenium, selenium, or other suitable conductive materials. Conductive vias 183 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. After conductive vias 183 are formed, a chemical mechanical polishing process is performed to remove excess metal material from the upper surface of dielectric layer 178.

[0071] FIG12B is an X-view of the integrated circuit 100 of FIG12A according to certain embodiments. FIG12C is a Y-view of the integrated circuit 100 of FIG12A according to certain embodiments. FIG12B shows the source / drain contact 173 and the conductive via 183 contacted by the dummy gate metal 156. FIG12C shows a conductive via contacted by the dummy gate metal 156.

[0072] Returning to FIG. 12A , after forming conductive vias 183, dielectric layer 179 is deposited on dielectric layer 178. Dielectric layer 179 acts as a hard mask layer. Dielectric layer 179 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 179 may be deposited via chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0073] In FIG. 12A , a dielectric layer 181 is formed on dielectric layer 179. Dielectric layer 181 serves as an interlayer dielectric. Dielectric layer 181 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 181 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0074] After depositing dielectric layers 179 and 181, a lithography process and a corresponding etching process are performed to create trenches in dielectric layers 179 and 181, thereby forming metal lines 185 in the front-side layer 0 metal. These trenches expose conductive vias 183 at selected locations. After forming the trenches for metal lines 185, metal lines 185 are formed by depositing a conductive material in the trenches. The conductive material may include tungsten, titanium, aluminum, titanium nitride, tantalum nitride, tantalum, ruthenium, selenium, or other suitable conductive materials. Metal lines 185 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0075] In some embodiments, before forming metal line 185, a conductive pad layer 187 is formed in the trench. Conductive pad layer 187 may include titanium nitride, tantalum nitride, or other suitable conductive materials. Conductive pad layer 187 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0076] Returning to Figures 12B and 12C, Figure 12B shows metal lines 185 in contact with three conductive vias 183, which in turn contact the source / drain contacts and the dummy gate metal 156. Figure 12C shows conductive vias 183 in contact with the dummy gate metal 156, and conductive vias 183 in contact with metal lines 185. Figure 12C also shows multiple other metal lines 185 formed in dielectric layer 181.

[0077] FIG13A is a perspective view of integrated circuit 100 according to certain embodiments. In FIG13A , integrated circuit 100 is flipped over, with substrate 102 at the top and metal line 185 at the bottom. Integrated circuit 100 is flipped over to form a feedthrough via 191, which electrically connects dummy gate metal 156 and adjacent source / drain contacts 173. Feedthrough 191 may also be referred to as a conductive backside via.

[0078] In FIG. 13A , a dielectric layer 189 is formed on the back side of the integrated circuit 100. Specifically, the dielectric layer 189 is formed on the semiconductor substrate 102 and the shallow trench isolation region 116. In this case, the semiconductor substrate 102 and the shallow trench isolation region 116 can be collectively considered a substrate. The dielectric layer 189 acts as a hard mask layer. The dielectric layer 189 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. The dielectric layer 189 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0079] In FIG. 13A , a lithography process and a corresponding etching process are performed to form a trench through the dielectric layer 189 and the substrate, thereby exposing the dummy gate metal 156 and selected source / drain contacts 173. After the trench is formed, a conductive pad layer 193 is formed in the trench. The conductive pad layer 193 may include titanium nitride, tantalum nitride, or other suitable conductive materials. The conductive pad layer 193 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0080] After forming the conductive pad layer 193, a feedthrough 191 is formed by depositing a conductive material in a trench on the conductive pad layer 193. The feedthrough 191 may comprise tungsten, aluminum, titanium, titanium nitride, tantalum nitride, ruthenium, selenium, or other suitable conductive materials. The feedthrough 191 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. After the feedthrough 191 is formed, a chemical mechanical polishing (CMP) process is performed to remove excess conductive material from the upper surface of the dielectric layer 189.

[0081] FIG13B is an X-view of the integrated circuit 100 of FIG13A according to certain embodiments. FIG13C is a Y-view of the integrated circuit 100 of FIG13A according to certain embodiments. FIG13B shows feedthrough 191 in contact with source / drain contacts 173 and dummy gate metal 156. FIG13C shows feedthrough 191 in contact with dummy gate metal 156. FIG13C also shows that the trench for feedthrough 191 extends into dummy gate metal 156 beyond at least one via 105b / 105c.

[0082] FIG14A is an X-view of integrated circuit 100 according to certain embodiments. FIG14B is a Y-view of integrated circuit 100 at the processing stage shown in FIG14A according to certain embodiments. Although the orientation of FIG14A and FIG14B (and the orientation in subsequent figures) is reversed so that the backside of integrated circuit 100 is at the bottom of each figure, the backside processing is performed with the orientation reversed, as described in FIG13A through FIG13C.

[0083] In Figures 14A and 14B, a dielectric layer 195 is formed on the back side of integrated circuit 100. Specifically, dielectric layer 195 is formed on dielectric layer 189. Dielectric layer 195 acts as a hard mask layer. Dielectric layer 195 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 195 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0084] A dielectric layer 197 is formed on the back side of integrated circuit 100. Specifically, dielectric layer 197 is formed on dielectric layer 195. Dielectric layer 197 serves as a backside interlayer dielectric layer. Dielectric layer 197 may include silicon oxide (SiO), silicon oxide nitride (SiON), silicon nitride (SiN), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxide nitride (SiON), or other suitable dielectric materials. Dielectric layer 197 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0085] In Figures 14A and 14B, a lithography process and a corresponding etching process are performed to form trenches through dielectric layers 195 and 197, thereby exposing feedthrough 191 and other selected locations. After the trenches are formed, a conductive pad layer 201 is formed in the trenches. Conductive pad layer 201 may include titanium nitride, tantalum nitride, or other suitable conductive materials. Conductive pad layer 201 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.

[0086] After forming the conductive pad layer 201, a conductive material is deposited in the trenches above the conductive pad layer 201 to form metal lines 199 of the backside layer 0 metal. Metal lines 199 may include tungsten, aluminum, titanium, titanium nitride, tantalum nitride, ruthenium, selenium, or other suitable conductive materials. Metal lines 199 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. After forming metal lines 199, a chemical mechanical polishing (CMP) process is performed to remove excess conductive material from the upper surface of the dielectric layer 197.

[0087] At the process stage shown in Figures 14A and 14B, front-side metal lines 185 and back-side metal lines 199 have been formed. At least one of the front-side metal lines 185 is electrically connected to at least one of the back-side metal lines 199 through feedthrough 191, dummy gate metal 156, and conductive via 183. Feedthrough 191, the gate structure including dummy gate metal 156, source / drain contacts 173, conductive via 183, front-side metal lines 185, and back-side metal lines 199 collectively form a feedthrough structure 206. Feedthrough structure 206 is bounded in the X direction by the low-continuity polysilicon diffusion edge structure 163 to minimize area loss. Feedthrough structure 206 is bounded in the Y direction by the gate isolation structures 157a / 157b, resulting in a longer length and lower resistance.

[0088] In some embodiments, the dummy gate metal 156 may also be referred to as a second gate metal. The dummy gate metal 156 is different from the gate metal 155 of other (logic) transistors 101 (e.g., (logic) transistor 101a and (logic) transistor 101d). The dummy gate metal 156 may include tungsten or other low-resistance materials, such as ruthenium, molybdenum, copper, iridium, or other suitable metals. Although not shown in Figures 14A and 14B, the dummy gate metal 156 may also include a conductive pad layer, such as titanium nitride, tantalum nitride, or other suitable conductive pad materials.

[0089] In some embodiments, a high-K gate dielectric layer 153, corresponding to the gate dielectric layer, may be present between the dummy gate metal 156 and the channel 105b / 105c, and between the dummy gate metal 156 and the gate spacer layer 134. The high-K gate dielectric layer 153 has a thickness between 0.1 nm and 5 nm and may include silicon (Si), oxygen (O), carbon (C), nitrogen (N), hafnium (Hf), or other suitable dielectric materials.

[0090] In some embodiments, the dummy gate metal 156 has a dimension D1 in the X direction. Dimension D1 can be between 8 nm and 54 nm, although other dimensions may be used without departing from the scope of this disclosure. In some embodiments, the dummy gate metal 156 has the same profile or dimensions as the gate metal 155.

[0091] In some embodiments, the feedthrough 191 protrudes into the dummy gate metal 156 by a dimension D2 corresponding to the distance between the bottom of the dummy gate metal 156 and the top of the feedthrough 191 and the orientation shown in FIG. 14B . Dimension D2 can be between 0.1 nm and 70 nm, although other dimensions may be used without departing from the scope of the present disclosure. Dimension D2 can depend in part on the rate at which the dummy gate metal 156 is etched by the etching process used to form the trench for the feedthrough 191.

[0092] In some embodiments, dimension D3 corresponds to the spacing between adjacent continuous polysilicon diffusion edge structures 163. Dimension D3 may correspond to twice the contact poly pitch (CPP). Dimension D3 is greater than or equal to twice the width of the feedthrough hole 191 in the X direction.

[0093] As previously described, dummy gate metal 156 is formed between gate-all-around (GAA) transistor 101a and gate-all-around transistor 101d. Dummy gate metal 156 surrounds channels 105b and 105c, with dimensions and characteristics substantially identical to those of channels 105a and 105d in transistors 101a and 101d. However, because source / drain contacts 173 are merged or shorted with dummy gate metal 156, channels 105b and 105c are no longer part of a functional transistor.

[0094] In some embodiments, transistors 101b and 101c correspond to dummy transistors having a transistor structure but do not function as transistors. Channels 105b and 105c are dummy channels. Source / drain contacts 173 are dummy source / drain contacts. In some embodiments, dummy gate metal 156 can be referred to as replacement gate metal or second gate metal.

[0095] FIG15A is an X-view of the integrated circuit 100 according to certain embodiments. FIG15B is a Y-view of the integrated circuit 100 at the process stage shown in FIG15A according to certain embodiments. The integrated circuit 100 in FIG15A and FIG15B is generally similar to the integrated circuit 100 in FIG14A and FIG14B. One difference is that in FIG15A and FIG15B , the high-K gate dielectric layer 153 (and the interfacial gate dielectric layer 151) are not present on the dummy gate metal 156. Therefore, the dummy gate metal 156 is in direct contact with the channel 105b / 105c and the gate spacer layer 134. As described in FIG9A through FIG9C , the gate dielectric layer can be removed during the removal of the gate metal 155.

[0096] FIG16A is an X-view of integrated circuit 100 according to certain embodiments. FIG16B is a Y-view of integrated circuit 100 at the processing stage shown in FIG16A according to certain embodiments. The integrated circuit 100 in FIG16A and FIG16B is generally similar to the integrated circuit 100 in FIG14A and FIG14B . One difference is that in FIG16A and FIG16B , the dummy gate metal 156 is substantially not recessed during the formation of feedthrough 191. Therefore, dimension D2 described in FIG14B is substantially zero in FIG16B . This is achieved by forming the trench for feedthrough 191 using an etching process that does not substantially etch the dummy gate metal 156.

[0097] FIG17 shows a Y-view of the integrated circuit 100 according to certain embodiments. In FIG17 , the vias 105a / 105b have been removed. As described in FIG9A through FIG9C , the vias 105a / 105b can be removed during the removal of the gate metal 155. Therefore, in FIG17 , the dummy gate metal 156 does not surround any vias 105. This further reduces the resistance of the feedthrough structure 206.

[0098] FIG. 18 is an X-ray view of integrated circuit 100 according to certain embodiments. In FIG. 18 , a single large conductive via 183 is formed that contacts source / drain contacts 173 and dummy gate metal 156. This can be achieved by patterning a single trench for conductive via 183 in dielectric layer 177 during the process stages described in FIG. 12A through FIG. 12C . This can further reduce the resistance of feedthrough structure 206.

[0099] FIG19A illustrates an X-axis view of integrated circuit 100 according to certain embodiments. In FIG19A , the X-axis dimension D4 of feedthrough 191 is larger than that shown in FIG14A and FIG15A . The etching process used to create the space for feedthrough 191 etches a portion of gate spacer layer 134 and the corresponding pad layer. Consequently, feedthrough 191 abuts dielectric layer 167 of the continuous polysilicon diffusion edge structure 163. Dimension D4 is nearly equal to dimension D3, corresponding to twice the contact-polysilicon pitch. This reduces the resistance of feedthrough 191.

[0100] FIG19B is a Y-view of the integrated circuit 100 of FIG19A according to certain embodiments. FIG19B shows that the width dimension D5 of the feedthrough 191 in the Y direction is substantially equal to the distance between the gate isolation structure 157a and the gate isolation structure 157b, which results in a lower overall resistance of the feedthrough 191.

[0101] FIG20A is an X-ray view of integrated circuit 100 according to certain embodiments. In FIG20A , source / drain contacts 173 have a vertical dimension D6. Dummy gate metal 156 has a vertical dimension D7. In certain embodiments, vertical dimension D7 is slightly larger than vertical dimension D6. Dummy gate metal 156 extends to the same height as source / drain contacts 173. In certain embodiments, vertical dimension D6 and vertical dimension D7 are substantially equal. As described in FIG18 , these conductive vias 183 can be combined into a single conductive via 183.

[0102] FIG20B is a perspective view of the integrated circuit 100 of FIG20A according to some embodiments. This perspective view does not show the dielectric layers present in the integrated circuit 100. The perspective view of FIG20B shows the source / drain region 140, the dummy gate metal 156, the source / drain contact 173, the conductive via 183, the metal line 185, and the feedthrough 191.

[0103] FIG21A is an X-ray view of integrated circuit 100 according to certain embodiments. In FIG21A , dielectric layers 205 and 207 are formed before forming source / drain contacts 173. The compositions of dielectric layers 205 and 207 are substantially similar to those of dielectric layers 176 and 177, respectively. Conductive vias 183 are then formed through dielectric layers 176 and 177. Conductive vias 183, which contact dummy gate metal 156, penetrate dielectric layers 207 and 205. As a result, the vertical dimension D6 of source / drain contacts 173 is greater than the vertical dimension D7 of dummy gate metal 156. Furthermore, source / drain contacts 173 extend to a greater height than dummy gate metal 156. As described in FIG18 , these conductive vias 183 can be combined into a single conductive via 183.

[0104] FIG21B is a perspective view of the integrated circuit 100 of FIG20A according to certain embodiments. This perspective view does not show the dielectric layers present in the integrated circuit 100. The perspective view of FIG21B shows the source / drain regions 140, the dummy gate metal 156, the source / drain contacts 173, the conductive vias 183, the metal lines 185, and the feedthroughs 191. In FIG21B, the conductive vias 183 are combined into a single conductive via that includes a downwardly protruding portion to contact the dummy gate metal 156.

[0105] FIG22 is a flow chart of a method 2200 for forming an integrated circuit according to certain embodiments. This method 2200 may utilize the structures, processes, and systems described in connection with FIG1 through FIG21B. In operation 2202, method 2200 includes forming a first transistor, the first transistor including a gate metal wrapped around a plurality of stacked first channels. An example of the first transistor is transistor 101a in FIG14A. An example of the gate metal is gate metal 155 in FIG14A. An example of the stacked first channels is channel 105a in FIG14A. In operation 2204, method 2200 includes forming a second transistor separated from the first transistor in a first lateral direction, the second transistor including a gate metal wrapped around a plurality of stacked second channels. An example of the second transistor is transistor 101d in FIG14A. An example of the gate metal is gate metal 155 in FIG14A. An example of a stacked second channel is channel 105d in FIG. 14A . At operation 2206, method 2200 includes forming a dummy structure between the first transistor and the second transistor, wherein the dummy structure includes a dummy gate metal. An example of a dummy structure is dummy structure 101b in FIG. 14A . An example of a dummy gate metal is dummy gate metal 156 in FIG. 14A . At operation 2208, method 2200 includes forming a feedthrough extending from beneath the dummy structure to contact the dummy gate metal. An example of a feedthrough is feedthrough 191 in FIG. 14A .

[0106] Embodiments of the present disclosure provide an integrated circuit (IC) having a feedthrough structure that provides an electrical connection between backside metal lines and frontside metal lines of the IC. The feedthrough structure incorporates source / drain contacts, dummy gate metal, and source / drain conductive vias. The dummy gate metal is formed to replace the gate metal of a gate-wrap transistor structure located between two continuous polysilicon diffusion edge structures. Consequently, the feedthrough unit exhibits low area loss and low resistance, thereby increasing processing speed and reducing power consumption.

[0107] In some embodiments, a method for manufacturing an integrated circuit includes forming a first transistor, forming a second transistor, forming a dummy structure, and forming a feedthrough. The first transistor includes a gate metal wrapped around a plurality of stacked first channels; the second transistor is separated from the first transistor in a first lateral direction and includes a gate metal wrapped around a plurality of stacked second channels; the dummy structure is between the first transistor and the second transistor, wherein the dummy structure includes a dummy gate metal having a lower resistivity than the gate metal; and the feedthrough extends from below the dummy structure to contact the dummy gate metal.

[0108] In some embodiments, the dummy gate metal wraps around the stacked plurality of dummy channels.

[0109] In some embodiments, the operation of forming the dummy structure includes: depositing gate metal around the plurality of dummy channels surrounding the dummy structure, around the plurality of first channels, and around the plurality of second channels, removing the gate metal from the dummy structure, and replacing the gate metal in the dummy structure with the dummy gate metal.

[0110] In some embodiments, the method further includes forming a first dummy source / drain contact of a dummy structure, forming a second dummy source / drain contact of the dummy structure, and forming a first metal line on the dummy structure, and electrically shorting the first dummy source / drain contact, the second dummy source / drain contact, and the dummy gate metal to the first metal line.

[0111] In some embodiments, the operation of electrically short-circuiting the first dummy source / drain contact, the second dummy source / drain contact, and the dummy gate metal to the first metal line includes: forming a first conductive via coupled between the first dummy source / drain contact and the first metal line, forming a second conductive via coupled between the second dummy source / drain contact and the first metal line, and forming a third conductive via coupled between the dummy gate metal and the first metal line.

[0112] In some embodiments, the operation of electrically short-circuiting the first dummy source / drain contact, the second dummy source / drain contact, and the dummy gate metal to the first metal line includes: forming a conductive via in contact with the first dummy source / drain contact, the second dummy source / drain contact, the dummy gate metal, and the first metal line.

[0113] In some embodiments, the method further includes forming a second metal line below the feedthrough hole and in contact with the feedthrough hole.

[0114] In some embodiments, the feedthrough hole contacts the first dummy source / drain contact and the second dummy source / drain contact.

[0115] In some embodiments, the method further includes forming a gate isolation structure to electrically isolate the gate metal of the first transistor from the dummy gate metal of the dummy structure.

[0116] In some embodiments, the method further includes forming a first polysilicon gate structure extending along a first lateral direction, forming a second polysilicon gate structure extending parallel to the first polysilicon gate structure, and forming a dummy gate metal and a feedthrough hole between the first polysilicon gate structure and the second polysilicon gate structure.

[0117] In some embodiments, an integrated circuit includes a substrate, a dummy structure, and a feedthrough. The dummy structure includes a dummy gate metal, a first dummy source / drain contact, and a second dummy source / drain contact. The feedthrough extends through the substrate and contacts the dummy gate metal, the first dummy source / drain contact, and the second dummy source / drain contact.

[0118] In some embodiments, the integrated circuit further includes a first transistor and a second transistor. The first transistor includes a plurality of stacked first channels and a gate metal. The gate metal surrounds the stacked first channels. The second transistor is separated from the first transistor along a first lateral direction and includes a plurality of stacked second channels. The gate metal surrounds the stacked second channels, and a dummy structure is located between the first transistor and the second transistor, wherein the dummy gate metal has a lower resistivity than the gate metal.

[0119] In some embodiments, the dummy gate metal includes: a plurality of stacked dummy channels, and the dummy gate metal surrounds the plurality of stacked dummy channels.

[0120] In some embodiments, the dummy gate metal is in direct contact with the stacked plurality of dummy channels.

[0121] In some embodiments, the dummy gate metal, the first dummy source / drain contact, and the second dummy source / drain contact extend to the same height.

[0122] In some embodiments, the feedthrough hole extends into the dummy gate metal.

[0123] In some embodiments, the integrated circuit further includes: a first metal line, a second metal line, and a conductive via. The first metal line is above the dummy structure; the second metal line is below and in contact with the feedthrough; and the conductive via is between the dummy gate metal and the first metal line and in contact with both the dummy gate metal and the first metal line.

[0124] In some embodiments, an integrated circuit includes: a first transistor, a second transistor, a dummy structure, a backside feedthrough, and a first metal line. The first transistor includes a gate metal; the second transistor includes a gate metal; the dummy structure is located between the first and second transistors and includes: a plurality of semiconductor nanostructures and a dummy gate metal. The dummy gate metal surrounds the plurality of semiconductor nanostructures; the backside feedthrough contacts a bottom portion of the dummy gate metal; and the first metal line is above the dummy gate metal and electrically connected to the backside feedthrough.

[0125] In some embodiments, the dummy structure includes a first dummy source / drain contact and a second dummy source / drain contact, wherein the first dummy source / drain contact and the second dummy source / drain contact are in contact with the back feedthrough hole.

[0126] In some embodiments, the back feedthrough includes a U-shaped cross section, the dummy gate metal contacts the back feedthrough at a bottom of the U-shaped cross section, and the first dummy source / drain contact and the second dummy source / drain contact contact contact the back feedthrough at respective tops of the U-shaped cross section.

[0127] The above summarizes the features of several embodiments to facilitate a better understanding of the various aspects of this disclosure by those skilled in the art. Those skilled in the art should understand that they can readily build upon the teachings of this disclosure to design or modify other processes and structures to achieve the same objectives and / or obtain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they may make various modifications, substitutions, and alterations to this disclosure without departing from the spirit and scope of this disclosure.

[0128] 100: Integrated Circuit 102: Base 103:Semiconductor stacking 104: semiconductor layer 106: semiconductor sacrificial layer 110: Groove 112:Semiconductor fins 116: Shallow trench isolation area 105: Channel 105a~105d: Channel 107:Semiconductor sacrificial nanostructures 118: Sacrificial gate structure 120: Source / drain trench 122: Stack 126: dielectric layer 130: dielectric layer 132: dielectric layer 159: Dielectric layer 161: Dielectric layer 167~169: Dielectric layer 175~179: dielectric layer 181: Dielectric layer 189: Dielectric layer 195: Dielectric layer 197: Dielectric layer 205: dielectric layer 128: Sacrificial gate layer 134: Gate spacer layer 136: Internal spacer 140: Source / Drain Region 140a~140b: source / drain region 144: contact etch stop layer 146: interlayer dielectric layer 101: Transistor 101a~101d: Transistor 151:Interface gate dielectric layer 153: High K gate dielectric layer 155: Gate Metal 142: Source / drain contact 173: Source / drain contact 157a~157b: Gate isolation structure 163:Continuous polysilicon diffusion edge structure 165: Polysilicon layer 171: Groove 156:Dummy Gate Metal 174: Silicide 185:Metal wire 199:Metal Wire 187: Conductive pad 193: Conductive pad 201: conductive pad 183: Conductive vias 191: Feedthrough hole 206: Feedthrough hole structure 2200:Method 2202~2208: Operation X: cutting line Y: cutting line 7B: Cutting line 8B: Cutting line 8C: Cutting Line D1~D5: scale D6~D7: vertical scale

Claims

1. A method for manufacturing an integrated circuit, comprising: A first transistor is formed, the first transistor including a gate metal that surrounds and encloses a plurality of stacked first channels; A second transistor is formed, the second transistor being separated from the first transistor in a first lateral direction, and the second transistor including the gate metal surrounding a plurality of stacked second channels; a dummy structure is formed between the first transistor and the second transistor, wherein the dummy structure includes a dummy gate metal, wherein the operation of forming the dummy structure includes: depositing the gate metal around the dummy channels surrounding the dummy structure, around the first channels, and around the second channels; removing the gate metal from the dummy structure; replacing the gate metal in the dummy structure with the dummy gate metal; and forming a feedthrough extending from below the dummy structure to contact the dummy gate metal.

2. A method of manufacturing an integrated circuit as described in claim 1, wherein the dummy gate metal encloses and surrounds a plurality of dummy channels stacked together.

3. The method of manufacturing an integrated circuit as described in claim 1 further includes: A first virtual source / drain junction is formed to form this virtual structure; A second dummy source / drain junction is formed to create this dummy structure; and a first metal line formed on the dummy structure; electrically short-circuit the first dummy source / drain contact, the second dummy source / drain contact and the dummy gate metal with the first metal line.

4. The method of manufacturing an integrated circuit as described in claim 3, wherein the operation of electrically shorting the first dummy source / drain contact, the second dummy source / drain contact, and the dummy gate metal from the first metal line includes: A first conductive via is formed and coupled between the first dummy source / drain contact and the first metal line; A second conductive via is formed, coupled between the second dummy source / drain contact and the first metal line; and a third conductive via is formed, coupled between the dummy gate metal and the first metal line.

5. The method of manufacturing an integrated circuit as described in claim 3, wherein the operation of electrically shorting the first dummy source / drain contact, the second dummy source / drain contact, and the dummy gate metal from the first metal line includes: A conductive via is formed, which is in contact with the first dummy source / drain contact, the second dummy source / drain contact, the dummy gate metal, and the first metal wire.

6. The method of manufacturing an integrated circuit as described in claim 1 further includes: A gate isolation structure is formed to electrically isolate the gate metal of the first transistor from the dummy gate metal of the dummy structure.

7. The method of manufacturing an integrated circuit as described in claim 1 further includes: A first polycrystalline silicon gate structure is formed and extends along the first lateral direction; A second polycrystalline silicon gate structure is formed, extending parallel to the first polycrystalline silicon gate structure; And between the first polycrystalline silicon gate structure and the second polycrystalline silicon gate structure, the dummy gate metal and the feedthrough are formed.

8. An integrated circuit, comprising: One base; A dummy structure includes: a dummy gate metal; a first dummy source / drain contact; and a second dummy source / drain contact; a feedthrough extending through the substrate and contacting the dummy gate metal, the first dummy source / drain contact, and the second dummy source / drain contact; a first transistor including: a plurality of stacked first channels; and a gate metal surrounding the first channels; and a second transistor separated from the first transistor along a first lateral direction, and including: a plurality of stacked second channels, the gate metal surrounding the second channels, the dummy structure being located between the first transistor and the second transistor, wherein the resistivity of the dummy gate metal is lower than that of the gate metal.

9. An integrated circuit, comprising: A first transistor including a gate metal; a second transistor including the gate metal; a dummy structure located between the first transistor and the second transistor, and including: a plurality of semiconductor nanostructures; and a dummy gate metal surrounding the semiconductor nanostructures; a back feedthrough contacting a bottom of the dummy gate metal, wherein the back feedthrough has a first top surface in contact with the dummy gate metal and a second top surface on both sides of the dummy gate metal, and the second top surface is higher than the first top surface; and a first metal wire on the dummy gate metal and electrically connected to the back feedthrough.

10. The integrated circuit as described in claim 9, wherein the dummy structure includes: First dummy source / drain junction; And a second dummy source / drain contact, wherein the first dummy source / drain contact and the second dummy source / drain contact are in contact with the back feedthrough.

11. The integrated circuit as claimed in claim 10, wherein the back-side feedthrough includes: A U-shaped cross-section is provided, in which the dummy gate metal contacts the bottom of the back feedthrough, and the first dummy source / drain contact and the second dummy source / drain contact contact the back feedthrough at their respective tops of the U-shaped cross-section.

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