Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device includes forming a bit line structure on a substrate, forming spacers along the sidewalls of the bit line structure, wherein each spacer includes an air gap. The method further includes forming conductive structures between and over the bit line structures, wherein the conductive structures expose portions of the bit line structures. The method further includes forming an isolation structure between the conductive structures and the bit line structures, implanting the isolation structure to form an implanted isolation structure, forming a support layer over the implanted isolation structure and the conductive structure, and forming a capacitor structure over the conductive structure and the implanted isolation structure.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. [Previous Technology]

[0002] A conventional semiconductor device connects a capacitor and a transistor. For example, the capacitor can sit perfectly on a landing pad. As technology miniaturizes, the overlay control between the capacitor and the landing pad requires greater precision to increase the process integration margin. However, the isolation structure between adjacent landing pads can be easily damaged during capacitor formation, resulting in electrical shorts and loss of air gap (AG) functionality. [Summary of the Invention]

[0003] This disclosure provides a method for manufacturing a semiconductor device. The method includes forming a bit line structure on a substrate, forming spacers along the sidewalls of the bit line structure, wherein each spacer includes an air gap. The method further includes forming conductive structures between and over the bit line structures, wherein the conductive structures expose portions of the bit line structures. The method further includes forming an isolation structure between the conductive structures and the bit line structures, implanting the isolation structure to form an implanted isolation structure, forming a support layer over the implanted isolation structure and the conductive structure, and forming a capacitor structure over the conductive structure and the implanted isolation structure.

[0004] This disclosure provides a semiconductor device. The semiconductor device includes a substrate, a bit line structure above the substrate, spacers along the sidewalls of the bit line structure, a conductive structure between the spacers, and an isolation structure between the conductive structure and the bit line structure, wherein each spacer includes an air gap and an implanted isolation structure.

[0005] A semiconductor device having an implanted isolation structure between the conductive structure and the bit line structure. The implanted isolation structure has high etching resistance and can prevent punching through the air gap AG when the capacitor structure is misaligned. In addition, the width of the bottom surface of the bottom electrode layer can be increased to improve the contact resistance between the capacitor structure and the landing pad.

Implementation Method

[0007] Embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0008] Referring to Figure 1, a substrate 100 is provided. The substrate 100 includes an active region 101 and an isolation structure 102 defining the active region 101 in the substrate 100. A dielectric layer 106 is formed over the active region 101 and the isolation structure 102. Bit line contacts 108 are formed in the dielectric layer 106 and contact the active region 101. The substrate 100 may be a silicon substrate or other suitable semiconductor substrate. The isolation structure 102 may be formed of silicon oxide, silicon nitride, etc. The dielectric layer 106 may be formed of silicon oxide, silicon nitride, etc.

[0009] A bitline structure 110 is formed above the substrate 100. The bitline structure 110 includes a barrier layer 112, a metal layer 114 above the barrier layer 112, and a hard mask layer 116 above the metal layer 114. The bitline structure 110 may be formed, for example, by sequentially forming a barrier material layer, a metal material layer, and a hard mask material layer above the substrate 100. Then, the barrier material layer, the metal material layer, and the hard mask material layer are patterned to form the barrier layer 112, the metal layer 114, and the hard mask layer 116, and the bitline structure 110 is formed.

[0010] A first spacer layer 122, a sacrificial spacer layer 124, and a second spacer layer 126 are sequentially formed along the sidewall of the bit line structure 110. First, a first spacer material layer conformally to the bit line structure 110 and the dielectric layer 106 is formed. Then, an anisotropic process is performed to remove the horizontal portion of the first spacer material layer, and the vertical portion of the first spacer material layer forms the first spacer layer 122. The first spacer layer 122 contacts and conforms to the sidewall of the bit line structure 110. Afterward, the first spacer layer 122, the bit line structure 110, and the dielectric layer 106 conformally form the second spacer material layer. Then, an anisotropic process is performed to remove the horizontal portion of the second spacer material layer, and the vertical portion of the second spacer material layer forms the sacrificial spacer layer 124. The sacrificial spacer layer 124 contacts and conforms to the first spacer layer 122. Subsequently, a conformal sacrificial spacer layer 124, a bit line structure 110, and a dielectric layer 106 form a second spacer layer 126. The first spacer layer 122, the sacrificial spacer layer 124, and the second spacer layer 126 are formed of a dielectric material such as silicon oxide or silicon nitride, and the sacrificial spacer layer 124 is formed of a material different from that of the first spacer layer 122 and the second spacer layer 126. For example, if the first spacer layer 122 and the second spacer layer 126 are formed of silicon nitride, the sacrificial spacer layer 124 is formed of silicon oxide.

[0011] Referring to Figure 2, trench T1 is formed between bit line structures 110 and exposes a portion of the substrate 100. Next, trench T1 is formed by performing an etching process to expose the substrate 100 through the second spacer layer 126 and the dielectric layer 106. During the formation of trench T1, the second spacer layer 126 above the bit line structures 110 is also removed, thereby exposing the top surface of the bit line structures 110.

[0012] Referring to Figure 3, a first conductive layer 132 is formed in a trench T1 between the bit line structures 110. Specifically, a first conductive material layer may be formed first to fill the trench T1. Then, a planarization process is performed to remove excess portions of the first conductive material layer above the bit line structures 110 to expose the top surface of the bit line structures 110. Subsequently, the first conductive material layer is etched back to form the first conductive layer 132 in the trench T1. In some embodiments, the first conductive layer 132 is formed of doped polysilicon.

[0013] Referring to Figure 4, a second conductive layer 134 is formed over the first conductive layer 132, a barrier layer 136 is formed over the second conductive layer 134, and a landing pad material layer 138' is formed by filling the trench T1 between the bit line structures 110. In some embodiments, the second conductive layer 134 can be formed by depositing a metal layer in contact with the top surface of the first conductive layer 132. In some other embodiments, the second conductive layer 134 can be formed by forming a second conductive material layer by filling the trench T1. Subsequently, a planarization process is performed to remove excess portions of the second conductive material layer over the bit line structure 110 to expose the top surface of the bit line structure 110. Subsequently, the second conductive material layer is etched back to form the second conductive layer 134 in the trench T1 and over the first conductive layer 132.

[0014] After forming the second conductive layer 134, a barrier layer 136 is formed above the second conductive layer 134. Specifically, the conformal bit line structure 110 and the second conductive layer 134 form a barrier material layer. Subsequently, the barrier material layer above the bit line structure 110 is removed to expose the top surface of the bit line structure 110, and the remaining portion of the barrier material layer forms the barrier layer 136. After forming the barrier layer 136, a landing pad material layer 138' is formed by filling the trench T1 between the bit line structures 110. In some embodiments, the second conductive layer 134 is formed of a metal silicate, the barrier layer 136 is formed of TaN or TiN, but is not limited thereto, and the landing pad material layer 138' is formed of Ti, TiN, Ta, TaN, W, Cu, Au, or an alloy thereof, but is not limited thereto.

[0015] Referring to Figure 5, a trench T2 is formed by removing a portion of the barrier layer 136, a portion of the landing pad material layer 138', and a portion of the bit line structure 110. After forming the trench T2, a landing pad 138 is formed by retaining the portion of the landing pad material layer 138' above the barrier layer 136 and the bit line structure 110. The vertically stacked first conductive layer 132, second conductive layer 134, barrier layer 136, and landing pad 138 can be collectively referred to as conductive structure 130. That is, after forming the trench T2, conductive structure 130 is formed between and above the bit line structures 110, and conductive structure 130 can serve as a contact to connect the active region 101 in the substrate 100 and the subsequently formed capacitor structure 200. A trench T2 can be formed by performing an etching process to expose the sacrificial spacer layer 124 (as shown in Figure 4), followed by removing the sacrificial spacer layer 124 to form an air gap AG between the first spacer layer 122 and the second spacer layer 126. Thus, a spacer 120 comprising the first spacer layer 122, the second spacer layer 126, and the air gap AG is formed along the sidewall of the bit line structure 110. The first spacer layer 122 contacts the bit line structure 110. The second spacer layer 126 contacts the conductive structure 130, and the first spacer layer 122 is separated from the second spacer layer 126 by the air gap AG. In some embodiments, the sacrificial spacer layer 124 is removed by performing a wet etching process.

[0016] Referring to Figure 6, an isolation layer 140' is formed through the filling trench T2. The isolation layer 140' is used to seal the air gap AG. The manufacturing process and material of the isolation layer 140' are selected to allow the isolation layer 140' to seal the air gap AG without flowing into the air gap AG. In some embodiments, the isolation layer 140' is formed of any suitable dielectric material such as silicon, silicon nitride, etc.

[0017] Referring to Figure 7, a planarization process is performed to remove the top of the isolation layer 140' above the landing pad 138 until the top surface of the landing pad 138 is exposed. Thus, an isolation structure 140 is formed between the bit line structure 110 and the conductive structure 130. In some embodiments, the top surface of the isolation structure 140 and the top surface of the landing pad 138 are coplanar.

[0018] Referring to Figure 8, a photoresist 142 is formed over the conductive structure 130. The photoresist 142 can be formed by depositing a photoresist layer over the conductive structure 130 and the isolation structure 140, followed by patterning the photoresist layer to expose the isolation structure 140. After the photoresist 142 is formed, an implantation process is performed on the exposed isolation structure 140. The photoresist 142 can act as a hard mask layer during the implantation process and prevent the conductive structure 130 from being implanted. In some embodiments, doping such as B or Si can be selected during the implantation process, providing specific characteristics such as a significantly reduced dry etch rate. According to implantation studies on nitride film materials, using Si with a dose exceeding 3.00E+16 (ion / cm²) at an energy of 10 keV, the dry etch rate of the material can be reduced to approximately 0.26 times that of the unimplanted material. When the material is implanted with a dose of more than 5.00E+16 (ion / cm²) of boron at an energy of 10 keV, the dry etch rate of the material can be reduced to approximately 0.75 times that of the unimplanted material. The dry etch rate is measured by using etch gases including C₄F₆, CH₂F₂, C₄F₈, and O₂ over 30 seconds. After the implantation process, the doping depth can be distributed at approximately 50 nm on the top surface of the implanted isolation structure 144 by a subsequent thermal process (not shown).

[0019] Referring to Figure 9, an implanted isolation structure 144 is formed by an implantation process, followed by the removal of photoresist 142. After the isolation structure 140 is implanted, the dry etch rate of the implanted isolation structure 144 can be lower than that of the unimplanted isolation structure 140. Depending on the doping selection, such as B or Si, the dry etch rate of the implanted isolation structure 144 can be reduced to approximately 0.26 to approximately 0.75 times during the implantation process. The implanted isolation structure 144 with such a low dry etch rate can serve as an etch stop layer in subsequent processes and prevent breakdown of the air gap AG.

[0020] Referring to Figure 10, a first support layer 210, a first sacrificial layer 212, a second support layer 214, a second sacrificial layer 216, and a third support layer 218 are sequentially formed above the conductive structure 130 and the implanted isolation structure 144. In some embodiments, the first support layer 210, the second support layer 214, and the third support layer 218 are formed of a dielectric material such as silicon nitride. The first sacrificial layer 212 and the second sacrificial layer 216 are formed of a dielectric material different from that of the first support layer 210, the second support layer 214, and the third support layer 218. The first sacrificial layer 212 and the second sacrificial layer 216 may be formed of silicon oxide.

[0021] Referring to Figure 11, a trench T3 is formed through the first support layer 210, the first sacrificial layer 212, the second support layer 214, the second sacrificial layer 216, and the third support layer 218, exposing the conductive structure 130. In some embodiments, the trench T3 can be formed by performing one or more etching processes. During the formation of the trench T3, an implanted isolation structure 144 is used to prevent the process from breaking down the air gap AG. In particular, ideally, the trench T3 completely covers the top surface of the conductive structure 130 and does not expose the implanted isolation structure 144. Therefore, subsequent processes form a bottom electrode layer 220 in the trench T3 with the largest contact area with the conductive structure 130. However, in some embodiments, the trench T3 may not be aligned with the top surface of the conductive structure 130, thus exposing part of the implanted isolation structure 144. The implanted isolation structure 144 has higher etch resistance than the first support layer 210 to the etchant used during the formation of the trench T3. In some embodiments, the first support layer 210 may have a dry etch rate 8.87 times higher than that of the implanted isolation structure 144, such that the implanted isolation structure 144 can act as an etch stop layer during trench formation T3. Therefore, even if the implanted isolation structure 144 is exposed during trench formation T3, it avoids the process exposure of the air gap AG as shown in Figure 11. The bottom electrode layer 220 may fill the air gap AG and cause an electrical short circuit between the subsequently formed capacitor structure 200 and the bit line structure 110.

[0022] Referring to Figure 12, a conformal trench T3 forms a bottom electrode layer 220. In some embodiments, a conformal trench T3 is first formed over a third support layer 218 to create a bottom electrode material layer. Then, for example, the bottom electrode material layer over the third support layer 218 is removed by performing a planarization process. The remaining portion of the bottom electrode material layer forms the bottom electrode layer 220 of the conformal trench T3. In some embodiments, the bottom electrode layer 220 may be formed of a metal, a metal compound, an alloy compound, other conductive materials, or a combination thereof, such as titanium nitride or silicon-doped titanium nitride.

[0023] Referring to Figure 13, the first sacrificial layer 212 and the second sacrificial layer 216 are removed. Specifically, removing the first sacrificial layer 212 and the second sacrificial layer 216 includes forming a hole in some of the third support layers 218 until the top surface of the second sacrificial layer 216 is exposed. Then, the second sacrificial layer 216 is removed through the hole by performing a wet etching process. After removing the second sacrificial layer 216, a hole is formed in some of the second support layers 214 until the top surface of the first sacrificial layer 212 is exposed, and then the first sacrificial layer 212 is removed through the hole by performing a wet etching process. Thus, the first support layer 210, the second support layer 214, the third support layer 218, and the bottom electrode layer 220 remain in place.

[0024] Referring to Figure 14, a conformal bottom electrode layer 220, a first support layer 210, a second support layer 214, and a third support layer 218 form a dielectric layer 230, and a top electrode layer 240 is formed between the dielectric layers 230. In some embodiments, the dielectric layer 230 may be formed of a high dielectric constant dielectric material such as ZrO2, and the top electrode layer 240 may be formed of a metal, a metal compound, an alloy compound, other conductive materials, or a combination thereof, such as titanium nitride or silicon-doped titanium nitride. Thus, a capacitor structure 200 is formed over the conductive structure 130 and the isolation structure 140. The bottom electrode layer 220 of the capacitor structure 200 contacts the conductive structure 130. The dielectric layer 230 conforms to the bottom electrode layer 220, and the top electrode layer 240 conforms to the dielectric layer 230.

[0025] Figure 14 shows the resulting semiconductor device. The resulting semiconductor device includes a substrate 100, a bit line structure 110, spacers 120, a conductive structure 130, an implanted isolation structure 144, and a capacitor structure 200. The bit line structure 110 is above the substrate 100. The spacers 120 are along the sidewalls of the bit line structure 110, and each spacer 120 includes an air gap AG. The conductive structure 130 is between the spacers 120. The implanted isolation structure 144 is between the conductive structure 130 and the bit line structure 110. The capacitor structure 200 includes a first support layer 210 above the implanted isolation structure 144, a bottom electrode layer 220 above the conductive structure 130, a dielectric layer 230 of the conformal bottom electrode layer 220, a second support layer 214 and a third support layer 218 of the conformal dielectric layer 230, and a top electrode layer 240.

[0026] Each implanted isolation structure 144 seals the air gap AG, and the implanted isolation structure 144 contacts the bit line structure 110 and the conductive structure 130. The implanted isolation structure 144, using Si and B as dopants at a specific dosage, can have a lower dry etch rate than the unimplanted isolation structure 140. Further, the ratio of the dry etch rate between the first support layer 210 and the implanted isolation structure 144 is approximately 8.87. As shown in Figure 15, if the capacitor structure 200 is displaced from the top surface of the conductive structure 130, the implanted isolation structure 144 is used to prevent the process of manufacturing the capacitor structure 200 from exposing the air gap AG through impact.

[0027] In Figure 15, the trench used to form the bottom electrode layer 220 (e.g., trench T3 in Figure 11) is displaced from the top surface of the conductive structure 130 due to misalignment. As previously described, the implantation isolation structure 144 performing the implantation process has high etch resistance to the etchant used to form the trench T3 for forming the bottom electrode layer 220. Therefore, the implantation isolation structure 144 acts as an etch stop layer, and the air gap AG below remains sealed after the capacitor structure 200 is formed. The resulting bottom electrode layer 220 is also displaced from the top surface of the conductive structure 130 and contacts the implantation isolation structure 144. If the implantation isolation structure 144 does not have high etch resistance to the etchant mentioned in Figure 11, and if the trench T3 used to form the bottom electrode layer 220 is displaced from the top surface of the conductive structure 130, the air gap AG will be opened. The bottom electrode layer 220 may fill the air gap AG and cause an electrical short circuit between the capacitor structure 200 and the bit line structure 110.

[0028] Figure 16 illustrates another embodiment of the semiconductor device of this disclosure. A trench T3 may be formed to have a width W1, which is greater than the width W2 of the top surface of the conductive structure 130 due to the higher etch resistance of the implanted isolation structure 144 (as shown in Figure 11). The trench T3 may expose portions of the top surfaces of the implanted isolation structure 144 and the conductive structure 130. After the bottom electrode layer 220 is formed, the width of the bottom surface of the bottom electrode layer 220 is greater than the width W2 of the top surface of the conductive structure 130, resulting in a larger contact area between the bottom electrode layer 220 and the conductive structure 130. The larger contact area between the bottom electrode layer 220 and the conductive structure 130 can result in the benefit of lower contact resistance.

[0029] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0030] It will be apparent to those skilled in the art that various modifications and changes can be made to the structure of this disclosure without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and changes to this disclosure that fall within the scope of the appended patent applications. [Simplified Explanation of the Diagram]

[0006] This disclosure can be more fully understood by reading the following embodiments and the detailed description in conjunction with the accompanying drawings: Figures 1 to 14 are cross-sectional views of manufacturing methods for forming semiconductor devices at various stages according to some embodiments of this disclosure. Figures 15 and 16 are cross-sectional views of semiconductor devices according to some embodiments of this disclosure. [Biomaterial Storage]

[0032] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for manufacturing a semiconductor device, comprising: A plurality of bit line structures are formed above a substrate; a plurality of spacers are formed along a plurality of sidewalls of the bit line structures, each spacer including an air gap; a plurality of conductive structures are formed between and above the bit line structures, wherein the conductive structures expose portions of the bit line structures; a plurality of isolation structures are formed between the conductive structures and the bit line structures; the isolation structures are implanted to form a plurality of implanted isolation structures; a support layer is formed above the implanted isolation structures and the conductive structures; and a plurality of capacitor structures are formed above the conductive structures and the implanted isolation structures.

2. The method as described in claim 1, wherein forming the spacers along the sidewalls of the bitline structures, each spacer including the air gap, comprises the step of: A first spacer layer, a sacrificial spacer layer, and a second spacer layer are sequentially formed along the sidewalls of these bit line structures; And after forming these conductive structures, the sacrificial spacer layer is removed.

3. The method as described in claim 1, wherein forming the conductive structures between and above the bit line structures comprises: A first trench is formed between these bit line structures, and the first trench exposes a portion of the substrate; A first conductive layer is formed in the first trench; A second conductive layer is formed above the first conductive layer; a barrier layer is formed above the second conductive layer; a landing pad is formed to overfill the first trench; and a second trench is formed by removing a portion of the barrier layer, a portion of the landing pad, and a portion of the bitline structures.

4. The method as described in claim 1, wherein forming the isolation structures between the conductive structures and the bit line structures comprises: An isolation layer is formed between and above these conductive structures and these bit line structures; And remove a top of the isolation layer, wherein a top surface of the isolation layer is coplanar with a top surface of the conductive structures.

5. The method as described in claim 1, wherein the isolation structures are implanted to form the implanted isolation structures, comprising: A photoresist layer is deposited over these conductive structures; the photoresist layer is patterned to expose a portion of these insulating structures; And implanting multiple dopants into the exposed portion of these isolation structures.

6. The method as described in claim 5, wherein the doping depth of the dopants is approximately 50 nm on a top surface of the implanted isolation structure.

7. The method as claimed in claim 1, wherein the implanted isolation structures have a first dry etch rate that is less than a second dry etch rate of the isolation structures.

8. The method as described in claim 1, wherein the implanted isolation structures have a first dry etch rate that is less than a third dry etch rate of the support layer.

9. The method as described in claim 8, wherein a ratio of the third dry etch rate to the first dry etch rate is greater than 8.

87.

10. The method as claimed in claim 1, wherein forming the capacitor structures over the conductive structures and the implanted isolation structures comprises: A plurality of bottom electrodes are formed above these conductive structures; a plurality of dielectric layers are formed conformally to these bottom electrodes; And to form a plurality of top electrode layers conforming to these dielectric layers.

11. A semiconductor device, comprising: One substrate; A complex number of unit line structures are located above the substrate; A plurality of spacers are arranged along a plurality of sidewalls of the bit line structures, each spacer including an air gap; a plurality of conductive structures are arranged between the spacers; and a plurality of implanted isolation structures are arranged between the conductive structures and the bit line structures.

12. The semiconductor device as claimed in claim 11, wherein each of the spacers comprises: A first spacer layer contacts one of the bit line structures; And a second spacer layer contacts one of the conductive structures, wherein the first spacer layer is separated from the second spacer layer by the air gap.

13. The semiconductor device as described in claim 11, further comprising: A plurality of capacitor structures are located above the conductive structures and the implanted isolation structures, wherein each capacitor structure includes: a bottom electrode contacting the conductive structure; a dielectric layer conforming to the bottom electrode; and a top electrode layer conforming to the dielectric layer.

14. The semiconductor device as claimed in claim 13, wherein the bottom electrodes of the capacitor structures further contact the implanted isolation structures.

15. The semiconductor device as claimed in claim 13, wherein the width of a bottom surface of the bottom electrodes is greater than the width of a top surface of the conductive structures.

16. The semiconductor device as claimed in claim 11, wherein a top surface of the implanted isolation structure is coplanar with a top surface of the conductive structure.

17. The semiconductor device as claimed in claim 11, wherein the implanted isolation structures are implanted with B and Si as a plurality of dopants.

18. The semiconductor device as claimed in claim 17, wherein the doping depth of the dopants is about 50 nm on a top surface of the implanted isolation structure.

19. The semiconductor device as claimed in claim 11, wherein the implanted isolation structures contact the spacers and the bit line structures.

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