Amplifier device

Abstract

An amplifier device. The amplifier device includes an inductor, a capacitor, an amplifier, a driver circuit, and a bias circuit. The inductor and capacitor are connected in series between a bias point and a first reference voltage terminal. The amplifier is coupled to the bias point to receive a bias signal. The driver circuit receives a start signal and provides a charge signal. The bias circuit is coupled to the bias point and the driver circuit. In a first mode, the start signal has a first threshold, and the bias circuit provides a bias signal at the bias point based on the bias reference signal and the charge signal. In a second mode, the start signal has a second threshold, and the bias circuit provides a bias signal at the bias point based on the bias reference signal.

Description

Technical Field

[0001] This invention relates to a circuit design technique for communication, and more particularly to an amplifier device. Prior Technology

[0002] Amplifiers are commonly used in wired or wireless communication technologies to amplify signals. Because current communication technologies demand higher signal transmission speeds, the signal processing frequency has also increased, leading to increased noise at the amplifier's input or bias terminals. To reduce noise and avoid affecting the overall signal linearity of the circuit, a relatively large capacitor is added at the amplifier's input or bias terminals.

[0003] However, this capacitor may prolong the amplifier's transient state, requiring a longer transient processing time to reach steady state. Therefore, one direction of technical research is to enable the amplifier to maintain its signal linearity while still having a short transient processing time. Summary of the Invention

[0004] The amplifier device of the present invention includes an inductor, a capacitor, an amplifier, a driver circuit, and a bias circuit. The capacitor and inductor are connected in series. The inductor and capacitor are connected in series between a bias point and a first reference voltage terminal. The amplifier is coupled to the bias point to receive a bias signal. The driver circuit receives a start signal and provides a charging signal. The bias circuit is coupled to the bias point and the driver circuit. In a first mode, the start signal has a first threshold, and the bias circuit provides the bias signal at the bias point based on a bias reference signal and the charging signal. In a second mode, the start signal has a second threshold, and the bias circuit provides the bias signal at the bias point based on the bias reference signal. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram of an amplifier circuit according to an embodiment of the present invention. Figure 2 is a circuit diagram of an amplifier circuit according to a first embodiment of the present invention. Figure 3 is a detailed circuit diagram of a low-dropout regulator according to an embodiment of the present invention. Figure 4 is a waveform diagram of the reference voltage, start signal, and charging signal according to an embodiment of the present invention. Figure 5 is a circuit diagram of a compensation circuit according to an embodiment of the present invention. Implementation

[0006] Figure 1 is a block diagram of an amplifier circuit 100 according to an embodiment of the present invention. The amplifier circuit 100 includes an inductor L1, a capacitor C1, an amplifier 110, a drive circuit 120, and a bias circuit 130. The capacitor C1 is connected in series with the inductor L1. The inductor L1 and the capacitor C1 are connected in series between the bias point NVX and the reference voltage terminal VREF2 (e.g., ground). The reference voltage terminal VREF2 has a reference voltage (e.g., ground voltage). In this embodiment, the capacitor C1 has a capacitance value of approximately 10nF to 50nF.

[0007] Amplifier 110 is coupled to the bias point NVX to receive the bias signal Sx at the bias point NVX. Driver circuit 120 receives a start signal STS and provides a charging signal CCS. Bias circuit 130 is coupled to the bias point NVX and driver circuit 120. Bias circuit 130 provides the bias signal Sx at the bias point NVX based on a bias reference signal (e.g., bias current IBIAS in this embodiment) and selectively based on the charging signal CCS.

[0008] In one embodiment, the activation or deactivation of the drive circuit 120 is controlled by a start signal STS. For example, in a first mode, the start signal STS has a first threshold (e.g., logic "1"). The drive circuit 120 is activated in response to the start signal STS with the first threshold and provides a charging signal CCS to the bias circuit 130. The bias circuit 130 provides a bias signal Sx at the bias point NVX based on a bias reference signal (e.g., bias current IBIAS) and the charging signal CCS. On the other hand, in a second mode, the start signal STS has a second threshold (e.g., logic "0"). The drive circuit 120 is deactivated in response to the start signal STS with the second threshold and does not provide a charging signal CCS to the bias circuit 130. The bias circuit 130 provides a bias signal Sx at the bias point NVX based on a bias reference signal (e.g., bias current IBIAS). In this embodiment, the bias signal Sx in the first mode is greater than the bias signal Sx in the second mode because the bias signal Sx in the first mode is also affected by the charging signal CCS, which increases its current / voltage. In the second mode, the bias circuit 130, based on the bias reference signal, may include at least the following embodiments, as long as the bias signal Sx in the first mode is greater than the bias signal Sx in the second mode: In one embodiment, in the second mode, the bias circuit 130 provides the bias signal Sx at the bias point NVX solely based on the bias reference signal (e.g., bias current IBIAS). In another embodiment, in the second mode, the bias circuit 130 provides the bias signal Sx at the bias point NVX solely based on the bias reference signal and stops providing the bias signal Sx at the bias point NVX based on the charging signal CCS. In yet another embodiment, in the second mode, the bias circuit 130 provides the bias signal Sx at the bias point NVX based on the bias reference signal and a value less than the charging signal CCS in the first mode.

[0009] Figure 2 is a circuit diagram of amplifier circuit 100-1 according to a first embodiment of the present invention. Amplifier circuit 100-1 in Figure 2 is one implementation of amplifier circuit 100 in Figure 1. Figure 2 mainly shows the detailed circuit structure of amplifier 110, drive circuit 120 and bias circuit 130. Amplifier 110 mainly includes transistor MA1 used as an amplifier. One end of transistor MA1 (e.g., collector terminal) can be coupled to reference voltage terminal VREF1 through inductor L2 to receive reference voltage (e.g., reference voltage VREF), and the other end of transistor MA1 (e.g., emitter terminal) is coupled to reference voltage terminal VREF2 (e.g., ground terminal or 0V). Control terminal (e.g., base terminal) of transistor MA1 is coupled to bias terminal NVX. In one embodiment, one end of transistor MA1 can be coupled to circuit operating voltage terminal through inductor L2 to receive circuit operating voltage (e.g., VCC or third reference voltage). In detail, in this embodiment, the voltage of the reference voltage terminal VREF1 may be, for example, the circuit operating voltage, the system voltage, or other reference voltage different from the reference voltage terminal VREF2, and its voltage value remains unchanged for at least a period of time (for example, it remains unchanged in the first mode and / or the second mode) or remains unchanged continuously.

[0010] The drive circuit 120 mainly includes a low-dropout regulator (LDO). The LDO receives a start signal STS to generate a charging signal CCS. The drive circuit 120 also includes a compensation circuit 140. The compensation circuit 140 generates the start signal STS. The start signal STS may be related to at least one of a reference voltage VREF (e.g., system voltage VDD), temperature, and PN junction voltage.

[0011] The amplifier circuit 100-1 in Figure 2 also includes a current source circuit 150, which provides a bias current IBIAS to the bias circuit 130. Specifically, the current source circuit 150 includes a current source 151, a current mirror circuit 152, and a current mirror circuit 155. One end of the current mirror circuit 152 receives the current IREF provided by the current source 151 and provides a current IREF1 to the other end of the current mirror circuit 155 via a first branch. The current mirror circuit 155 includes an operational amplifier OP1, a transistor M1 flowing with the bias current IBIAS, and a transistor M2 flowing with the current IREF1. The first terminals (e.g., source terminals) of transistors M1 and M2 are coupled to a reference voltage terminal VREF1 to receive a reference voltage (e.g., reference voltage VREF), and the second terminal (e.g., drain terminal) of transistor M2 provides the bias current IBIAS to the bias circuit 130. The non-inverting input terminal of the operational amplifier OP1 is coupled to the second terminal (e.g., drain terminal) of transistor M1. The inverting input of operational amplifier OP1 is coupled to the second terminal (e.g., drain terminal) of transistor M2. The output of operational amplifier OP1 is coupled to the control terminals (e.g., gate terminals) of transistors M1 and M2. By designing the transistor dimensions of transistors M1 and M2, the ratio of the bias current IBIAS to the current IREF1 can be adjusted. In one embodiment, the current source circuit 150 may not include operational amplifier OP1.

[0012] The bias circuit 130 includes a transistor T1. The control terminal (e.g., base terminal) of transistor T1 is coupled to the drive circuit 120 via resistor R2 to receive the charging signal CSS. The control terminal of transistor T1 and the first terminal of diode T2 can be coupled to the reference voltage terminal VREF1 via resistor R2 and transistor M1 to receive a reference voltage (e.g., reference voltage VREF). One end of transistor T1 (e.g., collector terminal) is coupled to the reference voltage terminal VREF1 to receive a reference voltage (e.g., reference voltage VREF, system voltage VDD, or a second reference voltage). The other end of transistor T1 (e.g., emitter terminal) is coupled to the bias terminal NVX via resistor R1. The bias terminal NVX can also be coupled to the signal input terminal VFIN via a capacitor. Amplifier 110 receives and amplifies the radio frequency signal from the signal input terminal VFIN. Inductor L1 and capacitor C1 form a resonant circuit to provide a lower impedance for the fundamental frequency signal and a higher impedance for the radio frequency signal. The charging signal CCS charges capacitor C1 through transistor T1. In one embodiment, one end of transistor T1 in bias circuit 130 is coupled to reference voltage terminal VREF1 to receive a reference voltage (e.g., reference voltage VREF), and one end (e.g., collector) of transistor MA1 in amplifier 110 can be coupled to reference voltage terminal VREF1 through inductor L2 to receive a reference voltage (e.g., reference voltage VREF). In another embodiment, one end of transistor T1 in bias circuit 130 is coupled to reference voltage terminal VREF1 to receive a reference voltage (e.g., reference voltage VREF), and one end (e.g., collector) of transistor MA1 in amplifier 110 can be coupled to circuit operating voltage terminal through inductor L2 to receive circuit operating voltage (e.g., VCC).

[0013] The bias circuit 130 also includes diodes T2 and T3. In this embodiment, diodes T2 and T3 can be implemented using transistors (e.g., bipolar transistors or field-effect transistors (FETs)). The first terminal (e.g., anode) of diode T2 is coupled to the control terminal of transistor T1 and is coupled to the second terminal of transistor T1 through resistor R2. The second terminal (e.g., cathode) of diode T2 is coupled to the first terminal (e.g., anode) of diode T3. The second terminal (e.g., cathode) of diode T3 is coupled to the reference voltage terminal VREF2 (e.g., ground). The drive circuit 120 in this embodiment can be implemented using a silicon-on-insulator (SOI) process. The bias circuit 130 and amplifier 110 can be implemented using a gallium arsenide (GaAs) process.

[0014] Figure 3 is a detailed circuit diagram of a low-dropout regulator (LDO) according to an embodiment of the present invention. The LDO includes an operational amplifier OP2, a transistor M3, and resistors R3 and R4. The inverting input of operational amplifier OP2 receives a start signal STS. The non-inverting input of operational amplifier OP2 is coupled to one end of resistor R3 and one end of resistor R4. The output of operational amplifier OP2 is coupled to the control terminal (e.g., gate terminal) of transistor M3. The first terminal (e.g., source terminal) of transistor M3 is coupled to a reference voltage terminal VREF1 (e.g., reference voltage VREF). The other end of resistor R4 is coupled to a reference voltage terminal VREF2 (e.g., ground). The second terminal of transistor M3 is coupled to the other end of resistor R3 and serves as the output of the LDO, providing a charging signal CCS. The other end of transistor M3 is coupled to another reference voltage terminal VREF1 (e.g., reference voltage VREF).

[0015] For example, Figure 4 is a waveform diagram of the reference voltage VREF, bias signal Sx, and start signal STS according to an embodiment of the present invention. Referring to Figure 4, the start signal STS can be a pulse signal. The start signal STS has a transition point TP1, and the start signal STS has a first level (e.g., logic "1") in a first time period T1 before the transition point TP1, and a second level (e.g., logic "0") in a second time period TP2 after the transition point TP1. The bias signal Sx (e.g., marked I1) in the first time period T1 before the transition point TP1 (that is, the time period between time point TP0 and the transition point TP1) is greater than the bias signal Sx (e.g., marked I2) in the second time period TP2 after the transition point TP1. The first time period T1 may correspond to a first mode, and the second time period TP2 may correspond to a second mode. In one embodiment, the reference voltage VREF (e.g., system voltage VDD) can maintain a high level (e.g., system voltage VDD) in both the first time period T1 and the second time period.

[0016] In another embodiment of the invention, the driving circuit 120 may not be disabled, but instead provides different types of charging signals CCS to the bias circuit 130. For example, the charging signal CCS in the first time period T1 before the transition point TP1 (that is, the time period between time point TP0 and transition point TP1) of the starting signal STS is greater than the charging signal CCS in the second time period TP2 after the transition point TP1 of the starting signal STS, and neither the first time period T1 nor the second time period T2 is equal to 0.

[0017] The start signal STS can be a signal generated by a corresponding parameter detection circuit. For example, the start signal STS is related to at least one of the reference voltage VREF (e.g., system voltage VDD or a second reference voltage), temperature, and PN junction voltage. For example, the start signal STS can be based on one of the following: system voltage (e.g., system voltage VDD), a temperature signal provided by an ambient temperature sensing circuit, a temperature compensation signal provided by a temperature compensation circuit, a drift-free signal provided by a drift-free voltage generator, a signal generated based on the PN junction voltage during semiconductor processing, etc., or a combination of these signals, wherein the PN junction voltage may be related to process variation. The charging signal CCS is generated by the start signal STS, therefore the charging signal CCS is also related to at least one of the reference voltage VREF (e.g., VDD), temperature, and process variation. Users of this embodiment can adjust the reference source associated with the start signal STS (e.g., reference voltage VREF, ambient temperature detection signal, PN junction voltage, drift-free signal, etc.) as needed. In this embodiment, the charging signal CCS is related to the reference voltage VREF as an example.

[0018] Figure 5 is a circuit diagram of a compensation circuit 140-1 according to an embodiment of the present invention. The compensation circuit 140-1 in Figure 5 is one implementation of the compensation circuit 140 in the amplifier circuit 100-1 of Figure 3. The compensation circuit 140-1 includes at least one reference signal source circuit (e.g., a temperature sensing circuit 142-1, a PN junction voltage detection circuit 142-2, a drift-free voltage generator 142-3, etc.) and an adder circuit 145. The temperature sensing circuit 142-1 generates a temperature sensing voltage VDET based on the sensing diode TD1. The PN junction voltage detection circuit 142-2 generates a detection voltage VT based on the PN junction voltage to obtain the process variation. In this embodiment, the sensing diode TD1 can be made of gallium arsenide (GaAs). The drift-free voltage generator 142-3 generates a drift-free voltage VBG.

[0019] The adder circuit 145 of this embodiment can perform calculations on these reference signals (e.g., temperature sensing voltage VDET, detection voltage VT, drift-free voltage VBG, and reference voltage VREF) to generate a start signal STS. For example, the adder circuit 145 in Figure 5 includes an operational amplifier OP3, resistors R0 to R7, resistor Rf, and resistor Rx. The first input terminal (e.g., non-inverting input terminal) of the operational amplifier OP3 receives the drift-free voltage VBG through resistor R0, the detection voltage VT through resistor R1, the temperature sensing voltage VDET through resistor R2, and the drift-free voltage VBG through resistor R3, and is coupled to the reference voltage terminal (e.g., ground terminal) through resistor Rx. The second input terminal (e.g., inverting input terminal) of the operational amplifier OP3 receives the ground signal GND through resistor R4, the reference voltage VREF through resistor R5, the drift-free voltage VBG through resistor R6, and the drift-free voltage VBG through resistor R7, and is coupled to the output terminal of the operational amplifier OP1 through resistor Rf. The resistance of resistor R4 is equal to the resistance of resistor R0, the resistance of resistor R5 is equal to the resistance of resistor R1, the resistance of resistor R6 is equal to the resistance of resistor R2, and the resistance of resistor R7 is equal to the resistance of resistor R3.

[0020] In this embodiment, the resistance values ​​of resistor Rf and resistor R0 can be set to have a multiple K0 (e.g., K0 = Rf / R0), the resistance values ​​of resistor Rf and resistor R1 can be set to have a multiple K1 (e.g., K1 = Rf / R1), the resistance values ​​of resistor Rf and resistor R2 can be set to have a multiple K2 (e.g., K2 = Rf / R2), and the resistance values ​​of resistor Rf and resistor R3 can be set to have a multiple K3 (e.g., K3 = Rf / R3). Therefore, the start signal STS in this embodiment will generate a detection voltage VT and multiples K0 to K3 based on the drift-free voltage VBG, the reference voltage VREF, the temperature sensing voltage VDET, and the PN junction voltage, and generate a bias signal Sx (e.g., Sx = K0 × VBG + K1 × (VBG - VREF) + K2 × (VDET - VBG) + K3 × (VT - VBG)). The low dropout regulator (LDO) receives a start signal STS to generate a charge signal CCS, and the bias circuit 130 provides a bias signal Sx at the bias point NVX based on a bias reference signal (e.g., bias current IBIAS) and the charge signal CCS.

[0021] In one embodiment, the compensation circuit 140-1 may comprise only a drift-free voltage generator 142-3 and an adder. This adder is coupled to a reference voltage terminal VREF1 to receive the reference voltage VREF, and is coupled to the drift-free voltage generator 142-3 to receive the drift-free voltage VBG, thereby altering the start signal CCS in response to changes in the reference voltage VREF. Specifically, in this embodiment, the reference voltage VREF (e.g., the system voltage VDD or a second reference voltage) may have a range of variation depending on different operating states. In one embodiment, therefore, when the reference voltage VREF is low, the driving capability of the bias signal Sx provided by the bias circuit 130 is weaker; therefore, the voltage of the start signal STS may be increased to enhance the charging signal CCS, thereby maintaining the driving capability of the bias signal Sx provided by the bias circuit 130. Conversely, when the reference voltage VREF is high, the bias signal Sx provided by the bias circuit 130 has a stronger driving capability. Therefore, the voltage of the start signal STS may be reduced to weaken the charging signal CCS in order to maintain the driving capability of the bias signal Sx provided by the bias circuit 130. Thus, the charging signal CCS can be correlated with the reference voltage VERF at the reference voltage terminal. In one embodiment, the charging signal CCS can be inversely proportional to the change in the reference voltage VREF.

[0022] In summary, the amplifier device of this embodiment of the invention utilizes the driving circuit 120 and related reference signals (such as ambient temperature variability, system voltage variability, process variability, etc.) to generate a start signal STS. The driving signal generates a charging signal CCS accordingly based on the start signal STS, and the bias circuit 130 charges the capacitor located at the amplifier bias point in real time based on the charging signal CCS, thereby reducing the transient processing time of the amplifier device and making the operation of the amplifier circuit more stable.

[0023] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0024] 100, 100-1: Amplifier Circuit 110: Amplifier 120: Drive circuit 130: Bias circuit 140: Compensation Circuit 142-1: Temperature Sensing Circuit 142-2: PN junction voltage detection circuit 142-3: Temperature Drift-Free Voltage Generator 145: Adder Circuit 150: Current source circuit 151: Current Source 152, 155: Current mirror circuit IBIAS: Bias Current STS: Start Signal CCS: Charging Signal NVX: Bias Point Sx: Bias signal L1, L2: Inductors C1: Capacitor VREF1, VREF2: Reference voltage terminals VREF, VR1: Reference voltage T1: First period T2: Second period TP0: Time point TP1: Transition point LDO: Low Dropout Voltage Regulator IREF, IREF1: Current OP1, OP2, OP3: Operational amplifiers M1~M3, MA1, T1: Transistors R0~R7, Rf, Rx: Resistors T2, T3: Diodes VFIN: Signal input terminal VDET: Temperature sensing voltage VT: Detection Voltage VBG: Voltage without temperature drift TD1: Sensing Diode I1, I2: Markers

Claims

1. An amplifier device, comprising: One inductor; A capacitor connected in series with the inductor, wherein the inductor and the capacitor are connected in series between a bias point and a first reference voltage terminal; an amplifier that receives and amplifies an RF signal from a signal input terminal, and the amplifier is coupled to the bias point to receive a bias signal; a driver circuit that receives a start signal and provides a charging signal. A bias circuit coupled to the bias point and the drive circuit, wherein, in a first mode, the start signal has a first level, and the bias circuit provides the bias signal at the bias point based on a bias reference signal and the charging signal; in a second mode, the start signal has a second level, and the bias circuit provides the bias signal at the bias point based on the bias reference signal; wherein the bias signal in the first mode is greater than the bias signal in the second mode.

2. The amplifier device as claimed in claim 1, wherein, In this second mode, the drive circuit is disabled.

3. The amplifier device as claimed in claim 1, wherein the driving circuit includes a low-dropout regulator that receives the start signal to generate the charging signal.

4. The amplifier device of claim 1, wherein the driving circuit includes a compensation circuit for generating the start signal, wherein the start signal is related to at least one of a second reference voltage at a second reference voltage terminal, a temperature, and a PN junction voltage.

5. The amplifier device as claimed in claim 4, wherein the second reference voltage terminal is coupled to one or both of the bias circuit and the amplifier.

6. The amplifier device as claimed in claim 1, wherein the bias circuit includes a first transistor, the transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to a second reference voltage terminal, the second terminal is coupled to the bias point, and the control terminal is coupled to the drive circuit to receive the charging signal.

7. The amplifier device as claimed in claim 6, wherein the control terminal of the first transistor is coupled to the drive circuit through a resistor.

8. The amplifier device of claim 7, wherein the bias circuit includes a first diode and a second diode, a first terminal of the first diode being coupled to the control terminal of the first transistor, a second terminal of the first diode being coupled to a first terminal of the second diode, and a second terminal of the second diode being coupled to the first reference voltage terminal.

9. The amplifier device as claimed in claim 6, wherein the charging signal charges the capacitor through the first transistor.

10. An amplifier device, comprising: One inductor; A capacitor connected in series with the inductor, wherein the inductor and the capacitor are connected in series between a bias point and a first reference voltage terminal; an amplifier receiving and amplifying an RF signal from a signal input terminal, and the amplifier being coupled to the bias point to receive a bias signal; a drive circuit receiving a start signal and providing a charging signal, wherein the charging signal is related to a second reference voltage at a second reference voltage terminal; and a bias circuit coupled to the bias point and the drive circuit, wherein the bias circuit provides the bias signal at the bias point based on a bias reference signal and the charging signal, wherein the start signal has a transition point, and the charging signal in a first time period before the transition point is greater than the charging signal in a second time period after the transition point.

11. The amplifier device as claimed in claim 10, wherein the start signal is a pulse signal.

12. The amplifier device of claim 10, wherein the drive circuit includes a compensation circuit for generating the charging signal, wherein the charging signal is related to a temperature or a PN junction voltage.

13. The amplifier device as claimed in claim 10, wherein the second reference voltage terminal is coupled to one or both of the bias circuit and the amplifier.

14. The amplifier device of claim 10, wherein the bias circuit includes a first transistor, the transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second reference voltage terminal, the second terminal is coupled to the bias point, and the control terminal is coupled to the drive circuit to receive the charging signal.

15. The amplifier device as claimed in claim 14, wherein the control terminal of the first transistor is coupled to the drive circuit through a resistor.

16. The amplifier device of claim 15, wherein the bias circuit includes a first diode and a second diode, a first terminal of the first diode being coupled to the control terminal of the first transistor, a second terminal of the first diode being coupled to a first terminal of the second diode, and a second terminal of the second diode being coupled to the first reference voltage terminal.

17. The amplifier device as claimed in claim 14, wherein the charging signal charges the capacitor through the first transistor.

18. The amplifier device as claimed in any one of claims 1 to 17, wherein the driving circuit is implemented using a silicon-on-insulator (SOI) process, and the bias circuit and the amplifier are implemented using a gallium arsenide (GaAs) process.

19. The amplifier device as claimed in any one of claims 1 to 17, wherein the inductor and the capacitor form a resonant circuit and provide an impedance to a fundamental frequency signal.

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