Electrostatic discharge protection circuit and control system

TWI938758BActive Publication Date: 2026-09-11NUVOTON
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Patent Information

Application Number
TW114100551
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-01-07
Publication Date
2026-09-11
Estimated Expiration
2045-01-06

AI Technical Summary

Technical Problem

Integrated circuits are vulnerable to damage from electrostatic discharge (ESD) events, which can occur when excess charge moves between objects of different potentials, necessitating effective ESD protection circuits.

Method used

An ESD protection circuit incorporating a depletion-type transistor and an ESD device with a PN junction is coupled between transmission lines, allowing ESD current to flow through the depletion-type transistor into the ESD device when a reverse breakdown voltage is exceeded, thereby protecting the circuit components.

Benefits of technology

The solution effectively directs ESD current away from sensitive components, preventing damage and ensuring the integrity of the integrated circuit during ESD events.

✦ Generated by Eureka AI based on patent content.

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Abstract

An electrostatic discharge (ESD) protection circuit is coupled between a first transmission line and a second transmission line, and includes a depletion-type transistor and an ESD device. The drain of the depletion-type transistor is coupled to the first transmission line. The gate of the depletion-type transistor is coupled to the second transmission line. The ESD device is coupled between the source of the depletion-type transistor and the second transmission line, and has a PN junction. When an ESD event occurs on the first transmission line and the second transmission line receives a ground voltage, an ESD current flows through the depletion-type transistor into the ESD device. When the voltage at the source of the depletion-type transistor is greater than a reverse breakdown voltage at the PN junction, the ESD current flows through the PN junction into the second transmission line.
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Description

Technical Field

[0001] This invention relates to a protection circuit, and more particularly to an electrostatic discharge protection circuit. Prior Technology

[0002] When excess charge accumulated on the surface of an object finds a path to reach an object with a different potential (such as a ground terminal), the sudden and instantaneous flow of current is called electrostatic discharge (ESD). When electrostatic charge moves into an integrated circuit (IC), it becomes a current that damages or destroys the components. Therefore, ESD protection is becoming increasingly important for the manufacturing of integrated circuits. Summary of the Invention

[0003] One embodiment of the present invention provides an electrostatic discharge (ESD) protection circuit coupled between a first transmission line and a second transmission line, and includes a depletion-type transistor and an ESD device. The drain of the depletion-type transistor is coupled to the first transmission line. The gate of the depletion-type transistor is coupled to the second transmission line. The ESD device is coupled between the source of the depletion-type transistor and the second transmission line, and has a PN junction. When an ESD event occurs on the first transmission line and the second transmission line receives a ground voltage, an ESD current flows through the depletion-type transistor into the ESD device. When the voltage at the source of the depletion-type transistor is greater than a reverse breakdown voltage of the PN junction, the ESD current flows through the PN junction into the second transmission line.

[0004] The present invention also provides a control system, including an operating circuit and an electrostatic discharge (ESD) protection circuit. The operating circuit is coupled between a first transmission line and a second transmission line, and includes a high-voltage side circuit and a low-voltage side circuit. The high-voltage side circuit is coupled between the first transmission line and a third transmission line. The low-voltage side circuit is coupled between a fourth transmission line and the first transmission line. The ESD protection circuit is coupled between the first and second transmission lines, and includes a depleted transistor and an ESD device. The drain of the depleted transistor is coupled to the first transmission line. The gate of the depleted transistor is coupled to the second transmission line. The ESD device is coupled between the source of the depleted transistor and the second transmission line, and has a PN junction. When an ESD event occurs on the first transmission line and the second transmission line receives a ground voltage, an ESD current flows through the depleted transistor into the ESD device. When the voltage at the source of the depleted transistor is greater than a reverse breakdown voltage of the PN junction, the ESD current flows through the PN junction into the second transmission line. When no electrostatic discharge event occurs, the voltage of the first transmission line is greater than the voltage of the fourth transmission line. Simple Explanation of the Diagram

[0005] Figure 1 is a schematic diagram of the control system of the present invention. Figure 2A is a schematic diagram of the electrostatic discharge device of the present invention. Figure 2B is another schematic diagram of the electrostatic discharge device of the present invention. Figure 2C is another schematic diagram of the electrostatic discharge device of the present invention. Figure 2D is another schematic diagram of the electrostatic discharge device of the present invention. Figure 3 is another schematic diagram of the control system of the present invention. Implementation

[0006] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0007] Figure 1 is a schematic diagram of the control system of the present invention. As shown in the figure, the control system 100 includes an operating circuit 110 and an electrostatic discharge protection circuit 120. The operating circuit 110 is coupled between transmission lines 130 and 140 and includes a high-side circuit 111 and a low-side circuit 112.

[0008] The high-voltage side circuit 111 is coupled between transmission lines 130 and 150. The present invention does not limit the architecture of the high-voltage side circuit 111. In this embodiment, the high-voltage side circuit 111 includes a core circuit 113 and a voltage clamping circuit 114. The core circuit 113 operates according to the voltage of transmission lines 130 and 150. The voltage clamping circuit 114 clamps the voltage of transmission lines 130 and 150, preventing electrostatic discharge current from transmission lines 130 or 150 from entering the core circuit 113.

[0009] For example, in a normal mode (no electrostatic discharge event occurs), the voltage of transmission line 130 is a first preset value, and the voltage of transmission line 150 is a second preset value. The core circuit 113 operates according to the voltages of transmission lines 130 and 150. In normal mode, the voltage clamping circuit 114 is inactive. When an electrostatic discharge event occurs on transmission line 130 and transmission line 150 receives a ground voltage, the voltage clamping circuit 114 is activated to release an electrostatic discharge current from transmission line 130 to transmission line 150.

[0010] The low-voltage side circuit 112 is coupled between transmission lines 140 and 160. The present invention does not limit the architecture of the low-voltage side circuit 112. In this embodiment, the low-voltage side circuit 112 includes a core circuit 115 and a voltage clamping circuit 116. The core circuit 115 and the voltage clamping circuit 116 are coupled between transmission lines 140 and 160. The core circuit 115 operates according to the voltage of transmission lines 140 and 160. The voltage clamping circuit 116 is used to protect the core circuit 115 from damage caused by electrostatic discharge current from transmission lines 140 or 160.

[0011] For example, in a normal mode (no electrostatic discharge event occurs), the voltage of transmission line 160 is a third preset value, and the voltage of transmission line 140 is a fourth preset value. The core circuit 115 operates based on the voltages of transmission lines 140 and 160. In normal mode, the voltage clamping circuit 116 is inactive. When an electrostatic discharge event occurs on transmission line 160 and transmission line 140 receives a ground voltage, an electrostatic discharge voltage enters the voltage clamping circuit 116, causing a PN junction within the voltage clamping circuit 116 to collapse in reverse. Therefore, the voltage clamping circuit 116 conducts, releasing an electrostatic discharge current from transmission line 160 to transmission line 140.

[0012] This invention does not limit the architecture of the voltage clamping circuit 116. In one possible embodiment, the voltage clamping circuit 116 is an N-type transistor 119. The drain of the N-type transistor 119 is coupled to the transmission line 160. The gate and source of the N-type transistor 119 are coupled to the transmission line 140. When an electrostatic discharge event occurs on the transmission line 160 and the transmission line 140 receives a ground voltage, a parasitic NPN transistor inside the N-type transistor 119 turns on. Therefore, the electrostatic discharge current flows from the transmission line 160, through the N-type transistor 119, and into the transmission line 140.

[0013] In normal mode, the voltage of transmission line 130 is a first preset value, the voltage of transmission line 150 is a second preset value, the voltage of transmission line 160 is a third preset value, and the voltage of transmission line 140 is a fourth preset value. In some embodiments, the difference between the first and second preset values ​​is equal to the difference between the third and fourth preset values, such as 20V. In other embodiments, the first preset value is greater than the third preset value. For example, the first preset value may be equal to or greater than 250V, and the third preset value may be equal to or less than 20V.

[0014] In other embodiments, the control system 100 further includes a diode 117 and a capacitor 118. Diode 117 is coupled between transmission lines 130 and 160. In this embodiment, the anode of diode 117 is coupled to transmission line 160, and the cathode of diode 117 is coupled to transmission line 130. Capacitor 118 is coupled between transmission lines 130 and 150. In one possible embodiment, in normal mode (no electrostatic discharge event occurs), transmission line 160 receives an operating voltage VCC. Since diode 117 is forward-biased, capacitor 118 begins to charge. When the voltage of capacitor 118 is approximately equal to the operating voltage VCC, capacitor 118 stops charging. In this example, when the voltage of transmission line 150 is equal to a second preset value (e.g., 600), due to the coupling effect of capacitor 118, the voltage of transmission line 130 is approximately equal to the second preset value plus the operating voltage VCC (e.g., 20V).

[0015] An electrostatic discharge (ESD) protection circuit 120 is coupled between transmission lines 130 and 140 and includes a depletion transistor 121 and an ESD device 122. The drain of the depletion transistor 121 is coupled to transmission line 130. The gate of the depletion transistor 121 is coupled to transmission line 140. The source of the depletion transistor 121 is coupled to the ESD device 122. In this embodiment, the depletion transistor 121 is an N-type transistor. The present invention does not limit the type of depletion transistor 121. In a possible embodiment, the depletion transistor 121 is a laterally diffused metal oxide semiconductor (LDMOS) transistor.

[0016] An electrostatic discharge (ESD) device 122 is coupled between the source of a depletion transistor 121 and a transmission line 140, and has a PN junction. When an ESD event occurs on transmission line 130 and transmission line 140 receives a ground voltage, an ESD current flows through the depletion transistor 121 into the ESD device 122. The ESD device 122 conducts when the voltage at the source of the depletion transistor 121 is greater than a reverse breakdown voltage of the PN junction of the ESD device 122. Therefore, the ESD current flows through the PN junction of the ESD device 122 into the transmission line 140. When no ESD event occurs, the voltage on transmission line 130 is greater than the voltage on transmission line 140. Since the voltage on transmission line 130 is less than the reverse breakdown voltage of the PN junction of the ESD device 122, the ESD device 122 does not conduct. Therefore, no current flows from transmission line 130 through the ESD protection circuit 120 into transmission line 140.

[0017] In some embodiments, the control system 100 has a plurality of electrostatic discharge (ESD) protection circuits 120. These ESD protection circuits 120 may be connected in parallel between transmission lines 130 and 140. Since each depleted transistor 121 is always on, a small current flows through the channel of each depleted transistor 121. Once the PN junction of the ESD device 122 is turned on, each depleted transistor 121 can be immediately triggered, uniformly releasing ESD stress.

[0018] Figure 2A is a schematic diagram of the electrostatic discharge device 122 of the present invention. In this embodiment, the electrostatic discharge device 122 includes a diode 210. The cathode of the diode 210 is coupled to the source of a depleted transistor 121. The anode of the diode 210 is coupled to a transmission line 140. When no electrostatic discharge event occurs on transmission lines 130 and 140, the diode 210 is not conducting. When an electrostatic discharge event occurs on transmission line 130 and transmission line 140 receives a ground voltage, the source voltage of the depleted transistor 121 gradually increases because the transistor is conducting. When the source voltage of the depleted transistor 121 is greater than the reverse breakdown voltage of the diode 210, the diode 210 conducts. Therefore, an electrostatic discharge current flows from transmission line 130, through the depleted transistor 121 and the diode 210, into transmission line 140.

[0019] Figure 2B is another schematic diagram of the electrostatic discharge device 122 of the present invention. In this embodiment, the electrostatic discharge device 122 includes an NPN dual-type transistor 220. The collector of the NPN dual-type transistor 220 is coupled to the source of a depletion-type transistor 121. The base and emitter of the NPN dual-type transistor 220 are coupled to a transmission line 140. When no electrostatic discharge event occurs on transmission lines 130 and 140, the NPN dual-type transistor 220 is not turned on. When an electrostatic discharge event occurs on transmission line 130 and transmission line 140 receives a ground voltage, the source voltage of the depletion-type transistor 121 gradually increases because the depletion-type transistor 121 is in a turned-on state. When the source voltage of the depletion-type transistor 121 is greater than the reverse breakdown voltage of the PN junction between the collector and base of the NPN dual-type transistor 220, the NPN dual-type transistor 220 turns on. Therefore, an electrostatic discharge current enters the transmission line 140 through the depletion transistor 121 and the NPN bipolar transistor 220 via the transmission line 130.

[0020] Figure 2C is another schematic diagram of the electrostatic discharge device 122 of the present invention. In this embodiment, the electrostatic discharge device 122 includes a PNP dual-cell transistor 230. The base and emitter of the PNP dual-cell transistor 230 are coupled to the source of a depleted transistor 121. The collector of the PNP dual-cell transistor 230 is coupled to a transmission line 140. When no electrostatic discharge event occurs on transmission lines 130 and 140, the PNP dual-cell transistor 230 is not turned on. When an electrostatic discharge event occurs on transmission line 130 and transmission line 140 receives a ground voltage, the source voltage of the depleted transistor 121 gradually increases because the depleted transistor 121 is in a turned-on state. When the source voltage of the depleted transistor 121 is greater than the turn-on voltage of the PN junction between the emitter and base of the PNP dual-cell transistor 230, the PNP dual-cell transistor 230 turns on. Therefore, an electrostatic discharge current enters the transmission line 140 through the depleted transistor 121 and the PNP bipolar transistor 230 via the transmission line 130.

[0021] Figure 2D is another schematic diagram of the electrostatic discharge device 122 of the present invention. In this embodiment, the electrostatic discharge device 122 includes an N-type transistor 240. The drain of the N-type transistor 240 is coupled to the source of a depleted transistor 121. The gate and source of the N-type transistor 240 are coupled to a transmission line 140. When no electrostatic discharge event occurs on transmission lines 130 and 140, the N-type transistor 240 is not turned on. When an electrostatic discharge event occurs on transmission line 130 and transmission line 140 receives a ground voltage, since the depleted transistor 121 is in a conducting state, the source voltage of the depleted transistor 121 rises sharply, turning on a parasitic NPN transistor (not shown) of the N-type transistor 240. Therefore, an electrostatic discharge current flows from transmission line 130, through the depleted transistor 121 and the N-type transistor 240, into transmission line 140.

[0022] Figure 3 is another schematic diagram of the control system of the present invention. Figure 3 is similar to Figure 1, except that the control system 300 includes an additional high-low voltage side connection circuit 310. The high-low voltage side connection circuit 310 is coupled between transmission lines 130 and 140. In normal mode, the low-voltage side circuit 112 does not trigger the high-low voltage side connection circuit 310. Therefore, the high-low voltage side connection circuit 310 does not operate. When an electrostatic discharge event occurs on transmission line 130 and transmission line 140 receives a ground voltage, the high-low voltage side connection circuit 310 is activated. Therefore, an electrostatic discharge current flows from transmission line 130, through the high-low voltage side connection circuit 310, and into transmission line 140.

[0023] The electrostatic discharge protection circuit 120 releases the electrostatic discharge current, preventing damage to the high-voltage side circuit 111, the low-voltage side circuit 112, and the high-low voltage side interconnection circuit 310. This invention does not limit the architecture of the high-low voltage side interconnection circuit 310. In one possible embodiment, the high-low voltage side interconnection circuit 310 includes a resistor 311 and an N-type transistor 312. The resistor 311 is coupled between the transmission line 130 and the drain of the N-type transistor 312. The gate of the N-type transistor 312 is coupled to the low-voltage side circuit 112. The source of the N-type transistor 312 is coupled to the transmission line 140. In another possible embodiment, the drain of the N-type transistor 312 is coupled to the anode of a diode 320 inside the high-voltage side circuit 111. In this example, the cathode of the diode 320 is coupled to the transmission line 130.

[0024] It is important to understand that when a component or layer is mentioned as being "coupled" to another component or layer, it means that it can be directly coupled or connected to the other component or layer, or that there are other components or layers between them. Conversely, if a component or layer is "connected" to another component or layer, there will be no other components or layers between them.

[0025] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, unless expressly stated otherwise, the definitions of terms in a general dictionary should be interpreted as consistent with their meaning in writings of the relevant technical field, and not as idealized or overly formal expressions. While terms such as “first” and “second” can be used to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. Within the claims, terms such as “first” and “second” are used as designations and are not intended to impose numerical requirements on their objects.

[0026] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments using hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention should be determined by the appended claims.

[0027] 100, 300: Control System 110: Operating Circuit 120: Electrostatic Discharge Protection Circuit 310: High and low voltage side connection circuit 121: Depletion-type transistor 122: Electrostatic discharge device 130, 140, 150, 160: Transmission lines 111: High-voltage side circuit 112: Low-voltage side circuit 113, 115: Core Circuit 114, 116: Voltage clamping circuit 117, 210, 320: Diode 118: Capacitor 119, 240, 312: N-type transistors VCC: Operating voltage NPN: Bipolar Transistor 220 230: PNP bipolar transistor 311: Resistor

Claims

1. An electrostatic discharge protection circuit, coupled between a first transmission line and a second transmission line, and comprising: A depletion-type transistor has a first drain, a first gate, and a first source. The first drain is coupled to a first transmission line, and the first gate is coupled to a second transmission line. An electrostatic discharge device is coupled between the first source and the second transmission line and has a first PN junction. When a first electrostatic discharge event occurs on the first transmission line and the second transmission line receives a ground voltage, a first electrostatic discharge current passes through the depletion-type transistor and enters the electrostatic discharge device. When the voltage of the first source is greater than a reverse breakdown voltage of the first PN junction, the first electrostatic discharge current passes through the first PN junction and enters the second transmission line.

2. The electrostatic discharge protection circuit as described in claim 1, wherein the depletion transistor system is a laterally diffused metal oxide semiconductor transistor.

3. The electrostatic discharge protection circuit as described in claim 2, wherein the electrostatic discharge device comprises: A first diode has a first cathode and a first anode, the first cathode being coupled to the first source and the first anode being coupled to the second transmission line.

4. The electrostatic discharge protection circuit as described in claim 2, wherein the electrostatic discharge device comprises: An NPN bipolar transistor has a first base, a first collector, and a first emitter, the first collector being coupled to the first source, and the first base and the first emitter being coupled to the second transmission line.

5. The electrostatic discharge protection circuit as described in claim 2, wherein the electrostatic discharge device comprises: A PNP bipolar transistor has a second base, a second collector, and a second emitter, wherein the second base and the second emitter are coupled to the first source, and the second collector is coupled to the second transmission line.

6. The electrostatic discharge protection circuit as described in claim 2, wherein the electrostatic discharge device comprises: An N-type transistor has a second drain, a second gate, and a second source. The second drain is coupled to the first source, and the second gate and the second source are coupled to the second transmission line.

7. The electrostatic discharge protection circuit as described in claim 6 further includes: A voltage clamping circuit is coupled between the second transmission line and a third transmission line and has a second PN junction, wherein: when a second electrostatic discharge event occurs on the third transmission line and the second transmission line receives the ground voltage, a second electrostatic discharge current enters the second PN junction, causing the second PN junction to collapse in reverse, and the second electrostatic discharge current enters the second transmission line through the second PN junction.

8. The electrostatic discharge protection circuit as described in claim 7 further includes: A second diode has a second cathode and a second anode, the second cathode being coupled to the first source and the second anode being coupled to the third transmission line.

9. A control system for an electrostatic discharge protection circuit, comprising: An operating circuit, coupled between a first transmission line and a second transmission line, includes: a high-voltage side circuit coupled between the first transmission line and a third transmission line; and a low-voltage side circuit coupled between a fourth transmission line and the first transmission line; an electrostatic discharge (ESD) protection circuit, coupled between the first and second transmission lines, includes: a depletion-type transistor having a drain, a gate, and a source, the drain being coupled to the first transmission line and the gate being coupled to the second transmission line; and an ESD device coupled between the source and the second transmission line, having a PN junction, wherein: when an ESD event occurs on the first transmission line and the second transmission line receives a ground voltage, an ESD current flows through the depletion-type transistor into the ESD device; when the voltage at the source of the depletion-type transistor is greater than a reverse breakdown voltage of the PN junction, the ESD current flows through the PN junction into the second transmission line. When the electrostatic discharge event does not occur, the voltage of the first transmission line is greater than the voltage of the fourth transmission line.

10. The control system for the electrostatic discharge protection circuit as described in claim 9 further includes: A capacitor is coupled between the first transmission line and a third transmission line; A diode is coupled between the second transmission line and a fourth transmission line, wherein: when the electrostatic discharge event does not occur, the fourth transmission line receives an operating voltage, the diode is forward-biased, and the capacitor begins to charge.

Citation Information

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