Integrated circuit device and method of manufacturing the same

Abstract

Some embodiments relate to integrated circuit devices including a two-sided capacitor structure. The integrated circuit device includes a plurality of dielectric layers disposed above a substrate and a capacitor structure comprising a plurality of capacitor portions. Each capacitor portion includes a first conductive element extending through the plurality of dielectric layers, a dielectric element extending through the plurality of dielectric layers and aligned along the first conductive element, and a second conductive element extending through the plurality of dielectric layers and aligned along the dielectric element. At least one of the plurality of dielectric layers includes a first dielectric layer extending laterally between a plurality of first adjacent pairs of capacitor portions, wherein the spacing between the capacitor portions in each of the first adjacent pairs is less than a first length. The first dielectric layer includes a sidewall defining a gap between each of a plurality of second adjacent pairs of capacitor portions, wherein the length of the gap is greater than or equal to the first length.

Description

Prior Technology

[0001] One area of ​​interest in integrated circuit (IC) technology is the improvement of capacitors used within IC devices (e.g., in terms of density, footprint, etc.). One advancement in this area is the three-dimensional (3D) metal-insulator-metal (MIM) capacitor, which achieves a capacitor with a high conductor surface area relative to the volume consumed within the IC device. Simple Explanation of the Diagram

[0002] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figure 1A shows a schematic side view during the fabrication of a single-side MIM (MIM) capacitor structure according to some embodiments of the present disclosure. Figure 1B shows a schematic side view during the fabrication of a double-side MIM capacitor structure according to some embodiments of the present disclosure. Figure 2A shows a schematic plan view of the fabrication process of a mechanically stable double-sided three-dimensional (3D) MIM capacitor structure according to some embodiments of the present disclosure. Figures 2B, 2C, and 2D respectively show a plan view, an orthogonal side view, and a diagonal side view of a mechanically stable double-sided 3D MIM capacitor structure according to some embodiments of the present disclosure. Figures 3 to 9, 10A and 10B, 11A and 11B, 12A, 12B and 12C, 13A and 13B, 14A and 14B, and 15A and 15B show various side views of an IC device, including a mechanically stable double-sided 3D MIM capacitor structure, at various manufacturing stages according to some embodiments of the present disclosure. Figures 16, 17A, and 17B, and Figures 18A and 18B show various side views of an IC device, including a mechanically stabilized dual-sided 3D MIM capacitor structure, at various manufacturing stages according to additional embodiments of the present disclosure. Figure 19 illustrates a method for forming an IC device including a mechanically stable double-sided 3D MIM capacitor structure according to some embodiments of the present disclosure. Implementation

[0003] This disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or above a second feature may include embodiments where the first and second features are formed in direct contact, and may further include embodiments where additional features may be formed between the first and second features, said embodiments where the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, for ease of description, this document uses spatially related terms such as "below," "down," "lower part," "above," and "upper part" to describe the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientation depicted in the figure, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or through other orientation methods), and the spatially relative descriptors used herein can be interpreted accordingly.

[0005] Figure 1A shows a schematic side view during the fabrication of a single-sided MIM capacitor structure 100A according to some embodiments of the present disclosure. As shown, multiple trenches 106 may be provided in a base substrate 101 (e.g., a dielectric layer, substrate, or the like). Along the upper surface of a layer or structure within the IC device, the trenches 106 may carry a first conductive element 102A, a dielectric element (e.g., an insulating element) 104, and a second conductive element 102B, which may respectively serve as a metal layer, an insulating layer, and a metal layer of the IC device. Furthermore, the MIM capacitor structure 100A using the first conductive element 102A, the insulating element 104, and the second conductive element 102B may include a horizontal body 107 and multiple columns 108 extending downward from the horizontal body 107. In this arrangement, from a mechanical point of view, all portions of the MIM capacitor structure 100A tend to be stable because each portion of the MIM capacitor structure 100A is fully supported during IC fabrication.

[0006] Figure 1B shows a schematic side view during the fabrication of a dual-sided MIM capacitor structure 100B according to some embodiments of the present disclosure. In this configuration, the first conductive element 102A may be formed as a plurality of upward-directed segments, and the insulating element 104 and the second conductive element 102B may be disposed above these segments to form the MIM capacitor structure 100B. In this arrangement, the upward-directed segments may be narrower and positioned closer than the trench 106 of the MIM capacitor structure 100A, thus potentially providing a larger area for the first conductive element 102A, the dielectric element 104, and the second conductive element 102B, thereby generating a higher potential capacitance value.

[0007] However, in this particular configuration, providing mechanical support for the upward-pointing segment (e.g., a portion of the first conductive element 102A) during the manufacture of the IC device may not be optimal, potentially leading to reduced device yield and increased device manufacturing costs.

[0008] To address these issues, this disclosure provides embodiments of an IC device and related manufacturing methods relating to a mechanically stable double-sided MIM capacitor structure. In some embodiments, the IC device may include a plurality of dielectric layers disposed above a substrate and a capacitor structure comprising a plurality of capacitor portions. Each capacitor portion may include a first conductive element extending through the plurality of dielectric layers, a dielectric element extending through the plurality of dielectric layers and aligned along the first conductive element, and a second conductive element extending through the plurality of dielectric layers and aligned along the dielectric element. At least one dielectric layer may laterally span or bridge the linear distance between each pair of adjacent capacitor portions, wherein each pair of adjacent capacitor portions is separated by an interval less than a certain length. Conversely, at least one dielectric layer may not laterally span or bridge the linear distance between each pair of adjacent capacitor portions, wherein each pair of adjacent capacitor portions is separated by an interval greater than or equal to the certain length.

[0009] Therefore, the use of some embodiments of the method can provide a physical feature (e.g., at least one of the dielectric layers described above) that provides mechanical stability to the capacitor structure by bridging the linear distance between each adjacent pair, particularly during the manufacture of the IC device. Furthermore, in some embodiments, since at least one of the dielectric layers does not span between other adjacent pairs of capacitor portions, it is possible to contact the lower layer of the IC device beneath at least one of the dielectric layers to provide material for one or more additional capacitor portions in addition to the plurality of first capacitor portions, thereby creating a double-sided MIM capacitor structure.

[0010] Figure 2A shows a plan view during the fabrication process of a mechanically stable, two-sided, three-dimensional (3D) MIM capacitor structure according to the present disclosure. In some embodiments, as discussed above in conjunction with Figure 1B, the first conductive element 102A combined with the first (bottom) electrode 202 (also referred to as the first electrode) can be configured as a plurality of first capacitor portions 220 comprising multiple vertically oriented portions (e.g., cylinders). Also as shown in Figure 2A, a portion of the first conductive element 102A can form part of a guard ring 222, which can provide structural and / or electrical isolation for the resulting 3D MIM capacitor structure.

[0011] To provide stability for the first conductive element 102A in subsequent processing steps, such as the addition of the insulating element 104 and the second conductive element 102B, a plurality of structural elements 242 may be laterally connected or span adjacent first capacitor portions 220 and / or laterally connected or span one or more first capacitor portions 220 to a portion of the guard ring 222. In some embodiments, the structural elements 242 may be formed from a structural dielectric layer 206 (or dielectric layer, first (structural) dielectric layer, first dielectric layer) (e.g., an etch stop layer). More specifically, in some embodiments, the structural dielectric layer 206 may be laterally connected or span adjacent first capacitor portions 220 separated by a gap of less than a certain length (e.g., a first length 252 less than the certain length). Furthermore, in some embodiments, the structural dielectric layer 206 may include sidewalls defining gaps between some adjacent first capacitor portions 220, wherein the length of the gap is greater than or equal to the certain length (e.g., a second length 254 greater than or equal to the certain length). Additionally, in some embodiments related to the plan view of FIG2A, the first capacitor portions 220 are arranged in a two-dimensional array, the structural dielectric layer 206 may join or span the first capacitor portions 220 along the rows and pillars of the array, and the structural dielectric layer 206 may define the gaps between the first capacitor portions 220 along the diagonal of the array.

[0012] Figures 2B, 2C, and 2D respectively show a plan view, an orthogonal side view, and a diagonal side view of a mechanically stable double-sided 3D MIM capacitor structure 200 according to the present disclosure. As shown, Figure 2A is a plan view of the capacitor structure 200 at a specific structural dielectric layer 206, which selectively spans the distance between pairs of first capacitor portions 220. In some embodiments, each first capacitor portion 220 may include a cylindrical structure presenting a circular shape, as shown in the plan view of Figure 2B. Further, each first capacitor portion 220 may include a cylindrical first conductive element 102A; a cylindrical dielectric (e.g., insulating) element 104, which is coaxially aligned and in contact with the first conductive element 102A; and a cylindrical second conductive element 102B, which is coaxially aligned and in contact with the dielectric element 104.

[0013] In some embodiments, as shown in FIG2B, the structural dielectric layer 206 laterally spans the linear distance between adjacent first capacitor portions 220 spaced apart by a predetermined length (e.g., along the orthogonal cross-section of FIG2C), but does not laterally span the linear distance between adjacent first capacitor portions 220 spaced apart by a predetermined length (e.g., along the diagonal cross-section of FIG2D).

[0014] Furthermore, in some embodiments, as depicted in the plan view of FIG2B, the first capacitor portion 220 can be arranged as a two-dimensional rectangular array having rows and columns. In the specific case of FIG2B, the first capacitor portions 220 are arranged in a 3×3 array. However, arrays of other sizes and configurations may be used in other embodiments (e.g., 1×2, 2×1, 2×2, 2×3, 3×2, 4×4, etc.). Thus, adjacent first capacitor portions 220 in a row or column of the two-dimensional array (e.g., along the cross-sectional view of FIG2C) are separated by a relatively short distance (e.g., less than a predetermined length), and thus said distance is spanned by the structural dielectric layer 206. Otherwise, adjacent first capacitor portions 220 not aligned along one of the rows or columns of the two-dimensional array (e.g., along the diagonal of the two-dimensional array, such as the cross-sectional view of FIG2D) are separated by a relatively long distance (e.g., greater than or equal to a predetermined length).

[0015] The first capacitor portion 220 is also shown in cross-sectional views of Figures 2C and 2D. In some embodiments, the first capacitor portion 220 may be laterally separated by one or more second capacitor portions 221 comprising a first conductive element 102A, a dielectric element 104, and a second conductive element 102B to facilitate a double-sided 3D MIM capacitor structure. As discussed in more detail below, the volumes between the first capacitor portions 220 used to form one or more second capacitor portions 221 may be contacted during manufacturing via one or more openings 224 in the structural dielectric layer 206 (e.g., as shown in Figure 2B).

[0016] Furthermore, in some embodiments, as shown in the optimal effect of the plan view in FIG2B, the first capacitor portion 220 and the second capacitor portion 221 may be laterally surrounded by a protective ring 222. In some embodiments, the protective ring 222 may include the core of a second conductive element 102B, which may be laterally surrounded by a dielectric element 104, which in turn may be laterally surrounded by a first conductive element 102A (e.g., in a manner similar to that of each first capacitor portion 220). In some embodiments, the protective ring 222 provides an electrical barrier between the capacitor structure 200 and surrounding electrical components that may be disposed in an IC device including the capacitor structure 200. Furthermore, in some embodiments, during manufacturing, the protective ring 222 may protect other circuitry surrounding the 3D MIM capacitor structure, for example, by confining solvents within the area of ​​the 3D MIM capacitor structure.

[0017] In some embodiments, as shown in the cross-sectional views of Figures 2C and 2D, a first (bottom) electrode 202 (e.g., comprising a metal or metal alloy (e.g., copper (Cu), another conductive metal or alloy, or another conductive material)) may be disposed above a dielectric layer 204, which in turn may be disposed above a substrate 201 (e.g., a semiconductor substrate comprising silicon (Si), another semiconductor material, or combinations thereof). In some embodiments, the first electrode 202 may be directly or indirectly connected to one or more first capacitor portions 220, second capacitor portions 221, and / or guard rings 222 to another electronic circuit or voltage reference of the IC device.

[0018] Furthermore, in some embodiments, the first capacitor portion 220, the second capacitor portion 221, and / or the guard ring 222 may be located within one or more dielectric layers 204, 206, and 208. In some embodiments, each of dielectric layer 204, dielectric layer 206, and dielectric layer 208 may include one or more dielectric materials, including but not limited to silicon oxide (SiOx) (e.g., silicon oxide (SiO2)), silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, and the like. For example, in some embodiments, dielectric layer 204 may include silicon oxide, dielectric layer 206 may include silicon oxynitride (SiON), silicon nitride (SiN), or silicon carbide (SiC) (e.g., used as an etch stop layer), and dielectric layer 208 may include silicon nitride (e.g., used as an interlayer dielectric). Moreover, while specific arrangements and thicknesses of dielectric layers 204, 206, and 208 are depicted in Figures 2C and 2D, other arrangements and thicknesses are possible in other embodiments. As described in more detail herein, dielectric layer 206 can provide mechanical stability to capacitor structure 200 during manufacturing. Additionally or alternatively, in some embodiments, one or more other dielectric layers 204, 206, and 208 may provide such stability.

[0019] Regarding the first capacitor portion 220 and the second capacitor portion 221, the first conductive element 102A (e.g., also referred to as capacitor bottom metal (CBM)) and the second conductive element 102B (e.g., also referred to as capacitor top metal (CTM)) may each comprise a metal (e.g., copper (Cu), other metals or metal alloys) or another conductive material (e.g., polycrystalline silicon, silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN), etc.). In some embodiments, the first conductive element 102A and the second conductive element 102B may comprise the same or different materials. Furthermore, in some embodiments, the dielectric element 104 may comprise an insulator and / or other insulating or dielectric materials.

[0020] As shown in the cross-sectional views of Figures 2C and 2D, a dielectric cover layer 210 may be disposed above the second conductive element 102B and the dielectric layer 204. Additionally, a dielectric spacer 211 may be disposed above the dielectric element 104 and laterally surround a portion of the dielectric cover layer 210, the dielectric layer 204, and the second conductive element 102B. In some embodiments, the dielectric cover layer 210 and the dielectric spacer 211 may be made of the same dielectric material, such as silicon nitride, but other dielectric materials may be used in other embodiments.

[0021] In some embodiments, the second electrode 212 may contact the second conductive element 102B. The second electrode 212 may include a conductive material, such as copper (Cu), a copper alloy, another metal, or another conductive material. Moreover, in some embodiments, the second electrode 212 may have a wider upper portion and a narrower lower portion. The narrower lower portion may extend through the dielectric cap layer 210 and the dielectric layer 204 to contact the second conductive element 102B.

[0022] The first electrode 202 and the second electrode 212 can be used as two electrical connections of the MIM capacitor structure 200 employed in the IC device. In some embodiments, the MIM capacitor structure 200 can be used as a component in digital or analog circuits, such as a bypass capacitor or a decoupling capacitor (e.g., for DC voltage, such as power supply voltage).

[0023] As shown in the cross-sectional view of Figure 2C, in some embodiments, one or more conductive interconnect structures 244 may be disposed in the dielectric layers 204, 206, and 208 near the first conductive element 102A and the second conductive element 102B. The one or more conductive interconnect structures 244 may include a plurality of conductive metal lines 246 stacked perpendicularly to the plurality of vias 240. The conductive materials of the conductive metal lines 246 and the vias 240 may include, for example, copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), some other conductive materials, or any combination of the foregoing materials.

[0024] Figures 3 to 9, 10A and 10B, 11A and 11B, 12A, 12B and 12C, 13A and 13B, 14A and 14B, and 15A and 15B show various side views of different stages of the manufacturing process of an IC device including a mechanically stabilized dual-sided 3D MIM capacitor structure (e.g., capacitor structure 200) according to some embodiments of this disclosure. More specifically, Figures 3 to 9 and 10A, 11A, 12A, 13A, 14A, and 15A are orthogonal cross-sectional views at the same section line as Figure 2C. Figures 10B, 11B, 12B, 13B, 14B, and 15B are diagonal cross-sectional views at the same section line as Figure 2D, and are views at the same manufacturing stage as Figures 10A, 11A, 12A, 13A, 14A, and 15A. Although Figures 3 through 9, 10A and 10B, 11A and 11B, 12A, 12B and 12C, 13A and 13B, 14A and 14B, and 15A and 15B are described as a series of actions, it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted, in whole or in part.

[0025] Figure 3 illustrates a first electrode 202 having a plurality of dielectric layers 204, 206, and 208 disposed thereon. In some embodiments, a substrate 201 (e.g., a silicon (Si) substrate) may support the first dielectric layer 204, and the first electrode 202 may be formed thereon, followed by the formation of successive additional dielectric layers 204, 206, and 208. As shown in Figure 3, the relatively thin dielectric layers 206 and 208 can be formed alternately between the thicker dielectric layer 204, although many other structures and formation sequences can be used with dielectric layers 204, 206, and / or 208. As described above, in some embodiments, each of the dielectric layers 204, 206, and 208 may include one or more dielectric materials, including but not limited to silicon oxide (SiOx) (e.g., silicon oxide (SiO2)), silicon nitride (SiN), and silicon carbide (SiC). For example, dielectric layer 204 may include silicon oxide (SiOx), dielectric layer 206 may include silicon carbide (SiC), and dielectric layer 208 may include silicon nitride (SiN), but other materials and combinations are also possible. Furthermore, in some embodiments, the upper dielectric layer 206 shown in FIG3 may be used as the structural dielectric layer 206 of FIG2B, FIG2C, and FIG2D.

[0026] Additionally, in some embodiments, one or more vias 240 and associated metal layers may be disposed in dielectric layers 204, 206, and 208 near (e.g., around) the 3D MIM capacitor structure to be manufactured, as depicted in the following figures.

[0027] Figure 4 illustrates the removal of multiple trenches 402 (e.g., through lithography and etching), which will determine the location of each first capacitor portion 220 and guard ring 222. In some embodiments, each trench 402 extends from the upper surface of the uppermost dielectric layer 204 to the upper surface of the first electrode 202.

[0028] Figure 5 illustrates the formation (e.g., conformal deposition) of the first conductive element 102A inside and outside (e.g., between) the trench 402. As described above, the first conductive element 102A may include a metal (e.g., copper (Cu)), a metal alloy, and / or another conductive material (e.g., polycrystalline silicon, tantalum nitride (TaN), etc.).

[0029] Figure 6 illustrates the formation (e.g., deposition) of a plurality of protective plugs 502 filling trench 402, and the formation of photoresist material 504 that can protect a plurality of portions of the first conductive element 102A not located between adjacent trenches 402. In some embodiments, the protective plugs 502 may be formed of a fluid organic-type material. The protective plugs 502 and the photoresist material 504 together can facilitate the selective removal (e.g., etching) of portions of the first conductive element 102A located between adjacent trenches 402, as shown in Figure 7, to form a plurality of individual first conductive elements 102A. Subsequently, Figure 8 illustrates the removal (e.g., dissolution) of the protective plugs 502 and the photoresist material 504.

[0030] Figure 9 illustrates the removal (e.g., wet removal or dissolution using a solvent such as hydrofluoric acid) of the upper dielectric layer 204 (e.g., silicon oxide (SiOx) (such as silicon dioxide (SiO2)) or another soluble dielectric material), extending downwards to an example of the upper structural dielectric layer 206. In some embodiments, the structural dielectric layer 206 may comprise silicon carbide (SiC) or another dielectric material that is more resistant to dissolution in a particular solvent than the dielectric layer 204.

[0031] Figures 10A and 10B show orthogonal and diagonal cross-sectional views, respectively, of a dielectric spacer structure 1002 formed (e.g., deposited) over an exposed conductive surface (e.g., the surface of the first conductive element 102A). In some embodiments, the deposited dielectric spacer structure 1002 may form a dielectric layer 204 having a non-uniform upper surface, which may generally follow the contours of at least some of the multiple portions of the first conductive element 102A and the structural dielectric layer 206 located below it.

[0032] Figures 11A and 11B show orthogonal and diagonal cross-sectional views, respectively, of dielectric material removed (e.g., extensive or "overall" etching) from the dielectric spacer wall structure 1002. In some embodiments, sufficient amount of dielectric material may be removed from the dielectric spacer wall structure 1002 to remove portions of a first (structural) dielectric layer 206 (also referred to as the first dielectric layer) between adjacent trenches 402 (e.g., associated with the first capacitor portion 220) of a plurality of trenches 402 spaced at least a first linear distance (e.g., length 254 between adjacent trenches 402 in a plan view along the diagonal of an associated two-dimensional array), as shown in Figure 11B. In some embodiments, the dielectric spacer wall structure 1002 may be thinner than the trenches 402 positioned along the diagonal direction. Furthermore, in such embodiments, such removal may leave an intact remaining portion of the first dielectric layer 206 (e.g., between adjacent portions of the plurality of trenches 402 in a plan view along orthogonal lines of an associated two-dimensional array), as shown in Figure 11A. Maintaining the integrity of these remaining portions of the first dielectric layer 206 can provide mechanical stability for further manufacturing stages.

[0033] For example, Figures 12A, 12B, and 12C respectively illustrate the removal (e.g., wet dip removal or dissolution) of some of the plurality of dielectric layers (e.g., through the removed portion of at least one of the first dielectric layers 206). For example, all exposed dielectric layers other than the first dielectric layer 206 (e.g., dielectric layers 204 and 208) can be removed, including those dielectric layers shown in Figure 12A, because the plurality of openings in the first dielectric layer 206 depicted in Figure 12B facilitate contact.

[0034] During this manufacturing stage, additional material layers may be formed to complete the fabrication of the first capacitor portion 220, the second capacitor portion 221, and / or the guard ring 222. For example, Figures 13A and 13B show orthogonal and diagonal cross-sectional views, respectively, of a first conductive material (e.g., to complete the first conductive element 102A of the first capacitor portion 220 and the second capacitor portion 221) formed (e.g., conformally deposited) inside and outside the plurality of trenches 402. In some embodiments, such deposition can facilitate the application of a conductive material (e.g., a metal (copper (Cu)), a metal alloy, or another conductive material (e.g., polycrystalline silicon, tantalum nitride (TaN), etc.) to the exposed upper and lower portions of the dielectric layer 206 and the previously present portions of the first conductive element 102A. For example, in some embodiments, the conductive material can be deposited via atomic layer deposition (ALD). This deposition can allow all exposed upper, lower, and side surfaces of the dielectric material of the dielectric layer 206 and the possible first conductive element 102A to be covered by the first conductive material.

[0035] Figures 14A and 14B show orthogonal and diagonal cross-sectional views, respectively, of a dielectric material (e.g., dielectric element 104 for forming the first capacitor portion 220 and the second capacitor portion 221) formed over a first conductive material (e.g., conformally deposited). In some embodiments, the dielectric material may include an insulator and / or other dielectric materials.

[0036] Figures 15A and 15B show orthogonal and diagonal cross-sectional views, respectively, of a second conductive material (e.g., to form a second conductive element 102B of the first capacitor portion 220 and the second capacitor portion 221) formed (e.g., deposited or filled) on the dielectric material. In some embodiments, a sufficient amount of the second conductive material may cover the entire dielectric element 104. Also as shown in Figures 15A and 15B, in some embodiments, one or more apertures 230 may be formed within the second conductive material 102B in one or more second capacitor portions 221 between the first capacitor portion 220 or the guard ring 222.

[0037] Subsequently, a dielectric cap layer 210 and a dielectric spacer wall 211 may be formed over the dielectric element 104 to laterally surround a portion of the dielectric cap layer 210, the dielectric layer 204, and the second conductive element 102B, as discussed above in conjunction with Figures 2C and 2D. Furthermore, in some embodiments, a second electrode 212 may be formed to extend through the dielectric cap layer 210 and the dielectric layer 204 to contact the second conductive element 102B.

[0038] In some embodiments, Figures 16, 17A, and 17B, and Figures 18A and 18A depict partial processes representing alternatives to the manufacturing stages discussed above with respect to Figures 6 through 9, and Figures 10A, 10B, 11A, and 11B. These partial processes pertain to the stage employed to create openings in the structural dielectric layer 206 after the formation (e.g., conformal deposition) of the first conductive element 102A shown in Figure 5.

[0039] For example, Figure 16 illustrates the formation (e.g., deposition) of protective plugs 502 filling trenches 402, and the formation of photoresist material 504, which can protect multiple portions of the first conductive element 102A not located between adjacent trenches 402 and multiple protective plugs 502 located in trenches 402 associated with the first capacitor portion 220. The protective plugs 502 and photoresist material 504 together can facilitate selective removal (e.g., etching) of portions of the first conductive element 102A located between adjacent trenches 402, as well as some dielectric layers 204, along rows or columns of the two-dimensional array, as shown in the cross-sectional view of Figure 17A. Additionally, in some embodiments, along the diagonal of the array, as shown in the cross-sectional view of Figure 17B, the underlying structural dielectric layer 206 (i.e., a portion of the structural dielectric layer 206) between trenches 402 can be removed (e.g., due to the greater distance between trenches 402 along the diagonal cross-section). The cross-sectional views of Figures 18A and 18B illustrate the subsequent removal (e.g., dissolution) of the protective plug 502 and the photoresist material 504.

[0040] At this stage, the process can be performed as shown in Figures 12A, 12B, and 12C, which respectively illustrate orthogonal cross-sectional views, diagonal cross-sectional views, and planar views of the removal (e.g., wet removal or dissolution) of some of the plurality of dielectric layers (e.g., removed portions through at least one of the first dielectric layers 206). As mentioned above, all exposed dielectric layers (e.g., dielectric layers 204 and 208) except for the first dielectric layer 206 can be removed, including those dielectric layers shown in Figure 12A, because the plurality of openings in the first dielectric layer 206 depicted in Figure 12B facilitate contact. Manufacturing can then continue as discussed above in conjunction with Figures 13A and 13B, Figures 14A and 14B, and Figures 15A and 15B.

[0041] Figure 19 illustrates a method 1900 for forming an IC device including a mechanically stable double-sided MIM capacitor structure (e.g., MIM capacitor structure 200 of Figures 2B, 2C, and 2D) according to some embodiments. Although the methods and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that this disclosure is not limited to the shown order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0042] At action 1902, for example, a first electrode (e.g., first electrode 202 of FIG. 2B, FIG. 2C, and FIG. 3) may be formed on a substrate (e.g., substrate 201 of FIG. 2C, FIG. 2D, and FIG. 3). At action 1904, multiple dielectric layers (e.g., dielectric layers 204, 206, and 208 of FIG. 3) may be formed over the first electrode. FIG. 3 shows cross-sectional views of some embodiments corresponding to actions 1902 and 1904.

[0043] At action 1906, multiple trenches (e.g., trench 402 in FIG. 4) can be formed through multiple dielectric layers. As described above, each trench can define the location of a corresponding first capacitor portion 220. FIG. 4 shows a cross-sectional view corresponding to some embodiments of action 1906.

[0044] At action 1908, the first conductive structure (e.g., the first conductive element 102A of FIG. 5) may be conformally deposited on multiple dielectric layers and deposited into multiple trenches. FIG. 5 shows a cross-sectional view corresponding to some embodiments of action 1908.

[0045] At action 1910, the portion of the first conductive structure outside the plurality of trenches can be removed. At action 1912, a portion of at least one of the plurality of dielectric layers located outside the plurality of trenches can be removed before the first dielectric layer (e.g., the structural dielectric layer 206 of FIG. 2B, FIG. 2C, and FIG. 2D). Furthermore, at action 1914, less than all of the first dielectric layer can be removed. FIG. 6 to 9, FIG. 10A and 10B, and FIG. 11A and 11B show cross-sectional views corresponding to some embodiments of actions 1910, 1912, and 1914. Alternatively, FIG. 16, FIG. 17A and 17B, and FIG. 18A and 18B show cross-sectional views corresponding to some embodiments of actions 1910, 1912, and 1914.

[0046] At action 1916, some of the other dielectric layers (e.g., dielectric layers 204 and 208 of FIG. 11A and FIG. 11B) may be removed through at least one removed portion of the first dielectric layer. FIG. 12A and FIG. 12B show cross-sectional views of some embodiments corresponding to action 1916.

[0047] At action 1918, a first conductive material (e.g., for the first conductive element 102A of Figures 13A and 13B) may be conformally deposited inside and outside the plurality of trenches. Figures 13A and 13B show cross-sectional views of some embodiments corresponding to action 1918.

[0048] At action 1920, dielectric material (e.g., dielectric element 104 of Figures 14A and 14B) may be conformally deposited on the first conductive material. Figures 14A and 14B show cross-sectional views of some embodiments corresponding to action 1920.

[0049] At action 1922, a second conductive material (e.g., the second conductive element 102B of Figures 15A and 15B) may be formed on the dielectric material. Figures 15A and 15B show cross-sectional views of some embodiments corresponding to action 1922.

[0050] At action 1924, a second electrode (e.g., second electrode 212 of Figures 2C and 2D) may be formed to contact the second conductive material. Therefore, in some embodiments, the first and second electrodes can serve as contact points for accessing a MIM capacitor structure (e.g., MIM capacitor structure 200 of Figures 2B, 2C, and 2D). Figures 2C and 2D show cross-sectional views corresponding to some embodiments of action 1924.

[0051] Some embodiments relate to an IC device. The IC device includes a plurality of dielectric layers disposed over a substrate and a capacitor structure comprising a plurality of capacitor portions. Each of the plurality of capacitor portions includes a first conductive element extending through the plurality of dielectric layers, a dielectric element extending through the plurality of dielectric layers and aligned along the first conductive element, and a second conductive element extending through the plurality of dielectric layers and aligned along the dielectric element. The plurality of dielectric layers include a first dielectric layer extending laterally between a plurality of first adjacent pairs of the plurality of capacitor portions, wherein the plurality of capacitor portions in the plurality of first adjacent pairs are spaced apart from each other by a length less than a first length. The first dielectric layer includes a sidewall defining a gap between each of a plurality of second adjacent pairs of the plurality of capacitor portions, wherein the length of the gap is greater than or equal to the first length.

[0052] Some embodiments relate to another type of IC device. The IC device includes a plurality of dielectric layers disposed above a substrate and a capacitor structure comprising a plurality of capacitor portions. Each of the plurality of capacitor portions includes a first conductive element extending through the plurality of dielectric layers, a dielectric element extending through the plurality of dielectric layers and aligned along the first conductive element, and a second conductive element extending through the plurality of dielectric layers and aligned along the dielectric element. In a top view of the IC device, the plurality of capacitor portions are arranged in a two-dimensional array. At least one of the plurality of dielectric layers bridges each adjacent pair of the plurality of capacitor portions aligned along rows or columns of the two-dimensional array. The at least one of the plurality of dielectric layers includes a gap between each adjacent pair of the plurality of capacitor portions.

[0053] Some embodiments relate to a method. The method includes forming a first electrode on a substrate; forming a plurality of dielectric layers over the first electrode; forming a plurality of trenches through the plurality of dielectric layers; conformally depositing a first conductive structure over the plurality of dielectric layers and in the plurality of trenches; removing portions of the plurality of first conductive structures outside the trenches; removing portions of at least one of the plurality of dielectric layers outside the plurality of trenches before (or above) the first dielectric layer of the plurality of dielectric layers; removing less than the entire first dielectric layer; removing other portions of the plurality of dielectric layers through at least one of the removed portions of the first dielectric layer; conformally depositing a first conductive material inside and outside the plurality of trenches; conformally depositing a dielectric material on the first conductive material; forming a second conductive material on the dielectric material; and forming a second electrode on the second conductive material.

[0054] It should be understood that in the written description and the appended claims, the terms "first," "second," "third," etc., are merely generic identifiers used for ease of description and to distinguish different terms. A figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" described in conjunction with a first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an embodiment not shown.

[0055] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

[0056] 100A, 100B, 200: MIM capacitor structure 101: Base Structure 102A: First conductive element 102B: Second conductive element 104: Dielectric components, insulating components 106, 402: Ditch 107: Horizontal Main Body 108: column 201: Base 202: First (bottom) electrode, first electrode 204, 208: Dielectric layers 206: Structural dielectric layer, dielectric layer, first dielectric layer, first (structural) dielectric layer 210: Dielectric cap layer 211: Dielectric spacer wall 212: Second electrode 220: First capacitor section 221: Second capacitor section 222: Protective Ring 224: Opening 230: Porosity 240: Through hole 242: Structural Components 244: Conductive interconnect structure 246: Conductive metal wire 252: First Length 254: Second Length 502: Protective plug 504: Photoresist material 1002: Dielectric spacer wall structure 1900: Method 1902, 1904, 1906, 1908, 1910, 1912, 1914, 1916, 1918, 1920, 1922, 1924: Actions

Claims

1. An integrated circuit (IC) device, comprising: Base; Multiple dielectric layers are disposed on the substrate; The capacitor structure includes a plurality of first capacitor portions, each of the plurality of first capacitor portions including: a first conductive element extending through the plurality of dielectric layers; a dielectric element extending through the plurality of dielectric layers and aligned with the first conductive element; and a second conductive element extending through the plurality of dielectric layers and aligned with the dielectric element, wherein in a cross-sectional view of the integrated circuit arrangement along the direction of the first conductive element, the dielectric element, and the second conductive element, the outermost wall of the first conductive element is aligned with the outermost wall of the dielectric element, and the outermost wall of the second conductive element is offset from the outermost wall of the first conductive element and the outermost wall of the dielectric element; wherein at least one of the plurality of dielectric layers includes a first dielectric layer extending laterally between a plurality of first adjacent pairs of the plurality of first capacitor portions, wherein the plurality of first capacitor portions in each of the plurality of first adjacent pairs of the plurality of first capacitor portions are spaced apart from each other by a first distance, wherein the first dielectric layer includes a sidewall defining a gap between each of a plurality of second adjacent pairs of the plurality of first capacitor portions, wherein the length of the gap is greater than the first distance.

2. The integrated circuit device as claimed in claim 1, wherein: In the plan view of the integrated circuit device, the plurality of first capacitor portions are arranged in a two-dimensional array; each of the plurality of first adjacent pairs of the plurality of first capacitor portions is aligned along a row or column of the two-dimensional array; and each of the plurality of second adjacent pairs of the plurality of first capacitor portions is aligned along a diagonal of the two-dimensional array.

3. The integrated circuit arrangement as claimed in claim 1, wherein the first dielectric layer is an etch stop layer, and wherein a portion of the first conductive element and a portion of the dielectric element are exposed by the second conductive element.

4. The integrated circuit device as claimed in claim 1, wherein the plurality of dielectric layers further includes a second dielectric layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials.

5. The integrated circuit device as claimed in claim 1, wherein, For each of the plurality of first capacitor portions: the first conductive element includes a first structure vertically oriented in a side view of the integrated circuit arrangement; the dielectric element includes a second structure coaxial with and located inside the first conductive element; and the second conductive element includes a third structure coaxial with and located inside the dielectric element.

6. The integrated circuit device as claimed in claim 1, further comprising: The first electrode is electrically connected to the first conductive element of each of the plurality of first capacitor portions; And a second electrode, electrically connected to the second conductive element of each of the plurality of first capacitor portions.

7. The integrated circuit arrangement as claimed in claim 1, wherein the capacitor structure further comprises: One or more second capacitor portions, each of the one or more second capacitor portions comprising: a first conductive element extending through the plurality of dielectric layers, wherein a portion of the first conductive element is shared with a portion of the first conductive element of at least one of the plurality of first capacitor portions; and a dielectric element extending through the plurality of dielectric layers and aligned along the first conductive element. And a second conductive element, extending through the plurality of dielectric layers and aligned along the dielectric element, wherein a pore is present in one of the plurality of first capacitor portions and one or more of the second capacitor portions.

8. An integrated circuit device, comprising: Base; Multiple dielectric layers are disposed on the substrate; The integrated circuit structure includes a plurality of first capacitor portions, each of the plurality of first capacitor portions comprising: a first conductive element extending through the plurality of dielectric layers; a dielectric element extending through the plurality of dielectric layers and aligned along the first conductive element; and a second conductive element extending through the plurality of dielectric layers and aligned along the dielectric element, wherein in a cross-sectional view of the integrated circuit arrangement along the directions of the first conductive element, the dielectric element, and the second conductive element, the outermost wall of the first conductive element is aligned with the outermost wall of the dielectric element, and the outermost wall of the second conductive element is offset from the outermost wall of the first conductive element and the outermost wall of the dielectric element; wherein in a plan view of the integrated circuit arrangement, the plurality of first capacitor portions are arranged in a two-dimensional array; wherein at least one of the plurality of dielectric layers bridges each adjacent pair of the plurality of first capacitor portions aligned along rows or columns of the two-dimensional array; and wherein the at least one of the plurality of dielectric layers has an opening between each adjacent pair of the plurality of first capacitor portions in the diagonal direction of the two-dimensional array.

9. A method of manufacturing an integrated circuit device, comprising: A first electrode is formed on the substrate; Multiple dielectric layers are formed on the first electrode; Multiple trenches are formed through the multiple dielectric layers; A first conductive structure is conformally deposited on the plurality of dielectric layers and deposited into the plurality of trenches; Remove the portion of the first conductive structure outside the plurality of trenches; At least one of the plurality of dielectric layers is partially removed outside the plurality of trenches and above the first dielectric layer of the plurality of dielectric layers; Partial removal of the first dielectric layer; By partially removing the first dielectric layer, some of the other dielectric layers are removed; A first conductive material is conformally deposited inside and outside the plurality of trenches; A dielectric material is conformally deposited on the first conductive material; A second conductive material is formed on the dielectric material; and a second electrode is formed on the second conductive material.

10. The method as described in claim 9, wherein: Partial removal of at least one of the plurality of dielectric layers outside the plurality of trenches and above the first dielectric layer in the plurality of dielectric layers includes removing the exposed portion of the plurality of dielectric layers outside the plurality of trenches until the first dielectric layer is exposed; Partial removal of the first dielectric layer includes: forming a plurality of dielectric spacer wall structures on the surface of the first electrode inside and outside the plurality of trenches; And partially remove portions of the dielectric spacer wall structure to remove portions of the first dielectric layer between adjacent trenches spaced at least a first linear distance, while leaving the complete remaining portion of the first dielectric layer.

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