Transistor and display device including the same

Abstract

This invention discloses a transistor and a display device comprising the transistor. The transistor includes: an active layer; a gate electrode having a region having a first length and a first width overlapping the active layer; and a gate insulating film disposed between the active layer and the gate electrode. The active layer may have an intrinsic region that protrudes from the center of the first width to a region that does not overlap with the gate electrode, rather than the edge of the first width.

Description

Technical Field

[0001] The present invention relates to a transistor, and more particularly to a transistor with improved reliability, and a display device including the transistor. Prior Art

[0002] Display devices for displaying images on devices such as televisions, monitors, smartphones, tablet computers, and laptops are used in various ways and forms.

[0003] The display device includes: a plurality of pixels configured to display images; and a transistor configured to control the operation of each pixel.

[0004] A display device includes a plurality of pixels and a plurality of driving and switching elements for driving and controlling the pixels. The driving and switching elements may be formed of transistors widely used in integrated circuits and pixels.

[0005] In recent years, various research and development efforts have been made to improve the performance and reliability of transistors. Summary of the Invention

[0006] An embodiment of the present invention provides a transistor configured such that an offset region is provided in the channel width direction of an active layer, thereby preventing the effective channel length formed during an ion doping process using a gate electrode as a mask from changing in the width direction.

[0007] An embodiment of the present invention provides a transistor configured so that changes in effective channel length in a transistor containing an oxide semiconductor are controlled, thereby improving the reliability of the transistor.

[0008] An embodiment of the present invention provides a transistor configured such that even if the transistor has a large channel width, changes in the effective channel length can be avoided or reduced, thereby avoiding changes in the threshold voltage.

[0009] An embodiment of the present invention provides a display device including a wide-width transistor with device stability in a display area or a non-display area.

[0010] An embodiment of the present invention provides a display device configured to reduce threshold voltage sensitivity due to channel width variation, thereby providing high design freedom and achieving a narrow frame by disposing high-power transistors in a non-display area with a small size.

[0011] Embodiments of the present invention provide a display device that can reduce the defective rate of the display device, thereby reducing the amount of materials used in the overall manufacturing process, such as the gas and etching liquid used to produce the display device, and thus reducing the generation of greenhouse gases caused by the process.

[0012] A transistor according to one embodiment of the present invention includes: an active layer; a gate electrode having a region having a first length and a first width that overlaps with the active layer; and a gate insulating film disposed between the active layer and the gate electrode, wherein the active layer has an intrinsic region that protrudes from the center of the first width to a region that does not overlap with the gate electrode, but not to an edge of the first width.

[0013] A display device according to one embodiment of the present invention includes: a substrate having a display area and a non-display area; a plurality of gate lines and a plurality of data lines intersecting each other in the display area, the plurality of gate lines and the plurality of data lines being configured to define a plurality of sub-pixels; a first transistor and a second transistor disposed in at least one of the plurality of sub-pixels; a light-emitting element connected to the second transistor; and a third transistor disposed in the non-display area. At least one of the first transistor, the second transistor, and the third transistor includes an active layer, a gate electrode having an area overlapping with the active layer, and a gate insulating film disposed between the active layer and the gate electrode. The active layer may have an intrinsic region that protrudes from the center of the width of the overlapping area to an area that does not overlap with the gate electrode, rather than to an edge of the width of the overlapping area. Simple diagram description

[0014] The following drawings are provided to provide a further understanding of the present invention and are incorporated into and constitute a part of this application. They depict embodiments of the present invention and together with the specification, serve to explain the principles of the present invention. In the drawings: Figure 1 is a schematic plan view showing a display device according to one embodiment of the present invention; Figure 2 is a circuit diagram showing a sub-pixel according to one embodiment of the present invention; Figure 3 is a plan view showing a transistor according to one embodiment of the present invention; Figure 4 is a plan view showing the active layer; Figure 5 is a sectional view taken along line I-I 'of Figure 3; Figure 6 is a sectional view taken along line II-II 'of Figure 3; Figure 7 is a cross-sectional view taken along line III-III 'of Figure 3; Figures 8A and 8B are plan and cross-sectional views of a transistor in which a doped region is diffused using a gate electrode as a mask; 9A and 9B are plan and cross-sectional views showing a doped region of a transistor formed according to one embodiment of the present invention; Figure 10 is a cross-sectional view showing a first transistor and a second transistor according to one embodiment of the present invention; FIG11 is a plan view showing a third transistor according to an embodiment of the present invention; and FIG. 12 is a cross-sectional view showing a display device according to an embodiment of the present invention. Implementation Method

[0015] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Whenever possible, the same reference symbols will be used throughout the drawings to refer to the same or similar components, unless otherwise specified. In the following description of the present invention, detailed descriptions of related known steps, components, functions, techniques, and configurations may be omitted because they may unnecessarily obscure the key points of the present invention. Furthermore, the component names used in the following description are selected for clarity of description and may differ from the component names of the actual product.

[0016] The shapes, sizes, proportions, angles, quantities, etc. depicted in the drawings to describe various exemplary embodiments of the present invention are provided by way of example only. The present invention is not limited to what is shown in the drawings. In the present invention, where terms such as "comprising," "having," "including," and the like are used, one or more elements may be included unless a term such as "only" is used. The terms used herein are used to describe specific aspects and are not intended to limit the present invention. When used herein, elements described in the singular are intended to include the plural. Unless the context clearly states otherwise, elements described in the singular are intended to include the plural, and vice versa.

[0017] When interpreting components or values, even if there is no explicit description of the error or tolerance range, the components or values ​​will be interpreted as including the error or tolerance range.

[0018] When describing various exemplary embodiments of the present invention, terms such as "on," "above," "below," and "near" are used to describe the positional relationship between two elements. Unless the terms "directly" or "immediately adjacent" are used, at least one intervening element may be present between the two elements. It should be understood that when an element or layer is referred to as being "connected" or "coupled" to another element or layer, it may be directly connected or coupled to the other element or layer, or one or more intervening elements may be present.

[0019] In describing various example embodiments of the present invention, when terms such as "after," "subsequently," "next," and "before" are used to describe the temporal relationship between two events, another event may occur therebetween, unless a more restrictive term such as "immediately" or "directly" is used.

[0020] When describing various exemplary embodiments of the present invention, terms such as "first" and "second" may be used to describe types of components. These terms are intended to distinguish identical or similar components from one another and do not limit the components. Therefore, throughout this specification, unless explicitly stated otherwise, a "first" component may be the same as a "second" component within the technical concept of the present invention.

[0021] As will be readily understood by those skilled in the art, the features of the various embodiments of the present invention may be coupled or combined, in part or in whole, and may interoperate and be technically driven in various ways. The embodiments of the present invention may be implemented independently of one another or together in a mutually dependent manner.

[0022] 1 is a schematic plan view showing a display device according to an embodiment of the present invention; and FIG. 2 is a circuit diagram showing a sub-pixel according to an embodiment of the present invention.

[0023] 1 and 2 , a display device 1000 according to an embodiment of the present invention may include a display panel 110, wherein the display panel 110 may include a substrate 111 including a display area AA and a non-display area NA surrounding the display area AA, and a driving unit connected to the substrate 111. The driving unit may be integrally integrated with the substrate 111 and formed together with an array disposed in the display area AA, and may be a chip-on-glass (COG) package connected to the substrate 111, a chip-on-film (COF) package connected to the substrate 111, or may be connected to a printed circuit board via a connector.

[0024] The display area AA is an area configured to display an image. A plurality of sub-pixels SP may be disposed in the display area AA of the display panel 110, and the plurality of sub-pixels SP may be used to display an image.

[0025] The display device 1000 may include a display panel 110 and a housing (not shown) configured to accommodate the sides and bottom of the display panel 110. The non-display area NA of the display panel 110 may be concealed by the housing or covered by a separate printed film. A printed circuit film and / or a battery may be disposed between the bottom of the display panel 110 and the housing.

[0026] The area where the plurality of sub-pixels SP are disposed may be a display area AA, and the area outside the display area may be a non-display area NA.

[0027] The non-display area NA may be an edge region surrounding the display area AA, which displays an image. At least one driving unit configured to drive a plurality of sub-pixels SP may be disposed in the non-display area NA. The driving unit may include a gate-in-panel (GIP). The gate-in-panel (GIP) may be connected to a plurality of gate lines GL in the display area AA and may sequentially supply gate voltage signals to the plurality of gate lines GL.

[0028] Various additional elements configured to drive the sub-pixels SP in the display area AA may be further disposed in the non-display area NA.

[0029] At least one of the plurality of sub-pixels SP may include: a first transistor T1; a second transistor T2; a storage capacitor Cst; a compensation circuit CC; and a light emitting element ED, as shown in FIG. 2 .

[0030] In one example, the first transistor T1 may be a switching transistor, and the second transistor T2 may be a driving transistor.

[0031] A first electrode (e.g., drain electrode) of the first transistor T1 is electrically connected to a data line DL, and a second electrode (e.g., source electrode) of the first transistor T1 is electrically connected to a first node N1. A gate electrode of the first transistor T1 is electrically connected to a gate line GL. The first transistor T1 transmits a data signal applied via the data line DL to the first node N1 in response to a scan signal applied via the gate line GL.

[0032] The storage capacitor Cst is electrically connected to the first node N1 to charge a voltage applied to the first node N1.

[0033] A first electrode (e.g., drain electrode) of the second transistor T2 receives a high-potential drive voltage EVDD, while a second electrode (e.g., source electrode) of the second transistor T2 is electrically connected to a first electrode (e.g., anode) of the light-emitting element ED. The second transistor T2 can control the amount of drive current flowing into the light-emitting element ED in response to a voltage applied to its gate electrode.

[0034] The semiconductor layers of the first transistor T1 and / or the second transistor T2 may include, but are not limited to, silicon, such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or low-temperature polycrystalline silicon (poly-Si); or oxide, such as indium gallium zinc oxide (IGZO). At least one of the first transistor T1 and the second transistor T2 may include an oxide semiconductor layer, which can be formed at a lower temperature than other materials, maintains amorphous properties, and has high mobility.

[0035] The light emitting element ED outputs light corresponding to the driving current. The light emitting element ED can output light corresponding to any one of red, green, blue, and white.

[0036] The light-emitting element ED may include an anode, an intermediate layer disposed on the anode, and a cathode to which a common voltage EVSS is applied. The intermediate layer may include at least one light-emitting layer, which may be configured to emit light of the same color, such as white light, on a pixel-by-pixel basis, or may be configured to emit light of different colors, such as red, green, or blue, on a sub-pixel basis. The intermediate layer may include various common layers and functional layers configured to efficiently supply holes and electrons to the light-emitting layer.

[0037] The light emitting element ED may be a front light emitting diode or a rear light emitting diode.

[0038] A compensation circuit CC may be further provided in the sub-pixel SP to compensate for the threshold voltage of the second transistor T2. The compensation circuit CC may include one or more transistors. The compensation circuit CC may include one or more transistors and capacitors and may be configured in various ways depending on the compensation method. The sub-pixel including the compensation circuit CC may include various circuits with different numbers of transistors (T) and / or capacitors (C), such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0039] Hereinafter, a transistor according to an embodiment of the present invention will be described. The transistor can be applied to a driving unit of a sub-pixel or non-display area including a compensation circuit CC, such as a transistor included in a gate-in-place (GIP) within a panel.

[0040] FIG3 is a plan view of a transistor according to an embodiment of the present invention. FIG4 is a plan view of an active layer. FIG5 is a cross-sectional view taken along line II' of FIG3; FIG6 is a cross-sectional view taken along line II-II' of FIG3; and FIG7 is a cross-sectional view taken along line III-III' of FIG3.

[0041] As shown in Figures 3 to 7, a transistor according to an embodiment of the present invention includes: an active layer ACT; and a gate electrode G, which has a region with a certain length L that overlaps with the active layer ACT in a first direction (X-axis or Y-axis), and a region with a certain width W that overlaps with the active layer ACT in a second direction (Y-axis or X-axis) that intersects the first direction.

[0042] The gate insulating film 125 is disposed between the active layer ACT and the gate electrode G.

[0043] The active layer ACT may have intrinsic regions UDP2 and UDP3, which protrude from the center of the width W of the region overlapping with the gate electrode G to the region not overlapping with the gate electrode G rather than the edge of the width W.

[0044] The intrinsic regions UDP1, UDP2, and UDP3 described herein are undoped regions. These regions are covered by a mask or gate electrode G during the doping process and are therefore undoped. In an embodiment of the present invention, the active layer ACT includes an intrinsic region outside the gate electrode G. Therefore, a separate mask can be used in addition to the gate electrode G during the doping process.

[0045] The intrinsic regions UDP2 and UDP3 may gradually decrease from the center C of the width W of the overlapping region between the active layer ACT and the gate electrode G toward the edge E of the width W. In addition to the intrinsic region UDP1 overlapping the gate electrode G, the active layer ACT further includes intrinsic regions UDP2 and UDP3 disposed in a region deviating from the gate electrode G so as to protrude toward the edge of the active layer ACT. In the plan view of FIG3 , each of the intrinsic regions UDP2 and UDP3 has an arc shape at the edge of the gate electrode G.

[0046] As shown in FIG4 , in the active layer ACT, the intrinsic regions UDP2 and UDP3 in the region not overlapping with the gate electrode G are connected to the intrinsic region UDP1 in the region overlapping with the gate electrode G, and the active layer ACT may have a doped region DP in the region not overlapping with the gate electrode G in addition to the intrinsic regions UDP2 and UDP3.

[0047] The active layer ACT of the transistor according to the embodiment of the present invention has intrinsic regions UDP1 , UDP2 , and UDP3 that are larger than the region overlapping with the gate electrode G.

[0048] Intrinsic regions UDP2 and UDP3 in the active layer ACT, offset from the gate electrode G, function as offset regions. The reason the center C of the width W of the active layer ACT has intrinsic regions UDP2 and UDP3 with larger areas toward the center C than at the edges E of the width W is to prepare for changes caused by differences in heat generation. After the doping process, during thermal treatment or during transistor driving, more heat is generated in the width direction at the center C than at the edges E.

[0049] Specifically, heat is generated in the active layer ACT, and dopants contained in the doped region DP diffuse toward its adjacent intrinsic region. Within the width W of the active layer ACT, diffusion is stronger at the center C than at the edge E, generating a relatively large amount of Joule heat. This can increase the channel length reduction ΔL along the width W. According to embodiments of the present invention, the active layer ACT can include larger intrinsic regions UDP2 and UDP3 at the center C of the width W of the active layer ACT. This prevents dopants from diffusing and overlapping the gate electrode G, maintaining the effective channel length substantially at the length L of the gate electrode G overlapping the active layer ACT. Referring to Figures 3 and 4, the channel length of the active layer ACT can include the length L of the region overlapping the gate electrode G and the extension length ΔLE of the intrinsic regions UDP2 and UDP3 in the active layer ACT offset from the gate electrode G. The extension length ΔLE of the active layer ACT offset from the gate electrode G varies across the width of the active layer ACT due to the amount of dopant diffusion. In this case, the maximum extension length of the intrinsic regions UDP2 and UDP3, located in the active layer ACT offset from the gate electrode G, can be located at the center C of the width W of the active layer ACT. Therefore, after transistor formation, the initial channel length can be maximized at the center C of the width W of the overlapping region between the active layer ACT and the gate electrode G. If dopant diffusion increases due to Joule heat generated during thermal processing or during transistor driving, the intrinsic region may decrease, and the extension length ΔLE may reach a value that is almost zero. Even in this case, the amount of dopant diffusion will still vary across the width, and because the intrinsic regions UDP2 and UDP3 exist in the active layer ACT due to this variation in diffusion, the boundary between the intrinsic region and the doped region may ultimately resemble the edge of the gate electrode G.

[0050] In a transistor according to an embodiment of the present invention, the intrinsic regions UDP2 and UDP3 are disposed outside the gate electrode G. When calculating the diffusion distance of the dopant after doping, the distance between the intrinsic regions UDP2 and UDP3 in the width direction is set differently due to the different Joule heat generated in each region.

[0051] Here, the dopant contained in the doping region DP may be, for example, bromine, phosphorus, or fluorine. However, examples of the dopant are not limited thereto, and elements with different molecular weights may be used as long as the element exhibits conductive properties when doped, taking into account the crystalline or amorphous nature of the active layer ACT.

[0052] The X direction in Figures 3 and 4 may be parallel to the gate line GL in Figure 1 , and the Y direction may be parallel to the data line DL in Figure 1 . In a transistor according to an embodiment of the present invention, the width W of the active layer ACT may be the width in the X-axis direction or the Y-axis direction, while the length L may be the length in a direction intersecting the width W. That is, if the width W of the active layer ACT is the width in the X-axis direction, the length L of the active layer ACT may be the length in the Y-axis direction. Alternatively, if the width W of the active layer ACT is the width in the Y-axis direction, the length L of the active layer ACT may be the length in the X-axis direction.

[0053] In a transistor according to an embodiment of the present invention, intrinsic regions UDP2 and UDP3 can be further disposed outside the gate electrode G to prevent dopants from penetrating into the gate electrode G during thermal diffusion. If doping is performed using only the gate electrode as a mask, Joule heating at the center of the channel width may increase during subsequent thermal processing or when driving the transistor, and the effective channel length (Leff) at the center of the channel width may decrease sharply. However, a transistor according to an embodiment of the present invention can avoid these problems.

[0054] As shown in Figures 3 to 7, a transistor according to an embodiment of the present invention may further include a source electrode S and a drain electrode D, each connected to a doped region DP of the active layer ACT located on either side of the gate electrode G. The doped region DP is a conductive region in the active layer ACT that directly contacts the metal. The doped region DP functions as a source-drain region in the active layer ACT. In the active layer ACT, the initial doped region DP may be spaced apart from the edge of the gate electrode G by the set length of the intrinsic regions UDP2 and UDP3.

[0055] The active layer ACT may include an oxide semiconductor. For example, the active layer ACT may be made of an oxide containing at least one of indium, gallium, zinc, tin, and iron, and preferably, an oxide containing two or more of indium, gallium, zinc, tin, and iron. However, the active layer ACT according to embodiments of the present invention is not limited to oxide semiconductors. As another example, the active layer ACT may include silicon, such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or low-temperature polycrystalline silicon (poly-Si).

[0056] When the active layer ACT is made of an oxide semiconductor, a crystallization process requiring a high temperature can be omitted while maintaining amorphous properties and having high mobility.

[0057] In structures that use the gate electrode as a mask for doping, the channel length reduction ΔL may increase in proportion to the channel width. This reduction in channel length means an increase in the conductive area of ​​the active layer, which reduces the total effective channel area of ​​the active layer and reduces the threshold voltage of the active layer required for switching. Furthermore, the threshold voltage tends to shift to negative values ​​in proportion to the channel length reduction ΔL.

[0058] Meanwhile, in recent years, there has been a growing desire to gradually increase the size of the active layer to form transistors with high power output, and to achieve correspondingly larger channel sizes, particularly wider channels. However, as described above, as the channel width increases, the effect of the ΔL reduction in channel length increases in the width direction due to differences in Joule heating. Furthermore, because doped regions are located on both sides of the channel in the intrinsic region, a 2ΔL channel length reduction can occur when the channel width increases in structures that use the gate electrode as a mask for doping. Therefore, in structures that use the gate electrode as a mask for doping, when using an active layer with a wide channel, the threshold voltage variation increases as the channel width increases due to the reduction in channel length, meaning that the threshold voltage becomes more sensitive to width variations.

[0059] Even with a wide channel, transistors according to embodiments of the present invention can avoid or minimize channel length variations by having intrinsic regions offset from the gate electrode in the channel width direction, resulting in different intrinsic regions. Therefore, when used in switching transistors requiring a wide channel for high output or in gate-in-panel (GIP) applications, this prevents channel width reduction in wide-channel transistors and mitigates the threshold voltage fluctuations that occur with increasing channel width.

[0060] Furthermore, in a transistor according to an embodiment of the present invention, the width dependence or width sensitivity of an active layer having a large width can be avoided, so that a transistor with high power output can be reliably implemented with a large width, thereby increasing design freedom and achieving a narrow frame when applied to a drive unit.

[0061] The cross-sectional structure of a transistor according to an embodiment of the present invention will be described below with reference to FIG. 5 to FIG. 7 .

[0062] A first insulating film 121 and a second insulating film 122 are sequentially disposed on the substrate 111. The first insulating film 121 and the second insulating film 122 are disposed on the substrate 111 to prevent impurities, such as moisture or charged particles, from penetrating structures on the substrate 111 and to flatten the surface. The first insulating film 121 and the second insulating film 122 can function as buffer layers.

[0063] For example, each of the first insulating film 121 and the second insulating film 122 may include at least one of a silicon oxide film (SiOx), a silicon nitride film (SiNx), and a silicon oxynitride film (SiOxNy), or a multilayer film formed by stacking inorganic films.

[0064] The light-shielding metal B is provided on the second insulating film 122. The light-shielding metal B is located below the active layer ACT formed thereon and can prevent external light entering from the substrate 111 from affecting the active layer ACT.

[0065] For example, the light-shielding metal B can be made of a conductive metal material. Specifically, the conductive metal material can include at least one of the following: aluminum-based metals, such as aluminum (Al) or aluminum alloys; silver-based metals, such as silver (Sg) or silver alloys; copper-based metals, such as copper (Cu) or copper alloys; molybdenum-based metals, such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti). In some cases, when the substrate 111 includes two active layers, one of the active layers can be a conductive layer.

[0066] The third insulating film 123 and the fourth insulating film 124 may be disposed on the second insulating film 122 in which the light-shielding metal B is located.

[0067] Each of the third insulating film 123 and the fourth insulating film 124 may include an inorganic insulating film.

[0068] The active layer ACT is disposed on the fourth insulating film 124 and overlaps with the light shielding metal B.

[0069] The gate insulating film 125 is disposed on the active layer ACT.

[0070] If the active layer ACT is made of an oxide semiconductor, when each of the fourth insulating film 124 and the gate insulating film 125 is made of a silicon oxide film, no hydrogen particles will be emitted during the heat treatment process, thereby preventing the reliability of the active layer ACT disposed adjacent to the fourth insulating film 124 and the gate insulating film 125 from being reduced due to hydrogen particles during the process.

[0071] As shown in FIG3 , the gate electrode G is disposed on the gate insulating film 125. The gate electrode G has a region having a length L overlapping with the active layer ACT in a first direction (X-axis or Y-axis), and has a region having a width W overlapping with the active layer ACT in a second direction (Y-axis or X-axis) intersecting the first direction.

[0072] The length L of the overlapping region between the active layer ACT and the gate electrode G is located between the source electrode S and the drain electrode D in the longitudinal direction of the channel.

[0073] The gate electrode G is made of, for example, a conductive metal material, and the conductive metal material may include at least one of the following: aluminum-based metals, such as aluminum (Al) or aluminum alloys; silver-based metals, such as silver (Sg) or silver alloys; copper-based metals, such as copper (Cu) or copper alloys; molybdenum-based metals, such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti).

[0074] After the gate electrode G is formed, a mask (see the offset mask OFM in FIG9B ) is prepared, which is configured to cover at least a majority of the non-doped region (intrinsic regions UDP2 and UDP3) surrounding the gate electrode G in FIG3 and FIG4 , and the active layer ACT not covered by the mask and the gate electrode G is doped with dopant ions to form a doped region DP.

[0075] As shown in FIG. 5 , a cross section taken along the channel length L direction corresponding to the edge E of the active layer channel width W shows that the boundary between the doped region DP and the intrinsic region UDP is close to the edge of the gate electrode G.

[0076] As shown in FIG6 , a cross section taken in the channel length L direction corresponding to the center C of the width W of the active layer channel shows that the boundary between the doped region DP and the intrinsic region UDP is spaced apart from the edge of the gate electrode G by a predetermined distance.

[0077] As shown in FIG. 7 , a cross-section taken in the channel length L direction corresponding to the space between the center C and the edge E of the width W of the active layer channel shows that the gate electrode G and the doped region DP are separated from each other by a distance smaller than the distance between the gate electrode G and the doped region DP in FIG. 6 .

[0078] 3 to 7 , the intrinsic region UDP (UDP1 + UDP2 + UDP3) has a shape in which the width W gradually decreases from the center C of the region where the active layer ACT overlaps the gate electrode G to the edge E of the width W.

[0079] The fifth insulating film 126 and the sixth insulating film 127 are sequentially disposed on the gate insulating film 125 on which the gate electrode G is disposed.

[0080] Each of the fifth insulating film 126 and the sixth insulating film 127 may be formed as a single film. Each of the fifth insulating film 126 and the sixth insulating film 127 may be made of an inorganic insulating material.

[0081] When the fifth insulating film 126 and the sixth insulating film 127 are sequentially provided, different inorganic insulating materials may be provided, or an inorganic film and an organic film may be provided sequentially. The fifth insulating film 126 may be made of an inorganic insulating material that releases less hydrogen than the sixth insulating film 127 during heat treatment.

[0082] The first to sixth insulating films (121, 122, 123, 124, 126, and 127) and the gate insulating film 125 formed on the substrate 111 are collectively referred to as the insulating film 120. In the insulating film 120, one layer of the multilayer insulating film between the active layer and the metal layer or between different metal layers may be omitted. Furthermore, the multilayer insulating film can be formed by sequentially depositing different materials or varying the ratios of their components.

[0083] At the same time, the light-shielding metal B can be connected to one side of the gate electrode G to apply a voltage of the same potential. In this case, the transistor has a dual-gate structure, with the gate electrodes located above and below the active layer ACT. This allows for more precise control of the current flowing through the active layer ACT and can be implemented as an overlapping structure, eliminating the need to increase the planar area for the transistor. Furthermore, compared to conventional gate structures for generating the same current, this gate structure can be implemented in a compact form factor, with the light-shielding metal B and gate electrode G overlapping each other. This is advantageous in forming high-resolution structures for display devices.

[0084] Hereinafter, a structure in which doping is performed using a gate electrode as a mask will be described.

[0085] 8A and 8B are a plan view and a cross-sectional view of a transistor in which a doped region is diffused using a gate electrode as a mask.

[0086] As shown in Figure 8B , a buffer layer BF is formed on a substrate SUB, followed by the active layer ACT1. Subsequently, a gate insulation layer GI is formed to cover the active layer ACT1, and a gate electrode GA is formed on the gate insulation layer GI to overlap the active layer ACT1. Subsequently, doping is performed on the active layer ACT1 on both sides of the gate electrode GA, using the gate electrode GA as a mask. After doping, as shown in Figures 8A and 8B , the dopant not only remains outside the gate electrode GA but also diffuses into the region overlapping the gate electrode GA. A channel length reduction ΔL may occur depending on the diffusion rate of the dopant.

[0087] 9A and 9B are a plan view and a cross-sectional view showing a doped region of a transistor formed according to one embodiment of the present invention.

[0088] As shown in FIG9B , during the manufacturing process of a transistor according to an embodiment of the present invention, a gate insulating film 125 is formed to cover the active layer ACT, and a gate electrode G is formed on the gate insulating film 125 with an overlapping region having a length L in a first direction and an overlapping region having a width W in a second direction intersecting the first direction.

[0089] Subsequently, as shown in Figures 9A and 9B , an offset mask OFM is formed, covering the top and side surfaces of the gate electrode G and partially overlapping the active layer ACT on both sides of the gate electrode G. When the offset mask OFM overlaps the active layer ACT with reference to Figure 9A , the center of the width, rather than the edges, protrudes in the direction of the width W, ensuring that the offset mask OFM fully covers the intrinsic regions UDP2 and UDP3 described with reference to Figures 3 and 4 . Furthermore, when the intrinsic regions UDP2 and UDP3 to be formed have an extension length ΔLE, a margin length ΔM is set to account for diffusion during the doping process. That is, the offset mask OFM has a maximum length of "ΔLE + ΔM" at the center C of the channel width W.

[0090] 9B is a cross-sectional view taken along line II-II' of FIG. 3 and taken through the center C of the channel of the active layer ACT of FIG. 9A .

[0091] In the example shown in FIG9B , the first to fourth insulating films (121, 122, 123, and 124) are formed on the substrate 111 as elements below the active layer ACT, and the light-shielding metal B is provided below the active layer ACT. However, the transistor according to the embodiment of the present invention is not limited to the example shown above and can be applied to a structure in which at least one of the first to fourth insulating films (121, 122, 123, and 124) and the light-shielding metal B is omitted.

[0092] Hereinafter, an embodiment of a circuit provided in a sub-pixel in which transistors T1 and T2 have different intrinsic areas will be described.

[0093] FIG. 10 is a cross-sectional view showing a first transistor and a second transistor according to an embodiment of the present invention.

[0094] As shown in Figure 10, the first transistor T1 according to an embodiment of the present invention includes: a first light-shielding metal B1, located on the substrate 111; a first active layer A1, overlapping with the first light-shielding metal B1; a first gate electrode G1, overlapping with a portion of the intrinsic region UDP of the first active layer A1; and a first source-drain electrode SD11 and a second source-drain electrode SD12, connected to the doped region DP of the first active layer A1 located on both sides of the first gate electrode G1.

[0095] In the first transistor T1, the first gate electrode G1 has a region with a length L that overlaps with the first active layer A1 in a first direction (X-axis or Y-axis); and a region with a width W that overlaps with the first active layer A1 in a second direction (Y-axis or X-axis) that intersects the first direction, as described with reference to Figures 3 to 7. The region overlapping the first active layer A1 and the first gate electrode G1 is the intrinsic region UDP. Furthermore, the intrinsic region UDP further includes different extension lengths ΔLE extending outward from the first gate electrode G1 in the width direction of the first active layer A1. That is, the first active layer A1 of the first transistor T1 further has: the intrinsic region UDP is longest outward from the first gate electrode G1 at the center of the width W that overlaps with the first gate electrode G1; the intrinsic region UDP gradually decreases toward the edges of the width W; and the intrinsic region UDP at the edges of the width W is approximately equal to the edge of the first gate electrode G1. That is, when the length of the intrinsic region UDP is viewed from the center toward the edge of the width of the first active layer A1, the length of the intrinsic region UDP changes from "L + ΔLE" to "L." This means that the length ΔLE extending from the intrinsic region to the outside of the gate electrode has changed, and "L + ΔLE" can be the channel width of the first active layer A1. Therefore, the channel length of the first transistor T1 can be "L" or greater.

[0096] The first light-shielding metal B1 can also function as a gate electrode that protects the first active layer A1 from light entering from below the substrate 111. In this case, the first light-shielding metal B1 is connected to the first gate electrode G1 and can apply a gate voltage signal of the same potential thereto.

[0097] The second transistor T2 includes: a second light-shielding metal B2 located on the substrate 111; a second active layer A2 overlapping with the second light-shielding metal B2; a second gate electrode G2 overlapping with the intrinsic region UDP of the second active layer A2; and a third source-drain electrode SD21 and a fourth source-drain electrode SD22 connected to the doped region DP of the second active layer A2 located on both sides of the second gate electrode G2.

[0098] In the example shown, the first transistor T1 and the second transistor T2 have a first active layer A1 and a second active layer A2 disposed on the same layer.

[0099] Among the first transistor T1 and the second transistor T2, the first transistor may have a first active layer A1 formed to have a large width for outputting relatively high power.

[0100] When the first active layer A1 has a large width and further includes an intrinsic region UDP with a changed extension length ΔLE outside the first gate electrode G1 in the width direction, even if conductivity diffusion occurs due to dopant diffusion during the manufacturing or driving process, the diffusion region can still extend by the length ΔLE outside the first gate electrode G1. This prevents dopant diffusion beneath the first gate electrode G1, thereby avoiding defects caused by a change in the effective channel length.

[0101] In the first transistor T1 and the second transistor T2, the first light-shielding metal B1 and the second light-shielding metal B2 are located on different layers. The first transistor T1, with the third insulating film 123 further disposed between the first active layer A1 and the first light-shielding metal B1, can prevent excessive electron accumulation at the interface of the first active layer A1 and prevent the charge in the channel of the first active layer A1 from decreasing over time. As a result, the first transistor T1 can achieve high-speed response, like a switching transistor, and have improved reliability.

[0102] The second light-shielding metal B2 and the second active layer A2 may be connected to the third source-drain electrode SD21 and may be controlled to have the same potential.

[0103] For example, if the first active layer A1 and the second active layer A2 include a light-sensitive semiconductor, the first transistor T1 and the second transistor T2 can effectively block light entering from below and prevent the off-state current of the first active layer A1 and the second active layer A2 from increasing due to the incident light, thereby improving reliability.

[0104] The second transistor T2 can have a shorter channel than the first transistor T1. In this case, the second transistor T2 with a narrower channel width generates only minimal Joule heating in the width direction during thermal processing or driving. Therefore, because the second transistor T2 is not particularly sensitive to width, a separate offset mask is not provided on the second gate electrode G2. Furthermore, when doping is performed using the second gate electrode G2, diffusion of dopants that overlap with the second gate electrode G2 is unlikely to occur.

[0105] Therefore, the first transistor T1 and the second transistor T2 can be formed with a large width and a small width depending on whether the intrinsic region UDP deviates from the gate electrodes G1 and G2.

[0106] The first transistor T1 having a relatively fast response and to which a high-voltage gate voltage is applied may be a transistor having a large width, and may further include an intrinsic region UDP offset from the first gate electrode G1.

[0107] The first transistor T1 may be a switching transistor, and the second transistor T2 may be a driving transistor. However, the transistor according to the embodiment of the present invention is not limited thereto, and each of the first transistor T1 and the second transistor T2 may include an intrinsic region offset from the gate electrode, or the second transistor T2 may be formed to include an intrinsic region offset from the gate electrode.

[0108] When a protruding intrinsic region is further provided on both sides of a transistor having a large width, the intrinsic region can still perform an offset function even in the presence of dopants diffused during the manufacturing process or driving process, and can prevent the dopants from penetrating the underside of the gate electrode. This can thereby prevent changes in the channel length of the active layer and avoid changes in the threshold voltage caused by a reduction in the channel area.

[0109] When a large-width transistor and a small-width transistor are disposed together in a sub-pixel or a driving unit, changes in the threshold voltage of the large-width transistor can be avoided or reduced to avoid characteristic differences, such as changes in the threshold voltage between the large-width transistor and the small-width transistor, thereby maintaining operational stability of the sub-pixel or the driving unit.

[0110] Furthermore, when a transistor having intrinsic regions on both sides of a protruding gate electrode is disposed in a driving unit, changes in channel length area in response to Joule heating characteristics can be avoided or reduced, thereby minimizing changes in channel length throughout the active layer. Consequently, a high-power transistor having a smaller area can be designed compared to a structure formed by reducing the channel length by a margin of ΔL, thereby enabling a narrow frame.

[0111] The first to sixth insulating films ( 121 , 122 , 123 , 124 , 126 , and 127 ) and the gate insulating film 125 may have the same or similar configuration or function as the insulating films or transistors described with reference to FIG. 5 to FIG. 7 .

[0112] FIG. 11 is a plan view showing a third transistor according to an embodiment of the present invention.

[0113] As shown in FIG. 11 , the third transistor WTFT according to the embodiment of the present invention is configured such that the active layer ACT overlaps the gate electrode G by a length L and has a width W greater than the length L.

[0114] The overlapping region between the active layer ACT and the gate electrode G has a length L in a first direction (Y axis or X axis) and a width W in a second direction (X axis or Y axis) intersecting the first direction.

[0115] As shown in FIG11 , the third transistor WTFT includes an intrinsic region UDP that protrudes further outward from the center C of the width W of the active layer ACT; an intrinsic region UDP that gradually decreases toward the edge E; and an intrinsic region UDP at the edge E that corresponds to the length L of the gate electrode G. The remaining area of ​​the active layer ACT, excluding the intrinsic region UDP, is a doped region DP. The source electrode S and the drain electrode D are connected to the doped region DP on either side via contact holes CT, while being spaced apart from the gate electrode G.

[0116] The cross-sectional shape of the third transistor WTFT may be the same as the cross-sectional structure described with reference to FIG. 5 to FIG. 7 .

[0117] The third transistor WTFT may be used in a driving unit disposed in the non-display area NA of the substrate, such as a buffer transistor or a gate-in-panel (GIP), and has a large channel to facilitate generation of high current.

[0118] Furthermore, another intrinsic region is positioned from the center to the edge relative to the maximum width. Therefore, even if the conductive diffusion distribution generated by Joule heat varies from region to region, the diffused dopant does not overlap with the gate electrode G, thereby avoiding or reducing changes in the effective channel length. This prevents changes in the threshold voltage caused by changes in channel length and improves device reliability.

[0119] Hereinafter, a display device according to an embodiment of the present invention will be described.

[0120] FIG. 12 is a cross-sectional view showing a display device according to an embodiment of the present invention.

[0121] Substrate 111 can be made of a plastic material to provide flexibility. In one example, substrate 111 can include a first organic film and a second organic film that overlap each other, with an inorganic interlayer insulating film interposed therebetween. The first and second organic films can be made of the same or different organic films, such as polyethylene terephthalate (PET) and polyimide. In some cases, an adhesive film, such as pressure-sensitive adhesive (PSA), can be disposed between the first and second organic films.

[0122] In another example, the substrate 111 may include a flexible thin glass material.

[0123] The substrate 111 is used to support and protect the components of the display device 1000 disposed thereon.

[0124] A plurality of stacked insulating films 120 (121 and 122, 123, 124, 125, 126, and 127) are disposed in the display area AA and non-display area NA of the substrate 111 (see FIG1 ). This insulates the electrodes B1, G1, SD11 / SD12, B2, G2, and SD21 / SD22 that comprise the first transistor T1 and the second transistor T2 from one another. The insulating films 120 may include a first insulating film 121, a second insulating film 122, a third insulating film 123, a fourth insulating film 124, a gate insulating film 125, a fifth insulating film 126, and a sixth insulating film 127.

[0125] A first insulating film 121 is disposed in the display area AA and the non-display area NA of the substrate 111. The first insulating film 121 can be referred to as a buffer film and can perform the same function as conventional buffer films. The first insulating film 121 can be disposed on the substrate 111 to protect structures on the substrate 111 from moisture penetrating through the substrate 111 and to planarize the surface of the substrate 111.

[0126] The first insulating film 121 may extend to the edge of the substrate 111 to prevent moisture from penetrating from the edge of the substrate 111. The first insulating film 121 may be composed of a single inorganic film or a plurality of inorganic films alternately stacked.

[0127] For example, the first insulating film 121 may include at least one of a silicon oxide film (SiOx), a silicon nitride film (SiNx), and a silicon oxynitride film (SiOxNy), or a multilayer film formed by stacking inorganic films.

[0128] The second insulating film 122 can be disposed on the first insulating film 121. For example, the second insulating film 122 can function as a second buffer film. In this case, some transistors included in the sub-pixels may include a polycrystalline silicon semiconductor layer (not shown), and the second insulating film 122 may be located below the polycrystalline silicon semiconductor layer. The second insulating film 122 can include an inorganic film, such as a silicon oxide film (SiOx) or a silicon nitride film (SiNx), or a multilayer film thereof. In some cases, the second insulating film 122 can function as a gate insulating film for transistors including a polycrystalline silicon semiconductor layer.

[0129] The first light-shielding metal B1 made of a conductive metal material can be disposed on the second insulating film 122. Specifically, the conductive metal material can include at least one of the following: aluminum-based metals, such as aluminum (Al) or aluminum alloys; silver-based metals, such as silver (Sg) or silver alloys; copper-based metals, such as copper (Cu) or copper alloys; molybdenum-based metals, such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti).

[0130] The first light-shielding metal B1 may form one electrode of a storage capacitor included in the sub-pixel.

[0131] The third insulating film 123 may be disposed on the first light-shielding metal layer B1, where the second insulating film 122 is disposed. The third insulating film 123 may function as an insulator for a storage capacitor connected to at least one of the first transistor T1 and the second transistor T2. Alternatively, the third insulating film 123 may function as an interlayer insulating film for a transistor including a polycrystalline silicon semiconductor layer.

[0132] The third insulating film 123 may include an inorganic material, such as a silicon nitride film (SiNx).

[0133] The second light-shielding metal B2 made of a conductive metal material is disposed on the third insulating film 123. The conductive metal material may include at least one of the following: aluminum-based metals, such as aluminum (Al) or aluminum alloys; silver-based metals, such as silver (Sg) or silver alloys; copper-based metals, such as copper (Cu) or copper alloys; molybdenum-based metals, such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti).

[0134] The first light-shielding metal B1 and the second light-shielding metal B2 can be disposed on the same layer, serving as the first and second electrodes of the storage capacitor, respectively. Each of the first light-shielding metal B1 and the second light-shielding metal B2 can be formed as a single layer, or can have a structure comprising a plurality of stacked different metal materials.

[0135] The fourth insulating film 124 can be disposed on the second light-shielding metal layer B2, where the third insulating film 123 is disposed. The fourth insulating film 124 can be located below the first active layer A1 and the second active layer A2 and can function as a buffer layer. The fourth insulating film 124 can be used to planarize the surface of the region where the first active layer A1 and the second active layer A2 are formed.

[0136] The fourth insulating film 124 may include an inorganic material. The inorganic material may include, for example, a silicon oxide film (SiOx) or a multilayer film formed by stacking inorganic films.

[0137] The first active layer A1 and the second active layer A2 are disposed on the fourth insulating film 124. Each of the first active layer A1 and the second active layer A2 comprises an oxide semiconductor material. The oxide semiconductor material may comprise a combination of at least one of zinc (Zc), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and an oxide. In some cases, a highly conductive metal such as iron (Fe) may be further included in the oxide semiconductor material to increase mobility.

[0138] More specifically, the oxide semiconductor material constituting the first active layer A1 and the second active layer A2 may be, for example, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), or iron indium zinc oxide (FIZO).

[0139] The gate insulating film 125 is disposed to cover the first active layer A1 and the second active layer A2 .

[0140] The first gate electrode G1 and the second gate electrode G2, which partially overlap the first active layer A1 and the second active layer A2, are disposed on the gate insulating film 125. Each of the first gate electrode G1 and the second gate electrode G2 can include at least one of the following: an aluminum-based metal, such as aluminum (Al) or an aluminum alloy; a silver-based metal, such as silver (Ag) or a silver alloy; a copper-based metal, such as copper (Cu) or a copper alloy; a molybdenum-based metal, such as molybdenum (Mo) or a molybdenum alloy; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti). Each of the first gate electrode G1 and the second gate electrode G2 can have a single-layer structure or a multi-layer structure.

[0141] The first gate electrode G1 may be connected to, for example, the gate line GL described with reference to FIG. 1 .

[0142] In one embodiment of the present invention, the first gate electrode G1 can be connected to the underlying first light-shielding metal B1, allowing for the application of a gate voltage signal having the same potential. In this case, the potential stabilization of the first light-shielding metal B1 and the use of a dual-gate structure for the first transistor T1 enable high-speed operation in a small size.

[0143] After forming the first gate electrode G1, an offset mask OFM (see FIG. 9B ) is further formed to cover the top and side surfaces of the first gate electrode G1, and doping is performed. Therefore, the intrinsic region UDP of the first active layer A1 can further extend from the edge of the first gate electrode G1 and can be arranged with an extension length ΔLE. The distance of the intrinsic region UDP extending from the edge of the first gate electrode G1 can gradually decrease from the center C toward the edge E of the width W of the first active layer A1, as described with reference to FIG. 3 , FIG. 4 , and FIG. 11 .

[0144] Therefore, the first active layer A1 has a larger amount of intrinsic region UDP protruding from the center of the region overlapping with the first gate electrode G1 to the region not overlapping with the first gate electrode G1, compared to the width of the region overlapping with the first gate electrode G1. Therefore, in addition to the region overlapping with the first gate electrode G1, the first active layer A1 also has intrinsic regions UDP protruding outward from both side edges of the first gate electrode G1, as well as doped regions DP outside the intrinsic regions UDP.

[0145] The second active layer A2 includes: a region overlapping with the second gate electrode G2, serving as an intrinsic region UDP; and a region outside the second gate electrode G2, serving as a doped region DP.

[0146] The fifth insulating film 126 and the sixth insulating film 127 are disposed on the gate insulating film 125, wherein the first gate electrode G1 and the second gate electrode G2 are disposed.

[0147] Each of the fifth insulating film 126 and the sixth insulating film 127 is made of an inorganic insulating material and, in some cases, may have a single-layer structure.

[0148] Each of the fifth insulating film 126 and the sixth insulating film 127 may include, for example, a silicon oxide film (SiOx) or a silicon nitride film (SiNx), or may include a multilayer film formed by stacking inorganic films.

[0149] The sixth insulating film 127, the fifth insulating film 126, and the gate insulating film 125 are selectively removed to form contact holes, through which the doped regions of the first active layer A1 and the second active layer A2 are exposed. Through the contact holes, the first active layer A1 is connected to the first source-drain electrode SD11 and the second source-drain electrode SD12, while the second active layer A2 is connected to the third source-drain electrode SD21 and the fourth source-drain electrode SD22.

[0150] Each of the first to fourth source-drain electrodes (SD11, SD12, SD21, and SD22) can include at least one of the following: an aluminum-based metal, such as aluminum (Al) or an aluminum alloy; a copper-based metal, such as copper (Cu) or a copper alloy; a molybdenum-based metal, such as molybdenum (Mo) or a molybdenum alloy; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti). Each of the first gate electrode G1 and the second gate electrode G2 can have a single-layer structure or a multi-layer structure.

[0151] The third source-drain electrode SD21 is connected to the second light-shielding metal B2 located below the second active layer A2 and further extending from one side of the second active layer A2, and can stabilize the potential of the second light-shielding metal B2.

[0152] The first transistor T1 includes: a first light-shielding metal B1 located on the substrate 111; a first active layer A1 overlapping with the first light-shielding metal B1; a first gate electrode G1 overlapping with a portion of the intrinsic region UDP of the first active layer A1; and a first source-drain electrode SD11 and a second source-drain electrode SD12 connected to the doped region DP of the first active layer A1 located on both sides of the first gate electrode G1.

[0153] The second transistor T2 includes: a second light-shielding metal B2 located on the substrate 111; a second active layer A2 overlapping with the second light-shielding metal B2; a second gate electrode G2 overlapping with the intrinsic region UDP of the second active layer A2; and a third source-drain electrode SD21 and a fourth source-drain electrode SD22 connected to the doped region DP of the second active layer A2 located on both sides of the second gate electrode G2.

[0154] A planarization film 129 configured to protect the first and second transistors T1 and T2 may be provided on the first to fourth source-drain electrodes ( SD11 , SD12 , SD21 , and SD22 ).

[0155] The planarization film 129 may include an organic material. The organic material may include at least one of acrylic resin, phenolic resin, polyimide resin, unsaturated polyester resin, polyamide resin, benzocyclobutene, polyphenylene ether resin, and polyphenylene sulfide resin.

[0156] The anode 141 may be further provided on the planarization film 129 and may be connected to the fourth source-drain electrode SD22 via a contact hole in the planarization film 129 .

[0157] The anode 141 , the cathode 143 opposite to the anode, and the intermediate layer 142 between the anode 141 and the cathode 143 constitute the light emitting element ED.

[0158] One of the anode 141 and the cathode 143 may include a reflective electrode, and the other may include a transparent electrode or a semi-reflective-semi-transparent electrode.

[0159] When anode 141 includes a reflective electrode, it can prevent light from entering the underlying transistor. Anode 141 can include, for example, a stacked structure of a transparent electrode, a reflective electrode, and a second transparent electrode. The second transparent electrode, the topmost electrode of anode 141, can be a dielectric, which can lower the barrier for hole injection into the interface of intermediate layer 142. Here, each of the first and second transparent electrodes can be a transparent oxide electrode, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The reflective electrode can include: silver; a silver alloy such as silver-palladium-copper (Ag-Pd-Cu, APC); aluminum; or an aluminum alloy.

[0160] For example, the anode 141 may be formed as a multilayer structure, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti); a stacked structure of aluminum (Al) and indium zinc oxide (ITO) (ITO / Al / ITO); a silver-palladium-copper (Ag / Pd / Cu) alloy; a stacked structure of a silver-palladium-copper alloy and indium zinc oxide (ITO / APC / ITO); or a stacked structure of silver (Ag) and molybdenum-titanium alloy (Ag / MoTi), or may include a single-layer structure having any one of the following materials: silver (Ag); aluminum (Al); molybdenum (Mo); gold (Au); magnesium (Mg); calcium (Ca); and barium (Ba); or an alloy of two or more of the above materials.

[0161] The pixel defining film 135 may be provided to surround an edge of the anode 141 , and the light emitting unit may be defined in an open area of ​​the pixel defining film 135 .

[0162] The pixel defining film 135 may include an inorganic material or an organic material. The pixel defining film 135 may include an opaque material (e.g., black) configured to prevent light interference between adjacent sub-pixels SP. In this case, the pixel defining film 135 may include a light-shielding material including at least one of a pigment, an organic black pigment, and carbon.

[0163] Intermediate layer 142 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Intermediate layer 142 may be formed as a tandem structure comprising a plurality of stacks, each stack comprising a hole transport layer, a light-emitting layer, and an electron transport layer. The charge generation layer may include, for example, an n-type charge generation layer and a p-type charge generation layer.

[0164] The light-emitting layer included in the intermediate layer 142 can be configured differently for each sub-pixel SP. The light-emitting layer can include a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, and a blue light-emitting layer that emits blue light. The red light-emitting layer, the green light-emitting layer, and the blue light-emitting layer can be provided on the anode 141 of each sub-pixel SP.

[0165] For example, a red light-emitting layer may be arranged and disposed on a red sub-pixel, a green light-emitting layer may be arranged and disposed on a green sub-pixel, and a blue light-emitting layer may be arranged and disposed on a blue sub-pixel. However, the present invention is not necessarily limited thereto, and at least two of the red light-emitting layer, the green light-emitting layer, and the blue light-emitting layer may be stacked and disposed in a single sub-pixel SP.

[0166] The light emitting layer may be a white light emitting layer that emits white light. In this case, the light emitting layer may be in the form of a common layer, wherein one or more layers may be commonly disposed on the sub-pixel SP, rather than being disposed in a pattern on the sub-pixel SP.

[0167] As described above, the intermediate layer 142 may be provided in a series structure of two or more stacked layers. In this case, each of the light-emitting elements ED may include a charge generation layer provided between the stacked layers. The charge generation layer may be provided on a common layer throughout the display area AA.

[0168] The cathode 143 can be formed by thinning a transparent electrode, such as indium tin oxide or indium zinc oxide, or a semi-reflective / semi-transparent electrode, such as silver, a silver alloy, magnesium, a magnesium alloy, ytterbium (Yb), or an ytterbium alloy. In another embodiment, the cathode 143 can be partially removed from the transmissive element or formed with a reduced thickness to increase the transmittance of the transmissive element. The cathode 143 can be a common layer provided in all sub-pixels SP to apply the same voltage. To this end, the cathode 143 can extend from the display area AA to a portion of the non-display area NA.

[0169] Cathode 143 can be a light-transmitting electrode. It can include a transparent conductive material (TCO), such as indium tin oxide or indium zinc oxide; or a translucent conductive material, such as magnesium, silver, or a magnesium-silver alloy, that transmits light. If cathode 143 is made of a translucent conductive material, luminous efficiency can be increased through microcavities.

[0170] As described above, a front-emitting light-emitting element has been described as an example of the light-emitting element ED. However, the present invention is not limited thereto, and the light-emitting element ED may be a rear-emitting light-emitting element in which light emitted from the intermediate layer 142 is emitted toward the substrate 111. In this case, the anode 141 may be made of a transparent or semi-transparent electrode material, while the cathode 143 may be made of a reflective electrode material.

[0171] The encapsulation layer 150 is disposed on the light-emitting element ED. The encapsulation layer 150 may cover the display area AA and the non-display area NA to prevent oxygen or moisture from penetrating into the light-emitting element ED. Other layers, such as a cover layer, may be inserted between the encapsulation layer 150 and the cathode 143 as needed.

[0172] Encapsulation layer 150 may include multiple layers. Encapsulation layer 150 may have a structure in which inorganic films including inorganic insulating materials and organic films including organic insulating materials are alternately stacked. For example, the inorganic insulating material may include one or more materials such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0173] The organic insulating material may include at least one selected from the group consisting of: polyethylene terephthalate; polyethylene naphthalate; polycarbonate; polyimide; polyethylene sulfonate; polyoxymethylene; polyarylate; and hexamethyldisiloxane.

[0174] A capping layer (not shown) may be further formed on the cathode 143 to protect the cathode 143 of the light emitting element ED and to increase light emitting efficiency in an upward direction.

[0175] In a transistor according to an embodiment of the present invention, an offset region can be provided in an area of ​​the active layer that does not overlap with the gate electrode along the channel width. The intrinsic region can be configured so that the center of the channel width is larger than its edges. This allows for further diffusion of dopants at the center of the channel width and maintains the area of ​​the active layer that overlaps with the gate electrode as the intrinsic region. Consequently, a transistor can be provided that prevents the effective channel length formed during ion doping using the gate electrode as a mask from varying along the width.

[0176] Transistors according to embodiments of the present invention offer the advantage of optimized manufacturing processes because the effective channel length can be controlled by adjusting the intrinsic region without adding additional manufacturing processes. Furthermore, increasing the intrinsic region can reduce the doping dose, thereby minimizing process impurities and eliminating detrimental process effects.

[0177] In the transistor according to the embodiment of the present invention, the change in the effective channel length of the transistor including the oxide semiconductor can be controlled, thereby improving the reliability of the transistor.

[0178] In a transistor according to an embodiment of the present invention, even if the transistor has a large channel width, changes in the effective channel length can be avoided or reduced, thereby avoiding or reducing threshold voltage variations. Therefore, when implementing a large-width transistor, the channel length margin can be minimized, enabling low-power operation compared to structures with a channel length margin.

[0179] The display device according to the embodiment of the present invention may include a wide-width transistor having device stability in a display area or a non-display area.

[0180] In the display device according to the embodiment of the present invention, the threshold voltage sensitivity caused by the variation of the channel width is reduced, thereby providing a high degree of design freedom, and a narrow frame is achieved by arranging high-power transistors in a non-display area with a small size.

[0181] The display device according to embodiments of the present invention has the advantages of controlling the variation in effective channel length and reducing threshold voltage sensitivity in wide-width transistors. This allows the use of small, high-power wide-width transistors, thereby reducing energy consumption and enabling the use of low-power devices. This also contributes to environmental sustainability and social well-being, achieving ESG (Environmental, Social, and Governance) goals.

[0182] A transistor according to one embodiment of the present invention may include: an active layer; a gate electrode having a region having a first length and a first width that overlaps with the active layer; and a gate insulating film disposed between the active layer and the gate electrode. The active layer may include an intrinsic region that protrudes from the center of the first width to a region that does not overlap with the gate electrode, rather than at the edge of the first width.

[0183] In the transistor according to an embodiment of the present invention, the intrinsic region may gradually decrease from the center of the first width toward the edge of the first width.

[0184] In a transistor according to an embodiment of the present invention, an intrinsic region of an active layer having an area that does not overlap with a gate electrode can be connected to an intrinsic region of an overlapping area, and the active layer can also have a doped region in an area that does not overlap with the gate electrode in addition to the intrinsic region.

[0185] The transistor according to one embodiment of the present invention may further include: a first source-drain electrode; and a second source-drain electrode, respectively connected to the doped regions of the active layer located on both sides of the gate electrode.

[0186] In a transistor according to an embodiment of the present invention, the channel length of the active layer may be maximum at the center of the first width and minimum at the edge of the first width.

[0187] In a transistor according to an embodiment of the present invention, the active layer may include an oxide semiconductor.

[0188] The transistor according to an embodiment of the present invention may further include a light-shielding metal disposed below the active layer, wherein the light-shielding metal continuously overlaps with the gate electrode and the intrinsic region in a region not overlapping with the gate electrode.

[0189] In a transistor according to an embodiment of the present invention, the same signal as that applied to the gate electrode may be applied to the light shielding metal.

[0190] In a transistor according to an embodiment of the present invention, the first width may be greater than or equal to the first length.

[0191] A display device according to one embodiment of the present invention may include: a substrate having a display area and a non-display area; a plurality of gate lines and a plurality of data lines intersecting each other in the display area, the plurality of gate lines and the plurality of data lines being configured to define a plurality of sub-pixels; a first transistor and a second transistor located in at least one of the plurality of sub-pixels; a light-emitting element connected to the second transistor; and a third transistor located in the non-display area. At least one of the first transistor, the second transistor, and the third transistor may include: an active layer; a gate electrode having a region overlapping with the active layer; and a gate insulating film disposed between the active layer and the gate electrode. The active layer may include an intrinsic region that protrudes from the center of the width of the overlapping region to the region not overlapping with the gate electrode, rather than the edge of the width of the overlapping region.

[0192] In the display device according to an embodiment of the present invention, the width of the active layer of the third transistor may be greater than the width of the active layer of each of the first transistor and the second transistor.

[0193] In a display device according to an embodiment of the present invention, the gate electrode may be connected to a gate line.

[0194] In a display device according to an embodiment of the present invention, an intrinsic region of an active layer having an area that does not overlap with a gate electrode can be connected to an intrinsic region of an overlapping area, and the active layer can also have a doped region in an area that does not overlap with the gate electrode in addition to the intrinsic region.

[0195] The display device according to one embodiment of the present invention may further include: a first source-drain electrode; and a second source-drain electrode, respectively connected to the doped regions of the active layer located on both sides of the gate electrode.

[0196] In a display device according to an embodiment of the present invention, the active layer may include an oxide semiconductor.

[0197] The display device according to an embodiment of the present invention may further include a light-shielding metal disposed below the active layer, wherein the light-shielding metal overlaps with the gate electrode and the intrinsic region in a region not overlapping with the gate electrode.

[0198] In a display device according to an embodiment of the present invention, the same signal as that applied to the gate electrode may be applied to the light shielding metal.

[0199] It should be clear from the above description that the transistor and the display device including the transistor according to an embodiment of the present invention have the following effects.

[0200] In a transistor according to an embodiment of the present invention, an offset region can be positioned in an area of ​​the active layer that does not overlap with the gate electrode along the channel width. The intrinsic region can be positioned so that the center of the channel width is larger than its edges, facilitating further diffusion of dopants at the center of the channel width while maintaining the active layer region that overlaps with the gate electrode as the intrinsic region. Consequently, a transistor can be provided that prevents the effective channel length formed during ion doping using the gate electrode as a mask from changing along the width direction.

[0201] Transistors according to embodiments of the present invention offer the advantage of optimized manufacturing processes because the effective channel length can be controlled by adjusting the intrinsic region without adding additional manufacturing processes. Furthermore, increasing the intrinsic region can reduce the doping dose, thereby minimizing process impurities and eliminating detrimental process effects.

[0202] In a transistor according to an embodiment of the present invention, changes in the effective channel length of the transistor containing an oxide semiconductor can be controlled, thereby improving the reliability of the transistor.

[0203] In a transistor according to an embodiment of the present invention, even if the transistor has a large channel width, changes in the effective channel length can be avoided or reduced, thereby avoiding or reducing changes in the threshold voltage. Therefore, when implementing a large-width transistor, the channel length margin can be minimized, enabling low-power operation compared to structures with a channel length margin.

[0204] The display device according to the embodiment of the present invention may include a wide-width transistor having device stability in a display area or a non-display area.

[0205] In the display device according to the embodiment of the present invention, the threshold voltage sensitivity caused by the variation of the channel width is reduced, thereby providing a high degree of design freedom, and a narrow frame is achieved by arranging high-power transistors in a non-display area with a small size.

[0206] The display device according to embodiments of the present invention has the advantage of controlling the variation in effective channel length and reducing threshold voltage sensitivity in wide-width transistors. This allows the use of small, high-power wide-width transistors, thereby reducing energy consumption and enabling the use of low-power devices. This improves environmental sustainability and social well-being, thereby achieving ESG (Environmental, Social, and Governance) goals.

[0207] Those skilled in the art will appreciate that various improvements and modifications may be made to the above description without departing from the technical concept of the present invention. Therefore, the technical scope of the present invention is defined by the following claims, rather than by the description of the present invention.

[0208] This application claims priority to Korean Patent Application No. 10-2024-0016643, filed on February 2, 2024, the entire contents of which are incorporated herein by reference.

[0209] 110: Display panel 111,SUB:Substrate 120: Insulation film 121: first insulating film 122: Second insulating film 123: Third insulating film 124: Fourth insulating film 125: Gate insulating film 126: Fifth insulating film 127: Sixth insulating film 129: Planarization film 135: Pixel definition film 141: Anode 142: Middle layer 143: cathode 150: Encapsulation layer 1000: Display device A1: The first active layer A2: Second active layer AA: Display Area ACT, ACT1: Active layer B:Light-shielding metal B1: First light-shielding metal B2: Second light-shielding metal BF: buffer layer C: Center CC: Compensation circuit Cst: Storage capacitor CT: Contact hole D: Drain electrode DL: Data Line DP: doped region E: Edge ED: Light Emitting Element EVDD: High potential drive voltage EVSS: common voltage G: Gate electrode G1: Gate electrode, first gate electrode G2: Gate electrode, second gate electrode GA: Gate electrode GI: Gate Insulator GL: Gate Line L: Length N1: first node NA: Non-display area OFM:Mask S: Source electrode SD11: First source-drain electrode SD12: Second source-drain electrode SD21: Third source-drain electrode SD22: Fourth source-drain electrode SP: Sub-Pixel T1: First transistor T2: Second transistor UDP, UDP1, UDP2, UDP3: intrinsic area W: width WTFT: Third transistor ΔL: Channel length reduction ΔLE: Extension length ΔM: Margin length

Claims

1. A display device, comprising: A substrate having a display area and a non-display area; a plurality of gate lines and a plurality of data lines intersecting each other in the display area, the plurality of gate lines and the plurality of data lines being configured to define a plurality of sub-pixels; a first transistor and a second transistor located in at least one of the plurality of sub-pixels; and a light-emitting element connected to the second transistor. The third transistor includes: an active layer; a gate electrode having an overlapping region with the active layer; and a gate insulating film located between the active layer and the gate electrode. The active layer has an intrinsic region protruding from a center of a width of the overlapping region to an edge of a non-overlapping region of the gate electrode, rather than the width of the overlapping region. The width of the overlapping region between the gate electrode and the active layer in the third transistor is greater than the width of an overlapping region between a gate electrode and an active layer in each of the first and second transistors.

2. The display device according to claim 1, wherein, In the third transistor, the intrinsic region gradually decreases from the center of the width of the overlapping region to the edge of the width of the overlapping region.

3. The display device according to claim 1, wherein: The intrinsic region of the active layer having a region that does not overlap with the gate electrode is connected to the intrinsic region of the overlapping region, and the active layer has a doped region in the region that does not overlap with the gate electrode in addition to the intrinsic region.

4. The display device according to claim 1, further comprising: A first source-drain electrode and a second source-drain electrode are respectively connected to the doped regions of the active layer located on both sides of the gate electrode.

5. The display device according to claim 1, wherein, The length of a channel in the active layer is maximum at the center of the width and minimum at the edge of the width.

6. The display device according to claim 1, wherein, The active layer comprises an oxide semiconductor.

7. The display device according to claim 1, further comprising: A light-shielding metal is disposed below the active layer, and the light-shielding metal continuously overlaps with the gate electrode and the intrinsic region located in the region that does not overlap with the gate electrode.

8. The display device according to claim 7, wherein, The same signal applied to the gate electrode is applied to the light-shielding metal.

9. The display device according to claim 1, wherein, The first transistor is a switching transistor, and the second transistor is a driving transistor, wherein the first transistor has an active layer that is contained in an intrinsic region outside the overlapping region between the gate electrode and the active layer.

10. The display device according to claim 9, wherein, The gate electrode of the first transistor is connected to one of the plurality of gate lines.

11. The display device according to claim 1, wherein, The active layer of at least one of the first transistor and the second transistor comprises an oxide semiconductor.

12. The display device according to claim 1, further comprising: A light-shielding metal is disposed below the active layer of at least one of the first transistor and the second transistor, and the light-shielding metal overlaps with the gate electrode and the intrinsic region located in the region that does not overlap with the gate electrode.

13. The display device according to claim 12, wherein, The same signal applied to the gate electrode is applied to the light-shielding metal.

14. The display device according to claim 1, wherein, The first transistor includes: a first light-shielding metal located on the substrate; a first active layer overlapping the first light-shielding metal; and a first gate electrode overlapping an intrinsic region of the first active layer. The second transistor includes: a second light-shielding metal located on the substrate; a second active layer overlapping the second light-shielding metal; and a second gate electrode overlapping an intrinsic region of the second active layer. The first light-shielding metal is continuously overlapped between the first gate electrode and the intrinsic region located in a non-overlapping region with the first gate electrode.

15. The display device according to claim 14, wherein: The second transistor further includes a first electrode and a second electrode connected to the doped regions of the second active layer located on both sides of the second gate electrode, and wherein the second light-shielding metal is electrically coupled to the first electrode and the second active layer.

16. The display device according to claim 14, wherein, The first active layer and the second active layer are disposed on the same layer, and the first light-shielding metal and the second light-shielding metal are disposed on different layers.

17. The display device according to claim 14, wherein, The first gate electrode is electrically coupled to the first light-shielding metal.

Images