Method and apparatus for SAR analog-to-digital conversion

Abstract

A sequential approximation register (SAR) analog-to-digital converter (ADC) can be used to generate an N-bit first digital data and an N-bit second digital data of analog data. When the second digital data and the first digital data contain a first most significant bit (MSB) sequence with the same value, the SAR ADC can be used in a partial mode to generate an N-bit third digital data of the analog data. In this partial mode, the SAR ADC is configured to skip determining the second MSB sequence of the third digital data and only determine the remaining bits of the third digital data. When the second digital data and the first digital data do not contain the first MSB sequence with the same value, the SAR ADC operates in a full mode to determine each bit of the N-bit third digital data.

Description

[Technical Field]

[0001] The present invention generally relates to the field of analog-to-digital conversion, and in a particular embodiment, to a method and apparatus for analog-to-digital conversion of a Continuous Approximate Register (SAR). [Previous Technology]

[0002] Analog-to-digital converters (ADCs) are commonly used in digital electronic systems to convert analog signals into digital signals. The digital signals can then be further processed by various digital processors, such as digital audio processors, digital video processors, wireless communication processors, and the like.

[0003] In some applications, an ADC can be implemented as a standalone semiconductor device, while in others, it can be integrated with other circuit systems onto a single integrated circuit. Although various analog digital architectures can be used, Continuous Approximation Register (SAR) ADCs are widely used in a variety of applications, such as battery-powered instruments, digital pens, industrial control, multiplexing data acquisition, and so on. SAR ADCs perform a continuous approximation algorithm (or sometimes referred to as a "binary search algorithm") to output a digital signal. The SAR architecture offers moderate sampling rates, moderate resolution, high efficiency, and low power consumption. [Summary of the Invention]

[0004] Technical advantages are generally achieved by describing embodiments of the present invention of a method and apparatus for analog-to-digital conversion of consecutive approximate registers.

[0005] According to one aspect of the present invention, a method is provided comprising: generating a first digital data of N bits and a second digital data of N bits of an analog voltage by using a continuous approximation register (SAR) analog-to-digital converter (ADC), wherein N is an integer greater than 1; and when it is determined that the second digital data and the first digital data contain a first most significant bit (MSB) sequence having the same value, using the SAR ADC in a certain mode to generate a third digital data of N bits of the analog data, wherein the SAR ADC is configured to skip determining (a few) values ​​of the second MSB sequence of the third digital data.

[0006] According to another aspect of the present invention, a method is provided, comprising: generating a first digital data and a second digital data of analog data by using a continuous approximation register (SAR) analog-to-digital converter (ADC), the first digital data and the second digital data each having N bits; determining whether the second digital data contains a first bit sequence having the same value as the first bit sequence of the first digital data, the first bit sequence starting from a first most significant bit (MSB); when the second digital data contains a first bit sequence having the same value as the first bit sequence of the first digital data, determining whether to use the SAR based on whether a condition is met. The ADC generates one of the N bits of analog data as third digital data in a partial mode; and when the condition is met, the third digital data is generated in the partial mode, the generation including: setting the second bit sequence of the third digital data to the values ​​of the second bit sequence of the second digital data using the values ​​of the second bit sequence of the second digital data, the second bit sequence starting from the first MSB and including less than N bits; and using the SAR ADC to determine the values ​​of the remaining bits of the third digital data.

Implementation Method

[0018] Cross-Reference to Related Applications This patent application claims priority to and is a continuation of U.S. Application No. 18 / 669,304, filed May 20, 2024, entitled “Method and Apparatus for SAR Analog-to-Digital Conversion,” which is hereby incorporated herein by reference as if reproduced in its entirety.

[0019] The following describes in detail the making and use of embodiments of the present invention. However, it should be understood that the concepts disclosed herein may be embodied in various specific texts, and the specific embodiments discussed herein are for illustrative purposes only and are not intended to limit the scope of the claims. Furthermore, it should be understood that various changes, substitutions, and modifications may be made to this document without departing from the spirit and scope of the invention as defined by the appended claims.

[0020] Furthermore, features from one or more of the embodiments described below may be combined to produce alternative embodiments not explicitly described, and features suitable for such combinations are understood within the scope of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

[0021] Continuous Approximate Register (SAR) analog-to-digital converters (ADCs) are widely used in various applications requiring moderate conversion speeds and resolutions, such as monitoring environments, data acquisition, or applications involving frequencies below the conversion frequency. SAR ADCs require less power in green energy applications.

[0022] Figure 1 is a schematic block diagram of a conventional SAR ADC 100. The SAR ADC 100 is configured to sample an analog signal and convert it into a digital signal, wherein each sampled value of the analog signal is converted into a digital value of N bits. Specifically, the SAR ADC 100 is configured to sample an input analog voltage (or value or data) VIN of the analog signal and convert it into an N-bit digital signal / data / value DOUT. The SAR ADC 100 may be referred to as an N-bit SAR ADC and has a resolution of N bits. N is an integer greater than 1. For example, N can be 4, 8, 12, etc.

[0023] In the illustrated example, the SAR ADC 100 includes a sample-and-hold (S / H) circuit 102, a comparator 104, a digital-to-analog converter (DAC) 106, a SAR block / circuit 108, and a clock block / circuit 110. The operation of the SAR ADC 100 typically includes a sampling stage and a conversion stage. In the sampling stage, the SAR ADC 100 samples the analog voltage VIN to obtain and hold a sampled analog value. In the conversion stage, the SAR ADC 100 converts the sampled analog value into an N-bit digital value.

[0024] Specifically, the S / H circuit 102 is configured to sample the analog voltage VIN to obtain a sampled analog value VSH and stores the sampled value VSH for use in the conversion stage. The terms "sampled analog value" and "sampled value" are used interchangeably herein. The S / H circuit 102 is coupled to comparator 104 and outputs the sampled value VSH to comparator 104.

[0025] Comparator 104 is an analog comparator configured to compare the output of S / H circuit 102 (i.e., the sampled value VSH) with an analog threshold value VDAC generated by DAC 106 based on a reference voltage VREF. Depending on the comparison performed by comparator 104, the output of comparator 104 can be 1 or 0. The output of comparator 104 is passed to SAR block 108 as a value of the current bit, which is converted, temporarily stored, and processed by SAR block 108. SAR block 108 controls the value of the threshold value VDAC generated by DAC 106 and outputs the converted digital value of the sampled analog value of the input analog signal VIN. The output of SAR block 108 is the N-bit digital signal DOUT of the input analog signal VIN. Clock block 110 provides a clock signal for the operation of S / H circuit 102 and SAR block 108. The threshold value VDAC used to determine a bit (which is currently being converted) is determined based on the reference voltage VREF and (some) previously determined bits.

[0026] Through a binary search procedure, the N bits of the digital value converted from the sampled value VSH are determined one by one in the order from the most significant bit (MSB) to the least significant bit (LSB) (e.g., from bit N to bit 1 (which can also be referred to as: from bit (N-1) to bit 0, from bit N to bit 1, from bit (N-1) to bit 0, based on various naming rules)). A SAR ADC typically requires one clock cycle to sample the input analog voltage to obtain a sampled value, and one clock cycle to determine the bits of its digital output corresponding to the sampled value. Therefore, an N-bit SAR ADC typically requires (N+1) clock cycles to digitize the sampled analog value into an N-bit digital value. Therefore, for a sampled value, the conversion time of an N-bit SAR ADC is (N+1) clock cycles. Therefore, the conversion rate is f / (N+1), where f is the clock signal frequency. The clock cycle can also refer to a switching cycle during which one bit of an N-bit digital value is determined.

[0027] Figure 200 illustrates an example conversion operation of a SAR ADC 100 with N=4. The horizontal axis represents time and the vertical axis represents voltage. Waveform 210 shows the threshold value VDAC determined for each bit. Line 220 (dashed line) shows the sampled analog value VSH (VIN). Four (4) clock cycles are used to determine the 4 bits of the digital value converted for the sampled analog value VSH. The binary search algorithm begins by determining the MSB (or the first MSB of 4 bits) of the sampled value VSH, i.e., bit 4. To determine the first MSB, the SAR ADC 100 generates a threshold value VDAC equal to half of a full-scale value (reference signal VREF) (i.e., VDAC = (VREF / 2)) and compares the sampled value VSH with the threshold value VDAC. Depending on the result of this comparison, the MSB (bit 4) is determined. For example, when V SH < V DAC, MSB is 0, and when V SH ≥ V DAC, MSB is 1. In this example, V SH < V DAC, that is, V SH < (V REF / 2), so bit 4 = 0.

[0028] To determine the next valid bit (second MSB) (i.e., bit 3), the SAR ADC 100 generates another threshold value V DAC = (V REF / 4) based on the previous comparison result of bit 4, since the previous comparison revealed that the sampled value is between 0 and (V REF / 2). The SAR ADC 100 then compares the sampled value V SH with this threshold value V DAC = (V REF / 4). Since V SH > V DAC (i.e., V SH > (V REF / 4)), bit 3 = 1.

[0029] For the next valid bit (i.e., bit 2), the SAR ADC 100 similarly generates another threshold value based on the previous comparison of bit 3. In this case, since the previous comparison revealed that the sampled value is between (V REF / 4) and (V REF / 2), the threshold value is set to V DAC = (3 / 8V REF). Because V SH < V DAC (i.e., V SH < (3 / 8V REF)), bit 2 = 0. This procedure continues until all four bits of the digital output are determined. For bit 1, V DAC = (5 / 16V REF) and bit 1 = 1. Therefore, the output digital value is 0101. Waveform 210 shows the different threshold values ​​used to determine the four bits.

[0030] The S / H circuit 102 and DAC 106 of the SAR ADC 100 can be implemented using a binary weighted capacitor array, which can be referred to as a capacitive DAC. For an N-bit SAR ADC, a capacitive DAC may comprise an array of N capacitors having binary weighted capacitance values ​​plus a "dummy LSB" capacitor. Figure 3 is a diagram of an exemplary circuit 300 for this implementation of the 4-bit SAR ADC described in Figure 2. As shown, circuit 300 includes a 4-bit capacitive DAC 310 connected to comparator 104. The capacitive DAC 310 includes four capacitors 312, 314, 316, and 318 having binary weighted capacitance values ​​(i.e., 8C, 4C, 2C, C) and a dummy LSB capacitor 320 having capacitance C. These capacitors are connected in parallel such that the total capacitance of the five capacitors 312 to 320 is equal to 16C. Each capacitor has a first terminal connected to a first terminal (e.g., the negative terminal) of comparator 104 and a second terminal coupled to an analog input voltage VIN, a reference voltage VREF, or ground via a switch (e.g., single-pole three-throw switches S1 to S5). The first terminals of capacitors 312 to 320 can be collectively referred to as a common terminal T1 of the capacitors (which is also a first terminal of comparator 104). A second terminal (positive terminal) T2 of comparator 104 is coupled to ground. That is, VT2 = 0. Capacitors 312, 314, 316, and 318 can be designated as corresponding to bits 4 to 1 of the output digital value, respectively. A switch S0 is connected between terminals T1 and T2. Switch S0 is used to control the switching between the sampling stage and the conversion stage.

[0031] During the sampling phase, switch S0 is closed, the common terminal T1 of the capacitors is connected to ground, and the second terminals of capacitors 312 to 318 are connected to the analog input voltage (VIN). Therefore, the analog input voltage is sampled onto capacitors 312 to 318 in the capacitor array, for example, a charge VSH is stored in the capacitor array.

[0032] During the transition phase, S0 is open, meaning the common terminal T1 is disconnected from ground, and the second terminals of capacitors 312 to 318 are disconnected from VIN. Connecting the lower plates of capacitors 312 to 318 to VREF or ground causes a redistribution of charge between the capacitors. This redistribution of charge will change the voltage appearing at the common terminal T1, i.e., the comparator input at the negative terminal of comparator 104.

[0033] During the conversion phase, in order to execute the binary search algorithm, capacitors 312 to 318 are first connected to ground. In this case, a voltage equal to -VSH will appear at the common terminal T1, i.e., VT1 = -VSH. During the first clock cycle used to determine the first MSB (i.e., bit 4 in this example), the lower plate of capacitor 312 (8C) (also referred to as the first MSB capacitor) is disconnected from ground and connected to VREF. This causes the voltage at the common terminal T1 to become VT1 = -VSH + VREF / 2. That is, VDAC = VREF / 2.

[0034] Comparator 104 compares VT1 with VT2 (i.e., 0 V), which is equivalent to comparing the sampled value VSH with the threshold value VREF / 2 (see Figure 2 for an example). The result of this comparison determines the first MSB value. This result also determines whether the first MSB capacitor 312 should be connected to VREF (when bit 4=1) or grounded (when bit 4=0) during the remaining time of the transition phase used to determine the remaining bits. If VT1 < 0 (i.e., VSH > VREF / 2), then comparator 104 outputs a logic 1, i.e., bit 4=1. If VT1 > 0 (i.e., VSH < VREF / 2), then comparator 104 outputs a logic 0, i.e., bit 4=0. If comparator 104 outputs a logic 1, then the lower plate of the first MSB capacitor 312 remains connected to VREF during the determination of the remaining valid bits. If comparator 104 outputs logic 0, the lower plate of the first MSB capacitor 312 is connected back to ground during the determination of the remaining valid bits. Taking the example illustrated in Figure 2, bit 4 = 0, and therefore the second terminal of capacitor 312 is connected to ground for the remaining time of the transition phase from bit 3 to bit 1.

[0035] In the second clock cycle used to determine the second MSB (i.e., bit 3), the corresponding capacitor (i.e., capacitor 314) is connected to VREF, which is equivalent to setting VDAC to VREF / 4 in the second clock cycle. This will increase the voltage VT1 at the common terminal by VREF / 4, i.e., VT1 = -VSH + 1 / 4 × VREF. Comparator 104 compares VT1 with zero (0) (or VT2) to determine the value of bit 3. Based on the comparison result, it is also determined whether capacitor 314 will be connected to VREF or ground for the remaining time of the transition phase. This procedure continues until all bits of the digital value are determined. Taking the example illustrated in FIG2, bit 4 is first determined to be 0 in the first clock cycle, and therefore capacitor 312 is connected to ground for the remaining time of the transition phase. Then, bit 3 is determined to be 1 in the second clock cycle, and capacitor 314 is connected to VREF for the remaining time of the transition phase. In the third clock cycle, decision bit 2 = 0, and capacitor 316 is connected to ground for the remainder of the transition phase. In the fourth clock cycle, decision bit 1 = 1.

[0036] Generally, the above-described procedure for digitizing a sampled analog value can be executed multiple times to obtain multiple N-bit digital values ​​of the input analog voltage, which are then processed to obtain a final N-bit digital value of the analog voltage. For example, the average of the multiple digital values ​​can be used as the final digital value for the input analog voltage conversion.

[0037] Figure 4 is a flowchart of an exemplary method 400 for performing SAR analog-to-digital (A / D) conversion using a SAR ADC (e.g., SAR ADC 100). In this example, the SAR ADC can be pre-configured to obtain M digital values ​​of an input analog voltage by performing M A / D conversions, where M is a positive integer greater than 1. In this invention, each of the M A / D conversions can refer to an ADC cycle. As shown, method 400 can begin at block 402, where a SAR A / D conversion can be started or configured to perform an A / D conversion on an input analog voltage. The SAR ADC can sample the input analog voltage to obtain and hold a sampled value VSH (block 404). The SAR ADC can then perform an N-bit A / D conversion on the sampled value VSH to obtain a digital value Dm (N:1) (block 406), where m is an integer and m = 1, 2, ..., M. (N:1) indicates that the digital value Dm has N bits, where N is the MSB and 1 is the LSB. The SAR ADC can then store the acquired digital value Dm(N:1) (block 408) and determine whether M digital values ​​have been generated or whether M conversions have been completed (block 410). For example, if m < M (i.e., the SAR ADC has not yet generated M digital values ​​of the input analog value), the SAR ADC proceeds to block 404 to perform the next N-bit A / D conversion, where the SAR ADC resamples the input analog voltage and performs an A / D conversion to generate another digital value. If m = M, the SAR ADC can process the acquired M digital values ​​D1, D2, ..., DM to obtain an N-bit digital output D(N:1) (block 412). D(N:1) is the converted digital value of the analog value output by the SAR ADC.

[0038] As described above, in one ADC cycle, an N-bit SAR ADC requires one clock cycle to perform sampling and N clock cycles to determine the N bits of a digital value; that is, one ADC cycle contains (1+N) clock cycles. To generate M digital values ​​of an analog value, an N-bit SAR ADC requires M(1+N) clock cycles. The conversion rate R of an N-bit SAR ADC used to convert an analog value to a digital value can be approximately expressed as: R=f / (M+M×N), where f is the frequency of the clock signal. Therefore, the conversion rate of an N-bit SAR ADC is relatively low. To improve the conversion rate and reduce the conversion time (improving the conversion rate), some existing techniques use higher frequencies or a combination of two types of ADCs to perform A / D conversion, such as a combination of a flash ADC and a SAR ADC or a sub-range ADC and a SAR ADC. A disadvantage is that these methods result in higher current consumption and require complex algorithms.

[0039] Embodiments of the present invention provide a mechanism / technique for SAR A / D conversion. This mechanism improves the conversion rate and reduces the current consumption of a SAR ADC while maintaining the required resolution. This mechanism can be applied to perform multiple SAR A / D conversions to obtain a digital value / data of an analog-to-digital ratio / data / voltage. In some embodiments, the mechanism can modify the SAR ADC operation flow in a later ADC cycle based on measurements of ADC output data obtained in an earlier ADC cycle, and control the conversion cycle in the conversion phase of the later ADC cycle. Specifically, the mechanism can control and change the number of comparisons (i.e., the number of clock cycles) required in the conversion phase of a later ADC cycle to obtain a converted digital value. Therefore, the number of clock cycles in the conversion phase can be reduced, thus reducing conversion time and improving the conversion rate. Using this mechanism, the conversion rate of the SAR ADC can be increased by, for example, about 20% to 30% compared to conventional SAR ADC methods. This mechanism can provide a higher conversion rate (or conversion frequency) and an increased ADC bandwidth. This mechanism can be implemented based on an existing SAR ADC architecture (such as the circuit in Figure 1), with the addition of some simple and low-cost circuits / operations (such as a data comparison circuit) and an addition operation.

[0040] As used herein for illustrative purposes, the N bits of a bit value are represented in order from MSB to LSB as bit N, bit (N-1), bit (N-2), ..., bit 2, bit 1. They may also be represented as bit (N-1), bit (N-2), ..., bit 1, bit 0, or in other applicable manner. As used herein for illustrative purposes, bit N may also refer to the first MSB, bit (N-1) may also refer to the second MSB, and so on. Bit 1 may also refer to the first LSB, bit 2 may also refer to the second LSB, and so on.

[0041] In some embodiments, an N-bit SAR ADC can operate in two conversion modes: a full mode and a partial mode. In full mode, the N-bit SAR ADC operates similarly to a conventional SAR ADC, determining N bits of a digit value one by one from MSB to LSB, and N clock cycles are used to determine the N bits. In partial mode, the N-bit SAR ADC only needs to determine a portion of the N bits (e.g., K bits from bit K to bit 1), where K < N, and the remaining bits (i.e., bits N to K+1) are set using values ​​based on previous conversions in (several) previous ADC cycles. A portion comprises a sequence of consecutive bits from bit K to bit 1; that is, when a portion comprises K bits, the portion comprises bit K, bit K-1, bit K-2, ..., bit 1. The remaining bits also comprise a sequence of consecutive bits from bit N to bit K+1. In this partial mode, only K clock cycles are used. The partial mode requires fewer clock cycles during the transition phase than the full mode. K can refer to the mode resolution of one of the partial modes, and K can be pre-configured and adjusted. The N-bit SAR ADC can switch between the two modes based on whether certain pre-configuration conditions are met, as described below.

[0042] In some embodiments, SAR A / D conversion can be performed in full mode to obtain one or more digital values ​​of an input analog value, based on which the value of one or more valid bits of the higher bits can be determined and fixed, and SAR A / D conversion can be performed in partial mode in a later ADC cycle to determine only the value of the remaining valid bits of the lower bits, thereby reducing the number of conversion cycles required in the later ADC cycle.

[0043] Figure 5 is a flowchart of an exemplary method 500 for N-bit SAR A / D conversion according to an embodiment of the present invention. Method 500 can be performed using a SAR ADC described in an embodiment of the present invention. In method 500, for an analog value / voltage, M (valid) N-bit digital values ​​D1, D2, ..., DM can be generated, for example, by performing M (valid) SAR A / D conversions (also referred to as M conversions) in M ​​ADC cycles. In the generation of each of the M digital values ​​(i.e., in each of the M SAR A / D conversions), the input analog voltage is sampled to obtain a sampled analog value, and the sampled analog value is converted into an N-bit digital value. For each of the M SAR A / D conversions, a full mode or a partial mode can be selected to determine the corresponding output digital value. For ease of illustration, the sampling / holding block / step is omitted in the following description and related illustrations. Sampling / holding can be performed before each A / D conversion to obtain a sampled analog value. For example, sampling / holding can be performed before or after selecting a conversion mode. As used herein, the terms "digital value" and "digital data" are used interchangeably. M is an integer greater than 1, for example, M can be 8, 10, 15, etc. A valid SAR A / D conversion refers to a SAR A / D conversion that results in an N-bit value falling within a valid data range. For example, an N-bit digital value containing N "1"s or "0"s is invalid. Method 500 can be performed in one of the following cases where M valid SAR A / D conversions are required (resulting in M ​​valid digital values) or in one of the following cases where M SAR A / D conversions are required (resulting in less than or equal to M valid digital values).

[0044] Method 500 begins at block 502, for example, when a SAR A / D conversion is initiated. A conversion mode (full or partial) can be selected for the SAR A / D conversion of an input analog voltage (block 504). In one embodiment, to allow the first or first few conversions of M conversions to be performed by the SAR ADC (or to generate the first or first few bit values), the full mode can always be selected and performed, i.e., performing an N-bit SAR ADC conversion. All N bits of the bit value are determined one by one in the N conversion cycles (or clock cycles) used for the first conversion. Selecting the full mode for the first conversion (or the first few conversions) can produce (some) more accurate bit values ​​as an initial estimate. In another embodiment, a partial mode can be selected and performed for the first or first few conversions, wherein only K consecutive LSBs (i.e., bit K, bit K-1, ..., bit 1) starting from bit 1 are determined. K can be pre-configured. The (NK) MSBs can be predetermined or known. In another instance, a lower-resolution A / D conversion can be performed for the first conversion or the first few conversions, for example, performing (several) S-bit SAR A / D conversions, where S < N. This approach is suitable when lower resolution is acceptable and shorter conversion times are more critical.

[0045] Based on the selected full mode, an N-bit SAR A / D conversion can then be performed using a SAR ADC (block 506). For the first conversion, an N-bit digital data D1(N:1) (i.e., Dm(N:1), where m=1) is generated by determining N bits one by one as described above for one sample analog value of the input analog voltage. As used herein, Dm(N:1) may also refer to Dm. (N:1) indicates that the digital value D1 has N bits, where bit N is the first MSB and bit 1 is the first LSB. S represents the number of bits converted by the SAR ADC, which is also the number of conversion cycles (clock cycles) used to determine the S bits. In this case, S=N. The N-bit digital data D1(N:1) is stored in a register for later processing (block 508).

[0046] In some embodiments, a validity check may be performed to determine whether the currently generated digital data is valid (block 510), for example, checking whether the digital data exceeds a data range. For example, the currently generated digital data D1(N:1) may be checked to determine whether it has an overflow (i.e., it contains all 1s) or an underflow (i.e., it contains all 0s). When D1(N:1) is determined to be invalid (e.g., it has an overflow or underflow), D1(N:1) may be marked as invalid (block 512), and method 500 returns to block 504, where an N-bit SAR A / D performs a conversion in full mode to regenerate D1(N:1). This may be referred to as "regeneration after invalidation". When digital data is marked as invalid, a signal (e.g., a control signal or a mode signal) may be generated to indicate whether full mode or partial mode is available for regeneration after invalidation. In some embodiments, a rule may be configured to specify which mode is used for regeneration after invalidation. As an example, the rule may specify that the same mode is available for regeneration after invalidation. As another example, if a partial mode was previously used, the rule can specify that a full mode can be used for regeneration after invalidation. Various rules and combinations can be configured. Invalidating digital data can include deleting the digital data in the register.

[0047] When it is determined that the currently generated digital data is valid, method 500 may determine whether M conversions have been completed or whether M digital values ​​have been generated (block 514). The M conversions in this document may refer to M valid conversions, in which M valid digital values ​​have been generated for the input analog voltage. When no invalid digital values ​​are generated, the number of conversions performed is equal to the number of digital values ​​generated. Otherwise, when (a number of) invalid digital values ​​are generated, the number of conversions performed will be greater than the number of digital values ​​generated to generate the required number of digital values. In one example, a counter with an initial value of zero (0) can be used to count the number of valid conversions performed or the number of valid digital values ​​generated. The counter may increment by 1 each time a valid digital value Dm (N:1) is generated. When m increments to equal M, method 500 may terminate (block 532).

[0048] When m < M (i.e., no M valid bit values ​​are obtained), method 500 can determine whether one of the previously generated bit values ​​of the input analog voltage (i.e., Dm-1(N:1)) is available (block 516). When the currently generated bit value is D1 (m=1) (i.e., the previously generated bit value is unavailable), method 500 proceeds to block 504 to perform the next N-bit SAR A / D conversion (second conversion) in full mode to generate D2(N:1), which can then be stored in a register. The second bit data D2 can also be generated in partial mode at a pre-configured resolution less than N.

[0049] When a previously generated bit value is available, method 500 compares the currently generated bit value Dm(N:1) with the previously generated bit value Dm-1(N:1) (block 518). Based on the comparison result, method 500 determines whether Dm has one or more consecutive valid bits starting from the first MSB, the corresponding value of which is the same as the value of Dm-1 (block 520). That is, method 500 determines whether there exists a bit sequence in Dm starting from the first MSB that has the same value as the bit sequence in Dm-1.

[0050] In some embodiments, the bit values ​​of Dm and Dm-1 can be compared starting from bit N. As an example, the values ​​of the first MSB (i.e., bit N) corresponding to Dm and Dm-1 can be compared, and if the values ​​are the same, the values ​​of the second MSB (bit N-1) corresponding to Dm and Dm-1 can be compared. If the values ​​of the second MSB (i.e., bit N-1) corresponding to Dm and Dm-1 are the same, the values ​​of the third MSB (i.e., bit N-2) corresponding to Dm and Dm-1 can be compared. This comparison can continue until a value is found to be different at a bit position (e.g., bit (NL)) corresponding to Dm and Dm-1. That is, the values ​​of bits N to (N-L+1) corresponding to Dm and Dm-1 are the same. In other words, the values ​​of the first L MSBs of Dm are the same as the values ​​of the first L MSBs of Dm-1. L is an integer and 1≤L≤N. The number of comparisons found is L. In the following text, the case of "a value of bit q in Dm is the same as a value of bit q in Dm-1" can also refer to "bit q in Dm is the same as bit q in Dm-1" or "Dm and Dm-1 have the same bit q".

[0051] Table 1 below shows an example of a digital value Dm (m=1, 2, ... M) generated for an input analog voltage, where M=5 and N=12. Table 1 will be used as an example below to illustrate embodiment method 500. Table 1 also shows the value of L of the generated digital value Dm. As an example, in Table 1, comparing D1 and D2, the first 5 MSBs (L=5) of D1 and D2 are the same (i.e., bits 12 to 8): 10110. Table 1 Number of digit values digit value L D1 1011 0110 1101 n / a D2 1011 0011 1011 5 D3 1011 0001 1010 6 D4 1011 0001 0101 8 D5 1011 0001 0111 10

[0052] If the N-bit value of Dm is not the same as the N-bit value of Dm-1, then method 500 proceeds to block 504, selects full mode and performs an N-bit SAR A / D conversion to generate the next bit value, such as D3(N:1). When no matching bits are found in Dm and Dm-1, full mode can be selected for the next ADC cycle to obtain an accurate conversion for subsequent comparison.

[0053] When Dm and Dm-1 (e.g., D1 and D2) have the same first L MSBs (i.e., bits N to (N-L+1)), method 500 then determines whether L is greater than a threshold value W (block 522). In some embodiments, the SAR ADC bandwidth can be set to approximately four (4) times the bandwidth of the input analog signal. Therefore, the maximum signal drift (error) is approximately 1 / 4 of the full scale, and W can be set to N / 4. W can be configured based on other considerations and applications.

[0054] If L < W, then method 500 returns to block 504 to generate the next bit value in full mode. In this case, one consideration is that since only the number of MSBs less than the threshold value W are the same, full mode is used again to generate a more accurate conversion. If L ≥ W, then method 500 may recommend partial mode for the next conversion (in the next ADC cycle) (block 524). The mode resolution K of the partial mode can be set (block 526), ​​where K < N. The mode resolution K (i.e., the number of bits determined by the SAR A / D conversion (i.e., K LSBs starting from bit 1)) can be preconfigured and configurable. In some embodiments, K can be set based on a predefined rule, for example, K can depend on any combination of N, W, and L detected in the current ADC cycle. As an example, K = N - L + 1. As another example, K = N - (LW) + 2. As yet another example, K can be a preconfiguration constant. As another example, starting from bit (N-L+1) to bit N, if bit Q is found to be the first bit with a value of zero (0), then K can be set to Q, that is, K=Q.

[0055] Using the example shown in Table 1, D1 and D2 have the same first 5 MSBs (from bit 12 to bit 8), i.e., 10110, L=5, W=N / 4=3. Therefore, since L>W, method 500 can recommend using a partial mode to perform the next transformation (third transformation) to produce the digital value D3. For example, K can be set to K=N-L+1=8, so for the third transformation, a partial mode can be performed only on K LSBs (i.e., bits 8 to 1) of D3 determined using the SAR ADC. Bits 12 to 9 of D3 can be set to have the same values ​​as their counterparts in D2.

[0056] Method 500 may determine whether a partial pattern is allowed for the next conversion (block 528). This step may be optional. This step may be based on a configuration or condition. The configuration may be set based on needs or applications (block 530). The configuration may be preset and adjustable. In one embodiment, the configuration may allow a partial pattern for the next conversion after a recommended partial pattern has been selected. In another embodiment, the configuration may allow a partial pattern for the next conversion after a preset number of recommended partial patterns have been selected. In another embodiment, the configuration may allow a partial pattern for the next conversion after a recommended partial pattern has been selected and after a preset number of valid digit values ​​have been generated. In another embodiment, the configuration may allow a partial pattern for the next conversion after a recommended partial pattern has been selected and after a preset number of full pattern conversions have been performed. Other applicable conditions / rules may also be used to set the configuration to specify whether a partial pattern is allowed for the next conversion. In some embodiments, for example, one or more of the rules described above may be combined to set the configuration. Those skilled in the art will recognize various embodiments, variations, and modifications for setting the configuration.

[0057] When it is determined that a partial mode is not allowed to be used for the next conversion, method 500 returns to block 504, where the full mode is selected to generate the next digit value D3.

[0058] When it is determined that partial mode is allowed for the next conversion, method 500 switches to partial mode (block 504) and performs a SAR A / D conversion in partial mode (block 532). Using Table 1 above as an example, in partial mode, K=8, the SAR ADC only determines the last 8 bits of D3 (bits 8 to 1), and bits 12 to 9 of D3 are assigned the value 1011, which is the same as the respective values ​​of bits 12 to 9 of D2. That is, the N-bit SAR ADC performs A / D conversion only for K LSBs, where (NK) MSBs are set to the same value as D2, which can be referred to as a K-bit partial SAR A / D conversion or a K-bit partial conversion. In an exemplary implementation (refer to Figure 2), for 1011, the corresponding capacitors for bits 12, 10, and 9 are connected to the reference voltage / bus, and the corresponding capacitor for bit 11 is connected to ground. Next, the SAR ADC performs an 8-bit SAR A / D conversion to determine the remaining 8 bits (bits 8 to 1) one by one, starting from bit 8. Therefore, for the third conversion, the SAR ADC only needs 8 clock cycles to determine 8 bits. The resulting N-bit value system in some modes is: Dm(N:1) = Dm-1(N:K+1) + Dm(K:1). That is, for Dm(N:1), its bits N to K+1 have the same values ​​as their counterparts in Dm-1(N:1), and its bits K to K1 have the values ​​determined by the SAR ADC during the current conversion. In the example in Table 1, D3(12:1) = D2(12:9) + D3(8:1). D3 can then be stored in a register (block 508). Method 500 then proceeds to block 510 to check if the generated digital value D3 is valid, and method 500 continues as previously described.

[0059] As shown in the examples in Table 1, since the first 6 MSBs (bits 12 to 7) of D3 are the same as the MSB of D2 (i.e., L=6), partial mode is recommended for the 4th conversion. If partial mode is allowed, D4 can be generated in partial mode by performing a K-bit partial conversion, where D4=D3(N:K+1)+D4(K:1). In this case, K=N-L+1=7 and D4(12:1)=D3(12:8)+D4(7:1). That is, during the 4th conversion, only 7 clock cycles are used instead of 12 clock cycles to obtain D4.

[0060] Similarly, as shown in Table 1, the first 8 MSBs of D4 are the same as those of D3 (i.e., L=8), and partial mode is recommended for the 5th conversion. If partial mode is allowed, D5 can be generated in partial mode by performing a K-bit partial conversion, where D5(12:1) = D4(N:K+1) + D5(K:1). If K=N-L+1=5, then D4=D3(12:6) + D4(5:1). That is, only 5 clock cycles are needed / used to obtain D5 during the 5th conversion. If only 5 significant digit values ​​(D1 to D5) are needed for the input analog voltage, then method 500 ends here. The register can output 5 digit values ​​D1 to D5, which can be processed to produce a digit output corresponding to one of the sampled analog values.

[0061] To generate the five digital values ​​D1 to D5 in the method 500 of the above embodiment, five ADC cycles are used, and the total number of clock cycles used is 12 + 12 + 8 + 7 + 5 = 44; when using conventional techniques, the total number of clock cycles required is 12 * 5 = 60. By utilizing a previously generated digital value of an analog voltage, the embodiment obtains an estimated range of analog values ​​and performs SAR A / D conversion within this range for the next conversion. Therefore, the embodiment reduces the number of bits determined in some ADC cycles and thus reduces the required conversion time and increases the conversion rate. The embodiment is more advantageous when the number of conversions (ADC cycles) to be performed is large and / or when the SAR ADC resolution (N) is large.

[0062] In some embodiments, the value of W can be determined by testing different values ​​of W using a set of analog voltage / sample values. As an example, embodiment method 500 can be used to convert a set of analog values ​​into digital values ​​using different values ​​of W. A value of W can be selected based on the conversion time corresponding to the different values ​​of W, and, where appropriate, based on other factors such as a conversion time limit. For example, a value of W corresponding to the minimum conversion time used can be selected. Other rules for selecting the value of W can also be applied, such as a rule that considers a trade-off between conversion time and conversion accuracy.

[0063] In some embodiments, method 500 may compare Dm at block 518 with the average of a plurality of previously generated digital values, Davg, instead of just Dm-1. As an example, Davg = average value {Dm-1, Dm-2, …, D(mJ)}, where J is an integer and 1 ≤ J ≤ m-1. Davg may be initialized to empty. When Dm is D1 (m=1), Davg is unavailable, and method 500 returns to block 504 to generate D2 in full mode.

[0064] In some embodiments, when a partial mode is selected (e.g., in block 504), a calibration function block / circuit can be provided to avoid generating overflow bit values ​​(performing an overflow check). One clock cycle is required to perform calibration using the calibration function block, which reduces the conversion rate, for example, by one clock cycle. As an example, the calibration function block may include a comparator configured to compare the generated bit value with one of the overflow reference voltages. When the generated bit value is greater than the overflow reference voltage, the SAR ADC can switch from partial mode to full mode to avoid data loss. When the generated bit value is not greater than the overflow reference voltage, the SAR ADC can continue to operate in partial mode.

[0065] The current conversion overflow reference voltage Dr(N:1) for some modes can be set based on a digital value Dm(N:1) previously generated by the SAR ADC. In one example, if bit P is found to have a second bit with a value of zero (0) starting from bit L of Dm to bit N, then Dr(N:1) can be set to Dm(N:1), but bit P is equal to 1. In another example, Dr(N:1) can be configured such that the values ​​of bits N to P of Dr are 1 and the values ​​of bits (P-1) to 1 of Dr are 0.

[0066] In some embodiments, steps 510 to 528 may be performed using a controller, which may be implemented by hardware, software, or a combination thereof. For example, the controller may be a microcontroller unit (MCU) configured to execute software / firmware. As an example, when Dm is generated during the current conversion, Dm may be sent to the MCU, where the validity of Dm is checked and it is determined whether partial mode is recommended and permitted. The MCU may generate an output (e.g., an instruction / command signal or a control signal / bit) to instruct the SAR ADC to operate in full mode or partial mode for the next conversion or to instruct the SAR ADC to regenerate a digital value of the input analog voltage. The SAR ADC may then select an indication mode and operate according to the selected mode to generate a digital value.

[0067] In some embodiments, partial mode can be disabled or enabled based on various application or A / D conversion requirements. Enabling partial mode can increase the SAR ADC bandwidth. Disabling partial mode can reduce high-frequency noise. In one instance, partial mode can be disabled if a longer conversion time is not a problem. In this case, steps 516 to 532 can be omitted, and method 400 can be used. In another instance, partial mode can be enabled to meet the requirement if an application requires a limited conversion time. The SAR ADC can switch between full mode and full + partial mode depending on the input analog signal. In some embodiments, the number of conversion bits can be fixed when the SAR ADC is operating (e.g., when only low-resolution conversion is required and only a few measurements of DC voltage are easily processed).

[0068] In some embodiments, the data validity check function of method 500 (block 510) may be enabled or disabled, for example, by using a control bit / signal. As an example, the control bit may be configured to indicate whether the data validity check function is enabled between the sampling phase and the conversion phase.

[0069] Figure 6 is a flowchart of another exemplary method 600 for N-bit SAR A / D conversion according to an embodiment of the present invention. Method 600 can be performed using one of the SAR ADCs described in the embodiments of the present invention. Method 600 may include generating a first N-bit digital data and a second N-bit digital data of analog data using a SAR ADC (block 602). Method 600 may further include: when it is determined that the second digital data and the first digital data contain a first most significant bit (MSB) sequence having the same value, using the SAR ADC to generate a third N-bit digital data of the analog data in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second MSB sequence of the third digital data (block 604).

[0070] Figure 7 is a flowchart of another exemplary method 700 for N-bit SAR A / D conversion according to an embodiment of the present invention. Method 700 can be performed using one of the SAR ADCs described in the embodiments of the present invention. Method 700 may include generating a first digital data and a second digital data of analog data by using a SAR ADC, wherein the first digital data and the second digital data each have N bits (block 702). Method 700 may further include determining whether the second digital data contains a first bit sequence having the same value as the first bit sequence of the first digital data (block 704). Method 700 may further include: when the second digital data contains a first bit sequence having the same value as the first bit sequence of the first digital data, determining whether to use a SAR ADC in a certain mode to generate a third digital data of N bits of the analog data based on whether a condition is met (block 706). Method 700 may further include: generating third digital data in partial mode (block 708) when conditions are met. As an example, generating third digital data in partial mode may include: setting a second bit sequence of the third digital data using the respective values ​​of the second bit sequence of the second digital data; and using a SAR ADC to determine the values ​​of the remaining bits of the third digital data. The first bit sequence and the second bit sequence each begin with a first MSB. The second bit sequence contains fewer than N bits.

[0071] It should be noted that various steps of the methods in the embodiments of the present invention may be changed in different embodiments (e.g., swapping, removing, reordering, enhancing, configuring, etc.) without altering the exemplary embodiments presented herein. In different embodiments, some steps may be skipped or combined, performed concurrently, or performed in an order different from that shown in the figures. As an example, steps 524 and 528 of method 500 may be combined or skipped. As another example, step 530 of method 500 may be removed, wherein it may be pre-configured before SAR ADC operation. As yet another example, the order of steps 508 and 510 of method 500 may be swapped.

[0072] Figure 8 is a block diagram of an exemplary circuit 800 of a SAR ADC according to an embodiment of the present invention. The SAR ADC is configured to generate a plurality of N-bit digital values / data Dm of an input analog value / data / voltage VIN, and implements the method of the above embodiment. The input analog voltage is sampled and held and converted into an N-bit digital value Dm. For ease of illustration, the sampling and holding operation is omitted below. The SAR ADC 800 includes a comparator 802, a SAR block / module 804, a DAC 806, a binary-to-thermometer code converter (BTCC) 808, and an ADC controller (ADC_C) 810.

[0073] Comparator 802 includes a first input terminal (negative terminal) connected to a constant voltage VCM set to VREF / 2 and a second input terminal (positive terminal) connected to a voltage VDAC output by DAC 806. The output terminal of comparator 802 is connected to SAR block 804. Comparator 802 compares VCM with VDAC and outputs a comparison result VC, which can be a logic 1 or 0. As an example, when VCM > VDAC, VC = 1; otherwise, when VCM ≤ VDAC, VC = 0. VC is then passed to SAR block 804. Comparator 802 operates similarly to comparator 104 described with respect to FIG. 1.

[0074] SAR block 804 is connected to comparator 802, BTCC 808, and ADC_C block 810. SAR block 804 is similar to SAR block 108 described with respect to Figure 1. SAR block 804 is configured to determine one of the current bits of the digital value Dm based on the comparison result VC and temporarily / store the determined bit. For example, when the comparison result is logic high, the current bit is determined to be 1, and when the comparison result is logic low, the current bit is determined to be 0. SAR block 804 is configured to output the digital value Dm generated for the input analog voltage in the current ADC cycle to ADC_C 810. SAR block 804 can be configured to operate in partial or full mode.

[0075] SAR block 804 is also configured to control the value of the analog voltage VDAC generated by DAC 806. In an exemplary operation, after SAR block 804 determines the current bit of the digital value Dm, SAR block 804 can output an intermediate N-bit digital value DI to BTCC 808, where DI contains the value of (a number of) bits of the digital value Dm that has been determined so far in the current ADC cycle. The remaining (a number of) undetermined bits have (a number of) values ​​of 0. The N-bit digital value DI may refer to the currently determined digital value of VIN. DI is provided to DAC 806 to determine VDAC for the next clock cycle when determining the value of the next bit of the digital value Dm.

[0076] The BTCC 808 is configured to receive an N-bit digital value DI and perform a binary-to-thermometer code conversion to obtain the thermometer code DT, i.e., a P-bit code, where P is generally an integer greater than N. The BTCC 808 increases the number of bits in the currently determined digital value and improves the accuracy of the VDAC determination. In some embodiments, when the SAR block 804 operates in partial mode, DI contains only the bit values ​​of the same bits determined by the SAR block 804, and one or more MSBs can be assigned to the bit values ​​determined in (several) previous ADC cycles. In this case, the BTCC 808 can obtain the bit values ​​of one or more MSBs from the ADC_C block 810. Using Table 1 as an example, SAR block 804 operates in partial mode to determine K=8 bits (bits 8 to 1) of D3. The current bit being determined is bit 8=0, and therefore DI=[0000 0000 0000]. BTCC can obtain D2 ([1011 0011 1011]) from ADC_C 810 and set DI to [1011 0000 0000], where bits 12 to 9 of DI have the same value as the corresponding bits of D2. BTCC 808 can then convert DI to P-bit thermometer code DT.

[0077] DAC 806 is configured to receive the P-bit code DT output from BTCC 808 and determine the voltage VDAC based on DT and VIN. Table 2 below shows example values ​​of VDAC in i clock cycles for determining a bit value Dm, where i is an integer in the range [1, N]. In this example, each clock cycle is used to determine one bit out of N bits, and from clock cycle 1 to clock cycle i, it is used to determine bits from N to 1. BN, BN-1, BN-2, ..., BN-(i-1) represent the bit values ​​of the determined bits N, N-1, N-2, ..., N-(i-1). Table 2 Clock cycle number i Determination bit V DAC 1 N VCM-V IN +VCM 2 N-1 VCM-V IN +VCM×(B N )+VCM / 2 3 N-2 VCM-V IN +VCM×(B N)+VCM / 2×(B N-1 )+VCM / 4 … … i VCM-V IN +VCM×(B N )+VCM / 2×(B N-1 )+VCM / 4×(B N-2 )+VCM / 8×(B N-3 )+…+VCM / (2 (i-2) )×(B N-(i-1) )+VCM / 2 (i-1)

[0078] The ADC_C block 810 is configured to receive and store (a number of) digital values ​​Dm (m=1, 2, ..., M) converted by the SAR block 804, determine whether the next ADC cycle will utilize full mode or partial mode, and control the SAR block 804 to operate in the corresponding mode. The ADC_C block 810 can be configured to output the final digital value converted by the SAR ADC for the input analog voltage.

[0079] The ADC_C block 810 can determine whether a partial mode can be used in the next ADC cycle by comparing a currently generated Dm with a previously generated Dm-1, as described above with respect to Figure 5. When a bit sequence starting from the first MSB in Dm and Dm-1 has the same value, the ADC_C block 810 can determine that a partial mode can be used to generate the bit value Dm+1 in the next ADC cycle, for example, when a condition / configuration is met as discussed above. In some embodiments, the mode can be determined by comparing a currently generated Dm with the average of a plurality of previously generated bit values, Davg. As an example, Davg can be the average of a previously generated bit value D1, D2, ..., Dm-1. As another example, Davg can be the average of a predetermined number J recently generated bit values ​​Dm-1, Dm-2, ..., Dm-J, where 1 ≤ J ≤ m-1. When J=1, the comparison is between Dm and Dm-1.

[0080] Various methods can be used to control the operation of the SAR ADC in decision mode. In one embodiment, the ADC_C block 810 can signal the SAR block to determine the bits of the digital value starting from the first MSB (bit N) in full mode or starting from the Kth MSB (bit K) in partial mode.

[0081] In another embodiment, control can be performed using clock signals. In each ADC cycle and conversion phase, N clock cycles (N clock signals) are used to determine the N bits of the digital output value Dm. In one embodiment, the N clock cycles (clock signals) can be numbered from 1 to N. That is, bit N is generated in clock cycle 1 according to clock signal 1 (first clock signal), bit N-1 is generated in clock cycle 2 according to clock signal 2 (second clock signal), ..., and bit 1 is generated in clock cycle N according to clock signal N (Nth clock signal). Table 2 above shows an example of numbered clock cycles. In an exemplary operation, when SAR block 804 receives clock signal 1 as an initial clock signal to begin A / D conversion in an ADC cycle, SAR block 804 operates in full mode and begins conversion from decision bit N; and when SAR block 804 receives clock signal K as an initial clock signal to begin A / D conversion in an ADC cycle, SAR block 804 operates in partial mode and begins conversion from decision bit K. Figure 9 illustrates an example of using a clock signal to control the operation of a SAR ADC in a decision mode. Those skilled in the art will recognize that various embodiments, changes, and modifications can be made to implement control.

[0082] FIG9 is a block diagram of another exemplary circuit 900 of a SAR ADC according to one embodiment of the present invention. Specifically, FIG9 shows exemplary circuitry for implementing SAR block 804 and ADC_C block 810. For illustrative purposes, SAR block 804, comparator 802, DAC 806, BTCC 808 and ADC_C block 810 are renumbered in FIG9.

[0083] Circuit 900 includes a SAR block 910, a BTCC 920, a DAC 930, a comparator 940 and an ADC controller 950, which operate similarly to SAR block 804, BTCC 808, DAC 806, comparator 802 and ADC_C block 810, respectively.

[0084] SAR block 910 includes a data latch 912, a SAR logic block 914, and a temporary register 916. During the current ADC cycle for converting a sampled value of an input analog voltage VIN into an N-bit digital value Dm (1≤m≤M), the data latch 912 receives a comparison result Vc (logic high or logic low) from the comparator 940 in each clock cycle according to the ADC_CLK (clock signal) during the conversion phase, and passes the comparison result Vc to the SAR logic block 914. The SAR logic block 914 determines the value (0 or 1) of a current bit of the digital value Dm based on the comparison result Vc, and passes the value of the current bit to the temporary register 916, which stores the value corresponding to the current bit. To determine the V DAC for the next clock cycle (next bit), register 916 sends an N-bit value DI (the currently determined value of V IN) to BTCC 920, which converts the binary code DI into a P-bit thermometer code DT. The thermometer code DT is passed to DAC 930, which generates the V DAC for the next clock cycle. Comparator 940 compares the newly generated V DAC with VCM to output a comparison result for the next clock cycle. SAR block 910 then determines the value of the next bit based on the comparison result. This process continues until bit 1 of Dm is determined, i.e., Dm is determined, and Dm is then sent from register 916 to ADC controller 950 by SAR block 910.

[0085] The ADC controller includes registers 952, 954, 958, and 960, a subtractor 956, and a clock signal generator 962. The digital value Dm generated in the current ADC cycle is sent to and stored in register 952. Register 952 receives and stores all digital values ​​D1 to DM generated by SAR block 910 for the input analog voltage, and outputs these digital values. Register 952 also sends Dm to register 954.

[0086] Register 954 is configured to calculate and store the average value of one of all (e.g., D1 to Dm-1) or some (e.g., D(mJ) to D(m-1)) bit values ​​generated in (a number of) previous ADC cycles, Davg. Davg can be initialized with null and updated each time a currently generated bit value Dm is received. For example, Davg can be updated with the currently generated bit value Dm as: Davg = (Davg + Dm) / 2. In one embodiment, when Dm = D1 (m = 1) (i.e., only the first bit value of the input analog voltage is generated), Davg can be updated to Davg = D1. In this case, ADC controller 950 can control SAR block 910 to perform full mode (i.e., for generating the next bit value D2) in the next ADC cycle to skip the operation of registers 956 and 958. As an example, the ADC controller 950 can send Davg=empty to the register 960 based on Davg, and the register 960 can control the clock signal generator 962 to generate an initial clock signal to indicate the use of full mode in the next ADC cycle.

[0087] Based on Dm and Davg, the ADC controller 950 determines whether to select the full mode or the partial mode for the next ADC cycle, and controls the SAR block 910, BTCC 920 and DAC 930 to operate according to the selected mode in the next ADC cycle.

[0088] In some embodiments, a subtraction can then be performed on Dm and Davg at subtractor 956 (before updating with the currently generated bit value) to obtain a difference Ddiff (N bits) between Dm and Davg. This is equivalent to comparing Dm and Davg to determine whether there exists an MSB sequence (starting from bit N) with the same value in Dm and Davg and how many bits are contained in the MSB sequence. For ease of illustration, in the following description, an MSB sequence (starting from bit N) containing L MSBs is referred to as "the same L MSBs".

[0089] Subtraction can be performed as: Ddiff = Dm - Davg or Ddiff = Davg - Dm, and therefore Ddiff can be a negative value. An absolute value of Ddiff can be obtained and used in subsequent processing. In the following text, when Ddiff is mentioned, it refers to the absolute value of Ddiff unless otherwise specified. The obtained Ddiff can be a value that can be represented as a Q-bit binary number, where Q is an integer and 0 ≤ Q ≤ N. For example, Ddiff is 20, which can be represented using Q = 5 bits. This indicates that Dm and Davg have different values ​​for the first 5 LSBs starting from bit 1, and therefore, starting from bit N, Dm and Davg have the same N-5 (i.e., L = N-5) MSBs. When Q = N, this indicates that Dm and Davg do not have the same consecutive MSBs starting from bit N. Ddiff is then passed to register 958 and stored therein. In one embodiment, register 958 may store only the maximum Ddiff (Ddiff-max) of the most recent R ADC cycles, where R is an integer and R < N. As an example, R may be set to N / 4 or N / 6. Ddiff-max may be expressed as Ddiff-max = max{Ddiffm, Ddiff(m-1), …, Ddiff(m-R+1)}.

[0090] The maximum Ddiff (i.e., Ddiff-max (or the number of bits Q of Ddiff-max)) is sent to the register 960. Based on this, the ADC controller 950 determines whether to select the full mode or the partial mode, and performs an initial configuration for the selected mode. In some embodiments, the partial mode can be selected when Q < N-1, and the full mode can be selected when Q ≥ N-1. In some embodiments, the mode can be selected based on the mode resolution K (which is determined based on Q), as described below. Other rules may also be applied to determine which mode to select based on Ddiff-max (or Q).

[0091] When a partial mode is selected for the next ADC cycle in generating the digital value Dm+1, an initial configuration can be performed on the partial mode. In some embodiments, the initial configuration may include configuring the mode resolution K for the partial mode and configuring DI for BTCC 920. Specifically, the mode resolution K is determined based on Q; and furthermore, the ADC controller 950 determines the LSB of the digital value Dm+1 that needs to be determined by the SAR block 910 and therefore determines the MSB of the digital value Dm+1 that does not need to be determined by the SAR block 910, wherein the values ​​of these MSBs are obtained based on the Davg received from the register 954 (before the update).

[0092] As an example, based on Ddiff-max (Q), control block 950 determines that Dm and Davg have the same L MSBs, where L=NQ. The mode resolution K can be set / defined as K=N-L+1=Q+1. Other ways of setting / defining K (e.g., as described above) are also applicable. Next, the (NK) MSBs of Dm+1 can be set to have the values ​​of bits N to (K+1) of Davg(N:1), and the K LSBs of Dm+1 will be determined by SAR block 910. That is, Dm+1(N:1)=Davg(N:K+1)+Dm+1(K:1), where Dm+1(K:1) is determined by SAR block 910. To enable SAR block 910 to begin A / D conversion from the decision bit K in the next ADC cycle, the DI in BTCC 920 can be initialized with the values ​​of Davg(N:K+1) from bits N to K+1, and bit K of DI is initialized with the value 1. This initialization is represented by DLSB and DMSB in Figure 9. DMSB(N:K+1) = Davg(N:K+1). DLSB has K bits, where bit K is initialized with 1, and bits K-1 to 1 are initialized with 0. That is, DLSB(K:1) = {1, 0, … 0}, where K-1 is "0". DLSB and DMSB are then fed to BTCC 920 as initial data for generating VDAC, which is used by SAR block 910 to determine bit K of Dm+1.

[0093] In some embodiments, K can be determined based on Q at register 960. When 1 ≤ K < N, the ADC controller selects partial mode for the next ADC cycle. The D LSB and D MSB can be initialized as discussed above. When K ≥ N (indicating that Dm and Davg do not have an MSB sequence with the same bit value), the ADC controller selects full mode for the next ADC cycle. In this case, the D MSB can be set to empty, and the D MSB can be set to have N bits, where bit N is initialized with the value 1.

[0094] In addition to the initial configuration performed, the ADC controller 950 also generates control signals to instruct the SAR block 910 which mode to select for the next ADC cycle. In some embodiments, as shown in FIG9, the register 960 may send bit information (e.g., K) about the DLSB and / or DMSB to the clock generator 962 as a control signal to control the clock generator 962 to generate an initial clock signal ADC_CLK to start the next ADC cycle when Dm+1 is generated. Based on the initial clock signal, the SAR block 910 understands whether it is operating in full mode or partial mode, and if partial mode is used, which bit (K) is the initial bit to be determined.

[0095] In one example where a clock signal is used to control the operation of a selected mode as discussed above, the register 960 may send a number K to the clock generator 962. Based on this, the clock generator 962 generates a clock signal of a number (N-K+1) as an initial clock signal for the next ADC cycle to indicate that the determination of bit K in the A / D conversion of Dm+1 in the next ADC cycle begins in the partial mode. The SAR block 910 determines bit K of Dm+1 and then continues to determine bits K-1, K-2, ..., 1.

[0096] When K≥N (i.e., (N-K+1)≤1), the clock generator 962 generates a clock signal 1 as an initial clock signal for one of the next ADC cycles to indicate that the A / D conversion in the next ADC cycle, starting from the decision bit N, begins in Dm+1. That is, the SAR ADC operates in full mode in the next ADC cycle.

[0097] Clock generator 962 can generate a clock signal based on bit information received from register 960 and a prescaled clock signal PCLK from an MCU or a chip logic control unit. Clock generator 962 can also send a control signal SH to DAC 930 to indicate that the input analog voltage is sampled before sending the initial clock signal for A / D conversion. VDAC is generated based on thermometer code DT and the sampled value of the input analog voltage.

[0098] It should be noted that the circuits in Figures 8 and 9 are merely examples provided for implementing the methods of embodiments of the present invention. One or more components in these circuits may be changed, removed, or enhanced, and new components may be added. As an example, subtractor 956 may be removed and replaced with a comparator; in this case, additional components may be added to determine L and K. As another example, register 958 may be removed. Other circuits with different structures and components may also be applied to implement the methods of embodiments of the present invention.

[0099] Although the "implementation methods" have been described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims. Furthermore, the scope of the invention is not intended to be limited to the specific embodiments described herein, as it will be readily apparent from the invention to those skilled in the art that existing or future programs, machines, manufactures, compositions, components, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such programs, machines, manufactures, compositions, components, methods, or steps within their scope. [Simplified Explanation of the Diagram]

[0007] To more fully understand the present invention and its advantages, reference is now made to the following description, in conjunction with the accompanying drawings, wherein:

[0008] Figure 1 is a schematic block diagram of an example of a continuous approximate register (SAR) based on a known technique, analogous to a digital converter (ADC);

[0009] Figure 2 shows a waveform diagram of one operation of the SAR ADC in Figure 1;

[0010] Figure 3 is a schematic block diagram of an example capacitive DAC that can be used in the SAR ADC of Figure 1;

[0011] Figure 4 is a flowchart of an example method for SAR analog-to-digital (A / D) conversion using a SAR ADC;

[0012] Figure 5 is a flowchart of an exemplary method for SAR A / D conversion according to an embodiment of the present invention;

[0013] Figure 6 is a flowchart of another exemplary method for SAR A / D conversion according to an embodiment of the present invention;

[0014] Figure 7 is a flowchart of another exemplary method for SAR A / D conversion according to an embodiment of the present invention;

[0015] Figure 8 is a block diagram of an exemplary SAR ADC circuit according to an embodiment of the present invention; and

[0016] Figure 9 is a block diagram of another exemplary SAR ADC circuit according to an embodiment of the present invention.

[0017] The corresponding numbers and symbols in different figures generally refer to the corresponding components, unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

Claims

1. A method for analog-to-digital conversion, the method comprising: A first digital data of N bits and a second digital data of N bits of analog data are generated by using a continuous approximation register (SAR) analog-to-digital converter (ADC), where N is an integer greater than 1; and when it is determined that the second digital data and the first digital data contain a first most significant bit (MSB) sequence with the same value by continuously comparing corresponding bits of the first digital data and the second digital data starting from a most significant bit until a first mismatch bit is detected, the SAR ADC is used in a certain mode to generate a third digital data of N bits of analog data, wherein the SAR ADC is configured to skip the determination of the value of each bit in the second MSB sequence of the third digital data.

2. As in request 1, wherein generating the N-bit third-digit data in this partial mode includes: The values ​​of each element in the second MSB sequence of the third digital data are set using the respective values ​​of one of the second digital data corresponding to the second MSB sequence; And use the SAR ADC to determine the value of the remaining bits of the third bit data.

3. The method of request item 1 or 2, wherein the second MSB sequence comprises fewer bits than the first MSB sequence.

4. The method of claim 1 or 2, further comprising: When the second digital data and the first digital data contain the first MSB sequence having the same value, it is determined whether to generate the third digital data of N bits of analog data in the partial mode based on whether a condition is met.

5. The method of request 4, wherein the condition is satisfied when the number L of the first MSB sequence is greater than a threshold number W, and L and W are integers between 1 and N.

6. The method of request item 5, wherein the number of threshold values ​​W is based on N.

7. The method of request item 4, wherein the condition is satisfied when a preset number of digits of the analog data have been generated.

8. The method of claim 1 or 2, further comprising: When the first, second, or third bit data is determined to be invalid, the SAR ADC is used in a full mode to regenerate the first, second, or third bit data. The full mode includes using the SAR ADC to determine each bit of a regenerated N-bit bit data.

9. The method of claim 1 or 2, wherein the first digital data or the second digital data is generated using the SAR ADC in a partial mode or a full mode, the full mode including using the SAR ADC to determine each bit of a digital data.

10. The method of claim 1 or 2, further comprising: The number of the second MSB sequence is determined based on N, the number of the first MSB sequence, or a combination thereof.

11. The method of claim 1 or 2, further comprising: When it is determined that the second digital data and the first digital data do not contain the first MSB sequence with the same value, the SAR ADC is used in a full mode to generate the N-bit third digital data of the analog data, the full mode including using the SAR ADC to determine each bit of the third digital data.

12. The method of request 1 or 2, wherein the first digital data is the average of one of a plurality of digital data converted for the analog data.

13. The method of claim 1 or 2, further comprising: Generates a clock signal indicating one of the modes of this part.

14. A method for analog-to-digital conversion, the method comprising: A first digital data and a second digital data of analog data are generated using a Sequential Approximation Register (SAR) analog-to-digital converter (ADC), each having N bits. The second digital data is determined to contain a first bit sequence with the same value as a first bit sequence of the first digital data, starting from a first most significant bit (MSB), by continuously comparing corresponding bits of the first and second digital data from a first most significant bit until a first mismatch bit is detected. When the second digital data contains a first bit sequence with the same value as the first digital data, a condition is met to determine whether to use the SAR ADC in a partial mode to generate a third digital data of the N bits of the analog data. When the condition is met, the third digital data is generated in that partial mode. This generation includes: The values ​​of each bit in the second bit sequence of the third digital data are set using the respective values ​​of the second bit sequence corresponding to one of the second digital data, the second bit sequence starting from the first MSB and including fewer than N bits; and the SAR ADC is used to determine the values ​​of the remaining bits of the third digital data.

15. The method of claim 14, wherein the second bit sequence comprises fewer bits than the first bit sequence.

16. The method of request 14 or 15, wherein the condition is satisfied when the number L of one of the first element sequences is greater than the number of a threshold value, and L and the number of the threshold values ​​are integers between 1 and N.

17. The method of request 14 or 15, wherein the condition is satisfied when a preset number of digits of the analog data have been generated.

18. The method of claim 14 or 15, further comprising: Determine whether the third digit is a valid digit. When the third bit data is invalid, the system switches from the partial mode to a full mode to regenerate the third bit data of N bits in the full mode. The full mode includes using the SAR ADC to determine each bit of the third bit data.

19. The method of claim 14 or 15, wherein the first digital data or the second digital data is generated using the SAR ADC in a partial mode or a full mode, the full mode including using the SAR ADC to determine each bit of a digital data.

20. The method of claim 14 or 15, further comprising: When the second digital data does not contain a first bit sequence having the same value as the first bit sequence of the first digital data, the SAR ADC is used in a full mode to generate the third digital data of N bits of the analog data, the full mode including using the SAR ADC to determine each bit of the third digital data.

21. The method of request item 16, wherein the number of threshold values ​​is based on N.

22. The method of claim 14 or 15, wherein the first digital data is the average of one of a plurality of digital data converted for the analog data.

23. The method of claim 14 or 15, further comprising: The number of the second bit sequence is determined based on N, the number of the first bit sequence, or a combination thereof.

24. The method of claim 14 or 15, further comprising: Generates a clock signal indicating one of the modes of this part.

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