Power converting circuit and control method thereof

Abstract

A power conversion circuit for converting input voltage to output voltage includes a transformer, a resonant capacitor, an upper-bridge transistor, a lower-bridge transistor, and a control circuit. The transformer includes a primary coil and a secondary coil coupled between a switching node and a resonant node. The resonant capacitor is coupled between the resonant node and ground, and a resonant current flows through the resonant capacitor. The upper-bridge transistor is coupled between the input voltage and the switching node, and the lower-bridge transistor is coupled between the switching node and ground. The control circuit drives the upper-bridge transistor and the lower-bridge transistor based on the output voltage and the resonant current. When the resonant current reaches a first threshold value, the control circuit turns off the lower-bridge transistor, causing the upper-bridge transistor to achieve zero-voltage switching.

Description

[Technical Field]

[0001] This invention relates to a power conversion circuit and its control method, and more particularly to a resonant power conversion circuit and its control method using pulse width modulation control. [Previous Technology]

[0002] With the continuous development of portable electronic devices, the development trend of power conversion circuits, like most power products, is towards higher efficiency, higher power density, higher reliability, and lower cost. Resonant power conversion circuits (including LLC resonant power conversion circuits) have advantages such as achieving zero-voltage switching (ZVS) on the primary side and zero-current switching (ZCS) on the secondary side rectifier diodes across the entire load range; using frequency control to ensure that the duty cycles of both the upper and lower bridge transistors are 50%; eliminating the need for output inductors; and allowing the use of lower voltage transistors on the secondary side to reduce costs and improve efficiency. In recent years, they have been increasingly used in DC-DC voltage converters.

[0003] However, due to the circuit characteristics of resonant power conversion circuits, a higher switching frequency is required when the output voltage is low or the load is light, resulting in poor conversion efficiency. In order to meet the current market demand for a wide range of output voltages, high output power, and high conversion efficiency, it is necessary to further optimize the power conversion circuit to meet market requirements. [Summary of the Invention]

[0004] This invention proposes a resonant power conversion circuit and its control method using pulse width modulation control, which meets the market demand for a wide range of output voltage, high output power, and high conversion efficiency. Furthermore, by turning on the upper and lower bridge transistors during trough switching and zero-voltage switching, the conversion efficiency of the resonant power conversion circuit is further improved.

[0005] In view of the above, the present invention proposes a power conversion circuit for converting an input voltage into an output voltage, comprising a transformer, a resonant capacitor, an upper-bridge transistor, a lower-bridge transistor, and a control circuit. The transformer includes a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and a resonant node. The resonant capacitor is coupled between the resonant node and a ground terminal, wherein a resonant current flows through the resonant capacitor. The upper-bridge transistor is coupled between the input voltage and the switching node. The lower-bridge transistor is coupled between the switching node and the ground terminal. The control circuit drives the upper-bridge transistor and the lower-bridge transistor based on the output voltage and the resonant current. When the resonant current reaches a first threshold value, the control circuit turns off the lower-bridge transistor, causing the upper-bridge transistor to achieve zero-voltage switching. When the resonant current exceeds a second threshold value, the control circuit turns off the upper-bridge transistor. The second threshold value is related to the output voltage.

[0006] According to some embodiments of the present invention, the power conversion circuit further includes a rectifier circuit, a feedback circuit, and a detection circuit. The rectifier circuit converts the energy of the secondary coil into the output voltage. The feedback circuit compares the output voltage with a reference voltage to generate a compensation signal. The detection circuit detects the resonant current to generate a current detection signal. When the current detection signal is less than a zero-voltage current threshold, the control circuit turns off the lower bridge transistor, causing the upper bridge transistor to achieve zero-voltage switching. When the current detection signal exceeds the compensation signal, the control circuit turns off the upper bridge transistor. The current detection signal corresponds to the resonant current, and the zero-voltage current threshold corresponds to the first threshold. The compensation signal corresponds to the second threshold.

[0007] According to some embodiments of the present invention, the aforementioned zero-voltage current threshold is determined by the parasitic capacitance of the upper bridge transistor, the parasitic capacitance of the lower bridge transistor, the input voltage, and a dead time. The aforementioned dead time is the time from when the lower bridge transistor is turned off to when the upper bridge transistor is turned on.

[0008] According to some embodiments of the present invention, the detection circuit further detects the voltage across the resonant capacitor to generate a voltage detection signal. When the voltage detection signal is less than a threshold voltage, the control circuit turns off the lower bridge transistor.

[0009] According to some embodiments of the present invention, the control circuit further includes an error amplifier. The error amplifier compares the current detection signal with the zero-voltage current threshold value to generate the threshold voltage.

[0010] According to some embodiments of the present invention, the control circuit further includes a valley detection circuit. The valley detection circuit is used to detect that the voltage across the upper bridge transistor or the lower bridge transistor is at a valley voltage and generate a valley detection signal. Based on the valley detection signal, the control circuit turns on the corresponding upper bridge transistor or the lower bridge transistor to achieve valley switching.

[0011] According to some embodiments of the present invention, the control circuit further includes a zero-current detection circuit. The zero-current detection circuit compares the current detection signal with a zero-current threshold value to generate a zero-current detection signal. When the resonant current is zero, the zero-current detection circuit enables the zero-current detection signal. Based on the enabled zero-current detection signal, the control circuit turns on the upper bridge transistor or the lower bridge transistor.

[0012] According to some embodiments of the present invention, the detection circuit includes a detection capacitor and a detection resistor. The detection capacitor is coupled to the resonant node. The detection resistor is coupled between the detection capacitor and the ground terminal. The voltage across the detection resistor is the current detection signal.

[0013] According to other embodiments of the present invention, the detection circuit includes a detection resistor. The detection resistor is coupled between the resonant capacitor and the ground terminal. The voltage across the detection resistor is the current detection signal.

[0014] According to some embodiments of the present invention, the detection circuit further includes a capacitor voltage divider circuit. The capacitor voltage divider circuit is connected in parallel across the resonant capacitor. The capacitor voltage divider circuit divides the voltage across the resonant capacitor to generate the voltage detection signal.

[0015] The present invention further proposes a power conversion circuit for converting an input voltage into an output voltage. The power conversion circuit includes a transformer, a resonant capacitor, a resonant inductor, an upper-bridge transistor, a lower-bridge transistor, a rectifier circuit, a feedback circuit, a detection circuit, and a control circuit. The transformer includes a primary coil and a secondary coil. A resonant current flows through the resonant capacitor. The primary coil, the resonant capacitor, and the resonant inductor are connected in series between a switching node and a ground terminal. The upper-bridge transistor is coupled between the input voltage and the switching node. The lower-bridge transistor is coupled between the switching node and the ground terminal. The rectifier circuit converts the energy of the secondary coil into the output voltage. The feedback circuit compares the output voltage with a reference voltage to generate a compensation signal. The detection circuit detects the resonant current and generates a current detection signal. The control circuit drives the upper-bridge transistor and the lower-bridge transistor based on the current detection signal and the compensation signal flowing through it. The control circuit controls the conduction time of one of the lower bridge transistors to a predetermined value. This predetermined value is less than half a resonant period. The resonant period is determined by the resonant capacitor and the resonant inductor. When the current detection signal exceeds the compensation signal, the control circuit turns off the upper bridge transistor.

[0016] According to some embodiments of the present invention, the detection circuit includes a zero-current detection circuit. The zero-current detection circuit compares the current detection signal with a zero-current threshold value to generate a zero-current detection signal. When the resonant current is zero, the zero-current detection circuit enables the zero-current detection signal. Based on the enabled zero-current detection signal, the control circuit turns on the upper bridge transistor or the lower bridge transistor.

[0017] The present invention further proposes a control method for controlling a power conversion circuit. The control method described above includes: within a switching cycle, comprising the following plurality of periods: a first drive time for turning on a first transistor of a primary device of the power conversion circuit and turning off a second transistor of the primary device; a first rest time for simultaneously turning off the first transistor and the second transistor after the first drive time; a second drive time for turning off the first transistor and turning on the second transistor after the first rest time; a second rest time for simultaneously turning off the first transistor and the second transistor after the second drive time; a third drive time for turning on the first transistor and turning off the second transistor after the second rest time; a third rest time for simultaneously turning off the first transistor and the second transistor after the third drive time; a fourth drive time for turning off the first transistor and turning on the second transistor after the third rest time; and a fourth rest time for simultaneously turning off the first transistor and the second transistor after the fourth drive time.

[0018] According to some embodiments of the present invention, the control method further includes: after the fourth rest time of a first switching cycle ends, starting the first drive time of a second switching cycle. When the first drive time of the second switching cycle turns on the first transistor, the first transistor turns on during trough switching.

[0019] According to some embodiments of the present invention, the length of the first driving time is related to the output voltage of one of the power conversion circuits.

[0020] According to some embodiments of the present invention, the control method further includes: adjusting the length of the first rest time to reduce the transvoltage of the second transistor when it is turned on during the second driving time.

[0021] According to some embodiments of the present invention, the length of the second driving time is related to whether the first transistor can achieve zero voltage switching during the third driving time.

[0022] According to some embodiments of the present invention, the control method further includes: adjusting the length of the second drive time and the second rest time to reduce the transverse voltage of the first transistor when the first transistor is turned on during the third drive time.

[0023] According to some embodiments of the present invention, the length of the third driving time is related to the output voltage of one of the power conversion circuits.

[0024] According to some embodiments of the present invention, the control method further includes: adjusting the length of the third rest time to reduce the transverse voltage of the second transistor when the second transistor is turned on during the fourth driving time.

[0025] According to some embodiments of the present invention, the first transistor achieves zero-voltage switching when the third driving time is turned on. The first transistor achieves trough switching when the first driving time is turned on.

[0026] According to some embodiments of the present invention, the second transistor achieves zero voltage switching when it is turned on during the second driving time and the fourth driving time.

Implementation Method

[0028] The following description is an embodiment of this disclosure. Its purpose is to illustrate the general principles of this disclosure and should not be regarded as a limitation of this disclosure. The scope of this disclosure shall be defined by the scope of the claims.

[0029] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of this disclosure. The specific examples and arrangements of elements described below are only used to briefly illustrate the spirit of this disclosure and are not intended to limit the scope of this disclosure. Furthermore, the same element symbols or words may be used repeatedly in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear explanation and is not intended to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0030] Furthermore, the description in the following specification of a feature being connected to, coupled to, and / or formed on another feature may actually include multiple different embodiments, including the features being in direct contact, or including other additional features formed between the features, such that the features are not in direct contact.

[0031] Furthermore, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the arrangement of the diagram is flipped so that it is upside down, the element described as being on the "lower" side will become the element on the "higher" side.

[0032] It is understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments disclosed herein.

[0033] Some embodiments disclosed herein can be understood in conjunction with the accompanying drawings, which are also considered part of the description of the embodiments disclosed herein. It should be understood that the drawings of the embodiments disclosed herein are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments disclosed herein. Furthermore, the structures and devices in the drawings are drawn schematically to clearly show the features of the embodiments disclosed herein.

[0034] Here, the terms "about," "approximately," and "roughly" generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, even without specific explanation of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0036] In some embodiments disclosed herein, terms such as "connection" and "interconnection" used to refer to joining or connecting, unless otherwise defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein other structures are disposed between the two structures. Furthermore, these terms regarding joining or connecting may also include situations where both structures are movable or both structures are fixed.

[0037] In the diagram, similar elements and / or features may have the same element symbol. Various elements of the same type may be distinguished by adding letters or numbers after the element symbol to differentiate similar elements and / or similar features.

[0038] Figure 1 shows a schematic diagram of a power conversion circuit according to an embodiment of the present invention. As shown in Figure 1, the power conversion circuit 100 is used to convert the input voltage VIN into the output voltage VOUT, and includes a transformer TM, a resonant inductor LR, a resonant capacitor CR, an input capacitor CIN, an upper bridge transistor 110, a lower bridge transistor 120, a detection circuit 130, a feedback circuit 140, a control circuit 150, and a gate drive circuit 160.

[0039] The transformer TM includes a primary coil PS and a secondary coil SS, wherein the primary coil PS is coupled to the resonant node NR. A resonant inductor LR is coupled between the switching node SW and the primary coil PS, and a resonant capacitor CR is coupled between the resonant node NR and ground. According to one embodiment of the invention, the resonant inductor LR can be replaced by the leakage inductance of the primary coil PS of the transformer TM. In other words, the primary coil PS can be coupled between the switching node SW and the resonant node NR.

[0040] As shown in Figure 1, the input capacitor CIN is coupled between the input voltage VIN and the ground terminal. The upper bridge drive signal HS drives the upper bridge transistor 110, thereby providing the input voltage VIN to the switching node SW. The lower bridge drive signal LS drives the lower bridge transistor 120, thereby coupling the switching node SW to the ground terminal. According to some embodiments of the present invention, the upper bridge transistor 110 and the lower bridge transistor 120 form a half-bridge circuit to drive the primary coil PS and the resonant capacitor CR.

[0041] The detection circuit 130 is coupled to the resonant node NR to generate a current detection signal ICR and a voltage detection signal VCR. According to some embodiments of the present invention, the current detection signal ICR represents the resonant current IR flowing through the resonant capacitor CR, and the voltage detection signal VCR represents the voltage across the resonant capacitor CR. According to one embodiment of the present invention, the detection circuit 130 may include a detection resistor (not shown in Figure 1) coupled between the resonant capacitor CR and ground, wherein the voltage across the detection resistor is the current detection signal ICR. According to some embodiments of the present invention, the current detection signal ICR is a voltage signal.

[0042] The feedback circuit 140 is used to compare the feedback voltage VFB with the reference voltage VREF to generate a compensation signal COMP. According to some embodiments of the present invention, the feedback voltage VFB is proportional to the output voltage VOUT. According to some embodiments of the present invention, the feedback circuit 140 may include an error amplifier, with the positive terminal of the error amplifier receiving the reference voltage VREF and the negative terminal receiving the feedback voltage VFB. The feedback circuit 140 compares the output voltage VOUT with the reference voltage VREF to generate the compensation signal COMP. This description uses the feedback voltage VFB to generate the compensation signal COMP and is not intended to limit the scope in any way. According to other embodiments of the present invention, the feedback circuit 140 may also compare the output voltage VOUT with the reference voltage VREF to generate the compensation signal COMP.

[0043] According to some embodiments of the present invention, the feedback circuit 140 generates a compensation signal COMP using the difference between the feedback voltage VFB and the reference voltage VREF, such that the output voltage VOUT reaches a target value and the feedback voltage VFB is equal to the reference voltage VREF. According to one embodiment of the present invention, when the feedback voltage VFB exceeds the reference voltage VREF, the feedback circuit 140 decreases the compensation signal COMP. According to another embodiment of the present invention, when the reference voltage VREF exceeds the feedback voltage VFB, the feedback circuit 140 increases the compensation signal COMP. According to one embodiment of the present invention, the feedback circuit 140 may include a voltage divider circuit for dividing the output voltage VOUT to generate the feedback voltage VFB.

[0044] The control circuit 150 generates an upper bridge gate drive signal HSW and a lower bridge gate drive signal LSW based on the voltage of the current detection signal ICR, the voltage detection signal VCR, and the compensation signal COMP. The gate drive circuit 160 generates an upper bridge drive signal HS based on the upper bridge gate drive signal HSW, and generates a lower bridge drive signal LS based on the lower bridge gate drive signal LSW.

[0045] According to other embodiments of the present invention, since the current detection signal ICR and the voltage detection signal VCR are both used to detect the resonant current IR flowing through the resonant capacitor CR, and the compensation signal COMP is used to represent the state of the output voltage VOUT, it can be regarded that the control circuit 150 drives the upper bridge transistor 110 and the lower bridge transistor 120 based on the output voltage VOUT and the resonant current IR.

[0046] As shown in Figure 1, the power conversion circuit 100 further includes a rectifier circuit 170. The rectifier circuit 170 includes a first rectifier element D1, a second rectifier element D2, and an output capacitor COUT. The first rectifier element D1 is coupled between the first node N1 of the secondary coil SS and the ground terminal. The second rectifier element D2 is coupled between the second node N2 of the secondary coil SS and the ground terminal. The output capacitor COUT is coupled between the intermediate node NC of the secondary coil SS and the ground terminal, and the output voltage VOUT is generated at the intermediate node NC.

[0047] According to some embodiments of the present invention, the first rectifier element D1 and the second rectifier element D2 rectify the energy of the secondary coil SS into a first current ID1 and a second current ID2 respectively and provide them to the output capacitor COUT, thereby generating an output voltage VOUT and an output current IOUT.

[0048] According to some embodiments of the present invention, the power conversion circuit 100 may be a resonant power conversion circuit. According to some embodiments of the present invention, the power conversion circuit 100 may be an LLC resonant power conversion circuit.

[0049] Figure 2 shows a schematic diagram of a detection circuit according to one embodiment of the present invention. The detection circuit 200 includes a detection capacitor CS, a detection resistor RS, and a capacitor voltage divider circuit 210. The detection capacitor CS is coupled to the resonant node NR, and the detection resistor RS is coupled between the detection capacitor CS and the ground terminal. In other words, the detection capacitor CS and the detection resistor RS are connected in series across the resonant capacitor CR. Furthermore, the voltage across the detection resistor RS generates a current detection signal ICR. According to some embodiments of the present invention, the current detection signal ICR is a voltage signal.

[0050] A capacitor voltage divider circuit 210 is coupled across the resonant capacitor CR and includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 and the second capacitor C2 are used to divide the voltage at the resonant node NR to generate a voltage detection signal VCR. According to other embodiments of the present invention, the detection resistor RS can also be connected in series between the resonant capacitor CR and the ground terminal, and the detection capacitor CS (not shown in Figure 2) is omitted, wherein the voltage across the detection resistor RS is the current detection signal ICR.

[0051] Figure 3 shows a schematic diagram of a control circuit according to one embodiment of the present invention. As shown in Figure 3, the control circuit 300 includes a first delay circuit 310, a first flip-flop FF1, a trough detection circuit 320, a lower bridge conduction control circuit 330, a second flip-flop FF2, and a first comparator CMP1.

[0052] The first flip-flop FF1, based on the output signal generated by delaying the inverted lower bridge gate drive signal LSB by the first delay circuit 310, enables the upper bridge gate drive signal HSW and simultaneously disables the inverted upper bridge gate drive signal HSB. According to some embodiments of the present invention, the delay time generated by the first delay circuit 310 is used to determine the dead time from the turn-off of the lower bridge transistor 120 to the turn-on of the upper bridge transistor 110 in Figure 1. The trough detection circuit 320, based on the enabled inverted upper bridge gate drive signal HSB, determines that the voltage of the switching node SW is in a trough by detecting the state of the current detection signal ICR, and then generates a trough detection signal SVD.

[0053] The lower bridge conduction control circuit 330 sets or resets the second flip-flop FF2 based on the trough detection signal SVD, the zero voltage-current threshold value IZV, and the voltage detection signal VCR, thereby generating the lower bridge gate drive signal LSW and the inverted lower bridge gate drive signal LSB. According to some embodiments of the present invention, the lower bridge conduction control circuit 330 can control the conduction time of the lower bridge gate drive signal LSW to a predetermined value. According to one embodiment of the present invention, the predetermined value may be less than the resonant period, wherein the resonant period is determined by the resonant capacitor CR and the resonant inductor LR in Figure 1.

[0054] When the compensation signal COMP generated by the feedback circuit 140 in Figure 1 does not exceed the current detection signal ICR, the first comparator CMP1 resets the first flip-flop FF1 and disables the upper bridge gate drive signal HSW.

[0055] Figure 4 is a schematic diagram showing a control circuit according to another embodiment of the present invention. Comparing the control circuit 400 in Figure 4 with the control circuit 300 in Figure 3, the lower bridge conduction control circuit 320 in Figure 3 is replaced by a sample-and-hold circuit 410, a transconductance amplifier GM, a transconductance resistor RM, a transconductance capacitor CM, and a second comparator CMP2, and the feedback circuit 140 in Figure 3 is replaced by an error amplifier EA. In other words, the feedback circuit 140 may include the error amplifier EA.

[0056] The trough detection circuit 320 generates a trough detection signal SVD by detecting the state of the current detection signal ICR based on the enabled inverted upper bridge gate drive signal HSB. The second flip-flop FF2 enables the lower bridge gate drive signal LSW and disables the inverted lower bridge gate drive signal LSB based on the enabled trough detection signal SVD. The sample-and-hold circuit 410 samples and holds the current detection signal ICR based on the enabled inverted lower bridge gate drive signal LSB.

[0057] The transconductance amplifier GM compares the current detection signal ICR held by the sample-and-hold circuit 410 with the zero-voltage current threshold value IZV to generate a threshold current ITH. The threshold current ITH flows through the transconductance resistor RM and the transconductance capacitor CM to generate a threshold voltage VTH. According to some embodiments of the present invention, the transconductance amplifier GM generates different threshold currents ITH based on different differences between the current detection signal ICR and the zero-voltage current threshold value IZV.

[0058] In other words, the transconductance amplifier GM, the transconductance resistor RM, and the transconductance capacitor CM generate different threshold voltages VTH based on the different differences between the current detection signal ICR and the zero-voltage current threshold value IZV. According to some embodiments of the present invention, the transconductance amplifier GM, the transconductance resistor RM, and the transconductance capacitor CM form an error amplifier.

[0059] The second comparator CMP2 compares the voltage detection signal VCR and the threshold voltage VTH, and resets the second flip-flop FF2, thereby disabling the lower bridge gate drive signal LSW and enabling the inverted lower bridge gate drive signal LSB.

[0060] Figure 5 shows a waveform diagram of a power conversion circuit according to one embodiment of the present invention. The following detailed description will be based on the power conversion circuit 100 of Figure 1 and the control circuit 400 of Figure 4. As shown in the waveform diagram 500 of Figure 5, in one switching cycle TSW, the lower bridge gate drive signal LSW is enabled at the initial time t0. At the first time t1, it is determined that the voltage detection signal VCR is lower than the threshold voltage VTH, and the lower bridge gate drive signal LSW is disabled.

[0061] According to some embodiments of the present invention, at a first time t1, the current detection signal ICR reaches the zero voltage-current threshold value IZV. The voltage detection signal VCR is less than the threshold voltage VTH generated by the transconductance amplifier GM, the transconductance resistor RM, and the transconductance capacitor CM, so that the upper bridge transistor 110 can achieve zero-voltage switching and turn on. The zero voltage-current threshold value IZV is determined by the upper bridge parasitic capacitance COS1 of the upper bridge transistor 110, the lower bridge parasitic capacitance COS2 of the lower bridge transistor 120, the input voltage VIN, and the dead time TDT generated by the first delay circuit 310, as shown in Formula 1: (Formula 1)

[0062] In other words, the resonant current IR flowing through the resonant capacitor CR must be sufficient to turn on the parasitic diode of the upper bridge transistor 110 so that the voltage of the switching node SW is equal to the input voltage VIN, thereby enabling the subsequent turn-on of the upper bridge transistor 110 to achieve zero-voltage switching and reduce power loss.

[0063] After the dead time generated by the first delay circuit 310 in Figure 4, the upper bridge gate drive signal HSW is enabled at the second time t2. According to one embodiment of the present invention, the upper bridge transistor 110 can achieve zero-voltage switching (ZVS) when it is turned on at the second time t2 to reduce switching power loss. At the third time t3, the current detection signal ICR exceeds the compensation signal COMP and the upper bridge gate drive signal HSW is disabled.

[0064] After the third time t3, the voltage of the switching node SW oscillates, and the valley detection circuit 320 determines that the voltage of the switching node SW has reached the valley (i.e., the lowest point) at the fourth time t4, and enables the lower bridge gate drive signal LSW, so that the lower bridge transistor 120 achieves valley switching (VS).

[0065] Figure 6 shows a schematic diagram of a valley detection circuit according to one embodiment of the present invention. As shown in Figure 6, the valley detection circuit 600 includes a second delay circuit 610, a third comparator CMP3, a third flip-flop FF3, and a first pulse generator 620. The second delay circuit 610 is used to control the delay time for providing the inverting upper bridge gate drive signal HSB to the third flip-flop FF3.

[0066] The third comparator CMP3 compares the current detection signal ICR and the zero current threshold value IZC to generate the clock signal of the third flip-flop FF3. Based on the output signal of the third comparator CMP3, the third flip-flop FF3 outputs the inverted upper bridge gate drive signal HSB provided by the enable circuit 610 as the zero current detection signal SZC.

[0067] According to some embodiments of the present invention, when the current detection signal ICR drops to the zero current threshold value IZC, the third comparator CMP3 outputs a positive pulse, causing the third flip-flop FF3 to respond to the positive pulse output by the third comparator CMP3 and output the inverted upper bridge gate drive signal HSB as the zero current detection signal SZC. According to some embodiments of the present invention, the zero current threshold value IZC may be zero or slightly greater than zero. According to other embodiments of the present invention, the zero current threshold value IZC may also be slightly less than zero. In other words, the zero current threshold value IZC is a value close to zero.

[0068] When the reverse upper bridge gate drive signal HSB is enabled, the zero current detection signal SZC output by the trough detection circuit 600 is also enabled. The first pulse generator 620 resets the third flip-flop FF3 based on the enabled zero current detection signal SZC. According to some embodiments of the present invention, the trough detection circuit 600 corresponds to the trough detection circuit 400 in Figure 4, and is used to detect when the current detection signal ICR drops to the zero current threshold value IZC.

[0069] Since the zero current threshold IZC is a value close to zero, when the resonant current IR corresponding to the current detection signal ICR drops to zero, it means that the voltage of the switching node SW at this time is at its minimum value. In other words, the detection of the current detection signal ICR dropping to the zero current threshold IZC is equivalent to the detection of the voltage of the switching node SW reaching a trough. According to some embodiments of the present invention, the trough detection circuit 600 corresponds to the trough detection circuit 320 in Figure 4, and the trough detection signal SVD in Figure 4 corresponds to the zero current detection signal SZC in Figure 6.

[0070] Figure 7 shows a schematic diagram of a control circuit according to another embodiment of the present invention. Compared with control circuit 400, control circuit 700 in Figure 7 outputs a first lower bridge gate drive signal LS1 from the second flip-flop FF2, and control circuit 700 further includes a third delay circuit 710, a fourth flip-flop FF4, a first zero current detection circuit 720, and a first OR gate OR1.

[0071] As shown in Figure 7, the third delay circuit 710 delays the inverted upper bridge gate drive signal HSB by a delay time, and uses it as the clock signal of the fourth flip-flop FF4. Based on the delayed inverted upper bridge gate drive signal HSB, the fourth flip-flop FF4 outputs the inverted upper bridge gate drive signal HSB as the second lower bridge gate drive signal LS2.

[0072] The first zero-current detection circuit 720 is used to detect when the current detection signal ICR drops to zero, thereby resetting the fourth flip-flop FF4 and disabling the second lower bridge gate drive signal LS2. According to some embodiments of the present invention, the first zero-current detection circuit 720 can be implemented using the trough detection circuit 600. The first OR gate OR1 performs a logical OR operation on the first lower bridge gate drive signal LS1 and the second lower bridge gate drive signal LS2 to generate the lower bridge gate drive signal LSW.

[0073] Figure 8 shows a waveform diagram of a power conversion circuit according to another embodiment of the present invention. The following detailed description will be based on the power conversion circuit 100 in Figure 1 and the control circuit 700 in Figure 7. As shown in waveform diagram 800 of Figure 8, the initial time t0 to the third time t3 are the same as those in waveform diagram 500 of Figure 5, and will not be repeated here.

[0074] When the upper bridge gate drive signal HSW is turned off at the third time t3, the third delay circuit 710 delays the output signal of the inverted upper bridge gate drive signal HSB as the clock signal of the fourth flip-flop FF4, so that the lower bridge gate drive signal LSW is enabled again at the fourth time t4, and the lower bridge transistor 120 is turned on. According to some embodiments of the present invention, the dead time from the third time t3 to the fourth time t4 is determined by the delay time of the third delay circuit 710. According to some embodiments of the present invention, the dead time from the third time t3 to the fourth time t4 is sufficient to allow the lower bridge transistor 120 to achieve zero voltage switching.

[0075] When the first zero-current detection circuit 720 determines that the current detection signal ICR drops to zero at the fifth time t5, the first zero-current detection circuit 720 generates a falling zero-current signal FZD to reset the fourth flip-flop FF4, thereby disabling the lower bridge gate drive signal LSW. At the seventh time t7, the trough detection circuit 320 determines that the voltage of the switching node SW has reached the trough (i.e., the lowest point), and enables the lower bridge gate drive signal LSW, causing the lower bridge transistor 120 to achieve trough switching.

[0076] Figure 9 shows a schematic diagram of a control circuit according to another embodiment of the present invention. Compared with control circuit 700, control circuit 900 in Figure 9 outputs a first upper bridge gate drive signal HS1 from the first flip-flop FF1, and control circuit 900 further includes a second zero current detection circuit 910, a second pulse generator 920, and a second OR gate OR2.

[0077] The second zero-current detection circuit 910 is used to detect the current detection signal ICR rising to zero, and generates a rising zero-current signal RZD. The second pulse generator 920 is enabled by the second lower bridge gate drive signal LS2, and generates a second upper bridge gate drive signal HS2 based on the rising zero-current signal RZD. According to some embodiments of the present invention, the enable time of the second upper bridge gate drive signal HS2 is determined by the pulse width generated by the second pulse generator 920. The second OR gate OR2 performs a logical OR operation on the first upper bridge gate drive signal HS1 and the second upper bridge gate drive signal HS2 to generate an upper bridge gate drive signal HSW.

[0078] Furthermore, compared to the control circuit 700, the trough detection circuit 320 of the control circuit 900 generates a trough detection signal SVD based on the second upper bridge gate drive signal HS2 and the current detection signal ICR. As shown in Figure 6, the trough detection circuit 320 of the control circuit 900 can be realized by replacing the inverted upper bridge gate drive signal HSB received by the trough detection circuit 600 with the second upper bridge gate drive signal HS2.

[0079] Figure 10 shows a schematic diagram of a second zero-current detection circuit according to one embodiment of the present invention. As shown in Figure 10, the second zero-current detection circuit 1000 includes a fourth delay circuit 1010, a fourth comparator CMP4, a fifth flip-flop FF5, and a third pulse generator 1020. The fourth delay circuit 1010 is used to control the delay time for providing the supply voltage VCC to the fifth flip-flop FF5. When the current detection signal ICR increases to the zero current threshold value IZC, the fourth comparator CMP4 outputs a positive pulse.

[0080] The fifth flip-flop FF5 outputs a rising zero-current signal RZD from the supply voltage VCC based on the rising edge generated by the fourth comparator CMP4. The third pulse generator 1020 resets the fifth flip-flop FF5 based on the rising zero-current signal RZD. In other words, when the current detection signal ICR increases to the zero-current threshold value IZC, the second zero-current detection circuit 1000 generates a positive pulse on the rising zero-current signal RZD.

[0081] Figure 11 shows a waveform diagram of a power conversion circuit according to another embodiment of the present invention. The following detailed description will be based on the power conversion circuit 100 in Figure 1 and the control circuit 900 in Figure 9. As shown in the waveform diagram 1100 of Figure 11, the initial time t0 to the fifth time t5 are the same as in Figure 8, and will not be repeated here.

[0082] At the sixth time t6, the second zero-current detection circuit 910 detects that the current detection signal ICR increases to the zero-current threshold value IZC, thereby enabling the upper bridge gate drive signal HSW, causing the voltage of the switching node SW to rise to the input voltage VIN. According to some embodiments of the present invention, the second zero-current detection circuit 910 is a valley detection circuit for detecting that the cross voltage of the upper bridge transistor 110 is at a valley voltage, and the valley detection circuit 320 is a valley detection signal SVD generated for detecting that the cross voltage of the lower bridge transistor 120 is at a valley voltage.

[0083] Furthermore, a higher voltage at the switching node SW helps to generate a lower trough voltage at the switching node SW. Therefore, when the lower bridge transistor 120 is turned on at the seventh time t7, the trough voltage at the switching node SW is lower than the trough voltage at the seventh time t7 in Figure 8. In other words, turning on the upper bridge transistor 110 again at the sixth time t6 helps to increase the conversion efficiency of the power conversion circuit 100. According to some embodiments of the present invention, when the voltage across the upper bridge transistor 110 or the lower bridge transistor 120 is not equal to zero, it indicates that there is still charge in the parasitic capacitance of the upper bridge transistor 110 or the lower bridge transistor 120. At this time, turning on the upper bridge transistor 110 or the lower bridge transistor 120 requires discharging the charge stored in the parasitic capacitance and converting it into heat. Therefore, zero-voltage switching improves the conversion efficiency more than trough switching.

[0084] Figure 12 shows a waveform diagram of a power conversion circuit according to another embodiment of the present invention. A detailed description will follow, in conjunction with the power conversion circuit 100 of Figure 1 and the control circuit 900 of Figure 9.

[0085] As shown in waveform diagram 1200 of Figure 12, the lower bridge transistor 120 is turned on in a trough-switching manner at the initial time t0. Between the initial time t0 and the first time t1, the voltage of the switching node SW rises, and the upper bridge transistor 110 is turned on in a trough-switching manner at the first time t1. At the second time t2, the current detection signal ICR exceeds the compensation signal COMP, and the upper bridge transistor 110 is turned off. Then, the lower bridge transistor 120 is turned on at the third time t3, where the period from the second time t2 to the third time t3 is the dead time, determined by the enable circuit 610 in Figure 6.

[0086] When the current detection signal ICR reaches the zero-voltage current threshold value IZV, the lower bridge transistor 120 is turned off, allowing the upper bridge transistor 110 to switch on at zero voltage at the fifth time t5. In other words, when the resonant current IR is sufficient (i.e., the resonant current IR flowing from the resonant node NR to the switching node SW is sufficient to turn on the parasitic diode of the upper bridge transistor 110 and pull the voltage of the switching node SW to the input voltage VIN), the lower bridge transistor 120 can be turned off.

[0087] When the current detection signal ICR increases to the zero current threshold IZC at the sixth time t6, the upper bridge transistor 110 is turned off. Then, the lower bridge transistor is turned on again at the seventh time t7. According to some embodiments of the present invention, since both the upper bridge transistor 110 and the lower bridge transistor 120 are turned on during trough switching or zero voltage switching, the conversion efficiency of the power conversion circuit 100 is improved.

[0088] Figure 13 shows a waveform diagram of a power conversion circuit according to another embodiment of the present invention. A detailed description will follow, in conjunction with the power conversion circuit 100 of Figure 1 and the control circuit 900 of Figure 9.

[0089] As shown in waveform diagram 1300 of Figure 13, the upper bridge transistor 110 is switched on at the trough of the initial time t0, and the current sensing signal ICR continuously increases between the initial time t0 and the first time t1. When the current sensing signal ICR exceeds the compensation signal COMP at the first time t1, the upper bridge transistor 110 is turned off. After the dead time, the lower bridge transistor 120 is turned on at the second time t2. When the current sensing signal ICR reaches the zero voltage current threshold value IZV at the third time t3, the lower bridge transistor 120 is turned off, so that the upper bridge transistor 110 can achieve zero voltage switching when it is turned on at the fourth time t4.

[0090] Next, when the current sensing signal ICR exceeds the compensation signal COMP at the fifth time t5, the upper bridge transistor 110 is turned off. After the dead time, the lower bridge transistor 120 is turned on at the sixth time t6. When the current sensing signal ICR drops to the zero current threshold value IZC, the lower bridge transistor 120 is turned off at the seventh time t7. Between the seventh time t7 and the eighth time t8, both the upper bridge transistor 110 and the lower bridge transistor 120 are turned off, and the voltage of the switching node SW rises. Finally, the upper bridge transistor 110 is turned on again at the eighth time t8.

[0091] Compared to waveform 1100 in Figure 11, which has two trough switchings in four transistor conductions, waveform 1300 reduces the number of trough switchings to one, which helps to ensure that power loss remains at a low level. Since both the upper bridge transistor 110 and the lower bridge transistor 120 conduct under zero-voltage switching or trough switching conditions, and the resonant current IR flowing through the resonant capacitor CR is zero during trough switching, the conversion efficiency of the power conversion circuit 100 is improved.

[0092] Figure 14 shows a simulated waveform diagram of a power conversion circuit according to some embodiments of the present invention. According to one embodiment of the present invention, the simulation conditions of the simulated waveform diagram 1400 are: input voltage VIN is 400V, output voltage VOUT is 20V, and output current IOUT is 5A.

[0093] The upper bridge transistor 110 is turned on during trough switching or zero-voltage switching based on the upper bridge gate drive signal HSW. The lower bridge transistor 120 is turned on during zero-voltage switching based on the lower bridge gate drive signal LSW. In addition, when the current detection signal ICR rises to zero, the upper bridge transistor 110 is turned on during trough switching.

[0094] Since the trough switching system turns on the switch when the current flowing through the switch is zero, and the zero-voltage switching system turns on the switch when the voltage across the switch is zero, both trough switching and zero-voltage switching help improve the conversion efficiency of the power conversion circuit. In addition, since the conduction periods of the upper bridge transistor 110 and the lower bridge transistor 120 in the power conversion circuit 100 do not need to be kept equal, a wide range of output voltage VOUT can be achieved by adjusting the conduction period.

[0095] Figure 15 is a flowchart showing a control method according to one embodiment of the present invention. The following description of the control method 1500 will be provided in conjunction with Figures 1, 9, and 13 for detailed explanation. According to other embodiments of the present invention, the control method 1500 can also be applied to waveform diagram 1100 in Figure 11 and waveform diagram 1200 in Figure 12. For the sake of simplicity, the present invention is described and explained here using waveform diagram 1300 in Figure 13 as an example, and is not limited thereto in any way.

[0096] First, at the initial time t0 in Figure 13, the first transistor (i.e., the upper bridge transistor 110 in the embodiment of Figure 13) is turned on (step S1510), and the first transistor remains on between the initial time t0 and the first time t1 (i.e., the first driving time). At the first time t1, the first transistor (i.e., the upper bridge transistor 110 in the embodiment of Figure 13) and the second transistor (i.e., the lower bridge transistor 120 in the embodiment of Figure 13) are simultaneously turned off (step S1520).

[0097] According to one embodiment of the present invention, the period from the first time t1 to the second time t2 is a first rest time, also known as a dead time. According to some embodiments of the present invention, the control circuit 150 of Figure 1 adjusts the length of the first rest time so that the second transistor (i.e., the lower bridge transistor 120 in the embodiment of Figure 13) achieves a zero-voltage transition when it is turned on at the second time t2. According to some embodiments of the present invention, the length of the first rest time is determined by the trough detection circuit 320 of Figure 9. As shown in Figure 6, the first rest time is determined by the second delay circuit 610.

[0098] At the second time t2, the second transistor is turned on (step S1530), and remains on for the second time. According to some embodiments of the present invention, the period from the second time t2 to the third time t3 is the second driving time. According to some embodiments of the present invention, the length of the second driving time is related to whether the first transistor can achieve zero voltage switching at the fourth time t4 during the aforementioned third driving time.

[0099] As shown in Figures 9 and 13, when the second comparator CMP2 determines that the voltage detection signal VCR is not less than the threshold voltage VTH, the second comparator CMP2 resets the second flip-flop FF2 and disables the lower bridge gate drive signal LSW, thereby turning off the second transistor (i.e., the lower bridge transistor 120 in the embodiment of Figure 13). According to some embodiments of the present invention, the length of the second drive time from the second time t2 to the third time t3 is used to determine the magnitude of the resonant current IR flowing from the resonant node NR to the switching node SW.

[0100] At the third time t3, both the first transistor and the second transistor are simultaneously turned off (step S1540), and a second rest period continues. According to some embodiments of the present invention, the third time t3 to the fourth time t4 is the second rest period. According to some embodiments of the present invention, the second rest period is determined by the first delay time 310 in Figure 9. According to some embodiments of the present invention, the lengths of the second drive time and the second rest period can be adjusted to ensure that the first transistor (i.e., the upper bridge transistor 110 in the embodiment of Figure 13) can be turned on at the fourth time t4 under zero-voltage switching.

[0101] At the fourth time t4, the first transistor is turned on (step S1550) and continues for the third driving time. According to some embodiments of the present invention, the fourth time t4 to the fifth time t5 is the third driving time. According to some embodiments of the present invention, the length of the third driving time is related to the output voltage VOUT. As shown in Figure 13, when the current detection signal ICR exceeds the compensation signal COMP related to the output voltage VOUT, the first transistor (i.e., the upper bridge transistor 110 in the embodiment of Figure 13) is turned off.

[0102] At the fifth time t5, both the first transistor and the second transistor are simultaneously turned off (step S1560), and a third rest period continues. According to some embodiments of the present invention, the fifth time t5 to the sixth time t6 is the third rest period. According to some embodiments of the present invention, the third rest period is determined by the third delay circuit 710.

[0103] At the sixth time t6, the second transistor is turned on (step S1570), and this continues for a fourth driving time. According to some embodiments of the present invention, the sixth time t6 to the seventh time t7 is the fourth driving time. At the seventh time t7, both the first transistor and the second transistor are turned off simultaneously (step S1580), and this continues for a fourth rest time. According to some embodiments of the present invention, the seventh time t7 to the eighth time t8 is the fourth rest time.

[0104] According to one embodiment of the present invention, when the first zero-current detection circuit 720 determines that the current detection signal ICR drops to the zero-current threshold value IZC, the first zero-current detection circuit 720 generates a falling zero-current signal FZD, and at the seventh time t7, the second transistor (i.e., the lower bridge transistor 120 in the embodiment of Figure 13) is turned off. In other words, when the resonant current IR flowing through the resonant capacitor CR is zero, the second transistor (i.e., the lower bridge transistor 120 in the embodiment of Figure 13) is turned off.

[0105] At the eighth time t8, which is also the initial time t0 of the next switching cycle TSW, the first transistor (i.e., the upper bridge transistor 110 in the embodiment of Figure 13) is turned on. According to some embodiments of the present invention, the first transistor (i.e., the upper bridge transistor 110 in the embodiment of Figure 13) is turned on when the current detection signal ICR increases to the zero current threshold value IZC. In other words, the first transistor (i.e., the upper bridge transistor 110 in the embodiment of Figure 13) is turned on when the resonant current IR increases to zero.

[0106] This invention proposes a resonant power conversion circuit and its control method using pulse width modulation control, which meets market demands for a wide range of output voltage, high output power, and high conversion efficiency. Furthermore, by turning on the upper and lower bridge transistors during trough switching and zero-voltage switching, the conversion efficiency of the resonant power conversion circuit is further improved.

[0107] Although the embodiments and advantages of this disclosure have been disclosed above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of this specification. Anyone skilled in the art can understand from the disclosure of some embodiments of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claim claims and embodiments. [Simplified Explanation of the Diagram]

[0027] Figure 1 shows a schematic diagram of a power conversion circuit according to one embodiment of the present invention; Figure 2 shows a schematic diagram of a detection circuit according to one embodiment of the present invention; Figure 3 shows a schematic diagram of a control circuit according to one embodiment of the present invention; Figure 4 shows a schematic diagram of a control circuit according to another embodiment of the present invention; Figure 5 shows a waveform diagram of a power conversion circuit according to one embodiment of the present invention; Figure 6 shows a schematic diagram of a trough detection circuit according to one embodiment of the present invention; Figure 7 shows a schematic diagram of a control circuit according to another embodiment of the present invention; Figure 8 shows a waveform diagram of a power conversion circuit according to another embodiment of the present invention; Figure 9 shows a schematic diagram of a control circuit according to another embodiment of the present invention; Figure 10 shows a schematic diagram of a second zero current detection circuit according to one embodiment of the present invention; Figure 11 shows a waveform diagram of a power conversion circuit according to another embodiment of the present invention; Figure 12 shows a waveform diagram of a power conversion circuit according to another embodiment of the present invention; Figure 13 shows a waveform diagram of a power conversion circuit according to another embodiment of the present invention. Figure 14 shows a simulated waveform of a power conversion circuit according to some embodiments of the present invention; and Figure 15 shows a flowchart of a control method according to one embodiment of the present invention.

Claims

1. A power conversion circuit for converting an input voltage into an output voltage, comprising: A transformer includes a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and a resonant node; a resonant capacitor is coupled between the resonant node and a ground terminal, wherein a resonant current flows through the resonant capacitor; an upper-bridge transistor is coupled between the input voltage and the switching node; a lower-bridge transistor is coupled between the switching node and the ground terminal; and a control circuit drives the upper-bridge transistor and the lower-bridge transistor based on the output voltage and the resonant current; wherein when the resonant current reaches a first threshold value, the control circuit turns off the lower-bridge transistor, causing the upper-bridge transistor to achieve zero-voltage switching; wherein when the resonant current exceeds a second threshold value, the control circuit turns off the upper-bridge transistor; wherein the second threshold value is related to the output voltage; wherein the zero-voltage current threshold value is determined by the parasitic capacitance of the upper-bridge transistor, the parasitic capacitance of the lower-bridge transistor, the input voltage, and a dead time. The aforementioned dead time is the time from when the lower bridge transistor is turned off to when the upper bridge transistor is turned on.

2. The power conversion circuit of claim 1 further includes: A rectifier circuit is provided to convert the energy of the secondary coil into the output voltage; a feedback circuit is provided to compare the output voltage with a reference voltage to generate a compensation signal; and a detection circuit is provided to detect the resonant current to generate a current detection signal; wherein when the current detection signal is less than a zero-voltage current threshold, the control circuit turns off the lower bridge transistor, causing the upper bridge transistor to achieve zero-voltage switching; wherein when the current detection signal exceeds the compensation signal, the control circuit turns off the upper bridge transistor; wherein the current detection signal corresponds to the resonant current, and the zero-voltage current threshold corresponds to the first threshold; wherein the compensation signal corresponds to the second threshold.

3. The power conversion circuit of claim 2, wherein the detection circuit further detects the voltage across the resonant capacitor to generate a voltage detection signal; wherein when the voltage detection signal is less than a threshold voltage, the control circuit turns off the lower bridge transistor.

4. The power conversion circuit as claimed in claim 3, wherein the aforementioned control circuit further includes: An error amplifier compares the current detection signal and the zero-voltage current threshold value to generate the threshold voltage.

5. The power conversion circuit of claim 2, wherein the control circuit further includes: A valley detection circuit is used to detect that the cross voltage of the upper bridge transistor or the lower bridge transistor is at a valley voltage and generate a valley detection signal; wherein the control circuit turns on the corresponding upper bridge transistor or the lower bridge transistor based on the valley detection signal to achieve valley switching.

6. The power conversion circuit of claim 2, wherein the control circuit further includes: A zero-current detection circuit compares the aforementioned current detection signal with a zero-current threshold value to generate a zero-current detection signal; wherein when the aforementioned resonant current is zero, the aforementioned zero-current detection circuit enables the aforementioned zero-current detection signal; wherein the aforementioned control circuit, based on the enabled aforementioned zero-current detection signal, turns on the aforementioned upper bridge transistor or the aforementioned lower bridge transistor.

7. The power conversion circuit as described in claim 2, wherein the aforementioned detection circuit includes: A detection capacitor is coupled to the aforementioned resonant node; A detection resistor is coupled between the detection capacitor and the ground terminal; wherein the voltage across the detection resistor is the current detection signal.

8. The power conversion circuit as described in claim 2, wherein the aforementioned detection circuit includes: A detection resistor is coupled between the resonant capacitor and the ground terminal; wherein the voltage across the detection resistor is the current detection signal.

9. The power conversion circuit of claim 2, wherein the above-mentioned detection circuit further includes: A capacitor voltage divider circuit is connected in parallel across the resonant capacitor; wherein the capacitor voltage divider circuit divides the voltage across the resonant capacitor to generate a voltage detection signal.

10. A power conversion circuit for converting an input voltage into an output voltage, comprising: A transformer includes a primary coil and a secondary coil; a resonant capacitor through which a resonant current flows; a resonant inductor, wherein the primary coil, the resonant capacitor, and the resonant inductor are connected in series between a switching node and a ground terminal; an upper-bridge transistor coupled to the input voltage and the switching node; a lower-bridge transistor coupled to the switching node and the ground terminal; a rectifier circuit for converting the energy of the secondary coil into the output voltage; a feedback circuit for comparing the output voltage with a reference voltage to generate a compensation signal; a detection circuit for detecting the resonant current to generate a current detection signal; and a control circuit for driving the upper-bridge transistor and the lower-bridge transistor based on the current detection signal and the compensation signal flowing through it; wherein the control circuit controls the on-time of one of the lower-bridge transistors to a predetermined value; wherein the predetermined value is less than half a resonant period; wherein the resonant period is determined by the resonant capacitor and the resonant inductor. When the current detection signal exceeds the compensation signal, the control circuit shuts off the upper bridge transistor.

11. The power conversion circuit of claim 10, wherein the aforementioned detection circuit includes: A zero-current detection circuit compares the aforementioned current detection signal with a zero-current threshold value to generate a zero-current detection signal; wherein when the aforementioned resonant current is zero, the aforementioned zero-current detection circuit enables the aforementioned zero-current detection signal; wherein the aforementioned control circuit, based on the enabled aforementioned zero-current detection signal, turns on the aforementioned upper bridge transistor or the aforementioned lower bridge transistor.

12. A control method for controlling a power conversion circuit, wherein the control method includes: Within a switching cycle, the following multiple periods are included: a first drive time is defined as turning on a first transistor on the primary side of the power conversion circuit and turning off a second transistor on the primary side; after the first drive time, both the first transistor and the second transistor are turned off simultaneously for a first rest time; after the first rest time, the first transistor is turned off and the second transistor is turned on for a second drive time; after the second drive time, both the first transistor and the second transistor are turned off simultaneously for a second rest time; after the second rest time, the first transistor is turned on and the second transistor is turned off for a third drive time; after the third drive time, both the first transistor and the second transistor are turned off simultaneously for a third rest time; after the third rest time, the first transistor is turned off and the second transistor is turned on for a fourth drive time; and after the fourth drive time, both the first transistor and the second transistor are turned off simultaneously for a fourth rest time.

13. The control methods as described in Request 12 further include: When the fourth rest time of a first switching cycle ends, the first drive time of a second switching cycle begins; wherein when the first drive time of the second switching cycle turns on the first transistor, the first transistor turns on during trough switching.

14. The control method of claim 12, wherein the length of the first drive time is related to the output voltage of one of the power conversion circuits.

15. The control methods as described in Request 12 further include: The length of the first rest time is adjusted to reduce the transverse voltage of the second transistor when it is turned on during the second drive time.

16. The control method of claim 12, wherein the length of the second driving time is related to whether the first transistor can achieve zero voltage switching during the third driving time.

17. The control methods as described in Request 16 further include: The lengths of the second drive time and the second rest time are adjusted to reduce the transverse voltage of the first transistor when it is turned on during the third drive time.

18. The control method of claim 12, wherein the length of the third drive time is related to the output voltage of one of the power conversion circuits.

19. The control methods as described in Request 12 further include: The length of the third rest period is adjusted to reduce the transverse voltage of the second transistor when it is turned on during the fourth drive period.

20. The control method of claim 12, wherein the first transistor achieves zero-voltage switching when the third driving time is turned on; wherein the first transistor achieves trough switching when the first driving time is turned on.

21. The control method of claim 12, wherein the second transistor achieves zero-voltage switching when it is turned on during the second drive time and the fourth drive time.

Images