Semiconductor device and methods of formation

Abstract

Semiconductor devices include electrostatic discharge (ESD) protection devices comprising multiple discontinuous implanted portions spaced apart from various well regions within the semiconductor device substrate. The spaces between the discontinuous implanted portions provide regions within the substrate into which dopants can diffuse from the discontinuous implanted portions. Therefore, dopants can diffuse into a larger substrate region than the source / drain regions including the continuous implanted portions. As a result, the dopant concentration from the implanted portions can be reduced within the substrate. This reduces dopant buildup and concentration near the gate structure, thereby reducing the electric field strength near the gate structure. The reduced electric field strength near the gate structure mitigates damage to the ESD protection device from multiple ESD events.

Claims

1. A semiconductor device, comprising: A substrate, including a doped well region, the doped well region including a first dopant type; And an electrostatic discharge protection device, located in the substrate, comprising: a plurality of discontinuous implanted regions located in the doped well region and including a second dopant type, wherein the plurality of discontinuous implanted regions are arranged laterally in the semiconductor device; a gate structure located above the substrate and adjacent to the edge of one of the plurality of discontinuous implanted regions; a first source / drain region adjacent to a first side of the gate structure; and a second source / drain region adjacent to a second side of the gate structure, the second side being opposite to the first side, wherein the second source / drain region includes the second dopant type, wherein the second source / drain region includes a plurality of discontinuous implanted segments, each of the plurality of discontinuous implanted segments including the second dopant type, and each implanted segment being disposed in each of the plurality of discontinuous implanted regions.

2. The semiconductor device as claimed in claim 1, further comprising: The first source / drain contact is coupled to the first source / drain region; And a second source / drain contact, coupled to one of the plurality of discontinuous implant segments.

3. The semiconductor device of claim 1, wherein portions of one or more of the plurality of discontinuous implanted segments are disposed in portions of the doped well region.

4. The semiconductor device as claimed in claim 1, further comprising an oxide layer located above the plurality of discontinuous implanted segments and above a portion of the gate structure.

5. The semiconductor device of claim 1, wherein adjacent implanted regions of the plurality of discontinuous implanted regions are spaced apart from each other in the lateral direction, and wherein a portion of the doped well region is located in the space between adjacent implanted regions of the plurality of discontinuous implanted regions.

6. A method for forming a semiconductor device, comprising: A plurality of discontinuous implantation regions are formed in a doped well region of a semiconductor device substrate, wherein a portion of the doped well region is laterally located between adjacent implantation regions of the plurality of discontinuous implantation regions; a gate structure of an electrostatic discharge protection device is formed above a portion of the doped well region; and a source / drain region is formed in the plurality of discontinuous implantation regions, wherein the source / drain region is adjacent to one side of the gate structure, wherein forming the source / drain region in the plurality of discontinuous implantation regions includes: forming a mask on a portion of the doped well region; and performing an ion implantation process on the exposed portions of the plurality of discontinuous implantation regions exposed by the mask to form each of a plurality of discontinuous source / drain segments in each implantation region of the plurality of discontinuous implantation regions.

7. A semiconductor device, comprising: The substrate, including the doped well region; A first gate structure and a second gate structure are located on the substrate, wherein the first gate structure and the second gate structure are spaced apart from each other along the direction of the top surface of the substrate; A plurality of doped regions are located in the doped well region, wherein the plurality of doped regions are spaced apart from each other and arranged along the direction of the top surface of the substrate; and a source / drain region is located in a portion of each of the plurality of doped regions, wherein the source / drain region is located between the first gate structure and the second gate structure, wherein the source / drain region includes a plurality of discontinuous segments between the edges of the first gate structure and the edges of the second gate structure, and the plurality of discontinuous segments are disposed in the top portion of each of the plurality of doped regions.

Images