Memory system with high bandwidth memory buffer bridge die in routing substrate

Abstract

A memory system and assembly method are described, wherein a memory system includes: a wiring substrate; a processor on a first side of the wiring substrate; a memory die stack on the first side of the wiring substrate; and a buffer bridging die embedded in the wiring substrate, and the memory die stack is electrically connected to the processor.

Description

Technical Field

[0001] The embodiments described herein relate to memory systems, and more specifically to high-bandwidth memory systems. Prior Technology

[0002] Memory storage is an integral part of electronic devices such as personal computers, servers, game consoles, and mobile devices. It is a particularly important component in high-performance computing (HPC) and highly niche workloads requiring high bandwidth and high-speed data access, such as artificial intelligence, analytics, and edge computing. While double data rate (DDR) memory solutions can meet most practical needs, the recently introduced high bandwidth memory (HBM) provides a memory platform that achieves even higher bandwidth (while consuming less power) and a smaller form factor than DDR. This is achieved by vertically stacking multiple dynamic random access memory (DRAM) dies onto a logic die (often called a buffer die) that typically includes buffer circuitry and test logic. Compared to DDR, HBM has a wider memory bus and drives a greater number of channels at a lower data rate, thus reducing power consumption. Compared to DDR, HBM is also significantly more expensive because it requires an interposer layer to accommodate a larger number of channels and finer wiring density. Summary of the Invention

[0003] This describes a memory system (particularly an HBM system) and its assembly method, wherein a memory system includes: a wiring substrate; a processor on a first side of the wiring substrate; a memory die stack (e.g., a DRAM die stack) on the first side of the wiring substrate; and a first buffer bridge die embedded in the wiring substrate and electrically connecting the memory die stack to the processor. The first buffer bridge die may include HBM-standard circuitry, including serialization / deserialization (SerDes) circuitry, buffer circuitry, error correction circuitry, and test circuitry. Depending on the memory system configuration, the memory die stack may include any suitable number of memory dies, such as 8 or 12. According to an embodiment, the memory die stack does not include a logic die, instead offloading this circuitry to the first buffer bridge die. The memory system configurations according to embodiments can also expand the types of wiring substrates available, and this does not necessarily require a silicon substrate. Nevertheless, the cabling substrate can still be mounted on a system substrate similar to a conventional HBM configuration.

[0004] These memory die stacks can also be configured in columns and rows adjacent to one edge of the processor. In one embodiment, the memory die stack is one of a first plurality of memory die stacks in a first row. Each memory die stack in the first plurality of memory die stacks can be connected to the processor using a corresponding buffer bridge die. In an alternative configuration, each memory die stack in the plurality of memory die stacks can be connected to the processor using the first buffer bridge die. In one embodiment, a second plurality of memory die stacks can be configured in a second row adjacent to the first row. In this configuration, a second buffer bridge die can also be embedded in the wiring substrate and electrically connected to one of the second plurality of memory die stacks.

[0005] Additionally, a bridging wiring chip may be embedded in the wiring substrate to connect various buffer bridging dies. In one embodiment, a bridging wiring chip connects channel wiring from the second buffer bridging die to the first buffer bridging die. Furthermore, the bridging wiring chip may be entirely passive without any active devices, or alternatively may be an active die, in which case it may include repeaters and / or re-drivers / re-timers. Alternatively, such repeaters and / or re-drivers / re-timers may be added to a bridging wiring chip closer to the processor. According to embodiments, both the first and second buffer bridging dies may include circuitry such as serialization / deserialization (SerDes) circuitry, buffering circuitry, error correction circuitry, and test circuitry. In one embodiment, the first buffer bridging die includes repeaters and / or re-drivers / re-timers coupled to the channel wiring from the second buffer bridging die. Simple Explanation of the Diagram

[0006] [Figure 1] is a schematic cross-sectional side view of a conventional HBM system. [Figure 2A] is a schematic cross-sectional side view of a memory system including an embedded buffer bridge die according to an embodiment. [Figure 2B] is a schematic bottom view of a memory system including an embedded buffer bridge die according to an embodiment. Figures 2C to 2D are schematic bottom views of a memory system with embedded buffer bridging dies and bridging wiring chips of different sizes according to an embodiment. Figures 3A to 3E are schematic cross-sectional side views illustrating a sequence of memory systems formed using a routing substrate-first method according to an embodiment. Figures 4A to 4D are schematic cross-sectional side views illustrating the sequence of forming a memory system using the routing substrate-last method according to the embodiment. [Figure 5] is a schematic cross-sectional side view of a heterogeneous memory system including an embedded buffer bridge die according to an embodiment. [Figure 6] is a schematic cross-sectional side view of a heterogeneous memory system including an embedded buffer bridge die according to an embodiment. [Figure 7] is a schematic cross-sectional side view of a memory system including an embedded buffer bridge die according to an embodiment. Implementation

[0007] Cross-referencing of related applications

[0008] This application claims priority to U.S. Provisional Patent Application No. 63 / 571,805, filed March 29, 2024, which is incorporated herein by reference.

[0009] The embodiments describe memory systems (such as HBM systems) and methods of manufacturing them, including memory die stacks, processors, wiring substrates, and a buffer bridging die embedded in the wiring substrate. Specifically, the processor may include a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence (AI) accelerator, a neural network processor, a system-on-chip (SoC), or other units that process data. The wiring substrate may be formed of various materials, such as a redistribution layer (RDL), a silicon interposer, a glass interposer, a printed circuit board, etc. The memory die stack according to the embodiments may be strictly limited to memory dies, without lower logic (buffer) dies. Specifically, the memory die stack may be a DRAM die stack for HBM. Depending on the generation of the memory system, the number of memory dies may be 8, 12, etc. According to embodiments, the buffer bridging die may include circuitry for conventional HBM, including serialization / deserialization (SerDes), buffering, error correction, and testing. Furthermore, the buffer bridging die may include channel wiring for die-to-die connections between the memory die stack and the processor. In some embodiments, the buffer bridging die may include repeaters and / or re-drivers / re-timers to achieve longer channel coverage.

[0010] In one embodiment, the buffer / logic dies from supplier HBM are decoupled, and circuitry for buffering, serialization / deserialization, error correction, etc., is embedded in the routing substrate (e.g., RDL, interposer). This allows for longer channels, additional columns of memory die stacking, greater control over memory management, and the fabrication of heterogeneous memory solutions (e.g., HBM and DDR). The buffer bridging dies can be passive or active and may include repeater / retimer circuitry to enable longer routing from the processor to the memory. Additionally, including channel routing in the buffer bridging dies leverages the fine fabrication conditions and capabilities of active silicon wafer fabs used to manufacture the buffer bridging dies.

[0011] In another embodiment, the overall cost of the memory system can be reduced by decreasing the active silicon area. For example, one or more buffer bridging dies can replace the silicon interposer found in conventional HBM systems, thereby significantly reducing the amount of active silicon required. Furthermore, one or more buffer bridging dies can be fragmented into (multiple) passive or active bridging wiring chips for signal relay, which can provide the required fine wiring at a lower cost by completely eliminating active silicon or using cheaper processing nodes for specific circuit systems. Additionally, the buffer bridging dies according to the embodiments can be customized to minimize energy and maximize data rate, bandwidth, and channel length. The cost of active silicon can be attributed to the time and expense required to fabricate active devices in silicon, as well as the time and cost of fabricating add-on wiring structures, which typically include low-dielectric-constant materials deposited using time-consuming vapor deposition techniques. The wiring of passive bridging wiring chips and / or wiring substrates can be achieved outside of the active silicon wafer fab, thereby saving processing time and cost.

[0012] When multiple buffer bridging dies are integrated into a memory system, these dies may have the same shape and circuitry, or they may have different shapes and / or circuitry. The core circuitry (such as buffering, serialization / deserialization, and error correction) in different groups of buffer bridging dies may be similar. Some circuitry may optionally exist in a single buffer bridging die and be shared by multiple buffer bridging dies. One group of buffer bridging dies may have additional circuitry (such as repeaters and / or re-drivers / re-timers for extending channel range), while another group of buffer bridging dies in the same memory system may not have these circuitry.

[0013] Various embodiments are described with reference to schematic diagrams. However, some embodiments may be practiced without one or more of these specific details or may be practiced in combination with other known methods and configurations. Numerous specific details (e.g., specific configurations, dimensions, and procedures) are set forth in the following description to provide a comprehensive understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily detracting from the present embodiments. Throughout this specification, "one embodiment" refers to a specific feature, structure, configuration, or characteristic described in connection with that embodiment that is included in at least one embodiment. Therefore, the phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, specific features, structures, configurations, or characteristics may be combined in any suitable manner.

[0014] As used herein, the terms "over," "to," "between," "spanning," and "on" can refer to the relative position of a layer with respect to other layers. A layer that is "over," "across," "on," "joined to," or "contacts" another layer may be in direct contact with that other layer or may have one or more interlayers. A layer that is "between" (or between) layers may be in direct contact with those layers or may have one or more interlayers.

[0015] Referring now to FIG1, a cross-sectional side view of a conventional HBM system is provided. As shown, this may include a silicon interposer 102, which includes a substrate silicon base 104 and a wiring layer 106 located above the substrate silicon base. The wiring layer may include a plurality of metal redistribution lines 108, vias 110, and a dielectric layer 112. Additionally, various wiring layers and vias may form die-to-die wiring 115 between a memory die stack 120 and a processor 116, both of which may be flip-chip mounted to the same side of the silicon interposer 102 using solder bumps 114 (e.g., microbumps). The memory die stack 120 may include a plurality of memory dies 118 (such as DRAM dies) and buffer dies 122.

[0016] Additionally, the silicon interposer 102 may include through-holes 101 (such as through silicon vias, TSVs) for connection to the back side of the system substrate 130 (e.g., a printed circuit board, PCB). For example, the connection may be made using a plurality of solder bumps 171, pins, etc. The system substrate may be a package substrate or a substrate for a larger module including additional components mounted thereon. As shown, electrical wiring within the silicon interposer 102 may provide direct connections between the system substrate 130 and the processor 116 and / or memory die stack 120 (e.g., HBM), as well as die-to-die wiring 115 corresponding to channels.

[0017] Referring now to Figures 2A and 2B, Figure 2A is a schematic cross-sectional side view of an HBM system including embedded buffer bridging dies according to an embodiment; Figure 2B is a schematic bottom view of an HBM system including embedded buffer bridging dies according to an embodiment. As shown, the memory system 100 may include a wiring substrate 140, which includes one or more embedded buffer bridging dies 142A, 142B embedded therein. When the plurality of embedded buffer bridging dies 142A, 142B are present, the plurality of embedded buffer bridging dies may be electrically connected to bridging wiring chips 144 also embedded in the wiring substrate 140. As shown, memory die stacks 120A, 120B include a plurality of memory dies 118 (e.g., DRAM) and do not include stacked buffer dies. Therefore, memory die stacks 120A, 120B include only memory dies 118. The memory die stacks 120A and 120B can be electrically connected to the processor 116 using one or more embedded buffer bridge dies 142A and 142B and(multiple) bridging wiring chips 144.

[0018] The embedded buffer bridging dies 142A and 142B according to embodiments may include conventional buffer die circuitry for serialization / deserialization (SerDes), buffering, error correction, and testing. Furthermore, the buffer bridging die may include channel wiring for die-to-die connections between the memory die stack and the processor. In some embodiments, the buffer bridging die may include repeaters and / or re-drivers / re-timers to achieve longer channel coverage.

[0019] Offloading the buffer circuitry from the memory die stack to the wiring substrate 140 further reduces the channel length and facilitates the design of custom circuitry systems separate from the memory die stack, potentially resulting in additional efficiency when interfacing with the processor 116. Reducing the channel length, and including repeaters and / or re-drivers / re-timers, can facilitate longer channel lengths and include multiple rows (A, B) of memory die stacks 120A, 120B, thereby further increasing the potential bandwidth of the memory system 100.

[0020] Referring specifically to Figure 2B, two rows (A, B) of memory die stacks 120A and 120B are illustrated, each row comprising multiple columns of memory die stacks, for a total of six memory die stacks. Although two columns are illustrated, it should be understood that embodiments may include a single row of memory die stacks adjacent to the edge of processor 116, but embodiments may also facilitate the expansion of memory rows. As shown, even if a single row of memory die stacks 120A is configured adjacent to processor 116, multiple columns of embedded buffer bridge dies 142A can still electrically connect multiple memory die stacks 120A to processor 116. Therefore, by removing the conventional silicon interposer 102, not only can silicon costs be significantly reduced, but silicon area can also be saved through column-by-column and row-by-row fragmentation of embedded buffer bridge dies. In other embodiments, a single embedded buffer bridge die 142A can connect multiple embedded buffer bridge dies 142A in the same row to processor 116.

[0021] Referring again to Figures 2A and 2B, the (multiple) bridging wiring chips 144 may be purely passive and primarily used for channel routing, or they may be active and include repeaters and / or re-drivers / re-timers to facilitate longer channel lengths. It should be understood that the (multiple) passive bridging wiring chips 144 can reduce costs by eliminating the need for active silicon. Including any repeaters and / or re-drivers / re-timers in an embedded buffer bridging die may be more cost-effective, as the cost of active silicon has already been absorbed.

[0022] Depending on the memory die stack configuration, cost, and bandwidth requirements, buffer bridging dies and bridging wiring chips can be configured in various ways. Referring to the embodiment shown in Figure 2C, a single bridging wiring chip 144 can connect multiple columns and rows of buffer bridging dies. This configuration may be cost-effective, especially when there is no active silicon in the bridging wiring chip 144. In the embodiment shown in Figure 2D, the buffer bridging die can span multiple columns of memory die stacks. Similarly, a single buffer bridging wiring chip 144 can be used to connect larger buffer bridging dies 142A, 142B.

[0023] When multiple buffer bridging dies are integrated into a memory system, the shapes and circuitry of these buffer bridging dies may be identical or different. Core circuitry (such as buffering, serialization / deserialization, and error correction) in different groups of buffer bridging dies may be similar. Certain circuitry may optionally exist in a single buffer bridging die and be shared by multiple buffer bridging dies. One group of buffer bridging dies may have additional circuitry (such as repeaters and / or re-drivers / re-timers for extending channel range), while another group of buffer bridging dies in the same memory system may not have these circuitry. In one embodiment, the first embedded buffer bridging die 142A includes repeaters and / or re-drivers / re-timers for channels from the second memory die stack 120B.

[0024] Figures 3A to 3E are schematic cross-sectional side views illustrating a sequence of forming a memory system (e.g., an HBM system) using a wiring substrate-first method according to an embodiment. It should be understood that the processing sequence is significantly simplified, and variations in the procedure are conceivable. Referring now to Figure 3A, a partially fabricated wiring substrate 140 is shown, comprising a substrate 104 (such as silicon, glass, etc., the substrate including a plurality of through-holes 101) and a wiring layer 106 located above the substrate 104. The wiring layer may include a plurality of dielectric layers 112, vias 110, and metal redistribution lines 108. Additionally, a first trench 150 may be formed in the wiring layer 106 using suitable techniques.

[0025] The substrate 104 may be integrated to provide structural stability to the wiring substrate 140, but the substrate 104 is not essential. Figure 3B shows an alternative partially fabricated wiring substrate 140, which includes a plurality of dielectric layers 112, vias 110, metal redistribution lines 108, and a first trench 150, similar to that shown in Figure 3A. The dielectric layers 112, vias 110, and metal redistribution lines 108 of Figures 3A to 3B can be fabricated using suitable techniques, such as thin-film deposition techniques commonly used to form package redistribution layers (RDLs). For example, the dielectric layers 112 can be formed using liquid solution techniques (such as spin coating, slot coating, etc.), lamination techniques, or more time-consuming techniques (such as chemical vapor deposition (CVD) or physical vapor deposition (PVD)). The metal vias and redistribution lines can be formed using suitable techniques (such as electroplating, chemical vapor deposition, or lamination). Since the channel wiring represented by the die-to-die wiring in the (multiple) embedded buffer bridging dies and (multiple) optional bridging wiring wafers 144 can have a finer pitch, smaller linewidth and higher density than the surrounding redistribution lines 108, various coarser manufacturing techniques can optionally be used for the redistribution lines 108.

[0026] Referring now to Figures 3C through 3E, a processing sequence continuing the structure of Figure 3A is shown, but it will be understood that the same processing sequence can also be performed using the structure of Figure 3B. For clarity and brevity, only the processing sequence shown in Figure 3A is considered. As shown in Figure 3C, an optional bridging wiring chip 144 may be placed in an optional first trench 150, which may then be filled with a gap-filling material 152 (such as epoxy resin or other materials). The bridging wiring chip 144 may be placed face up, with the landing pad 158 facing up. The bridging wiring chip 144 may be formed of various materials. For example, the bridging wiring chip 144 may include a substrate 151 (e.g., silicon), one or more dielectric layers 153, a metal wiring layer 156, and vias (not shown). The metal wiring layer 156 and the vias may together provide die-to-die wiring for a plurality of channels. According to an embodiment, the bridging wiring chip 144 may be passive and therefore does not include active devices. In other embodiments, the bridging wiring chip 144 may optionally include active devices, such as repeaters and / or re-drivers / re-timers, at a cost.

[0027] After placing the bridging wiring die 144, applying the gap filler material 152, and forming an additional layer of wiring substrate 140, one or more second trenches 159 may be formed in the wiring substrate 140 to expose the bridging wiring die 144 and optionally expose any redistribution lines 108 (or contact pads connected thereto). Then, for example, one or more buffer bridging dies 142 may be mounted into one or more second trenches 159 using flip-chip bonding and solder bumps 164 (microbumps). As shown, the buffer bridging die 142 may include a back-side landing pad 162 coupled to the solder bumps 164, a substrate 161 (e.g., silicon), one or more dielectric layers 163, a metal wiring layer 166, and vias (not shown). Furthermore, a plurality of through-holes 165 (e.g., through-silicon vias) may extend through the substrate 161 for back-side connections. The metal wiring layer 166 and vias together provide die-to-die routing for a plurality of channels, as well as additional logic routing. According to an embodiment, the buffer bridging die 142 may be an active die, wherein active devices are formed in the substrate 161 according to standard procedures. The buffer bridging die according to an embodiment may include circuitry for conventional HBM, including serialization / deserialization (SerDes), buffering, error correction, and testing. Furthermore, the buffer bridging die may include channel routing for die-to-die connections between the memory die stack and the processor. In some embodiments, one or more of the buffer bridging dies may include repeaters and / or re-drivers / re-timers to achieve longer channel coverage.

[0028] Referring now to FIG3E, a gap filler material 170 may be formed around one or more buffer bridging dies 142 in one or more second trenches 159 to embed the buffer bridging dies 142 into the wiring substrate 140. This may be followed by additional processing, such as using solder bumps 114 to flip-chip attach one or more memory die stacks 120A, 120B and processor 116 to the same side of the wiring substrate 140. As shown, solder bumps may be mounted on landing pads 168 for embedding the buffer bridging dies 142 and landing pads coupled to redistribution lines 108 of the wiring substrate 140. A plurality of solder bumps 171 may also be placed on landing pads on the back side of the wiring substrate 140 opposite the mounted memory die stacks 120A, 120B and processor 116.

[0029] According to the embodiment, the electrical wiring path can extend directly from the solder bump 171 to the processor 116, or directly to one or more memory die stacks 120A, 120B. As shown, the electrical wiring path can also extend from the solder bump 171 to the buffer bridging die 142, and optionally to the bridging wiring chiplet 144.

[0030] The memory system 100 according to the embodiment can also be manufactured using the last-mover method of the wiring substrate. Figures 4A to 4D are schematic cross-sectional side views illustrating the sequence of forming a memory system (e.g., an HBM system) using the last-mover method of the wiring substrate according to the embodiment. It should be understood that the processing sequence is significantly simplified and program variations are conceivable. As shown in Figure 4A, a reconfigured structure is illustrated, in which the processor 116 and one or more memory die stacks 120A, 120B are encapsulated in a molding compound layer 180, and the processor 116 landing pad 182 and the memory die stack landing pad 184 are exposed. Then, one or more buffer bridging dies 142 can be mounted onto the exposed landing pads using solder bumps 114. As shown in Figure 4B, the first buffer bridging die 142 is mounted on the landing pad 182 of the processor 116 and the landing pad 184 of one or more of the innermost memory die stacks 120A. The second buffer bridging die 142 is also mounted on the landing pad 184 of one or more memory die stacks 120B in the second row, and so on for additional row expansion.

[0031] Then, the wiring substrate dielectric layer 112, via 110, and redistribution line 108 may be partially fabricated so that the landing pad 162 of the buffer bridging die 142 is still exposed, as shown in FIG4C. This can then be followed by mounting an optional bridging wiring chip 144 onto the landing pad 184 using solder bumps 164, as shown in FIG4D, after which the wiring substrate 140 is completed and the solder bumps 171 are placed.

[0032] Although the embodiments described so far have described homogeneous memory die stacks, multi-row memory die stacks, and multiple bridging wiring chips 144, various alternative configurations are conceivable.

[0033] Referring now to Figures 5 and 6, a schematic cross-sectional side view is provided illustrating a heterogeneous memory system including embedded buffer bridge dies according to an embodiment. In the embodiment shown in Figure 5, a second row of memory dies 119 may be provided adjacent to the first row of memory die stacks 120A, wherein the type of memory dies 119 is different from the type of memory dies 118 forming the memory die stack 120A. For example, the memory die stack 120A may be designed for HBM, while the memory dies 119 may be designed for DDR memory. In the embodiment shown in Figure 6, the memory die stack 120B may include fewer memory dies 118 than the memory die stack 120A, or memory dies of lower quality.

[0034] Figure 7 is a schematic cross-sectional side view of a memory system including an embedded buffer bridge die according to an embodiment. As shown, a single embedded buffer bridge die 142 may span and be electrically connected to multiple rows of memory die stacks 120A, 120B. The single embedded buffer bridge die 142 may include separate circuitry (e.g., serialization / deserialization (SerDes), buffering, error correction, and testing) for buffering separate memory die stacks 120A, 120B, and may also include partially shared circuitry for separate memory die stacks 120A, 120B. Furthermore, the buffer bridge die may include die-to-die channel wiring for die-to-die connections between memory die stacks 120A, 120B and the processor. In some embodiments, the buffer bridge die may include repeaters and / or re-drivers / re-timers to achieve longer channel coverage.

[0035] In using the various embodiments, those skilled in the art will understand that combinations or variations of the above embodiments are feasible for forming memory systems with embedded buffer bridge dies. Although embodiments have been described in specific language of structural features and / or methodological actions, it should be understood that the additional claims are not necessarily limited to the specific features or actions described. Instead, the specific features or actions disclosed should be understood as embodiments that can be used to illustrate the claims.

[0036] 100: Memory System 101: Through hole 102: Silicon Intermediate Layer 104: Silicon substrate; substrate 106: Wiring Layer 108: Redistribution Line 110: Through hole 112: Dielectric layer; Dielectric layer of wiring substrate 114: Solder bump 115: Grain-to-grain wiring 116: Processor 118: Memory chip 120: Memory chip stacking 120A: Memory die stacking 120B: Memory die stacking; Second memory die stacking 122: Buffer grains 130: System substrate 140: Wiring substrate 142: Buffered bridging die; Embedded buffered bridging die; First buffered bridging die; Second buffered bridging die 142A: Embedded buffer bridging die; buffer bridging die; first embedded buffer bridging die 142B: Embedded Buffer Bridged Diode; Buffer Bridged Diode 144: Bridging wiring chip; Passive bridging wiring chip; Buffered bridging wiring chip 150: First trench 151: Substrate 152: Gap filling material 153: Dielectric layer 156: Metallic wiring layer 158: Landing mat 159: Second trench 161: Substrate 162: Dorsal landing pad; landing pad 163: Dielectric layer 164: Solder bump 165: Through hole 166: Metallic wiring layer 168: Landing mat 170: Gap filling material 171: Solder bump 180: Molded compound layer 182: Landing mat 184: Memory chip stack landing pad; landing pad

Claims

1. A memory system comprising: a wiring substrate; a processor on a first side of the wiring substrate; a memory die stack on the first side of the wiring substrate; and a first buffer bridging die embedded in the wiring substrate and electrically connected to the processor, wherein the first buffer bridging die includes a serialization / deserialization (SerDes) circuit system, a buffer circuit system, and an error correction circuit system.

2. The memory system of claim 1, wherein the first buffer bridge die includes a test circuit system.

3. The memory system of claim 1, wherein the memory chip stack comprises eight or more memory chips.

4. The memory system of request item 1, wherein the memory die stack does not include a logic die.

5. The memory system of claim 1, wherein the wiring substrate does not include a silicon substrate.

6. The memory system of claim 1, wherein the wiring substrate is mounted on a system substrate.

7. The memory system of claim 1, wherein the memory die stack is one of a first plurality of memory die stacks in a first row.

8. The memory system of claim 7, wherein each memory die stack in the first plurality of memory die stacks is connected to the processor using a corresponding buffer bridge die.

9. The memory system of claim 7, wherein each memory die stack in the plurality of memory die stacks is connected to the processor using the first buffer bridge die.

10. The memory system of claim 7, further comprising a second plurality of memory chips stacked in a second row adjacent to the first row.

11. The memory system of claim 10, further comprising a second buffer bridge die embedded in the wiring substrate and electrically connected to one of the second memory die stacks of the second plurality of memory die stacks.

12. The memory system of claim 11, further comprising a bridging wiring chip embedded in the wiring substrate, the bridging wiring chip connecting channel wiring from the second buffer bridging die to the first buffer bridging die.

13. The memory system of claim 12, wherein the bridging wiring chip is passive and does not include active devices.

14. The memory system of claim 12, wherein the second buffer bridge die includes a serialization / deserialization (SerDes) circuit system, a buffer circuit system, an error correction circuit system, and a test circuit system.

15. The memory system of claim 14, wherein the first buffer bridging die includes a repeater coupled to the channel wiring from the second buffer bridging die.

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