High-linearity two-stage complementary amplifier

Abstract

A two-stage complementary amplifier includes a common-source input stage, a common-gate output stage, and a fifth inductor. The common-source input stage includes stacked N-type and P-type common-source amplifiers to receive a first signal and a second signal, and output a third signal and a fourth signal across a first inductor and a second inductor, respectively. The common-gate output stage includes stacked N-type and P-type common-gate amplifiers to receive the third signal and the fourth signal via a first capacitor and a second capacitor, respectively, and output a fifth signal and a sixth signal across a third inductor and a fourth inductor, respectively. The fifth inductor terminates in a load, wherein the third, fourth, and fifth inductors are closely spaced and substantially parallel to provide strong mutual coupling.

Description

[Technical Field]

[0001] This disclosure relates to amplifiers, and in particular to amplifiers with a two-stage complementary structure. [Previous Technology]

[0002] A metal-oxide-semiconductor field-effect transistor (MOST) is an active device with a source, gate, and drain, and can be used to implement an amplifier. A MOST can be an N-channel MOST (NMOST) or a P-channel MOST (PMOST). A MOST has a threshold voltage. When the gate-source voltage is greater than the threshold voltage but the gate-drain voltage is less than the threshold voltage, the MOST is in the "saturation region" and can operate effectively as an amplifier. When both the gate-source voltage and the gate-drain voltage are greater than the threshold voltage, the MOST is in the "triode region" and can operate effectively as a switch.

[0003] A MOST can be configured as a common-source amplifier to convert the input voltage received at its gate into an output current delivered through its drain, while its source is connected to a sufficiently low impedance node so that the voltage at its source remains substantially constant, regardless of the dynamic nature of the input voltage. An increase in input voltage leads to an increase in output current, and the ratio between the latter and the former is called "transconductance," which quantifies the effectiveness of the common-source amplifier in performing the input voltage to output current conversion. When "source degeneration" occurs, the impedance at the source is not low enough, and the transconductance decreases. The linearity of a common-source amplifier is measured by the degree to which the transconductance remains substantially the same as the amplitude of the input voltage increases. To maintain good linearity, the MOST must remain in the "saturation region" with the input voltage amplitude as large as possible.

[0004] A MOST amplifier can also be configured as a common-gate amplifier, receiving input current from its source and transmitting output current through its drain, while its gate is connected to a sufficiently low impedance node so that the voltage at its source and gate remains substantially constant regardless of the dynamic nature of the input current. A common-gate amplifier can effectively direct input current into output current, such that an increase in input current results in a substantially equal increase in output current.

[0005] In the cascode structure, the second MOST can be stacked on top of a first NMOST of the same type, wherein the second MOST and the first MOST share the same current path, and the output current of the first MOST becomes the input current of the second MOST. One advantage of the cascode structure is that it can provide good reverse isolation, so that changes in load conditions seen at the drain of the second MOST have only a minor effect on the first MOST.

[0006] US Patent 10,447,218 discloses an amplifier based on a hybrid differential common-source structure combining NMOST and PMOST. The disclosed amplifier can effectively mitigate the adverse effects of undesirable source degradation (caused by non-zero impedance at the source node) often present in examples of conventional common-source amplifiers. However, its linearity still faces the problem of degradation when large input voltages cause NMOST and PMOST to enter the "triple region".

[0007] However, amplifiers that maintain good linearity even when NMOST and PMOST enter the "triple pole region" are highly desirable. [Summary of the Invention]

[0008] In one embodiment, a two-stage complementary amplifier includes a common-source input stage, a common-gate output stage, and a fifth inductor. The common-source input stage includes stacked N-type common-source amplifiers and P-type common-source amplifiers for receiving a first signal and a second signal, and outputting a third signal and a fourth signal across the first inductor and the second inductor, respectively. The N-type common-source amplifier includes stacked first NMOSTs and second NMOSTs configured as common-source and stacked structures, respectively, while the P-type common-source amplifier includes stacked first PMOSTs and second PMOSTs configured as common-source and stacked structures, respectively. The common-gate output stage includes stacked N-type common-gate amplifiers and P-type common-gate amplifiers for receiving the third signal and the fourth signal via a first capacitor and a second capacitor, respectively, and outputting a fifth signal and a sixth signal across the third inductor and the fourth inductor, respectively. The N-type common-gate amplifier includes stacked third NMOSTs and fourth NMOSTs configured as common-gate and stacked structures, respectively, while the P-type common-gate amplifier includes stacked third PMOSTs and fourth PMOSTs configured as common-gate and stacked structures, respectively. The fifth inductor is connected to a load, wherein the third, fourth and fifth inductors are closely arranged and substantially parallel to have strong mutual coupling.

Implementation Method

[0010] This invention relates to amplifiers. While several exemplary embodiments considered advantageous modes for carrying out the invention are described in this specification, it should be understood that the invention can be implemented in many ways and is not limited to the specific examples described below or the specific ways in which any feature of such examples is implemented. In other instances, well-known details have not been shown or described in order to avoid obscuring the various aspects of the invention.

[0011] Those skilled in the art will understand the microelectronics-related terms and basic concepts used in this disclosure, such as "voltage," "current," "signal," "differential signal," "capacitor," "inductor," "resistor," "transistor," "metal-oxide-semiconductor transistor (MOST)," "P-channel metal-oxide-semiconductor transistor (PMOST)," "N-channel metal-oxide-semiconductor transistor (NMOST)," "alternating current (AC)," "direct current (DC)," "source," "gate," "drain," "node," "ground node," "power supply node," "cascode," "amplifier," "common-source," "common-gate," "transconductance," "admittance," and "impedance." Those skilled in the art can recognize the inductor and capacitor symbols. Those skilled in the art can recognize the MOST (NMOST or PMOST) symbol and its associated "source," "gate," and "drain" terminals. Such terms and basic concepts are obvious to those skilled in the art and therefore will not be described in detail herein.

[0012] Those skilled in the art can read circuit diagrams containing NMOST, PMOST, inductors and capacitors without needing to describe in detail how one component in the diagram is connected to another component.

[0013] In this disclosure, "DC" represents direct current and "AC" represents alternating current. A DC node is a node with a substantially stable voltage. In practice, "VDD" is the first DC node referred to as the power supply node, and "VSS" is the second DC node referred to as the ground node.

[0014] A signal is a voltage with a variable level that carries specific information and changes over time. The level of a signal at a given moment represents the state of the signal at that moment. In this disclosure, "signal" and "voltage" generally refer to the same thing and are therefore interchangeable.

[0015] In this disclosure, differential signals are widely used, wherein a signal includes a first voltage and a second voltage, indicated by the subscripts "+" and "-", respectively, having the same DC component and opposite AC components. For example, in a differential signal embodiment, signal V1 includes voltage V1+ and voltage V1-, wherein voltage V1+ and voltage V1 have the same DC component and opposite AC components.

[0016] Figure 1 illustrates a schematic diagram of a two-stage complementary amplifier (TSCA) 100 according to an embodiment of this disclosure. The two-stage complementary amplifier 100 includes a common-source input stage (CSIS) 100_1 and a common-gate output stage (CGOS) 100_2. The common-source input stage 100_1 includes a stacked N-type common-source amplifier (NCSA) 110, a P-type common-source amplifier (PCSA) 120, a first inductor L1, and a second inductor L2. The common-gate output stage 100_2 includes a stacked N-type common-gate amplifier (NCGA) 130, a P-type common-gate amplifier (PCGA) 140, capacitors C1, C2, C3, C4, a third inductor L3, a fourth inductor L4, a fifth inductor L5, and a load RL.

[0017] The N-type common-source amplifier 110 includes NMOSTs 111, 112, 113, and 114 for receiving a first signal V1 (including voltages V1+ and V1- in the differential signal embodiment) and outputting a third signal V3 across a first inductor L1 (including voltages V3+ at the first drain node DN1 and V3- at the second drain node DN2 in the differential signal embodiment). The first inductor L1 is inserted between the first drain node DN1 and the second drain node DN2. NMOSTs 111 and 112 are configured as a common-source topology to convert voltages V3+ and V3- into currents output to NMOSTs 113 and 114, respectively. NMOSTs 113 and 114 are configured as a stacked structure to guide the currents output from NMOSTs 111 and 112 to the first drain node DN1 and the second drain node DN2, respectively. NMOST 113 and 114 are biased by the first gate bias voltage VGB1. A center tap of the first inductor L1 is connected to the power supply node VDD.

[0018] The P-type common-source amplifier 120 includes PMOSTs 121, 122, 123, and 124 for receiving a second signal V2 (including voltages V2+ and V2- in the differential signal embodiment) and outputting a fourth signal V4 across a second inductor L2 (including voltages V4+ at the third drain node DN3 and V4- at the fourth drain node DN4 in the differential signal embodiment). The second inductor L2 is inserted between the third drain node DN3 and the fourth drain node DN4. PMOSTs 121 and 122 are configured as a common-source structure to convert voltages V2+ and V2- into currents output to PMOSTs 123 and 124, respectively. PMOSTs 123 and 124 are configured as a stacked structure to guide the currents output from PMOSTs 121 and 122 to the third drain node DN3 and the fourth drain node DN4, respectively. PMOST 123 and 124 are biased by the second gate bias voltage VGB2. One center tap of the second inductor L2 is connected to the ground node VSS.

[0019] In one embodiment, voltages V1+, V1-, V2+, and V2- can be mathematically modeled using the following equations:

[0020] Here, t is a time variable; is the angular frequency of the input signal; is the DC level of voltages V1+ and V1-; is the DC level of voltages V2+ and V2-; and represent the amplitude and phase of the first signal V1 as a function of time, respectively; and and represent the amplitude and phase of the second signal V2 as a function of time, respectively. In a preferred but non-limiting embodiment, and are the same, while and are the same. and together determine the bias conditions of NMOST 111, 112 and PMOST 121, 122.

[0021] The N-type common-source amplifier 110 and the P-type common-source amplifier 120 are both circuits known in the prior art, and therefore will not be explained in further detail. However, when the N-type common-source amplifier 110 is used in the prior art, the sources of NMOST 111, 112 are typically connected to the low-side DC node (e.g., ground node), and therefore suffer from source degradation (due to the non-zero impedance of the low-side DC node). Similarly, when the P-type common-source amplifier 120 is used in the prior art, the sources of PMOST 121, 122 are typically connected to the high-side DC node (e.g., power supply node), and therefore suffer from source degradation (due to the non-zero impedance of the high-side DC node). However, in the common-source input stage 100_1, the sources of NMOST 111, 112 and PMOST 121, 122 are all connected to the same center node CN. Because the first signal V1 and the second signal V2 are differential signals with opposite AC components, the voltage at the center node CN remains substantially fixed even if it has dynamic characteristics. This mitigates the source degradation and "ground bounce" or "power bounce" problems commonly found in the prior art. Furthermore, it should be noted that the common-source input stage 100_1 is an embodiment of the differential hybrid amplifier disclosed in U.S. Patent 10,447,218, and therefore will not be further explained here. Any adjustments, such as adding the "neutralizing capacitor" and / or "feedback capacitor" and / or "cross-coupling capacitor" disclosed therein, can be applied to the common-source input stage 100_1 according to the circuit designer's judgment.

[0022] The N-type common-gate amplifier 130 includes NMOSTs 131, 132, 133, and 134. NMOSTs 131 and 132 are configured as a common-gate structure, while NMOSTs 133 and 134 are configured as a stacked structure. NMOSTs 131 and 132 receive a first current I1 and a second current I2 from the first source node SN1 and the second source node SN2, respectively, and output currents to NMOSTs 133 and 134, respectively. NMOSTs 133 and 134 guide the currents output from NMOSTs 131 and 132 to the fifth drain node DN5 and the sixth drain node DN6, respectively, to establish a fifth signal V5 containing voltages V5+ and V5- at the fifth drain node DN5 and the sixth drain node DN6, respectively. A third inductor L3 is inserted between the fifth drain node DN5 and the sixth drain node DN6. One center tap of the third inductor L3 is connected to the power supply node VDD. NMOST 131 and 132 are biased by the third gate bias voltage VGB3. NMOST 133 and 134 are biased by the fourth gate bias voltage VGB4.

[0023] The P-type common-gate amplifier 140 includes PMOSTs 141, 142, 143, and 144. PMOSTs 141 and 142 are configured as common-gate amplifiers, while PMOSTs 143 and 144 are configured as stacked amplifiers. PMOSTs 141 and 142 receive a third current I3 and a fourth current I4 from the first source node SN1 and the second source node SN2, respectively, and output currents to PMOSTs 143 and 144, respectively. PMOSTs 143 and 144 guide the currents output from PMOSTs 141 and 142 to the seventh drain node DN7 and the eighth drain node DN8, respectively, to establish a sixth signal V6 containing voltages V6+ and V6- at the seventh drain node DN7 and the eighth drain node DN8, respectively. A fourth inductor L4 is inserted between the seventh drain node DN7 and the eighth drain node DN8. One center tap of the fourth inductor L4 is connected to the ground node VSS. PMOST 141 and 142 are biased by the fifth gate bias voltage V GB5. PMOST 143 and 144 are biased by the sixth gate bias voltage V GB6.

[0024] In a suitable embodiment, the common-gate output stage 100_2 further includes a fifth capacitor C5 and a sixth capacitor C6. The fifth capacitor C5 is connected in parallel with the third inductor L3 and inserted between the fifth drain node DN5 and the sixth drain node DN6. The sixth capacitor C6 is connected in parallel with the fourth inductor L4 and inserted between the seventh drain node DN7 and the eighth drain node DN8. In this way, a resonant condition can be established to increase the gain and amplify the amplitude of the fifth signal V5 and the sixth signal V6. The third gate bias voltage VGB3 and the fifth gate bias voltage VGB5 together determine the bias conditions of NMOST 131, 132 and PMOST 141, 142.

[0025] The arrangement of the third inductor L3, the fourth inductor L4, and the fifth inductor L5 exhibits strong mutual coupling. In other words, the mutual coupling K34 between the third inductor L3 and the fourth inductor L4, the mutual coupling K35 between the third inductor L3 and the fifth inductor L5, and the mutual coupling K45 between the fourth inductor L4 and the fifth inductor L5 are all very strong. Due to this strong mutual coupling, the third inductor L3, the fourth inductor L4, and the fifth inductor L5 can store magnetic energy more effectively, and the fifth signal V5 and the sixth signal V6 can be coupled more effectively to establish the seventh signal V7 at the load RL.

[0026] In one embodiment, by way of example and not limitation, the secondary complementary amplifier 100 is integrated and fabricated on a silicon substrate in a multilayer architecture using complementary metal-oxide semiconductor (CMOS) process technology. This multilayer architecture includes multiple metal layers, including an ultra-thick metal (UTM) layer and a redistribution (RDL) layer above the UTM layer. Figure 2 shows a top view of an exemplary layout of the third inductor L3, the fourth inductor L4, and the fifth inductor L5. An illustration is shown in description block 210. As shown, the third inductor L3 and the fourth inductor L4 are arranged concentrically on the UTM layer and are parallel to each other with a close spacing. This allows for a very strong mutual coupling between the third inductor L3 and the fourth inductor L4. The fifth inductor L5 is also arranged in a substantially concentric circle on the RDL layer above the third inductor L3 and the fourth inductor L4, and is also substantially parallel to the third inductor L3 and the fourth inductor L4. In this way, a very strong mutual coupling can be established between the third inductor L3 and the fifth inductor L5, as well as between the fourth inductor L4 and the fifth inductor L5.

[0027] The common-source input stage 100_1 and the common-gate output stage 100_2 are both balanced differential circuits, each of which can be divided into two essentially identical halves. In other words, NMOST 111 (113) is the same as NMOST 112 (114), PMOST 121 (123) is the same as PMOST 122 (124), NMOST 131 (133) is the same as NMOST 132 (134), PMOST 141 (143) is the same as PMOST 142 (144), and capacitor C1 (C3) is the same as capacitor C2 (C4). In one embodiment, capacitor C1 (C2) is the same as capacitor C3 (C4).

[0028] By way of example, but not limitation, the ground node VSS is 0 volts; the power supply node VDD is 3 volts; NMOST 111, 112, 113, 114, 131, 132, 133, 134 have approximately the same critical voltage of 0.4 volts; PMOST 121, 122, 123, 124, 141, 142, 143, 144 have approximately the same critical voltage of 0.4 volts; 2 volts; 1 volt; 2.7 volts; 0.3 volts; 2 volts; 2.7 volts; 1 volt; 0.3 volts. In this way, all transistors in the two-stage complementary amplifier 100 can be biased in the saturation region.

[0029] In one embodiment, by way of example but not limitation, NMOST 111 (112) and PMOST 121 (122) are designed to be appropriately sized to have substantially the same transduction. Similarly, NMOST 131 (132) and PMOST 141 (142) are designed to be appropriately sized to have substantially the same transduction. This arrangement will be readily understood by those skilled in the art and will therefore not be described in further detail.

[0030] In one embodiment, by way of example but not limitation, capacitors C1, C2, C3, and C4 have the same capacitance value Ci; the first inductor L1 and the second inductor L2 have the same inductance value Li; and the transconductance is significantly greater than the admittance of capacitors C1, C2, C3, and C4, in other words:

[0031] In other words, the impedances of NMOST 131 (PMOST 141) and NMOST 132 (PMOST 142) observed from the first source node SN1 and the second source node SN2 are much smaller than the impedances of capacitors C1, C2, C3 and C4.

[0032] The inductance value Li and the capacitance value Ci are selected such that the first inductor L1 resonates with capacitors C1 and C2, and the second inductor L2 resonates with capacitors C3 and C4. Mathematically, the condition for resonance is satisfied if the following equation holds:

[0033] At resonance, the reactance of the first inductor L1 (second inductor L2) is largely canceled out by the reactance of capacitors C1 (C3) and C2 (C4). However, due to the inherent resistance impairment of the first inductor L1, the second inductor L2, and capacitors C1, C2, C3, and C4, as well as their non-zero values, the N-type common-source amplifier 110 and the P-type common-source amplifier 120 still have finite impedance. In one embodiment, the non-zero value impairment of the impedance will dominate and can be considered as the equivalent series resistance (ESR) of capacitors C1, C2, C3, and C4. By applying the series-to-parallel conversion easily understood by those skilled in the art, it can be seen that the impedances from the drains of NMOST 113, 114 and PMOST 123, 124 to drain nodes DN1, DN2, DN3, and DN4 are all approximately [value missing].

[0034] By applying communication analysis, we can obtain the following expression:

[0035] Here, is the gain of the N-type common-source amplifier 110, is the gain of the P-type common-source amplifier 120, is the phase shift caused by the N-type common-source amplifier 110, and is the phase shift caused by the P-type common-source amplifier 120. Similarly, () is approximately equal to the transconductance of NMOST 111 (PMOST 121) multiplied by the impedance from the N-type common-source amplifier 110 (P-type common-source amplifier 120) to the first drain node DN1 (third drain node DN3), and can be approximated by the following expression:

[0036] In terms of AC analysis, the first current I1 and the third current I3 are approximately the same, and are approximately equal to the AC portion of the voltage V3+ multiplied by the admittance of capacitor C1, with a phase shift of 90 degrees. In other words:

[0037] Similarly, the second current I2 is approximately the same as the fourth current I4, and can be approximated by the following expression:

[0038] The above analysis is based on the assumption that NMOST 131, 132 and PMOST 141, 142 remain in the saturation region and therefore exhibit impedance. However, as the amplitudes of and increase, NMOST 131, 132 and PMOST 141, 142 eventually enter the triode region. Fortunately, when this happens, NMOST 131, 132 and PMOST 141, 142 effectively become resistors with a resistance value equal to . In other words, even if the underlying physics and operating regions of NMOST 131, 132 and PMOST 141, 142 change, the above expression remains valid. In this way, high linearity can be achieved. Although NMOST 111, 112 and PMOST 121, 122 eventually enter the triode region (as the amplitudes of and increase), this situation is unavoidable in any common-source amplifier circuit. However, in a two-stage complementary amplifier, the nonlinearity of the output stage will dominate the nonlinearity of the input stage because the output stage receives a larger amplitude due to the amplification of the input stage. However, in the two-stage complementary amplifier 100, since the common-gate output stage 100_2 can present approximately the same load to the common-source input stage 100_1 regardless of the amplitude of the input signal (i.e., I1 and I2), and although NMOSTs 131, 132, 133, and 134 may enter the triode region, the first current I1, the second current I2, the third current I3, and the fourth current I4 can still be linearly guided directly to the fifth drain node DN5, the sixth drain node DN6, the seventh drain node DN7, and the eighth drain node DN8, respectively. Therefore, the linearity of the output stage can be greatly improved.

[0039] It should be noted that Formula XII and Formula XIII are used in the case of AC signal, and the DC parts of the first current I1, the second current I2, the third current I3 and the fourth current I4 are omitted.

[0040] Those skilled in the art may choose to stack additional transistors in a stacked configuration to enhance reverse isolation or reduce stress on the transistors.

[0041] It will be readily understood by those skilled in the art that various changes and modifications can be made to the apparatus and methods described in this disclosure without departing from the teachings of this disclosure. Therefore, this disclosure should not be construed as being limited only to the scope and limits of the appended claims. [Simplified Explanation of the Diagram]

[0009] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below: Figure 1 shows a schematic diagram of a two-stage complementary amplifier according to an embodiment of this disclosure; and Figure 2 shows a top view of an exemplary layout of the three inductors used in the two-stage complementary amplifier of Figure 1. [Biomaterial Storage]

[0043] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A two-stage complementary amplifier, comprising: a common-source input stage including a stacked N-type common-source amplifier and a stacked P-type common-source amplifier for receiving a first signal and a second signal, and outputting a third signal and a fourth signal respectively across a first inductor and a second inductor; a common-gate output stage including a stacked N-type common-gate amplifier and a stacked P-type common-gate amplifier for receiving the third signal and the fourth signal respectively through a first capacitor and a second capacitor, and outputting a fifth signal and a sixth signal respectively across a third inductor and a fourth inductor; and a fifth inductor terminated in a load, wherein the third inductor, the fourth inductor and the fifth inductor are closely arranged and substantially parallel to have strong mutual coupling.

2. The dual-stage complementary amplifier as claimed in claim 1, wherein the N-type common-source amplifier includes a stacked first N-channel metal-oxide-semiconductor field-effect transistor (NMOST) and a second NMOST; the first NMOST is configured as a common-source structure to receive the first signal from a gate of the first NMOST and output a first internal current through a drain of the first NMOST; and the second NMOST is configured as a stacked structure to guide the first internal current received from a source of the second NMOST to the first inductor through a drain of the second NMOST.

3. The dual-stage complementary amplifier as claimed in claim 2, wherein the P-type common-source amplifier includes a stacked first P-channel metal-oxide-semiconductor field-effect transistor (PMOST) and a second PMOST; the first PMOST is configured in a common-source configuration to receive the second signal from a gate of the first PMOST and output a second internal current via a drain of the first PMOST; and the second PMOST is configured in a stacked configuration to guide the second internal current received from a source of the second PMOST to the second inductor via a drain of the second PMOST.

4. The two-stage complementary amplifier as claimed in claim 1, wherein the N-type common-gate amplifier includes a stacked first NMOST and a second NMOST; the first NMOST is configured as a common-gate structure to receive a first current from a source node via a source of the first NMOST and output a first internal current via a drain of the first NMOST; the second NMOST is configured as a stacked structure to guide the first internal current from a source of the second NMOST via a drain of the second NMOST to the third inductor; and the source node is coupled to the third signal and the fourth signal via the first capacitor and the second capacitor, respectively.

5. The two-stage complementary amplifier as claimed in claim 4, wherein the P-type common-gate amplifier includes a stacked first PMOST and a second PMOST; the first PMOST is configured in a common-gate configuration to receive a second current from the source node via a source of the first PMOST and output a second internal current via a drain of the first PMOST; and the second PMOST is configured in a stacked configuration to guide the second internal current from a source of the second PMOST via a drain of the second PMOST to the fourth inductor.

6. The two-stage complementary amplifier as claimed in claim 1, wherein the first inductor and the first capacitor form a resonant network at a frequency approximately equal to that of the first signal and the second signal.

7. The two-stage complementary amplifier as claimed in claim 1, wherein the second inductor and the second capacitor form a resonant network at a frequency approximately equal to that of the first signal and the second signal.

8. The two-stage complementary amplifier as claimed in claim 1 further includes a third capacitor and a fourth capacitor, the third capacitor being connected in parallel with the third inductor to resonate with the third inductor, and the fourth capacitor being connected in parallel with the fourth inductor to resonate with the fourth inductor.

9. The two-stage complementary amplifier as claimed in claim 1, wherein a center tap of the first inductor is connected to a power supply node, and a center tap of the second inductor is connected to a ground node.

10. The two-stage complementary amplifier as claimed in claim 1, wherein a center tap of the third inductor is connected to a power supply node, and a center tap of the fourth inductor is connected to a ground node.

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