Semiconductor device and method for preparing the same

Abstract

This disclosure provides a semiconductor device comprising a source / drain structure, a dielectric layer, a plurality of first contact structures, a polysilicon stack, and a second contact structure. The source / drain structure is disposed on a semiconductor substrate. The dielectric layer is disposed on the source / drain structure. The plurality of first contact structures extend through the dielectric layer and the source / drain structure. The second contact structure is disposed on the polysilicon stack. The polysilicon stack and the second contact structure are disposed between two of the plurality of first contact structures. Each of the plurality of first contact structures includes a first pad and a first conductive layer surrounded by the first pad.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 19 / 004,572 (i.e., priority date "December 30, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device having two types of contacts and a method for fabricating the same. Prior Technology

[0003] Semiconductor components play a vital role in many modern applications. With advancements in electronic technology, semiconductor components are becoming increasingly smaller, offering more functions and incorporating more integrated circuits. Due to this miniaturization, various types and sizes of semiconductor components, providing different functions, are integrated and packaged into single modules. Furthermore, numerous manufacturing processes are implemented to integrate these diverse types of semiconductor components.

[0004] However, the manufacturing and integration of semiconductor devices involves many complex steps and operations. The integration of semiconductor devices is becoming increasingly complex. This increased complexity in manufacturing and integrating semiconductor devices can lead to defects. Therefore, continuous improvement of semiconductor device manufacturing processes is necessary to address these issues.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of the "prior art" of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a source / drain structure, a dielectric layer, a plurality of first contact structures, a polysilicon stack, and a second contact structure. The source / drain structure is disposed on a semiconductor substrate. The dielectric layer is disposed on the source / drain structure. The plurality of first contact structures extend through the dielectric layer and the source / drain structure. The second contact structure is disposed on the polysilicon stack. The polysilicon stack and the second contact structure are disposed between two of the plurality of first contact structures. Each of the plurality of first contact structures includes a first pad and a first conductive layer surrounded by the first pad.

[0007] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes: forming a source / drain structure on a semiconductor substrate; forming a dielectric layer on the source / drain structure; forming a plurality of first contact structures penetrating the dielectric layer and the source / drain structure; and forming a second contact structure between two of the plurality of first contact structures, wherein the second contact structure is formed on the source / drain structure. The step of forming the plurality of first contact structures penetrating the dielectric layer and the source / drain structure includes: performing a first etching process to form a plurality of first openings penetrating the dielectric layer and the source / drain structure and extending into the semiconductor substrate; forming a first pad covering the sidewalls and bottom surface of each of the plurality of first openings; forming a second pad on the first pad; and after forming the second pad, filling a remaining portion of the plurality of first openings with a first conductive layer. The first pad and the second pad are made of different materials.

[0008] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a source / drain structure, a dielectric layer, a first contact structure, a polysilicon stack, and a second contact structure. The semiconductor substrate includes an array region and a peripheral region. The dielectric layer is disposed on the source / drain structure. The first contact structure is disposed on the peripheral region and extends through the dielectric layer. The first contact structure includes a first pad and a first conductive layer. The first pad comprises tantalum, tantalum nitride, or a combination thereof. The first conductive layer is disposed on the first pad and comprises copper (Cu).

[0009] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes: forming a source / drain structure on a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; forming a dielectric layer on the source / drain structure; forming a first contact structure within the peripheral region, and the first contact structure penetrating the dielectric layer; forming a polysilicon stack within the array region and on the source / drain structure; and forming a second contact structure on the polysilicon stack. The step of forming the first contact structure within the peripheral region, and the first contact structure penetrating the dielectric layer, includes: performing a first etching process to form a first opening penetrating the dielectric layer; forming a first pad, the first pad covering the sidewalls and bottom surface of the first opening; forming a second pad on the first pad, wherein the first pad and the second pad are made of different materials; and after forming the second pad, filling a remaining portion of the first opening with a first conductive layer.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] For a better understanding of all aspects of this disclosure, please refer to the following detailed description and diagrams. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily enlarged or reduced for clarity of discussion. Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 2 is a schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 3 is a schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 4 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 5 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 6 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 7 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 8 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 9 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 10 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 11 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 12 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 13 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 14 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 15 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 16 shows an intermediate stage in the formation of a semiconductor device according to some embodiments. Figure 17 shows an intermediate stage in the formation of a semiconductor element according to some other embodiments. Figure 18 shows an intermediate stage in the formation of a semiconductor device according to some other embodiments. Figure 19 shows an intermediate stage in the formation of a semiconductor device according to some other embodiments. Figure 20 shows an intermediate stage in the formation of a semiconductor element according to some other embodiments. Figure 21 is a flowchart of a method for fabricating a semiconductor element according to some embodiments. Figure 22 is a flowchart of a method for fabricating a semiconductor element according to some embodiments. Implementation

[0012] The following disclosure provides many different embodiments or examples to implement different features of the invention. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and should not be construed as limiting the scope of this disclosure. For example, when the description refers to a first feature being formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where other features are formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or designations may be repeated in various examples in this disclosure. These repetitions are for simplification and clarity and are not intended to limit the relationship between the different embodiments and / or configurations discussed.

[0013] Furthermore, the spatially related terms used herein, such as "below," "under," "down," "above," "up," and similar terms, are for the convenience of describing the relationship between one element or feature shown in the diagram and one or more other elements or features. These spatially related terms are used to cover different orientations of the device in use or operation, in addition to the orientation depicted in the diagram. The instrument may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used therein can be interpreted accordingly.

[0014] Figures 1, 2, and 3 show schematic cross-sectional views of semiconductor elements 100A, 100B, and 100C according to some embodiments. In some embodiments, semiconductor element 100A, semiconductor element 100B, semiconductor element 100C, or a combination thereof, is part of dynamic random access memory (DRAM).

[0015] The entire DRAM comprises numerous electronic components. These electronic components are disposed on the array region DA (also known as the dense region) and the peripheral region LA (also known as the sparse region) of the semiconductor substrate 101. Semiconductor elements 100A and 100B are disposed on the array region DA. A portion of semiconductor element 100C is disposed within the peripheral region LA, while another portion of semiconductor element 100C is disposed within the array region DA.

[0016] Semiconductor devices 100A, 100B, and 100C include a source / drain structure 109 disposed on a semiconductor substrate 101, and a dielectric layer 107 disposed on the source / drain structure 109. The source / drain structure 109 includes an epitaxial layer 103 and a silicate layer 105 disposed on the epitaxial layer 103. In some embodiments, the epitaxial layer 103 is completely covered by the silicate layer 105, such that the epitaxial layer 103 is separated from the dielectric layer 107 by the silicate layer 105. In some embodiments, the epitaxial layer 103 comprises silicon (Si), and the silicate layer 105 comprises cobalt silicate (CoSi x).

[0017] Semiconductor devices 100A and 100C further include a gate structure 125 that penetrates the dielectric layer 107, the silicate layer 105, and the epitaxial layer 103, and faces the semiconductor substrate 101. The gate structure 125 is disposed within the array region DA. In some embodiments, the gate structure 125 is a recessed gate structure. The gate structure 125 extends into the semiconductor substrate 101, and the bottom surface of the gate structure 125 is within the semiconductor substrate 101.

[0018] Semiconductor devices 100A, 100B, and 100C further include a polysilicon stack 139 and a contact structure 159 disposed directly above the polysilicon stack 139. The polysilicon stack 139 and the contact structure 159 are disposed within the array region DA. The polysilicon stack 139 is disposed within the dielectric layer 107 and on the source / drain structure 109. In some embodiments, the polysilicon stack 139 and the contact structure 159 are surrounded by the dielectric layer 107. In semiconductor devices 100A and 100C, the polysilicon stack 139 and the contact structure 159 are disposed between gate structures 125.

[0019] The polycrystalline silicon stack 139 includes a first polycrystalline silicon layer 133 and a second polycrystalline silicon layer 135 disposed on and surrounded by the first polycrystalline silicon layer 133. In some embodiments, the second polycrystalline silicon layer 135 is separated from the dielectric layer 107 by the first polycrystalline silicon layer 133. In some embodiments, the first polycrystalline silicon layer 133 is undoped, and the second polycrystalline silicon layer 135 is doped. In some embodiments, the second polycrystalline silicon layer 135 is doped with arsenic (As), boron (B), or phosphorus (P).

[0020] The first polycrystalline silicon layer 133 has a U-shaped profile in the cross-sectional view. The first polycrystalline silicon layer 133 contacts the sidewalls and bottom surface of the second polycrystalline silicon layer 135. In other words, the first polycrystalline silicon layer 133 has a recess in the cross-sectional view, and the second polycrystalline silicon layer 135 fills this recess. The top portion of the first polycrystalline silicon layer 133 and the top portion of the second polycrystalline silicon layer 135 contact the contact structure 159. The second polycrystalline silicon layer 135 is surrounded by the first polycrystalline silicon layer 133 and the contact structure 159.

[0021] The contact structure 159 includes a barrier layer 153 and a conductive layer 155. The conductive layer 155 is disposed on and surrounded by the barrier layer 153. In some embodiments, the barrier layer 153 comprises titanium (Ti), titanium nitride (TiN), or a combination thereof. In some embodiments, the conductive layer 155 comprises tungsten (W). In some embodiments, the conductive layer 155 is separated from the polycrystalline silicon stack 139 by the barrier layer 153. In some embodiments, the barrier layer 153 has a lower portion 153L, and the lower portion 153L is surrounded by the polycrystalline silicon stack 139. In other words, the second polycrystalline silicon layer 135 has a recess in the cross-sectional view, and the lower portion 153L is disposed in the recess of the second polycrystalline silicon layer 135. In some embodiments, the contact structure 159 is electrically connected to the source / drain structure 109 by the polycrystalline silicon stack 139.

[0022] The semiconductor device 100B further includes a contact structure 207. The contact structure 207 includes a first pad 201, a second pad 203, and a conductive layer 205. The first pad 201 is disposed on the semiconductor substrate 101 and contacts the semiconductor substrate 101, the epitaxial layer 103, the silicate layer 105, and the dielectric layer 107. The second pad 203 is disposed on and surrounded by the first pad 201. The conductive layer 205 is disposed on and surrounded by the second pad 203.

[0023] The first pad 201 and the second pad 203 have a U-shaped profile in the cross-sectional view. In some embodiments, the thickness 201BT of the bottom portion of the first pad 201 is greater than or equal to the thickness 201ST of the sidewall portion of the first pad 201. In some embodiments, the thickness 203BT of the bottom portion of the second pad 203 is greater than or equal to the thickness 203ST of the sidewall portion of the second pad 203. In some embodiments, the thickness 201BT of the bottom portion of the first pad 201 is greater than or equal to the thickness 203BT of the bottom portion of the second pad 203. In some embodiments, the thickness 201ST of the sidewall portion of the first pad 201 is greater than or equal to the thickness 203ST of the sidewall portion of the second pad 203. In some embodiments, the width 205W of the conductive layer 205 is greater than the thickness 203ST of the sidewall portion of the second pad 203. In some embodiments, the width 205W of the conductive layer 205 is greater than the thickness 201ST of the sidewall portion of the first pad 201.

[0024] In some embodiments, the first pad 201 and the second pad 203 are collectively referred to as a barrier layer. In some embodiments, the first pad 201 may be omitted.

[0025] The contact structure 207 is disposed within the array region DA. In some embodiments, as shown in FIG2, the contact structure 159 and the polysilicon stack 139 are disposed between the contact structure 207.

[0026] Semiconductor device 100C further includes a contact structure 307. The contact structure 307 includes a first pad 301, a second pad 303, and a conductive layer 305. The first pad 301 is disposed on and contacts the source / drain structure 109 and the dielectric layer 107. The second pad 303 is disposed on and surrounded by the first pad 301. The conductive layer 305 is disposed on and surrounded by the second pad 303. As shown in FIG3, the contact structure 307 is disposed within the peripheral region LA.

[0027] In some embodiments, the first pad 301 and the second pad 303 are collectively referred to as a barrier layer. In some embodiments, the first pad 301 may be omitted.

[0028] In some embodiments, the first pad 301 and the first pad 201 comprise the same material. In some embodiments, the second pad 303 and the second pad 203 comprise the same material. In some embodiments, the conductive layer 305 and the conductive layer 205 comprise the same material.

[0029] In some embodiments, the first pad 301 and the first pad 201 are made of tantalum (Ta), tantalum nitride (TaN), or a combination thereof. In some embodiments, the second pad 303 and the second pad 203 are made of CuMn. In some embodiments, the conductive layer 305 and the conductive layer 205 are made of Cu.

[0030] The first pad 301 and the second pad 303 have a U-shaped profile in the cross-sectional view. In some embodiments, the thickness 301BT of the bottom portion of the first pad 301 is greater than or equal to the thickness 301ST of the sidewall portion of the first pad 301. In some embodiments, the thickness 303BT of the bottom portion of the second pad 303 is greater than or equal to the thickness 303ST of the sidewall portion of the second pad 303. In some embodiments, the thickness 301BT of the bottom portion of the first pad 301 is greater than or equal to the thickness 303BT of the bottom portion of the second pad 303. In some embodiments, the thickness 301ST of the sidewall portion of the first pad 301 is greater than or equal to the thickness 303ST of the sidewall portion of the second pad 303. In some embodiments, the width 305W of the conductive layer 305 is greater than the thickness 303ST of the sidewall portion of the second pad 303. In some embodiments, the width 305W of the conductive layer 305 is greater than the thickness 301ST of the sidewall portion of the first pad 301.

[0031] In some embodiments, the width 205W of the conductive layer 205 is smaller than the width 305W of the conductive layer 305. In some embodiments, the thickness 201ST of the sidewall portion of the first pad 201 is smaller than the thickness 301ST of the sidewall portion of the first pad 301, and the thickness 203ST of the sidewall portion of the second pad 203 is smaller than the thickness 303ST of the sidewall portion of the second pad 303. In some embodiments, the depth 207D of the contact structure 207 is greater than the depth 307D of the contact structure 307.

[0032] See Figures 4 through 16. Figures 4 through 16 show intermediate stages of forming a semiconductor device 100B according to some embodiments of this disclosure.

[0033] As shown in Figure 4, a source / drain structure 109 comprising an epitaxial layer 103 and a silicate layer 105 is formed on a semiconductor substrate 101.

[0034] In some embodiments, the semiconductor substrate 101 is a semiconductor wafer, such as a silicon wafer. Alternatively, the semiconductor substrate 101 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0035] The source / drain structure 109 may be a raised or elevated source / drain structure formed on the semiconductor substrate 101. In some embodiments, the epitaxial layer 103 of the source / drain structure 109 comprises silicon, and the silicate layer 105 of the source / drain structure 109 comprises cobalt silicide (CoSi x). In some embodiments, the epitaxial layer 103 is formed by an epitaxial growth method, which may include metal-organic chemical vapor deposition (MOCVD), vapor-phase epitaxy (VPE), molecular-beam epitaxy (MPE), liquid-phase epitaxy (LPE), or other suitable processes. Furthermore, in some embodiments, the silica layer 105 is formed by a process that includes depositing a metal layer (e.g., cobalt (Co)) and annealing the metal layer so that the metal layer can react with the epitaxial layer 103 to form a silica layer 105.

[0036] According to some embodiments, after forming the source / drain structure 109, a dielectric layer 107 is formed on the silicon layer 105 of the source / drain structure 109. In some embodiments, the dielectric layer 107 comprises silicon oxide, silicon nitride, silicon oxynitride, a dielectric material having a low dielectric constant (low-k), or a combination thereof. The dielectric layer 107 can be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0037] As shown in FIG. 5, an opening 120 is formed through the dielectric layer 107 and the source / drain structure 109. In some embodiments, the opening 120 extends into the upper portion of the semiconductor substrate 101, such that the bottom surface of the opening 120 is located within the semiconductor substrate 101. The opening 120 can be formed by an etching process, and the location of the opening 120 can be defined by a patterned mask (not shown) formed on the dielectric layer 107. The etching process may include a dry etching process, a wet etching process, or a combination thereof. After the etching process, the patterned mask on the dielectric layer 107 is removed.

[0038] As shown in FIG6, a padding material 201a is formed within the opening 120 and on the top surface 107TS of the dielectric layer 107 to line the opening 120. In some embodiments, the padding material 201a is made of Ta, and the padding material 201a is formed by a deposition process, such as CVD, ALD, PVD, or a combination thereof. In other embodiments, the padding material 201a is made of TaN. In various embodiments, the padding material 201a is made of both Ta and TaN.

[0039] As shown in FIG7, a liner material 203a is formed within the opening 120 and on the liner material 201a. In some embodiments, the liner material 203a is made of CuMn and is formed by a deposition process, such as CVD, ALD, PVD or a combination thereof.

[0040] As shown in Figure 8, a conductive material 205a is formed on the pad material 203a to fill the opening 120. The conductive material 205a is separated from the dielectric layer 107, the source / drain structure 109, and the semiconductor substrate 101 by the pad material 201a and the pad material 203a. In some embodiments, the conductive material 205a is made of Cu, and the conductive material 205a is formed by a deposition process, such as CVD, ALD, PVD, sputtering, plating, or a combination thereof.

[0041] As shown in Figure 9, a planarization process, such as a CMP process, is performed on the pad material 201a, pad material 203a, and conductive material 205a to remove any excess material on the top surface 107TS of the dielectric layer 107, so that the remaining pad material 201a, the remaining pad material 203a, and the remaining conductive material 205a become the first pad 201, the second pad 203, and the conductive layer 205, respectively. Therefore, a contact structure 207 comprising the first pad 201, the second pad 203, and the conductive layer 205 is obtained.

[0042] As shown in FIG. 10, an opening 130 is formed through the dielectric layer 107. In some embodiments, the opening 130 is located between the contact structures 207, and the opening 130 partially exposes the top surface 105TS of the silicon layer 105. The opening 130 is formed by an etching process, and the location of the opening 130 can be defined by a patterned mask (not shown) formed on the dielectric layer 107 and the contact structures 207. In some embodiments, the etching process includes a dry etching process, a wet etching process, or a combination thereof. After the etching process, the patterned mask is removed.

[0043] As shown in FIG11, a polycrystalline silicon material 133a is formed within the opening 130, and the polycrystalline silicon material 133a extends onto the top surface 107TS of the dielectric layer 107. In some embodiments, the polycrystalline silicon material 133a is formed by a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0044] As shown in FIG12, a polycrystalline silicon material 135a is formed within the opening 130 and on the polycrystalline silicon material 133a. In some embodiments, the polycrystalline silicon material 135a is formed by a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0045] In some embodiments, the polycrystalline silicon material 133a is undoped, and the polycrystalline silicon material 135a is doped with arsenic (As), boron (B), or phosphorus (P). In some embodiments, the polycrystalline silicon material 135a is in-situ doped during the deposition process. In some embodiments, the polycrystalline silicon material 135a is not in-situ doped, but rather doped by an implantation process.

[0046] As shown in Figure 13, an etch-back process is performed on polycrystalline silicon materials 133a and 135a to remove portions of polycrystalline silicon materials 133a and 135a on the top surface 107TS of the dielectric layer 107, and to remove portions of polycrystalline silicon materials 133a and 135a occupying the portion above the opening 130. As shown, the remaining portions of polycrystalline silicon materials 133a and 135a form a polycrystalline silicon stack 139. More specifically, the remaining portion of polycrystalline silicon material 133a becomes the first polycrystalline silicon layer 133, and the remaining portion of polycrystalline silicon material 135a becomes the second polycrystalline silicon layer 135.

[0047] It should be noted that an opening 140 is formed on the second polycrystalline silicon layer 135. The opening 140 is a part of the opening 130.

[0048] In some embodiments, the etch-back process includes a dry etching process, a wet etching process, or a combination thereof. Furthermore, the polycrystalline silicon material 133a may be etched back before the deposition process forming the polycrystalline silicon material 135a is performed.

[0049] It should be noted that although only two polycrystalline silicon layers (i.e., the first polycrystalline silicon layer 133 and the second polycrystalline silicon layer 135) are shown in the polycrystalline silicon stack 139, the polycrystalline silicon stack 139 may have more than two polycrystalline silicon layers. In some embodiments, the process of forming the first polycrystalline silicon layer 133 and the second polycrystalline silicon layer 135 is repeated in a cyclic manner to form more polycrystalline silicon layers on the second polycrystalline silicon layer 135. For example, an undoped third polycrystalline silicon layer is formed on the second polycrystalline silicon layer 135, and a fourth polycrystalline silicon layer doped with arsenic, boron, or phosphorus is formed on the third polycrystalline silicon layer.

[0050] As shown in Figure 14, a barrier material 153a is formed within the opening 130, and the barrier material 153a fills the opening 140. The barrier material 153a is further formed on the polycrystalline silicon stack 139 and extends to the top surface 107TS of the dielectric layer 107. In some embodiments, the barrier material 153a comprises titanium (Ti), titanium nitride (TiN), or a combination thereof. In some embodiments, the barrier material 153a is formed by a deposition process, such as CVD, PVD, ALD, or a combination thereof.

[0051] As shown in Figure 15, an etching process is performed on the barrier material 153a to remove excess portions of the barrier material 153a on the top surface 107TS of the dielectric layer 107. In some embodiments, the excess portions of the barrier material 153a are removed by an etch-back process or a planarization process (e.g., CMP, polishing, or similar processes). After the etching process, the remaining portion of the barrier material 153a becomes the barrier layer 153.

[0052] The portion of the barrier layer 153 disposed within the opening 140 forms the lower portion 153L of the barrier layer 153. The lower portion 153L is surrounded by the second polycrystalline silicon layer 135. In some embodiments, the barrier layer 153 directly contacts the first polycrystalline silicon layer 133, the second polycrystalline silicon layer 135, and the dielectric layer 107.

[0053] As shown in FIG16, the remaining portion of the opening 130 is filled with conductive material 155a, and the conductive material 155a extends to the top surface 107TS of the dielectric layer 107. In some embodiments, the conductive material 155a comprises tungsten (W). In some embodiments, the conductive material 155a is formed by a deposition process, such as CVD, PVD, ALD, or a combination thereof.

[0054] Subsequently, a planarization process is performed on the conductive material 155a to remove the excess portion of the conductive material 155a on the top surface 107TS of the dielectric layer 107. After the planarization process, the remaining conductive material 155a becomes the conductive layer 155. As shown in FIG2, a junction structure 159 surrounded by the dielectric layer 107 and including the barrier layer 153 and the conductive layer 155 is formed on the polysilicon stack 139.

[0055] In some embodiments, the planarization process may include a CMP process. After obtaining the contact structure 159, a semiconductor device 100B is obtained. Since the polysilicon stack 139 has an undoped polysilicon layer (i.e., a first polysilicon layer 133) and a doped polysilicon layer on top of the undoped polysilicon layer (i.e., a second polysilicon layer 135), and the polysilicon stack 139 is formed between the source / drain structure 109 and the contact structure 159, the contact resistance can be reduced. As a result, the device performance of the semiconductor device 100B can be improved.

[0056] Regarding semiconductor device 100A, the intermediate stages for forming semiconductor device 100A are similar to the intermediate stages for forming semiconductor device 100B. Specifically, the intermediate stages for forming semiconductor device 100B shown in Figures 4, 5, and 10 to 16 are substantially the same as the intermediate stages for forming semiconductor device 100A. After the process shown in Figure 5, a gate structure 125 is formed within the opening 120, except for the intermediate stages shown in Figures 6 to 9. In some embodiments, the gate structure 125 is a recessed gate structure of a DRAM. Each gate structure 125 includes a gate dielectric (not shown) and a gate electrode (not shown) disposed on and surrounded by the gate dielectric. Each gate dielectric may comprise silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high-k), or a combination thereof, and each gate electrode may comprise a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or a multilayer structure comprising any combination of the aforementioned materials.

[0057] In some embodiments, forming the gate structure 125 includes depositing a gate dielectric material (not shown) over the top surface 107TS of the dielectric layer 107 within the liner opening 120, depositing a gate electrode material (not shown) within the remaining portion of the opening 120 and on the top surface 107TS of the dielectric layer 107, and performing a planarization process on the gate dielectric material and the gate electrode material. In some embodiments, the deposition process includes CVD, PVD, ALD, or other suitable processes. In some embodiments, the planarization process includes CMP, polishing, etching, or other suitable processes.

[0058] Figures 17 to 20 show intermediate stages of forming the contact structure 307 of a semiconductor element 100C according to some embodiments of the present disclosure. For simplicity, Figures 17 to 20 only show the peripheral region LA of the semiconductor element 100C.

[0059] The formation of semiconductor element 100C in array region DA is substantially the same as the formation of semiconductor element 100A. In some embodiments, the contact structure 307 shown in FIGS. 17 to 22 is formed after the gate structure 125 is formed. In other embodiments, the contact structure 307 shown in FIGS. 17 to 22 is formed before the gate structure 125 is formed. In various embodiments, the contact structure 307 shown in FIGS. 17 to 22 is formed after the contact structure 159 is formed.

[0060] As shown in FIG. 17, an opening 310 is formed through the dielectric layer 107. In some embodiments, the opening 310 extends toward the semiconductor substrate 101, and the bottom surface of the opening 310 is substantially coplanar with the top surface 109TS of the source / drain structure 109. The opening 310 can be formed by an etching process, and the location of the opening 310 can be defined by a patterned mask (not shown) formed on the dielectric layer 107. The etching process may include a dry etching process, a wet etching process, or a combination thereof. After the etching process, the patterned mask on the dielectric layer 107 is removed.

[0061] As shown in Figure 18, a padding material 301a is formed within the opening 310 and on the top surface 107TS of the dielectric layer 107 to line the opening 310. The padding material 301a covers the bottom surface 310BS and sidewalls 310SW of the opening 310. In some embodiments, the padding material 301a is made of Ta, and the padding material 301a is formed by a deposition process, such as CVD, ALD, PVD, or a combination thereof. In other embodiments, the padding material 301a is made of TaN. In various embodiments, the padding material 301a is made of both Ta and TaN.

[0062] As shown in FIG19, a liner material 303a is formed within the opening 310 and on the liner material 301a. In some embodiments, the liner material 303a is made of CuMn and is formed by a deposition process, such as CVD, ALD, PVD or a combination thereof.

[0063] As shown in Figure 20, a conductive material 305a is formed on the pad material 303a to fill the opening 310. The conductive material 305a is separated from the dielectric layer 107 and the source / drain structure 109 by the pad material 301a and the pad material 303a. In some embodiments, the conductive material 305a is made of Cu and is formed by a deposition process, such as CVD, ALD, PVD, sputtering, plating, or a combination thereof.

[0064] Next, a planarization process, such as a CMP process, is performed on the pad material 301a, pad material 303a, and conductive material 305a to remove any excess material on the top surface 107TS of the dielectric layer 107, so that the remaining pad material 301a, the remaining pad material 303a, and the remaining conductive material 305a become the first pad 301, the second pad 303, and the conductive layer 305, respectively. Thus, a contact structure 307 comprising the first pad 301, the second pad 303, and the conductive layer 305 is obtained.

[0065] See Figure 21. Figure 21 is a flowchart of a method 400 for fabricating a semiconductor device 100B according to some embodiments of the present disclosure. Method 400 includes steps S402, S404, S406, S408, and S410. For simplicity, method 400 is described using reference numerals as shown in Figures 1 to 20.

[0066] Please refer to Figure 4. In step S402, a source / drain structure 109 is formed on the semiconductor substrate 101. In step S404, a dielectric layer 107 is formed on the source / drain structure 109.

[0067] In step S406, a plurality of contact structures 207 are formed penetrating the dielectric layer 107 and the source / drain structure 109. In some embodiments, step S406 includes several sub-steps, which are shown in Figures 5 to 9.

[0068] In step S408, a polycrystalline silicon stack 139 is formed on the source / drain structure 109. In some embodiments, step S408 includes several sub-steps, which are shown in Figures 10 to 13.

[0069] In step S410, a contact structure 159 is formed between two of the plurality of contact structures 207, wherein the contact structure 159 is formed on the source / drain structure 109. In some embodiments, step S410 includes several sub-steps, which are shown in Figures 14 to 16.

[0070] See Figure 22. Figure 22 is a flowchart of a method 500 for fabricating a semiconductor device 100C according to some embodiments of the present disclosure. Method 500 includes steps S502, S504, S506, S508, S510, and S512. For simplicity, method 500 is described using reference numerals as shown in Figures 1 to 20.

[0071] In step S502, a source / drain structure 109 is formed on a semiconductor substrate 101, wherein the semiconductor substrate 101 includes an array region DA and a peripheral region LA. In step S504, a dielectric layer 107 is formed on the source / drain structure 109.

[0072] In step S506, a contact structure 307 penetrating the dielectric layer 107 is formed in the peripheral region LA. In some embodiments, step S506 includes several sub-steps, which are shown in Figures 17 to 20.

[0073] In step S508, a plurality of gate structures 125 are formed in the array region DA, penetrating the dielectric layer 107 and the source / drain structure 109.

[0074] In step S510, a polycrystalline silicon stack 139 is formed within the array region DA and on the source / drain structure 109. In some embodiments, step S510 includes several sub-steps, which are shown in Figures 10 to 13.

[0075] In step S512, a contact structure 159 is formed on the polysilicon stack 139, wherein the contact structure 159 is disposed between two of the gate structures 125. In some embodiments, step S512 includes several sub-steps, which are shown in Figures 14 to 16.

[0076] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a source / drain structure, a dielectric layer, a plurality of first contact structures, a polysilicon stack, and a second contact structure. The source / drain structure is disposed on a semiconductor substrate. The dielectric layer is disposed on the source / drain structure. The plurality of first contact structures extend through the dielectric layer and the source / drain structure. The second contact structure is disposed on the polysilicon stack. The polysilicon stack and the second contact structure are disposed between two of the plurality of first contact structures. Each of the plurality of first contact structures includes a first pad and a first conductive layer surrounded by the first pad.

[0077] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes: forming a source / drain structure on a semiconductor substrate; forming a dielectric layer on the source / drain structure; forming a plurality of first contact structures penetrating the dielectric layer and the source / drain structure; and forming a second contact structure between two of the plurality of first contact structures, wherein the second contact structure is formed on the source / drain structure. The step of forming the plurality of first contact structures penetrating the dielectric layer and the source / drain structure includes: performing a first etching process to form a plurality of first openings penetrating the dielectric layer and the source / drain structure and extending into the semiconductor substrate; forming a first pad covering the sidewalls and bottom surface of each of the plurality of first openings; forming a second pad on the first pad; and after forming the second pad, filling a remaining portion of the plurality of first openings with a first conductive layer. The first pad and the second pad are made of different materials.

[0078] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a source / drain structure, a dielectric layer, a first contact structure, a polysilicon stack, and a second contact structure. The semiconductor substrate includes an array region and a peripheral region. The dielectric layer is disposed on the source / drain structure. The first contact structure is disposed on the peripheral region and extends through the dielectric layer. The first contact structure includes a first pad and a first conductive layer. The first pad comprises tantalum, tantalum nitride, or a combination thereof. The first conductive layer is disposed on the first pad and comprises Cu.

[0079] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes: forming a source / drain structure on a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; forming a dielectric layer on the source / drain structure; forming a first contact structure within the peripheral region, and the first contact structure penetrating the dielectric layer; forming a polysilicon stack within the array region and on the source / drain structure; and forming a second contact structure on the polysilicon stack. The step of forming the first contact structure within the peripheral region, and the first contact structure penetrating the dielectric layer, includes: performing a first etching process to form a first opening penetrating the dielectric layer; forming a first pad, the first pad covering the sidewalls and bottom surface of the first opening; forming a second pad on the first pad, wherein the first pad and the second pad are made of different materials; and after forming the second pad, filling a remaining portion of the first opening with a first conductive layer.

[0080] The embodiments disclosed herein have several advantages. In some embodiments, by forming a polysilicon stack between the source / drain structure and the contact structure, contact resistance can be reduced and device performance can be improved. In some embodiments, by forming conductive contacts with barrier layers of different thicknesses, the conductive layer on the barrier layer can be void-free, and device performance can be improved.

[0081] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0082] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0083] 100A: Semiconductor Components 100B: Semiconductor Components 100C: Semiconductor Components 101: Semiconductor substrate 103: Epitaxial layer 105: Silicon layer 105TS: Top surface 107: Dielectric layer 107TS: Top surface 109: Source / Drain Structure 109TS: Top surface 120: Opening 125: Gate structure 130: Opening 133: First polycrystalline silicon layer 133a: Polycrystalline silicon material 135: Second polycrystalline silicon layer 135a: Polycrystalline silicon material 139: Polycrystalline silicon stacking 140: Opening 153: Barrier Layer 153a: Barrier Materials 153L: Lower Part 155: Conductive layer 155a: Conductive material 159: Contact Structure 201: First Pad 201a: Padding Material 201BT: Thickness 201ST: Thickness 203: Second pad 203a: Padding material 203BT: Thickness 203ST: Thickness 205: Conductive layer 205a: Conductive materials 205W: Width 207: Contact Structure 207D: Depth 301: First gasket 301a: Padding Material 301BT: Thickness 301ST: Thickness 303: Second gasket 303a: Gasket material 303BT: Thickness 303ST: Thickness 305: Conductive layer 305a: Conductive material 305W: Width 307: Contact Structure 307D: Depth 310: Opening 310BS: Bottom 310SW: Sidewall 400: Method 500: Methods DA: Array area LA: Surrounding Area S402: Steps S404: Steps S406: Steps S408: Steps S410: Steps S502: Steps S504: Steps S506: Steps S508: Steps S510: Steps S512: Steps

Claims

1. A semiconductor element, comprising: A single-source / drain structure is disposed on a semiconductor substrate; A dielectric layer is disposed on the source / drain structure; Multiple first-junction structures, penetrating the dielectric layer and the source / drain structure; a polycrystalline silicon stack; and a second contact structure disposed on the polysilicon stack, wherein the polysilicon stack and the second contact structure are disposed between two of the plurality of first contact structures, wherein each of the plurality of first contact structures includes: a first pad; and a first conductive layer surrounded by the first pad, wherein the second contact structure includes: a barrier layer comprising titanium, titanium nitride or a combination thereof; and a second conductive layer comprising tungsten, wherein the second conductive layer is surrounded by the barrier layer.

2. The semiconductor element as claimed in claim 1, wherein each of the plurality of first contact structures further comprises: A second pad is disposed between the first pad and the first conductive layer.

3. The semiconductor device as claimed in claim 2, wherein the second pad comprises CuMn.

4. The semiconductor device as claimed in claim 1, wherein the first pad comprises tantalum, tantalum nitride, or a combination thereof, and the first conductive layer comprises Cu.

5. The semiconductor element as claimed in claim 1, wherein the plurality of first contact structures extend into the semiconductor substrate.

6. The semiconductor device as claimed in claim 1, wherein the barrier layer has a lower portion surrounded by the polysilicon stack.

7. The semiconductor device as claimed in claim 1, wherein the source / drain structure comprises: An epitaxial layer contacts the semiconductor substrate; And a silicon layer is disposed between the epitaxial layer and the dielectric layer.

8. The semiconductor device as claimed in claim 7, wherein the silicate layer comprises cobalt silicate.

9. The semiconductor device as claimed in claim 1, wherein the polysilicon stack comprises: The first polycrystalline silicon layer; And a second polycrystalline silicon layer disposed on the first polycrystalline silicon layer, wherein the dopant concentration of the second polycrystalline silicon layer is different from the dopant concentration of the first polycrystalline silicon layer.

10. The semiconductor device as claimed in claim 9, wherein the first polysilicon layer is undoped and the second polysilicon layer is doped.

11. The semiconductor device as claimed in claim 9, wherein the polysilicon stack further comprises: A third polycrystalline silicon layer is disposed on the second polycrystalline silicon layer, wherein the third polycrystalline silicon layer is undoped; And a fourth polycrystalline silicon layer disposed on the third polycrystalline silicon layer, wherein the fourth polycrystalline silicon layer is doped.

12. The semiconductor device as claimed in claim 9, wherein the second polysilicon layer is separated from the dielectric layer by the first polysilicon layer.

13. The semiconductor element as claimed in claim 1, wherein the semiconductor element is part of a dynamic random access memory, and the plurality of first contact structures and the second contact structures are disposed in an array region of the semiconductor element.

Images