Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for fabricating a semiconductor device, which mainly involves first forming a first groove in a substrate, then forming a gate dielectric layer in the first groove, forming a gate structure on the gate dielectric layer, removing part of the gate structure and part of the substrate to form a second groove, forming a pad layer in the second groove, forming a field electrode in the second groove, forming a protective layer on the gate structure, forming a source electrode on the substrate and connecting it to the field electrode, and finally forming a drain electrode on the back side of the substrate.

Claims

1. A method for fabricating a semiconductor device, characterized in that it comprises: forming a first groove in a substrate; forming a gate structure in the first groove; removing the gate structure and the substrate to form a second groove; and forming a field electrode in the second groove; wherein, The method further includes: forming a substrate region on the substrate; forming a first doped region on the substrate region; forming a plurality of second doped regions on both sides of the first groove; forming the first groove; forming a gate dielectric layer in the first groove; forming the gate structure on the gate dielectric layer; forming the second groove; forming a pad layer in the second groove; forming the field electrode on the pad layer; forming a protective layer on the gate structure; forming a source electrode on the substrate and connecting it to the field electrode; and forming a drain electrode on the back side of the substrate.

2. The method as described in claim 1, wherein the substrate region and the second doped regions contain the same conductivity type.

3. The method as described in claim 1, wherein the substrate region and the first doped region comprise different conductivity types.

4. The method as described in claim 1, wherein the first doped region and the second doped regions comprise different conductivity types.

5. The method as described in claim 1, wherein the depth of the second doped region is greater than the depth of the first doped region.

6. The method as described in claim 1, wherein the depth of the first groove is greater than the depth of the base region.

7. A semiconductor device, characterized in that it comprises: a field electrode disposed within a substrate; a first gate structure disposed on one side of the field electrode; a second gate structure disposed on the other side of the field electrode; a first gate dielectric layer disposed beside the first gate structure; a pad layer disposed between the field electrode and the first gate structure, wherein the pad layer and the first gate dielectric layer have different thicknesses, and the dielectric constant of the first gate dielectric layer is greater than the dielectric constant of the pad layer; a source electrode disposed on the substrate and connected to the field electrode; and a drain electrode disposed on the back side of the substrate.

8. The semiconductor device as described in claim 7 further comprises: a substrate region disposed on both sides of the first gate structure and the second gate structure; a first doped region and a second doped region disposed on one side of the first gate structure; a third doped region and a fourth doped region disposed on one side of the second gate structure; and a protective layer disposed on the first gate structure and the second gate structure.

9. The semiconductor device as described in claim 7 further includes a second gate dielectric layer disposed next to the second gate structure, wherein the first gate dielectric layer and the second gate dielectric layer comprise the same material.

10. The semiconductor device as described in claim 7, wherein the first gate dielectric layer comprises a high dielectric constant dielectric layer.

11. The semiconductor device as described in claim 7, wherein the thickness of the first gate dielectric layer is less than the thickness of the pad layer.

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