Integrated circuit, device and method of manufacturing integrated circuit

Abstract

This disclosure provides an integrated circuit, an apparatus, and a method of manufacturing the integrated circuit. The integrated circuit includes a substrate having a front side and a back side opposite to the front side. The substrate includes at least one active region on the front side. A circuit is located on the front side of the substrate, and a front-side metallization layer is disposed above the circuit. A back-side metallization layer is disposed below the back side of the substrate, and a first power supply is located on a first side of the circuit. The first power supply is configured to deliver one or more voltages from the back-side metallization layer to the front-side metallization layer, the back-side metallization layer being electrically coupled to at least one active region.

Description

Prior Technology

[0001] Typically, integrated circuits include a power delivery or power distribution network (PDN) for delivering power to the components within the integrated circuit. Some integrated circuits include a front-side PDN with front-side conductors for power delivery, while others include a back-side PDN with back-side conductors for power delivery. The back-side PDN may be referred to as a "super power rail" (SPR). Furthermore, some integrated circuits include a dual-side power rail structure that incorporates both front-side and back-side PDNs. Dual-side power rail structures reduce the area of ​​the integrated circuit and, due to the shunting of power from the front and back sides, reduce the source resistance from the power supply to the integrated circuit components, thereby increasing circuit speed. Simple Explanation of the Diagram

[0002] The various aspects of this disclosure are best understood from the following detailed description when reading the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for the purpose of discussing clarity. Furthermore, the illustrations are illustrative of embodiments of this disclosure and are not intended to be limiting. Figure 1 is a schematic diagram illustrating an apparatus including circuitry (such as clock cells or clock circuits) and power supply cells or circuits according to some embodiments. Figure 2 is a schematic diagram illustrating a clock cell and a power supply cell located on one side of the clock cell, based on some embodiments. Figure 3 is a schematic illustration of a clock cell, and a first power supply cell and a second power supply cell located on the opposite side of the clock cell, according to some embodiments. Figure 4 is a schematic illustration of a clock cell, and a first power access cell and a second power access cell that are longer than the clock cell, according to some embodiments. Figure 5 is a schematic illustration of a clock cell, and a first power-taking cell and a second power-taking cell located on the short side of the clock cell, according to some embodiments. Figure 6 is a schematic illustration of a clock cell, and a first power-accessing cell and a second power-accessing cell located on the short side of the clock cell, according to some embodiments. Figure 7 is a schematic diagram illustrating the clock cell and the power supply cells surrounding all sides of the clock cell according to some embodiments. Figure 8 is a schematic diagram illustrating circuit options including a reference circuit, a single-sided power supply cell circuit, and a dual-sided power supply cell circuit, based on some embodiments. Figure 9 is a schematic diagram illustrating an apparatus including a substrate according to some embodiments, the substrate including an N-type well active region for a power supply voltage VDD and a P-type well active region for a power supply voltage VSS. Figure 10 includes a diagram illustrating the apparatus of Figure 9 according to some embodiments, the apparatus including a VB-type power supply structure, a first front metallization layer M0 and a first back metallization layer BMO. Figure 11 is a schematic diagram illustrating a cross-section of the device taken from Figure 10 along line AA in Figure 10 according to some embodiments. Figure 12 is a schematic diagram illustrating a device including a clock cell located next to or adjacent to a power supply cell, according to some embodiments. Figure 13 is a schematic diagram illustrating a cross-section taken from the VDD power supply cell along line BB in Figure 12, according to some embodiments. Figure 14 is a schematic diagram illustrating, according to some embodiments, a device including an FTV-type power supply cell structure, a first front metallization layer M0, and a first back metallization layer BMO for transmitting power supply voltage VDD. Figure 15 is a schematic diagram illustrating a cross-section of the device taken from Figure 14 along the CC line in Figure 14, according to some embodiments. Figure 16 is a schematic diagram illustrating, according to some embodiments, a device including an FTV-type power supply cell structure, a first front metallization layer M0, and a first back metallization layer BMO for transmitting power supply voltage VSS. Figure 17 is a schematic diagram illustrating a cross-section of the device taken from Figure 16 along line DD in Figure 16 according to some embodiments. Figure 18 is a schematic diagram illustrating, according to some embodiments, a device including an FTV-type power supply cell structure, a first front metallization layer M0, and a first back metallization layer BMO for transmitting power supply voltage VDD. Figure 19 is a schematic diagram illustrating a cross-section of the device taken from Figure 18 along line EE in Figure 18, according to some embodiments. Figure 20 is a schematic diagram illustrating, according to some embodiments, a device including an FTV-type power supply cell structure, a first front metallization layer M0, and a first back metallization layer BMO for transmitting power supply voltage VSS. Figure 21 is a schematic diagram illustrating a cross-section of the device taken from Figure 20 along line FF in Figure 20, according to some embodiments. Figure 22 is a diagram illustrating the characteristics of VB-type power supply cells and FTV-type power supply cells according to some embodiments. Figure 23 is a schematic diagram illustrating, according to some embodiments, a device including a clock cell and power-taking cells surrounding all sides of the clock cell. Figure 24 is a diagram illustrating a method for manufacturing an integrated circuit according to some embodiments. Figure 25 is a block diagram illustrating, according to some embodiments, an example of a computer system configured to provide means (including electronic devices and semiconductor devices) and the methods disclosed herein. Figure 26 is a block diagram of a semiconductor device manufacturing system and an associated semiconductor device manufacturing process according to some embodiments. Implementation

[0003] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features form direct contact, and may also include embodiments where an additional feature may be formed between the first and second features, such that the first and second features do not necessarily form direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between the elements or features shown in the figures and another element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0005] In circuits with a dual-side power rail structure, the reduced power supply voltage between the front-side PDN and the back-side PDN can degrade performance due to uneven power distribution and high-resistance power supply draw cells or circuits. For example, front-to-back power supply draw cells formed in metal-covered drains (MD) and epitaxial layers increase resistance.

[0006] The disclosed embodiments include power supply cells or circuits that reduce current-resistance (IR) voltage drop and improve wiring resources. The disclosed embodiments include different types of power supply structures, such as back-side via (VB) and through-hole via (FTV) structures. The disclosed embodiments further include different placement arrangements of power supply cells or structures next to circuits or cells (e.g., clock cells). In some embodiments, the power supply cell is located on one side of the circuit or along one side. In some embodiments, the power supply cell is located on two opposite sides of the circuit or along two opposite sides. In some embodiments, the power supply cell is located on all sides of the circuit.

[0007] The disclosed embodiments include an integrated circuit comprising a substrate having at least one active region and circuitry located on the front side of the substrate. A front-side metallization layer is disposed above the circuitry, while a back-side metallization layer electrically coupled to the at least one active region is disposed below the back side of the substrate. A first power source is located on a first side of the circuitry and configured to deliver one or more voltages from the back-side metallization layer to the front-side metallization layer. In some embodiments, the integrated circuitry includes a second power source located on a second side of the circuitry (opposite to the first side of the circuitry) and configured to deliver one or more voltages from the back-side metallization layer to the front-side metallization layer.

[0008] In some embodiments, the integrated circuit includes a VB, an epitaxial layer, an MD contact, and a via-to-drain (VDR) contact, wherein the back metallization layer is electrically connected to the VB, the VB is electrically connected to the epitaxial layer, the epitaxial layer is electrically connected to the MD contact, the MD contact is electrically connected to the VDR contact, and the VDR contact is electrically connected to the front metallization layer. Thus, voltage is conducted between the back metallization layer and the front metallization layer through the VB, the epitaxial layer, the MD contact, and the VDR contact. In some embodiments, the integrated circuit includes an FTV, an MD contact, and a VDR contact, wherein the back metallization layer is electrically connected to the FTV, the FTV is electrically connected to the MD contact, the MD contact is electrically connected to the VDR contact, and the VDR contact is electrically connected to the front metallization layer. Thus, voltage is conducted between the back metallization layer and the front metallization layer through the FTV, the MD contact, and the VDR contact. The MD contact is also electrically connected to the epitaxial layer.

[0009] The disclosed embodiments further include an apparatus comprising circuitry located on the front side of a substrate, a front metallization layer disposed above the substrate, and a back metallization layer disposed below the back side of the substrate. Power supply is located on one side of the circuitry. The power supply includes an FTV, MD contacts, and a VDR contact, which are electrically connected from the back metallization layer to the front metallization layer. The MD contacts are located between epitaxial layers and are not electrically connected to the epitaxial layers.

[0010] Further disclosed embodiments include a method of manufacturing an integrated circuit, comprising forming a substrate having a front side and a back side opposite to the front side; forming an active region on the front side of the substrate; forming a circuit on the front side of the substrate; forming a front metallization layer above the circuit; forming a back metallization layer below the back side of the substrate and electrically coupling it to at least one active region of the active region; and forming a power supply draw on one side of the circuit to transfer one or more voltages from the back metallization layer to the front metallization layer.

[0011] Figure 1 is a schematic diagram illustrating apparatus 40 according to some embodiments. Apparatus 40 includes circuitry 42, such as clock cells or clock circuits, and power-supply cells or circuitry 44. In some embodiments, apparatus 40 includes a plurality of circuits 42. In some embodiments, apparatus 40 includes a plurality of power-supply cells 44. In some embodiments, each circuit 42 includes transistors, diodes, resistors, and / or other circuit elements constituting a circuit. In some embodiments, apparatus 40 includes one or more semiconductors. In some embodiments, apparatus 40 includes one or more integrated circuits.

[0012] In different layouts, device 40 may include different placement positions of power extraction cell 44 relative to circuit 42. In some embodiments, power extraction cell 44 is located on or along one side of circuit 42. In some embodiments, power extraction cell 44 is located on or along two opposite sides of circuit 42. In some embodiments, power extraction cell 44 is located on all sides of circuit 42.

[0013] The power extraction cell 44 is configured to deliver one or more voltages, such as power supply voltages VDD and VSS, from the back side of device 40 to the front side of device 40. The power extraction cell 44 reduces the wire length from the power supply to circuit 42. Furthermore, the power extraction cell 44 reduces IR voltage drop from the power supply to circuit 42 and improves wiring resources. In some embodiments, the power extraction cell 44 is attached to circuit 42. In some embodiments, the power extraction cell 44 is located near circuit 42.

[0014] The power access cell 44 may include different types of power access structures. In some embodiments, the power access cell 44 includes a VB-type power access structure. In some embodiments, the power access cell 44 includes an FTV-type power access cell structure.

[0015] Figure 2 is a schematic diagram illustrating clock cell 46 and power extraction cell 48 located on one side of clock cell 46 according to some embodiments. Power extraction cell 48 is embedded in a device, such as device 40 of Figure 1, and clock cell 46 is located on the front side of the device. In some embodiments, clock cell 46 is similar to circuit 42 (shown in Figure 1). In some embodiments, power extraction cell 48 is similar to power extraction cell 44 (shown in Figure 1).

[0016] Clock cell 46 has a length L1, while power extraction cell 48 has the same length L1 as clock cell 46, L2. Clock cell 46 includes two long sides 50a and 50b and two short sides 52a and 52b, and power extraction cell 48 includes two long sides 54a and 54b and two short sides 56a and 56b. The long side 54b of power extraction cell 48 is located next to or adjacent to the long side 50a of clock cell 46. In other embodiments, the long side 54a of power extraction cell 48 is located next to or adjacent to the long side 50b of clock cell 46. In some embodiments, power extraction cell 48 must be at least as long as clock cell 46.

[0017] Power supply cell 48 is configured to deliver one or more voltages, such as power supply voltages VDD and VSS, from the back side of the device to the front side. In some embodiments, power supply cell 48 is attached to clock cell 46. In other embodiments, power supply cell 48 is located near clock cell 46. Furthermore, in some embodiments, power supply cell 48 is configured to deliver one or more voltages to clock cell 46.

[0018] Power supply cell 48 reduces the wire length from the power supply to the clock cell 46. Furthermore, power supply cell 44 reduces the IR voltage drop from the power supply to the clock cell 46 and improves wiring resources.

[0019] Figure 3 is a schematic diagram illustrating a clock cell 60 and a first power-taking cell 62 and a second power-taking cell 64 located on either side of the clock cell 60, according to some embodiments. The first power-taking cell 62 is located on a first side of the clock cell 60, while the second power-taking cell 64 is located on a second side of the clock cell 60. The first side of the clock cell 60 is relative to the second side of the clock cell 60.

[0020] Each of the first power-supply cell 62 and the second power-supply cell 64 is embedded in a device, such as device 40 of FIG. 1, and the clock cell 60 is located on the front side of the device. In some embodiments, the clock cell 60 is similar to circuit 42 (shown in FIG. 1). In some embodiments, each of the first power-supply cell 62 and the second power-supply cell 64 is similar to power-supply cell 44 (shown in FIG. 1).

[0021] Clock cell 60 has a length L3, and each of the first power-taking cell 62 and the second power-taking cell 64 has the same length L4 as the clock cell 60. Clock cell 60 includes two long sides 66a and 66b and two short sides 68a and 68b. First power-taking cell 62 includes two long sides 70a and 70b and two short sides 72a and 72b, and second power-taking cell 64 includes two long sides 74a and 74b and two short sides 76a and 76b. The long side 70b of the first power-taking cell 62 is located next to or adjacent to the long side 66a of the clock cell 60, and the long side 74a of the second power-taking cell 64 is located next to or adjacent to the long side 66b of the clock cell 60. In some embodiments, each of the first power-taking cell 62 and the second power-taking cell 64 must be at least as long as the clock cell 60.

[0022] Each of the first power-supply cell 62 and the second power-supply cell 64 is configured to deliver one or more voltages, such as power supply voltages VDD and VSS, from the back side of the device to the front side of the device. In some embodiments, one or more of the first power-supply cell 62 and the second power-supply cell 64 are attached to the clock cell 60. In some embodiments, one or more of the first power-supply cell 62 and the second power-supply cell 64 are located near the clock cell 60. Furthermore, in some embodiments, one or more of the first power-supply cell 62 and the second power-supply cell 64 are configured to deliver one or more voltages to the clock cell 60.

[0023] The first power supply cell 62 and the second power supply cell 64 reduce the wire length from the power supply to the clock cell 60. Furthermore, the first power supply cell 62 and the second power supply cell 64 reduce the IR voltage drop from the power supply to the clock cell 60 and improve wiring resources.

[0024] Figure 4 is a schematic diagram illustrating a clock cell 80 and a first power-taking cell 82 and a second power-taking cell 84, which are longer than the clock cell 80, according to some embodiments. The first power-taking cell 82 is located on a first side of the clock cell 80, and the second power-taking cell 84 is located on a second side of the clock cell 80. The first side of the clock cell 80 is relative to the second side of the clock cell 80.

[0025] Each of the first power-supply cell 82 and the second power-supply cell 84 is embedded in a device, such as device 40 of FIG. 1, and the clock cell 80 is located on the front side of the device. In some embodiments, the clock cell 80 is similar to circuit 42 (shown in FIG. 1). In some embodiments, each of the first power-supply cell 82 and the second power-supply cell 84 is similar to power-supply cell 44 (shown in FIG. 1).

[0026] Clock cell 80 has a length L5, and each of the first power-taking cell 82 and the second power-taking cell 84 has a length L6, which is greater than the length L5 of clock cell 80. Clock cell 80 includes two long sides 86a and 86b and two short sides 88a and 88b. First power-taking cell 82 includes two long sides 90a and 90b and two short sides 92a and 92b, and second power-taking cell 84 includes two long sides 94a and 94b and two short sides 96a and 96b. The long side 90b of the first power-taking cell 82 is located next to or adjacent to the long side 86a of clock cell 80, and the long side 94a of the second power-taking cell 84 is located next to or adjacent to the long side 86b of clock cell 80.

[0027] Each of the first power-supply cell 82 and the second power-supply cell 84 is configured to deliver one or more voltages, such as power supply voltages VDD and VSS, from the back side of the device to the front side of the device. In some embodiments, one or more of the first and second power-supply cells 82 and 84 are attached to the clock cell 80. In some embodiments, one or more of the first and second power-supply cells 82 and 84 are located near the clock cell 80. Furthermore, in some embodiments, one or more of the first power-supply cell 82 and the second power-supply cell 84 are configured to deliver one or more voltages to the clock cell 80.

[0028] The first power supply cell 82 and the second power supply cell 84 reduce the wire length from the power supply to the clock cell 80. Furthermore, the first power supply cell 82 and the second power supply cell 84 reduce the IR voltage drop from the power supply to the clock cell 80 and improve wiring resources.

[0029] Figure 5 is a schematic illustration of a clock cell 100, and a first power-taking cell 102 and a second power-taking cell 104 along the shorter side of the clock cell 100, according to some embodiments. The first power-taking cell 102 is located on the first side of the clock cell 100, and the second power-taking cell 104 is located on the second side of the clock cell 100. The first side of the clock cell 100 is relative to the second side of the clock cell 100.

[0030] Each of the first power-supply cell 102 and the second power-supply cell 104 is embedded in a device, such as device 40 of FIG. 1, and the clock cell 100 is located on the front side of the device. In some embodiments, the clock cell 100 is similar to circuit 42 (shown in FIG. 1). In some embodiments, each of the first and second power-supply cells 102 and 104 is similar to power-supply cell 44 (shown in FIG. 1).

[0031] Clock cell 100 has a short side length L7, and each of the first power-taking cell 102 and the second power-taking cell 104 has a long side length L8 that is the same as the length L7 of clock cell 100. Clock cell 100 includes two long sides 106a and 106b and two short sides 108a and 108b. First power-taking cell 102 includes two long sides 110a and 110b and two short sides 112a and 112b, and second power-taking cell 104 includes two long sides 114a and 114b and two short sides 116a and 116b. The long side 110b of the first power-taking cell 102 is located next to or adjacent to the short side 108a of clock cell 100, and the long side 114a of the second power-taking cell 104 is located next to or adjacent to the short side 108b of clock cell 100. In some embodiments, the long side of the first power-access cell 102 and the second power-access cell 104 must be at least as long as the short side of the clock cell 100.

[0032] Each of the first power-taking cell 102 and the second power-taking cell 104 is configured to deliver one or more voltages, such as power supply voltages VDD and VSS, from the back side of the device to the front side of the device. In some embodiments, one or more of the first power-taking cell 102 and the second power-taking cell 104 are attached to the clock cell 100. In some embodiments, one or more of the first power-taking cell 102 and the second power-taking cell 104 are located near the clock cell 100. Furthermore, in some embodiments, one or more of the first power-taking cell 102 and the second power-taking cell 104 are configured to deliver one or more voltages to the clock cell 100.

[0033] The first power supply cell 102 and the second power supply cell 104 reduce the wire length from the power supply to the clock cell 100. In addition, the first power supply cell 102 and the second power supply cell 104 reduce the IR voltage drop from the power supply to the clock cell 100 and improve wiring resources.

[0034] Figure 6 is a schematic illustration of a clock cell 120, and a first power-taking cell 122 and a second power-taking cell 124 along the short side of the clock cell 120, according to some embodiments. The first power-taking cell 122 is located on the first short side of the clock cell 120, and the second power-taking cell 124 is located on the second short side of the clock cell 120. The first short side of the clock cell 120 is relative to the second short side of the clock cell 120.

[0035] Each of the first power-supply cell 122 and the second power-supply cell 124 is embedded in a device, such as device 40 of FIG. 1, and the clock cell 120 is located on the front side of the device. In some embodiments, the clock cell 120 is similar to circuit 42 (shown in FIG. 1). In some embodiments, each of the first power-supply cell 122 and the second power-supply cell 124 is similar to power-supply cell 44 (shown in FIG. 1).

[0036] Clock cell 120 has a short side length L9, and each of the first power-taking cell 122 and the second power-taking cell 124 has a long side length L10, which is longer than the short side length L9 of clock cell 120. Clock cell 120 includes two long sides 126a and 126b and two short sides 128a and 128b. First power-taking cell 122 includes two long sides 130a and 130b and two short sides 132a and 132b, and second power-taking cell 124 includes two long sides 134a and 134b and two short sides 136a and 136b. The long side 130b of the first power-taking cell 122 is located next to or adjacent to the short side 128a of clock cell 120, and the long side 134a of the second power-taking cell 124 is located next to or adjacent to the short side 128b of clock cell 120.

[0037] Each of the first power-taking cell 122 and the second power-taking cell 124 is configured to deliver one or more voltages, such as power supply voltages VDD and VSS, from the back side of the device to the front side of the device. In some embodiments, one or more of the first power-taking cell 122 and the second power-taking cell 124 are attached to the clock cell 120. In some embodiments, one or more of the first and second power-taking cells 122 and 124 are located near the clock cell 120. Furthermore, in some embodiments, one or more of the first power-taking cell 122 and the second power-taking cell 124 are configured to deliver one or more voltages to the clock cell 120.

[0038] The first power supply cell 122 and the second power supply cell 124 reduce the wire length from the power supply to the clock cell 120. In addition, the first power supply cell 122 and the second power supply cell 124 reduce the IR voltage drop from the power supply to the clock cell 120 and improve wiring resources.

[0039] Figure 7 is a schematic diagram illustrating clock cell 140 and power-taking cells 142 surrounding all sides of clock cell 140 according to some embodiments. Power-taking cells 142 are embedded in a device, such as device 40 of Figure 1, and clock cell 140 is located on the front side of the device. In some embodiments, clock cell 140 is similar to circuit 42 (shown in Figure 1). In some embodiments, power-taking cell 142 is similar to power-taking cell 44 (shown in Figure 1).

[0040] Clock cell 140 includes two long sides 146a and 146b and two short sides 148a and 148b, and power extraction cell 142 includes two long sides 150a and 150b and two short sides 152a and 152b. Power extraction cell 142 is configured to deliver one or more voltages, such as power supply voltages VDD and VSS, from the back side of the device to the front side of the device. In some embodiments, power extraction cell 142 is attached to clock cell 140 along the two long sides 146a and 146b and the two short sides 148a and 148b. In some embodiments, power extraction cell 142 is located near clock cell 140 along the two long sides 146a and 146b and the two short sides 148a and 148b. Furthermore, in some embodiments, power extraction cell 142 is configured to deliver one or more voltages to clock cell 140.

[0041] The power supply cell 142 reduces the wire length from the power supply to the clock cell 140. Furthermore, the power supply cell 142 reduces the IR voltage drop from the power supply to the clock cell 140 and improves wiring resources.

[0042] Figure 8 is a schematic diagram illustrating circuit option 160 according to some embodiments. Circuit option 160 includes reference circuit 162, single-sided power supply cell circuit 164, and dual-sided power supply cell circuit 166. Each of reference circuit 162, single-sided power supply cell circuit 164, and dual-sided power supply cell circuit 166 includes circuit 168, such as clock cell, FTV-I 170, and FTV-O 172.

[0043] Reference circuit 162 includes circuit 168, which has an FTV-I 170 on one side and an FTV-O 172 on the other side, the other side being opposite to the first side. Reference circuit 162 has an input / output (I&O) cell height of 6X, an input (I) cell height of 4X, and an output (O) cell height of 4X. The delay of the wires is used as a reference value.

[0044] The single-sided power-supply cell circuit 164 includes a power-supply cell 174 located between circuit 168 and FTV-O 172. The single-sided power-supply cell circuit 164 has an I&O cell height of 7x, an I cell height of 5x, and an O cell height of 5x. The I&O delay is -2.5% of a reference value, the I delay is -2.2% of a reference value, and the O delay is -2.3% of a reference value. In other embodiments, the power-supply cell 174 may be located between circuit 168 and FTV-I 170.

[0045] The dual-side power supply cell circuit 166 includes a first power supply cell 176 located between circuit 168 and FTV-I 170, and a second power supply cell 178 located between circuit 168 and FTV-O 172. The dual-side power supply cell circuit 166 has an I&O cell height of 8x, an I cell height of 6x, and an O cell height of 6x. The I&O delay is -3.9% of the reference value, the I delay is -3.5% of the reference value, and the O delay is -3.5% of the reference value.

[0046] Figure 9 is a top view illustrating apparatus 200 according to some embodiments. Apparatus 200 includes a substrate 202, the substrate including an N-type well active region 204 for a power supply voltage VDD and a P-type well active region 206 for a power supply voltage VSS. Apparatus 200 includes a back-side metallization layer 208 for transmitting power supply VDD and a back-side metallization layer 210 for transmitting power supply VSS. In some embodiments, apparatus 200 is similar to apparatus 40 of Figure 1.

[0047] Power supply VDD is delivered from the back metallization layer 208 to the circuitry in device 200 via power supply cells. Power supply VSS is delivered from the back metallization layer 210 to the circuitry in device 200 via one or more power supply cells. In some embodiments, each circuitry is similar to circuitry 42 (shown in FIG. 1). In some embodiments, each power supply cell is similar to power supply cell 44 (shown in FIG. 1). In some embodiments, the circuitry is a clock cell.

[0048] Figures 10 and 11 are schematic diagrams illustrating the device 200 of Figure 9, including VB-type power extraction cells or structures 220a-220f for transferring power VDD and power VSS from the back side to the front side of the device 200. The VB-type power extraction structures 220a-220f simultaneously transfer power VDD and power VSS from the back side to the front side of the device 200. In some embodiments, the device 200 is similar to the device 40 of Figure 1.

[0049] Figure 10 is a top view, schematically illustrating VB-type power extraction structures 220a-220f, first front metallization layers M0 222a-222g, and first back metallization layers BMO 208 and 210 (shown in Figure 9), according to some embodiments. The first front metallization layers M0 222a-222g are located above or on top of the VB-type power extraction structures 220a-220f, while the first back metallization layers BMO 208 and 210 are located below or beneath the VB-type power extraction structures 220a-220f. The power distribution network in the first front metallization layers M0 222a-222g is different for power supply VDD and power supply VSS. Furthermore, the device 200 includes gate contacts 224, such as polysilicon (PO) gates or wires, and edge fingers 226, such as edge PO fingers. For clarity, the first front metallization layers M0 222a~222g and the first back metallization layers BM0 208 and 210 are drawn separately.

[0050] The VB-type power supply structures 220a~220c pass through the active region 204 of the N-type well used for the power supply voltage VDD, while the VB-type power supply structures 220d~220f pass through the active region 206 of the P-type well used for the power supply voltage VSS.

[0051] Each VB-type power supply structure 220a-220c includes VB contacts 228a-228c, a P-type epitaxial layer active region 230, MD contacts 232a-232c, and a VDR contact 234. A first back-side metallization layer BMO 208 electrically connects to and transmits power VDD to the VB contacts 228a-228c. These VB contacts are electrically connected to the P-type epitaxial layer active region 230, which is electrically connected to the MD contacts 232a-232c. The MD contacts are electrically connected to the VDR contact 234, and the VDR contact is electrically connected to a first front-side metallization layer MO 222a for power VDD.

[0052] Each VB-type power supply structure 220d~220f includes VB contacts 228d~228f, an N-type epitaxial layer active region 236, MD contacts 232d~232f, and a VDR contact 238. A first back-side metallization layer BMO 210 electrically connects to and transmits power VSS to the VB contacts 228d~228f. These VB contacts are electrically connected to the N-type epitaxial layer active region 236, which is electrically connected to the MD contacts 232d~232f. The MD contacts are electrically connected to the VDR contacts 238, and the VDR contacts are electrically connected to a first front-side metallization layer MO 222g for the power VSS.

[0053] Figure 11 is a schematic illustration of a cross-section of device 200 taken along line AA in Figure 10 according to some embodiments. Device 200 includes a first front metallization layer Mo 222a~222g located above or on top of VB-type power extraction structures 220b and 220e, and a first back metallization layer BMO 208 and 210 located below or under the VB-type power extraction structures 220b and 220e.

[0054] The VB-type power supply structure 220b passes through the N-type well active region 204 for the power supply voltage VDD, while the VB-type power supply structure 220e passes through the P-type well active region 206 for the power supply voltage VSS.

[0055] The VB-type power supply structure 220b includes a VB contact 228b, a P-type epitaxial layer active region 230, an MD contact 232b, and a VDR contact 234. A first back-side metallization layer BMO 208 is electrically connected to and transmits power VDD to the VB contact 228b. The VB contact is electrically connected to the P-type epitaxial layer active region 230, which is electrically connected to the MD contact 232b. The MD contact is electrically connected to the VDR contact 234, and the VDR contact is electrically connected to a first front-side metallization layer MO 222a for the power VDD. The power supply voltage VDD flows from the first back-side metallization layer BMO 208 to the VB contact 228b, then to the P-type epitaxial layer active region 230, then to the MD contact 232b, then to the VDR contact 234, and finally to the first front-side metallization layer MO 222a. In some embodiments, it flows to the VDD distribution network.

[0056] The VB-type power supply structure 220e includes a VB contact 228e, an N-type epitaxial layer active region 236, an MD contact 232e, and a VDR contact 238. A first back-side metallization layer BMO 210 electrically connects to and transmits power VSS to the VB contact 228e. The VB contact is electrically connected to the N-type epitaxial layer active region 236, which is electrically connected to the MD contact 232e. The MD contact is electrically connected to the VDR contact 238, and the VDR contact is electrically connected to a first front-side metallization layer MO 222g for the power VSS. The power voltage VSS flows to or out of the first back-side metallization layer BMO 210, to the VB contact 228e, to the N-type epitaxial layer active region 236, to the MD contact 232e, to the VDR contact 238, and to the first front-side metallization layer MO 222g. In some embodiments, it flows to the VSS distribution network.

[0057] Figure 12 is a schematic diagram illustrating, according to some embodiments, a device 250 including a clock cell 252 located next to or adjacent to a power supply cell 254. The clock cell 252 is located on the element side of the device 250, while the power supply cell 254 transmits power supply voltages VDD and VSS from the back side of the device 250 to the element side of the device 250 and the clock cell 252. The clock cell 252 includes epitaxial active regions 256a-256c, while the power supply cell 254 includes epitaxial active regions 258a and 258b.

[0058] The power supply cell 254 includes a VDD power supply cell 260, which transmits the power supply voltage VDD from the back side of the device 250 to the component side of the device 250, and a clock cell 252. The VDD power supply cell 260 is a VB-type power supply cell that transmits the power supply voltage VDD to the first metal layer M0, which serves as the VDD power rail 262.

[0059] Power supply cell 254 includes VSS power supply cells 264a and 264b, which transmit the power supply voltage VSS from the back side of device 250 to the element side of device 250 and clock cell 252. VSS power supply cells 264a and 264b transmit the power supply voltage VSS to a first metal layer M0, which serves as VSS power rail 266. In some embodiments, VSS power supply cells 264a and 264b are VB-type power supply cells or structures.

[0060] Device 250 includes a first metal layer M0 VDD power rail 262 and a first metal layer M0 VSS power rail 266. The first metal layer M0 VDD power rail 262 is electrically connected to a second front metallization layer M1 270, to a second via 268b, and to the first front metallization layer M0, which serves as the clock cell VDD power rail 272, via a first via 268a. Furthermore, the first metal layer M0 VDD power rail 262 is electrically connected to another second front metallization layer M1 274, to a fourth via 268d, and to the first front metallization layer M0, which serves as the clock cell VDD power rail 272, via a third via 268c.

[0061] The first metal layer M0 VSS power rail 266 is electrically connected to the second front metallization layer M1 276, to the sixth via 268f, and to the first front metallization layer M0, which serves as the clock cell VSS power rail 278, through the fifth via 268e. The first metal layer M0 VSS power rail 266 is electrically connected to the second front metallization layer M1 280, to the eighth via 268h, and to the first front metallization layer M0, which serves as the clock cell VSS power rail 278, through the seventh via 268g.

[0062] Figure 13 is a schematic cross-sectional view of the VDD power supply cell 260 taken along line BB in Figure 12, according to some embodiments. The VDD power supply cell 260 includes a first back-side metallization layer BMO 282, a first VB 284, a second VB 286, a clock cell P-type epitaxial active region 256c, a power supply cell P-type epitaxial active region 258a, an MD layer 288 (also shown in Figure 12), a VDR 290 (also shown in Figure 12), and a first metallization layer M0 VDD power rail 262.

[0063] VDD power supply cell 260 passes through the N- or P-well active region 292 of device 250 to deliver power supply voltage VDD from the back side of device 250 to the component side of device 250. A first back-side metallization layer BMO 282 of VDD power supply cell 260 is electrically connected to a first VB 284, which is electrically connected to a clock cell P-type epitaxial layer active region 256c and a second VB 286. The second VB 286 is electrically connected to a power supply cell P-type epitaxial layer active region 258a. The clock cell P-type epitaxial layer active region 256c and the power supply cell P-type epitaxial layer active region 258a are electrically connected to an MD layer 288, which is electrically connected to a VDR 290, which is electrically connected to a first metallization layer MO VDD power rail 262.

[0064] The power supply voltage VDD flows from the first back-side metallization layer BMO 282 to the first VB 284 and the active region 256c of the clock cell P-type epitaxial layer, as well as the second VB 286 and the active region 258a of the power supply cell P-type epitaxial layer. Then, the power supply voltage VDD flows from the active region 256c of the clock cell P-type epitaxial layer and the active region 258a of the power supply cell P-type epitaxial layer to the MD layer 288, VDR 290, and the first metallization layer MO VDD power rail 262, and in some embodiments, to the VDD distribution network. Therefore, the power supply voltage VDD is transmitted from the first back-side metallization layer BMO 282 to the clock cell 252 and the power supply cell 254 via the VDD power supply cell 260.

[0065] Figures 14 and 15 are schematic illustrations of a device 300 including an FTV-type power supply cell or structure 302 for transmitting a power supply voltage VDD from the back side of the device 300 to the element side of the device 300. In some embodiments, the device 300 is similar to the device 40 of Figure 1.

[0066] Figure 14 is a schematic diagram illustrating, according to some embodiments, an apparatus 300 including an FTV power supply cell structure 302, first front metallization layers MO 304a-304g, and first back metallization layers BMO 306 and 308 for transmitting power supply voltage VDD. The first front metallization layers MO 304a-304g are located above or on top of the FTV power supply cell structure 302, while the first back metallization layers BMO 306 and 308 are located below or beneath the FTV power supply cell structure 302. The power distribution network in the first front metallization layers MO 304a-304g is different for power supply VDD and power supply VSS. Furthermore, the apparatus 300 includes gate contacts 310, such as PO gates or lines, and edge fingers 312, such as edge PO fingers. For clarity, the first front metallization layers M0 304a~304g and the first back metallization layers BM0 306 and 308 are drawn separately.

[0067] The device 300 includes an N-type well active region 314 having a P-type epitaxial layer active region 316, and a P-type well active region 318 having an N-type epitaxial layer active region 320. The FTV power take-up cell structure 302 passes through the N-type well active region 314 and the P-type well active region 318 to transmit the power supply voltage VDD.

[0068] The FTV power supply cell structure 302 includes FTV contacts 322, MD contacts 324a and 324b, and VDR contacts 326. The first back-side metallization layer BMO 306 includes a base portion 328 and an extension or micro-displacement 330 extending from the base portion 328 and located below the FTV contacts 322. The height of the micro-displacement 330 is referred to as the micro-displacement distance J. The first back-side metallization layer BMO 308 is recessed or recessed to avoid interference between the first back-side metallization layer BMO 306 and the first back-side metallization layer BMO 308. An extension or micro-shift 330 of the first back-side metallization layer BM0 306 is electrically connected to and transmits power VDD to the FTV contact 322, the FTV contact 322 is electrically connected to the MD contacts 324a and 324b, the MD contacts 324a and 324b are electrically connected to the VDR contact 326, and the VDR contact 326 is electrically connected to the first front-side metallization layer M0 304a for power VDD.

[0069] Figure 15 is a schematic diagram illustrating a cross-section of device 300 taken along line CC in Figure 14 according to some embodiments. Device 300 includes a first front metallization layer Mo 304a~304g located above or on top of FTV power extraction cell structure 302, and a first back metallization layer BMO 306 and 308 located below or under FTV power extraction cell structure 302.

[0070] The FTV power supply cell structure 302 extends through the N-type well active region 314 and the P-type well active region 318. The FTV power supply cell structure 302 includes FTV contacts 322, MD contacts 324a and 324b, and a VDR contact 326. An extension or micro-shift 330 of the first back-side metallization layer BMO 306 electrically connects to and transmits power VDD to the FTV contact 322. The FTV contact 322 is electrically connected to the MD contacts 324a (and MD contacts 324b), and the MD contacts 324a and 324b are electrically connected to the VDR contact 326. The VDR contact 326 is electrically connected to the first front-side metallization layer MO 304a for power VDD. Furthermore, the MD contact 324a is electrically connected to the P-type epitaxial layer active region 316. The power supply voltage VDD flows from the first back metallization layer BM0 306 to the FTV contact 322, to the MD contact 324a (and MD contact 324b), to the VDR contact 326, and to the first front metallization layer MO 304a, and in some embodiments, to the VDD distribution network.

[0071] Figures 16 and 17 are schematic illustrations of a device 340 including an FTV-type power supply cell or structure 342 for transmitting a power supply voltage VSS from the back side of the device 340 to the front side of the device 340. In some embodiments, the device 340 is similar to the device 40 of Figure 1.

[0072] Figure 16 is a schematic illustration of a device 340 according to some embodiments, including an FTV power supply cell structure 342, first front metallization layers MO 344a-344g, and first back metallization layers BMO 346 and 348 for transmitting power supply voltage VSS. The first front metallization layers MO 344a-344g are located above or on top of the FTV power supply cell structure 342, while the first back metallization layers BMO 346 and 348 are located below or beneath the FTV power supply cell structure 342. The power distribution network in the first front metallization layers MO 344a-344g is different for power supply VDD and power supply VSS. Furthermore, the device 340 includes gate contacts 350, such as PO gates or lines, and edge fingers 352, such as edge PO fingers. For clarity, the first front metallization layers M0 344a~344g and the first back metallization layers BMO 346 and 348 were drawn separately.

[0073] Device 340 includes an N-type well active region 354 having a P-type epitaxial layer active region 356, and a P-type well active region 358 having an N-type epitaxial layer active region 360. The FTV power supply cell structure 342 allows the power supply voltage VSS to pass through the N-type well active region 354 and the P-type well active region 358.

[0074] The FTV power supply cell structure 342 includes FTV contacts 362, MD contacts 364a and 364b, and VDR contacts 366. The first back-side metallization layer BMO 348 includes a base portion 368 and an extension or micro-displacement 370 extending from the base portion 368 and located below the FTV contacts 362. The height of the micro-displacement 370 is referred to as the micro-displacement distance J. The first back-side metallization layer BMO 346 is recessed or recessed to avoid interference between the first back-side metallization layer BMO 346 and the first back-side metallization layer BMO 348. An extension or micro-shift 370 of the first back-side metallization layer BM0 348 is electrically connected to and transmits the power supply voltage VSS to the FTV contact 362. The FTV contact 362 is electrically connected to the MD contacts 364a and 364b. The MD contacts 364a and 364b are electrically connected to the VDR contact 366. The VDR contact 366 is electrically connected to the first front-side metallization layer M0 344g for the power supply VSS.

[0075] Figure 17 is a schematic diagram illustrating a cross-section of device 340 taken along line DD in Figure 16 according to some embodiments. Device 340 includes a first front metallization layer Mo 344a~344g located above or on top of FTV power extraction cell structure 342, and a first back metallization layer BMO 346 and 348 located below or under FTV power extraction cell structure 342.

[0076] The FTV power supply cell structure 342 extends through the N-type well active region 354 and the P-type well active region 358. The FTV power supply cell structure 342 includes FTV contacts 362, MD contacts 364a and 364b, and a VDR contact 366. An extension or micro-shift 370 of the first back-side metallization layer BMO 348 electrically connects to and transmits power VSS to the FTV contact 362. The FTV contact 362 is electrically connected to the MD contacts 364a (and MD contacts 364b), the MD contacts 364a and 364b are electrically connected to the VDR contact 366, and the VDR contact 366 is electrically connected to the first front-side metallization layer MO 344g for the power VSS. Furthermore, the MD contact 364a is electrically connected to the N-type epitaxial layer active region 360. The power supply voltage VSS flows from the first back metallization layer BM0 348 to the FTV contact 362, to the MD contact 364a (and MD contact 364b), to the VDR contact 366, and to the first front metallization layer MO 344g, and in some embodiments, to the VSS distribution network.

[0077] Figures 18 and 19 are schematic illustrations of a device 400 including an FTV-type power extraction cell or structure 402 for transmitting a power supply voltage VDD from the back side of the device 400 to the front side of the device 400. The FTV-type power extraction cell structure 402 is located in the central region of the device 400, and a protrusion or micro-shift 430 of the first back-side metallization layer BMO 406 extends into the central region to contact the FTV-type power extraction cell structure 402. Furthermore, a recess or indentation in the first back-side metallization layer BMO 408 corresponds to the micro-shift 430 to avoid interference between the first back-side metallization layer BMO 406 and the first back-side metallization layer BMO 408. The height of the micro-shift 430 is referred to as the micro-shift distance J. In some embodiments, the device 400 is referred to as a power extraction cell. In some embodiments, the device 400 is similar to the device 40 of Figure 1.

[0078] Figure 18 is a schematic illustration of a device 400 according to some embodiments, including an FTV power extraction structure 402, first front metallization layers MO 404a-404g, and first back metallization layers BMO 406 and 408 for transmitting power supply voltage VDD. The first front metallization layers MO 404a-404g are located above or on top of the FTV power extraction structure 402, and the first back metallization layers BMO 406 and 408 are located below or beneath the FTV power extraction structure 402. The power distribution network in the first front metallization layers MO 404a-404g is different for power supply VDD and power supply VSS. Furthermore, the device 400 includes gate contacts 410, such as PO gates or lines, and edge fingers 412, such as edge PO fingers. For clarity, the first front metallization layers M0 404a~404g and the first back metallization layers BMO 406 and 408 were drawn separately.

[0079] The device 400 includes an N-type well active region 414 having a P-type epitaxial layer active region 416, and a P-type well active region 418 having an N-type epitaxial layer active region 420. The FTV power supply structure 402 passes through the N-type well active region 414 and the P-type well active region 418 to deliver the power supply voltage VDD.

[0080] The FTV power supply structure 402 includes an FTV contact 422, an MD contact 424, and a VDR contact 426. A first back-side metallization layer BMO 406 includes a base portion 428 and a protrusion (extension) or micro-shift 430 extending from the base portion 428 and located below the FTV contact 422. The first back-side metallization layer BMO 408 is recessed or recessed to avoid interference between the first back-side metallization layers BMO 406 and itself. The micro-shift 430 of the first back-side metallization layer BMO 406 electrically connects to and transmits power VDD to the FTV contact 422, the FTV contact 422 is electrically connected to the MD contact 424, the MD contact 424 is electrically connected to the VDR contact 426, and the VDR contact 426 is electrically connected to a first front-side metallization layer MO 404d for power VDD. The first front metallization layer M0 404d is electrically connected to the second front metallization layer M1 432 through the first via 434, and the second front metallization layer M1 432 is electrically connected to the first front metallization layer M0 404a through the second via 436. In some embodiments, the first front metallization layer M0 404a is connected to the VDD PDN.

[0081] Figure 19 is a schematic cross-sectional view of the device 400 taken along line EE in Figure 18, according to some embodiments. The device 400 includes a first front metallization layer M0 404a-404g located above or on top of the FTV power extraction structure 402, and a first back metallization layer BMO 406 and 408 located below or beneath the FTV power extraction structure 402. Furthermore, a second front metallization layer M1 432 is located above or on top of the first front metallization layers M0 404a-404g.

[0082] The FTV power extraction structure 402 passes through the N-type well active region 414 and the P-type well active region 418. The FTV power extraction structure 402 includes an FTV contact 422, an MD contact 424, and a VDR contact 426. An extension or micro-shift 430 of the first back-side metallization layer BMO 406 electrically connects to and transmits power VDD to the FTV contact 422. The FTV contact 422 is electrically connected to the MD contact 424, the MD contact 424 is electrically connected to the VDR contact 426, and the VDR contact 426 is electrically connected to the first front-side metallization layer MO 404d. The first front-side metallization layer MO 404d is electrically connected to the second front-side metallization layer M1 432 through a first via 434, and the second front-side metallization layer M1 432 is electrically connected to the first front-side metallization layer MO 404a for power VDD through a second via 436.

[0083] The power supply voltage VDD flows from the first back metallization layer BM0 406 to the FTV contact 422, to the MD contact 424, to the VDR contact 426, to the first front metallization layer M0 404d, to the first via 434, to the second front metallization layer M1 432, to the second via 436, and to the first front metallization layer M0 404a, and in some embodiments, to the VDD distribution network.

[0084] Figures 20 and 21 are schematic illustrations of a device 440 including an FTV-type power extraction cell or structure 442 for transmitting a power supply voltage VSS from the back side of the device 440 to the front side of the device 440. The FTV-type power extraction structure 442 is located in the central region of the device 440, and a protrusion or micro-shift 470 of the first back-side metallization layer BMO 448 extends to the central region to contact the FTV-type power extraction structure 442. Furthermore, a recess or indentation in the first back-side metallization layer BMO 446 corresponds to the micro-shift 470 to avoid interference between the first back-side metallization layer BMO 446 and the first back-side metallization layer BMO 448. The height of the micro-shift 470 is referred to as the micro-shift distance J. In some embodiments, the device 440 is referred to as a power extraction cell. In some embodiments, the device 440 is similar to the device 40 of Figure 1.

[0085] Figure 20 is a schematic diagram illustrating, according to some embodiments, an apparatus 440 including an FTV power extraction structure 442, first front metallization layers MO 444a-444g, and first back metallization layers BMO 446 and 448 for transmitting power supply voltage VSS. The first front metallization layers MO 444a-444g are located above or on top of the FTV power extraction structure 442, and the first back metallization layers BMO 446 and 448 are located below or beneath the FTV power extraction structure 442. The power distribution network in the first front metallization layers MO 444a-444g is different for power supply VDD and power supply VSS. Furthermore, the apparatus 440 includes gate contacts 450, such as PO gates or lines, and edge fingers 452, such as edge PO fingers. For clarity, the first front metallization layers M0 444a~444g and the first back metallization layers BMO 446 and 448 are drawn separately.

[0086] Device 440 includes an N-type well active region 454 having a P-type epitaxial layer active region 456, and a P-type well active region 458 having an N-type epitaxial layer active region 460. FTV power supply structure 442 passes through the N-type well active region 454 and the P-type well active region 458 to deliver power supply voltage VSS.

[0087] The FTV power supply structure 442 includes an FTV contact 462, an MD contact 464, and a VDR contact 466. A first back-side metallization layer BMO 448 includes a base portion 468 and a protrusion (extension) or micro-shift 470 extending from the base portion 468 and located below the FTV contact 462. The first back-side metallization layer BMO 446 is recessed or recessed to avoid interference between the first back-side metallization layer BMO 446 and the first back-side metallization layer BMO 448. The micro-shift 470 of the first back-side metallization layer BMO 448 electrically connects to and transmits power VSS to the FTV contact 462, the FTV contact 462 is electrically connected to the MD contact 464, the MD contact 464 is electrically connected to the VDR contact 466, and the VDR contact 466 is electrically connected to a first front-side metallization layer MO 444d for the power VSS. The first front metallization layer M0 444d is electrically connected to the second front metallization layer M1 472 through a first via 474, and the second front metallization layer M1 472 is electrically connected to the first front metallization layer M0 444g through a second via 476. In some embodiments, the first front metallization layer M0 444g is connected to the VSS PDN.

[0088] Figure 21 is a schematic cross-sectional view of device 440 taken along line FF in Figure 20 according to some embodiments. Device 440 includes a first front metallization layer M0 444a~444g located above or on top of FTV power extraction structure 442, and a first back metallization layer BMO 446 and 448 located below or below FTV power extraction structure 442. In addition, a second front metallization layer M1 472 is located above or on top of the first front metallization layers M0 444a~444g.

[0089] The FTV power extraction structure 442 passes through the N-type well active region 454 and the P-type well active region 458. The FTV power extraction structure 442 includes an FTV contact 462, an MD contact 464, and a VDR contact 466. An extension or micro-shift 470 of the first back-side metallization layer BMO 448 electrically connects to and transmits power VSS to the FTV contact 462. The FTV contact 462 is electrically connected to the MD contact 464, the MD contact 464 is electrically connected to the VDR contact 466, and the VDR contact 466 is electrically connected to the first front-side metallization layer MO 444d. The first front-side metallization layer MO 444d is electrically connected to the second front-side metallization layer M1 472 through a first via 474, and the second front-side metallization layer M1 472 is electrically connected to the first front-side metallization layer MO 444g for power VSS through a second via 476.

[0090] The power supply voltage VSS flows from the first back metallization layer BM0 448 to the FTV contact 462, to the MD contact 464, to the VDR contact 466, to the first front metallization layer M0 444d, to the first via 474, to the second front metallization layer M1 472, to the second via 476, and to the first front metallization layer M0 444g, and in some embodiments, to the VSS distribution network.

[0091] Figure 22 is a diagram illustrating the features of a VB-type power supply cell in row 500 and an FTV-type power supply cell in row 502, according to some embodiments. The power supply cell features include a first back-side metallization layer BMO pattern in column 504, power connections in column 506, and resistors and capacitors in column 508.

[0092] In row 500, the first back-side metallization layer BMO pattern in column 504 of the VB-type power supply cell does not have an extension or micro-shift for connecting to the power supply cell. However, in row 502, the first back-side metallization layer BMO pattern in column 504 of the FTV-type power supply cell has an extension or micro-shift for connecting to the power supply cell.

[0093] In row 500, the power supply connected in column 506 of the VB type power supply cell is VDD and / or VSS, while in row 502, the power supply connected in column 506 of the FTV type power supply cell is either VDD or VSS.

[0094] In row 500, the resistance and capacitance of the VB type power supply cell in column 508 are relatively high, while in row 502, the resistance and capacitance of the FTV type power supply cell in column 508 are relatively low.

[0095] Figure 23 is a schematic diagram illustrating, according to some embodiments, a device 520 including a clock cell 522 and power-taking cells 524 surrounding all sides of the clock cell 522. The power-taking cells 524 are embedded in the device 520, and the clock cell 522 is located on the element side of the device 520. In some embodiments, the device 520 is similar to the device 40 of Figure 1. In some embodiments, the clock cell 522 is similar to circuit 42 (shown in Figure 1). In some embodiments, the power-taking cell 524 is similar to power-taking cell 44 (shown in Figure 1). In some embodiments, the clock cell 522 is similar to clock cell 140 (shown in Figure 7). In some embodiments, the power-taking cell 524 is similar to power-taking cell 142 (shown in Figure 7).

[0096] Clock cell 522 includes two long sides 526a and 526b and two short sides 528a and 528b, and power supply cell 524 includes two long sides 530a and 530b and two short sides 532a and 532b. Power supply cell 524 is configured to deliver one or more voltages, such as power supply voltages VDD and VSS, from the back side of device 520 to the component side of device 520.

[0097] The power extraction cell 524 includes a plurality of VDD power extraction structures 534, which deliver a power voltage VDD from the back side of the device 520 to the front side of the device 520. The plurality of VDD power extraction structures 534 deliver the power voltage VDD to VDD power rails 536a and 536b located on two opposing or opposite long sides 526a and 526b of the clock cell 522. The VDD power extraction structures 534 deliver the power voltage VDD to a first metal layer M0 serving as VDD power rail 536a and a first metal layer M0 serving as VDD power rail 536b. In some embodiments, each VDD power extraction structure 534 is similar to the VDD power extraction cell 260, delivering the power voltage VDD from the back side of the device 250 to the element side of the device 250 and the clock cell 252, as shown and described in Figures 12 and 13.

[0098] The power extraction cell 524 includes a plurality of VSS power extraction structures 538, which transmit power voltage VSS from the back side of the device 520 to the front side of the device 520. The plurality of VSS power extraction structures 538 transmit power voltage VSS to M0 VSS power rails 540a-540c located on two opposing or opposite long sides 530a and 530b of the power extraction cell 524 and at the center of the device 520. The VSS power extraction structures 538 transmit power voltage VSS to the first metal layer M0 serving as M0 VSS power rail 540a, the first metal layer M0 serving as M0 VSS power rail 540b, and the first metal layer M0 serving as M0 VSS power rail 540c. The M0 VSS power rails 540a-540c are electrically connected to each other via a second front metallization layer M1 serving as M1 VSS power rails 542a-542f. In this embodiment, the M1 VSS power rails 542a~542f are electrically connected to the M0 VSS power rails 540a~540c through through holes 544. In some embodiments, each VSS power extraction structure 538 is similar to one or more VB-type power extraction structures 220a~220f, which transfer the power supply voltage VSS from the back side of the device 200 to the component side of the device 200, as shown and described in Figures 9~11.

[0099] The power supply cell 524 reduces the wire length from power supplies VDD and VSS to clock cell 522. Furthermore, the power supply cell 524 reduces the IR voltage drop from power supplies VDD and VSS to clock cell 522 and improves wiring resources.

[0100] Figure 24 is a diagram illustrating a method for manufacturing an integrated circuit according to some embodiments. In step 560, the method includes providing a substrate having a front side and a back side opposite to the front side. In some embodiments, the substrate is similar to substrate 202 (shown in Figure 9).

[0101] In step 562, the method includes forming an active region on the front side of the substrate, and in step 564, the method includes forming an epitaxial active region within the active region. In some embodiments, the active region is an N-type well active region and a P-type well active region. In some embodiments, the active region is similar to well active regions 204 and 206 (shown in FIG. 11), 292 (shown in FIG. 13), 314 and 318 (shown in FIG. 15), 354 and 358 (shown in FIG. 17), 414 and 418 (shown in FIG. 19), and 454 and 458 (shown in FIG. 21). In some embodiments, the epitaxial active region is similar to an N-type epitaxial active region or a P-type epitaxial active region, such as active regions 230 and 236 (shown in FIG. 11), 256c and 258a (shown in FIG. 13), 316 and 320 (shown in FIG. 15), 356 and 360 (shown in FIG. 17), 416 and 420 (shown in FIG. 19), and 456 and 460 (shown in FIG. 21).

[0102] In step 566, the method includes forming an MD contact electrically connected to the active region, and in step 568, the method includes forming a VDR contact electrically connected to the MD contact. In some embodiments, the MD contact is similar to MD contacts 232b and 232e (shown in FIG. 11), 288 (shown in FIG. 13), 324a (shown in FIG. 15), 364a (shown in FIG. 17), 424 (shown in FIG. 19), and 464 (shown in FIG. 21). In some embodiments, the VDR contact is similar to VDR contacts 234 and 238 (shown in FIG. 11), 290 (shown in FIG. 13), 326 (shown in FIG. 15), 366 (shown in FIG. 17), 426 (shown in FIG. 19), and 466 (shown in FIG. 21).

[0103] In step 570, the method includes forming a front-side metallization layer electrically connected to the VDR contact on the VDR contact, and in step 572, the method includes forming a back-side metallization layer electrically coupled to at least one active region in the active region below the back side of the substrate. A transistor is formed in a circuit on the front side of the substrate, and a first power supply is formed on a first side of the circuit to transfer one or more voltages from the back-side metallization layer to the front-side metallization layer. In some embodiments, the front-side metallization layer is similar to front-side metallization layers 222a-222g (shown in FIG. 11), 262 (shown in FIG. 13), 304a-304g (shown in FIG. 15), 344a-344g (shown in FIG. 17), 404a-404g (shown in FIG. 19), and 444a-444g (shown in FIG. 21). In some embodiments, the back metallization layers are similar to back metallization layers 208 and 210 (shown in FIG. 11), 282 (shown in FIG. 13), 306 and 308 (shown in FIG. 15), 346 and 348 (shown in FIG. 17), 406 and 408 (shown in FIG. 19), and 446 and 448 (shown in FIG. 21).

[0104] In some embodiments, the first power source is similar to power source cells 220 (shown in FIG. 11), 260 (shown in FIG. 13), 302 (shown in FIG. 15), 342 (shown in FIG. 17), 402 (shown in FIG. 19), and / or 442 (shown in FIG. 21). In some embodiments, the circuit is similar to circuit 42 (shown in FIG. 1) and / or clock cell 252 (shown in FIG. 12).

[0105] In some embodiments, the method includes forming a second power supply draw on a second side of the circuit, the second side being opposite to a first side of the circuit, to transfer one or more voltages from a back-side metallization layer to a front-side metallization layer.

[0106] In some embodiments, the method includes forming a VB contact electrically connected to at least one active region of the epitaxial layer, wherein forming the back metallization layer includes electrically connecting the back metallization layer to the VB contact.

[0107] In some embodiments, the method includes forming an FTV electrically connected to at least one of the MD contacts, wherein forming a back-side metallization layer includes electrically connecting the back-side metallization layer to the FTV. In some embodiments, the method includes forming a back-side metallization layer including micro-shift extensions for electrically connecting to the FTV.

[0108] Figure 25 is a block diagram schematically illustrating an example of a computer system 600 configured to provide devices (including electronic devices and semiconductor devices) and the methods disclosed herein, according to some embodiments. Some or all of the design, layout, and fabrication of the semiconductor devices (also referred to as semiconductor circuits) may be performed by or with the assistance of the computer system 600. Furthermore, some or all of the design, layout, and fabrication of devices, including electronic devices, may be performed by or with the assistance of the computer system 600. In some embodiments, the computer system 600 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an integrated circuit.

[0109] In some embodiments, system 600 is a general-purpose computing device including processor 602 and non-transitory computer-readable storage medium 604. Computer-readable storage medium 604 may be encoded with (i.e., stored) computer program code, such as executable instructions 606. When processor 602 executes instructions 606, it provides (at least partially) a design tool that implements some or all of the functions of system 600, such as pre-placement simulation, post-placement simulation, routing, rerouting, and final placement for manufacturing. Further, manufacturing tools 608 are included to design and manufacture semiconductor devices for further placement and physical implementation. In some embodiments, processor 602, when executing instructions 606, provides (at least partially) a design tool that implements some or all of the functions of system 600. In some embodiments, system 600 includes a commercial router. In some embodiments, system 600 includes an automatic place and route (APR) system.

[0110] Processor 602 is electrically coupled to computer-readable storage medium 604 via bus 610 and to I / O interface 612 via bus 610. Network interface 614 is also electrically connected to processor 602 via bus 610. Network interface 614 is connected to network 616, enabling processor 602 and computer-readable storage medium 604 to connect to external components using network 616. Processor 602 is configured to execute computer program code or instructions 606 encoded in computer-readable storage medium 604 to cause system 600 to perform some or all of the functions of system 600, such as providing the semiconductor apparatus and methods disclosed herein and other functions of system 600. In some embodiments, processor 602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0111] In some embodiments, computer-readable storage media 604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system or device. For example, computer-readable storage media 604 may include semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), read-only memory (ROM), hard disk, and / or optical disc. In some embodiments using optical discs, computer-readable storage media 604 may include a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disc (DVD).

[0112] In some embodiments, computer-readable storage medium 604 stores computer program code or instructions 606 configured to cause system 600 to perform some or all of the functions of system 600. In some embodiments, computer-readable storage medium 604 also stores information that facilitates the performance of some or all of the functions of system 600. In some embodiments, computer-readable storage medium 604 stores a database 618, including one or more component libraries, digital circuit cell libraries, and databases.

[0113] System 600 includes an I / O interface 612 coupled to external circuitry. In some embodiments, the I / O interface 612 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and instructions to processor 602.

[0114] Network interface 614 is coupled to processor 602 and allows system 600 to communicate with network 616, to which one or more other computer systems are connected. Network interface 614 includes a wireless network interface, such as BlueTouch, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In some embodiments, some or all of the functionality of system 600 may be performed in two or more systems similar to system 600.

[0115] System 600 is configured to receive information through I / O interface 612. The information received through I / O interface 612 includes one or more instructions, data, design rules, components and cell libraries, and / or other parameters for processing by processor 602. The information is transmitted to processor 602 via bus 610. Furthermore, system 600 is configured to receive information related to the user interface (UI) through I / O interface 612. This UI information can be stored in computer-readable storage media 604 as UI 620.

[0116] In some embodiments, some or all of the functions of system 600 are implemented through a standalone software application executed by a processor. In some embodiments, some or all of the functions of system 600 are implemented in a software application that is part of an additional software application. In some embodiments, some or all of the functions of system 600 are implemented as a plug-in to the software application. In some embodiments, at least one function of system 600 is implemented as a software application that is part of an electronic design automation (EDA) tool. In some embodiments, some or all of the functions of system 600 are implemented as a software application used by system 600. In some embodiments, layout diagrams are generated using, for example, VIRTUOSO, available from Cadence Design Systems, Inc., or another suitable layout generation tool.

[0117] In some embodiments, wiring, layout, and other processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical discs, such as digital video discs or digital multifunction discs (DVDs), magnetic disks such as hard disks, semiconductor memories such as read-only memory (ROM) and random access memory (RAM), memory cards, etc.

[0118] As described above, embodiments of system 600 include manufacturing tool 608 for implementing manufacturing processes for system 600. For example, based on the final layout, a photolithography mask can be generated, which is used to manufacture semiconductor devices using manufacturing tool 608.

[0119] Referring to FIG26, which discloses further details of device fabrication, FIG26 is a block diagram of a semiconductor device fabrication system 622 and its associated semiconductor device fabrication process according to some embodiments. In some embodiments, based on the layout diagram, the fabrication system 622 is used to fabricate one or more semiconductor photomasks and / or at least one element in a semiconductor device layer.

[0120] In Figure 26, the semiconductor device manufacturing system 622 includes entities such as a design studio 624, a photomask fabrication terminal 626, and a semiconductor device fabrication plant ("plant") 628, which interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of semiconductor devices (as described herein). The entities in system 622 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 624, photomask fabrication terminal 626, and semiconductor device fabrication plant 628 are owned by a single, larger company. In some embodiments, two or more of the design studio 624, photomask fabrication terminal 626, and semiconductor device fabrication plant 628 coexist in a shared facility and use shared resources.

[0121] Design studio (or design team) 624 generates a semiconductor device design layout 630. The semiconductor device design layout 630 includes various geometric patterns, or a semiconductor device layout designed for a semiconductor device. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various elements of the semiconductor structure to be manufactured. The layers are bonded together to form various semiconductor device features. For example, portions of the semiconductor device design layout 630 include various semiconductor device features such as diagonal vias, active regions or regions, gate electrodes, source electrodes, drain electrodes, metal lines, partial vias, and openings for bonding pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 624 performs design procedures to generate the semiconductor device design layout 630. The semiconductor device design layout 630 is presented in one or more data files containing geometric pattern information. For example, the semiconductor device design layout 630 can be expressed in GDSII or DFII file format. In some embodiments, the design process includes one or more of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, distribution network (PDN) design including power via design, supply voltage trace design, reference voltage trace design, placement and wiring conventions, and physical layout design.

[0122] The photomask fabrication end 626 includes data preparation 632 and photomask fabrication 634. The photomask fabrication end 626 uses a semiconductor device design layout 630 to fabricate one or more photomasks 636 for use in fabricating various layers of a semiconductor device or semiconductor structure. The photomask fabrication end 626 performs photomask data preparation 632, wherein the semiconductor device design layout 630 is translated into a representative data file (RDF). Photomask data preparation 632 provides the RDF to photomask fabrication 634. Photomask fabrication 634 includes a photomask writer that converts the RDF into an image on a substrate, such as a photomask (screen) 636 or a semiconductor wafer 638. The semiconductor device design layout 630 is manipulated by photomask data preparation 632 to conform to the characteristics of the photomask writer and / or the standards of the semiconductor device fabrication plant 628. In Figure 26, photomask data preparation 632 and photomask fabrication 634 are shown as separate elements. In some embodiments, photomask data preparation 632 and photomask fabrication 634 may be collectively referred to as photomask data preparation.

[0123] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. OPC adjusts the semiconductor device design layout diagram 630. In some embodiments, mask data preparation 632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0124] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC) that examines the semiconductor device design layout 630, which has been processed in the OPC, using a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margin to account for the variability of the semiconductor manufacturing process, and the like. In some embodiments, the MRC modifies the semiconductor device design layout 630 to compensate for constraints during mask manufacturing 634, which may undo some modifications performed by the OPC to comply with the mask creation rules.

[0125] In some embodiments, mask data preparation 632 includes lithography process checking (LPC), a process simulated by a semiconductor device fabrication plant 628. LPC simulates this process based on the semiconductor device design layout 630 to create a simulated fabricated device. Processing parameters in the LPC simulation may include parameters related to various processes in the semiconductor device manufacturing cycle, parameters related to the tools used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and similar or combinations thereof. In some embodiments, after the simulated fabricated device has been created by LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the semiconductor device design layout 630.

[0126] For clarity, the description of the above photomask data preparation 632 has been simplified. In some embodiments, data preparation 632 includes additional features such as logic operations (LOPs) to modify the semiconductor device design layout 630 according to manufacturing rules. Furthermore, the processes applied to the semiconductor device design layout 630 during data preparation 632 can be performed in various different sequences.

[0127] After photomask data preparation 632 and during photomask fabrication 634, a photomask 636 or a set of photomasks 636 is fabricated based on a modified semiconductor device design layout 630. In some embodiments, photomask fabrication 634 includes performing one or more lithography exposures based on the semiconductor device design layout 630. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on the photomask (photomask or reticle) 636 based on the modified semiconductor device design layout 630. The photomask 636 can be formed using different techniques. In some embodiments, the photomask 636 is formed using a binary technique. In some embodiments, the photomask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary photomask version of photomask 636 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary photomask. In another example, photomask 636 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of photomask 636, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuating PSM or an alternating PSM. The photomask produced by photomask fabrication 634 is used in various processes. For example, such a photomask is used in ion implantation processes to form various doped regions in semiconductor wafer 638, in etching processes to form various etched regions in semiconductor wafer 638, and / or for other suitable processes.

[0128] Semiconductor device fabrication plant 628 includes wafer fabrication 640. Semiconductor device fabrication plant 628 is a semiconductor device manufacturing plant that includes one or more manufacturing facilities for manufacturing various semiconductor device products. In some embodiments, semiconductor device fabrication plant 628 is a semiconductor foundry. For example, there are manufacturing facilities for fabricating the front end of line (FEOL) of multiple semiconductor device products, while a second manufacturing facility can provide fabrication of the back end of line (BEOL) for interconnects and packaging of semiconductor device products, and a third manufacturing facility can provide other foundry services.

[0129] Semiconductor device fabrication plant 628 uses a photomask 636, fabricated by photomask fabrication end 626, to fabricate the semiconductor structure or semiconductor device 642 disclosed herein. Therefore, semiconductor device fabrication plant 628 uses at least indirectly the semiconductor device design layout 630 to fabricate the semiconductor structure or semiconductor device 642 disclosed herein. Furthermore, semiconductor wafer 638 includes a silicon substrate or other suitable substrate having material layers formed thereon, and semiconductor wafer 638 also includes one or more various doped regions, dielectric features, multilayer interconnects, and the like (formed in subsequent fabrication steps). In some embodiments, semiconductor wafer 638 is fabricated by semiconductor device fabrication plant 628 using photomask 636 to form the semiconductor structure or semiconductor device 642 disclosed herein. In some embodiments, semiconductor device fabrication includes performing one or more lithography exposures at least indirectly based on semiconductor device design layout 630.

[0130] Therefore, the disclosed embodiments include different placements of power supply structures next to circuits (e.g., clock cells) and different types of power supply structures, such as VB-type power supply structures and FTV-type power supply cell structures.

[0131] The disclosed embodiments include an apparatus comprising a substrate having at least one active region and circuitry located on the substrate element side. A front metallization layer is disposed above the circuitry, while a back metallization layer is disposed below the back side of the substrate. A first power extraction structure is located on one side of the circuitry for transmitting one or more voltages from the back metallization layer to the front metallization layer, and in some embodiments, a second power extraction structure is located on the other side of the circuitry, opposite to one side of the circuitry, for transmitting one or more voltages from the back metallization layer to the front metallization layer.

[0132] In some embodiments, the power supply structure includes a back metallization layer electrically connected to VB, VB electrically connected to an epitaxial layer, the epitaxial layer electrically connected to an MD contact, the MD contact electrically connected to a VDR contact, and the VDR contact electrically connected to a front metallization layer. Thus, the power supply voltage is conducted from the back metallization layer to the front metallization layer via VB, the epitaxial layer, the MD contact, and the VDR contact.

[0133] In some embodiments, the power supply structure includes an FTV, an MD contact, and a VDR contact, wherein the back metallization layer is electrically connected to the FTV, the FTV is electrically connected to the MD contact, the MD contact is electrically connected to the VDR contact, and the VDR contact is electrically connected to the front metallization layer. Thus, the power supply voltage is conducted from the back metallization layer to the front metallization layer through the FTV, MD contact, and VDR contact.

[0134] The disclosed embodiments further include a method of manufacturing an integrated circuit, comprising forming a substrate having a component side and a back side opposite to the component side; forming an active region on the component side of the substrate; forming a circuit on the component side of the substrate; forming a front metallization layer above the circuit; forming a back metallization layer below the back side of the substrate and electrically coupling it to at least one active region in the active region; and forming a power-harvesting cell on one side of the circuit to transfer one or more voltages from the back metallization layer to the front metallization layer.

[0135] According to some embodiments, an integrated circuit includes a substrate having a component side and a back side opposite to the component side. The substrate includes at least one active region on the component side. A circuit is located on the component side of the substrate, and a front metallization layer is disposed above the circuit. A back metallization layer is disposed below the back side of the substrate, and a first power supply is located on a first side of the circuit. The first power supply is configured to deliver one or more voltages from the back metallization layer to the front metallization layer, the back metallization layer being electrically coupled to at least one active region.

[0136] According to a further embodiment, the device includes a substrate having a component side and a back side opposite to the component side. A circuit is located on the component side of the substrate, and a first front-side metallization layer is disposed on the substrate. A back-side metallization layer is disposed below the back side of the substrate, and a first power supply is located on a first side of the circuit. The first power supply includes an FTV, an MD contact, and a VDR contact, electrically connected from the back-side metallization layer to the first front-side metallization layer.

[0137] According to a further disclosed aspect, a method of manufacturing an integrated circuit includes providing a substrate having a component side and a back side opposite to the component side; forming an active region on the component side of the substrate; forming an epitaxial active region in the active region; forming an MD contact electrically connected to the active region; forming a VDR contact electrically connected to the MD contact; forming a front metallization layer above the VDR contact and electrically connected to the VDR contact; forming a back metallization layer below the back side of the substrate and electrically coupled to at least one active region in the active region, wherein transistors are formed in the circuit on the component side of the substrate, and a first power supply is formed on a first side of the circuit to deliver one or more voltages from the back metallization layer to the front metallization layer.

[0138] This disclosure outlines various embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications to this document without departing from its spirit and scope.

[0139] 40, 200, 250, 300, 340, 400, 440, 520: Device 42, 168: Circuit 44, 48, 142, 174, 254, 524, PU: Power supply cells 46, 60, 80, 100, 120, 140, 252, 522: Clock cell 62, 82, 102, 122, 176: First power supply cell 64, 84, 104, 124, 178: Second power supply cells 50a, 50b, 54a, 54b, 66a, 66b, 70a, 70b, 74a, 74b, 86a, 86b, 90a, 90b, 94a, 94b, 106a, 106b, 110a, 110b, 114a, 114b, 126a, 126b, 130a, 130b, 134a, 134b, 146a, 146b, 150a, 150b, 526a, 526b, 530a, 530b: Long side 52a, 52b, 56a, 56b, 68a, 68b, 72a, 72b, 76a, 76b, 88a, 88b, 92a, 92b, 96a, 96b, 108a, 108b, 112a, 112b , 116a, 116b, 128a, 128b, 132a, 132b, 136a, 136b, 148a, 148b, 152a, 152b, 528a, 528b, 532a, 532b: short side 160: Circuit Options 162: Reference Circuit 164: Single-sided power supply cell circuit 166: Dual-sided power supply cell circuit 170:FTV-I 172:FTV-O 202:Substrate 204, 314, 354, 414, 454: Active regions of N-type traps 206, 318, 358, 418, 458: Active region of P-type trap 208, 210, 306, 308, 346, 348, 406, 408, 446, 448, BMO: First back-side metallization layer 220a~220f: VB type power supply structure 222a~222g, 304a~304g, 344a~344g, 404a~404g, 444a~444g, M0: First front metallization layer 224, 310, 350, 410, 450: Gate contact 226, 312, 352, 412, 452: Edge finger-like structures 228a~228f: VB contact element 230, 316, 356, 416, 456: Active regions of P-type epitaxial layers 232a~232f, 324a, 324b, 364a, 364b, 424, 464: MD contacts 234, 238, 326, 366, 426, 466: VDR contacts 236, 320, 360, 420: Active regions of N-type epitaxial layers 256a~256c, 258a, 258b: Active regions of epitaxial layers 260: VDD power supply cell 262: First metal layer M0 VDD power rail 264a, 264b: VSS power supply cells 266: First metal layer M0 VSS power rail 268a, 434, 474: First through hole 268b, 436, 476: Second through hole 268c: Third through hole 268d: Fourth through hole 268e: Fifth through hole 268f: Sixth through hole 268g: Seventh through hole 268h: Eighth through hole 270, 274, 276, 280, 432, 472, M1: Second front metallization layer 272: Clock Cell VDD Power Rail 278: Clock Cell VSS Power Rail 288: MD layer 290:VDR 328, 368, 428, 468: Basic Part 330, 370, 430, 470: Micro-shift 302, 342: FTV power supply cell structure 322, 362, 422, 462: FTV contact components 402, 442: FTV power supply structure 500, 502: lines 504, 506, 508: Columns 534: VDD power supply structure 536a, 536b: VDD power rails 538: VSS power supply structure 540a~540c:M0 VSS power rail 542a~542f:M1 VSS power rail 544: Through hole 560, 562, 564, 566, 568, 570, 572: Steps 600, 622: System 602: Processor 604: Storage Media 606: Instruction 608: Manufacturing Tools 610: Busbar 612:I / O interface 614: Network Interface 616: Internet 618: Database 620: User Interface (UI) 624: Design Studio 626: Photomask manufacturing end 628: Manufacturing Plant 630: IC Design Layout Diagram / IC Design Layout Diagram 632: Data Preparation 634: Photomask Manufacturing 636: Photomask 638: Wafer 640: Wafer Fabrication 642: Semiconductor device AA, BB, CC, DD, EE, FF: Line FTV: Through-hole J: Micro-movement distance L1, L2, L3, L4, L5, L6, L7, L8, L9, L10: Length VB: Backside through hole VDD, VSS: Power supply voltage

Claims

1. An integrated circuit, comprising: A substrate having a front side and a back side opposite to the front side, the substrate including at least one active region on the front side; The circuit is located on the front side of the substrate; A front metallization layer is disposed above the circuit; a back metallization layer is disposed below the back side of the substrate; a first power supply cell is located on a first side of the circuit and configured to transfer one or more voltages from the back metallization layer to the front metallization layer, the back metallization layer being electrically coupled to the at least one active region. The back metallization layer includes a through-hole, a first metal-covered drain contact, and a first through-hole to drain contact, wherein the back metallization layer is electrically coupled to the front metallization layer through the through-hole, the first metal-covered drain contact, and the first through-hole to drain contact, wherein the first metal-covered drain contact is electrically connected to a P-type epitaxial layer, and the back metallization layer includes a body and a segment, wherein the segment extends from the body and includes a micro-shift for connection to the through-hole, and the width of the segment is shorter than the width of the body.

2. The integrated circuit as claimed in claim 1, including a second power supply cell located on a second side of the circuit, the second side being opposite to a first side of the circuit, and configured to transfer the one or more voltages from the back metallization layer to the front metallization layer.

3. The integrated circuit as claimed in claim 1, comprising a first back-side via, a P-type epitaxial layer, a second metal-covered drain contact, and a second via-to-drain contact, wherein the back-side metallization is electrically coupled to the front-side metallization through the first back-side via, the P-type epitaxial layer, the second metal-covered drain contact, and the second via-to-drain contact, such that a first voltage of the one or more voltages is conducted between the back-side metallization and the front-side metallization through the first back-side via, the P-type epitaxial layer, the second metal-covered drain contact, and the second via-to-drain contact.

4. The integrated circuit as claimed in claim 3, comprising a second back-side via, an N-type epitaxial layer, a third metal-covered drain contact, and a third via-to-drain contact, wherein the back-side metallization is electrically coupled to the front-side metallization through the second back-side via, the N-type epitaxial layer, the third metal-covered drain contact, and the third via-to-drain contact, such that a second voltage of the one or more voltages is conducted between the back-side metallization and the front-side metallization through the second back-side via, the N-type epitaxial layer, the third metal-covered drain contact, and the third via-to-drain contact.

5. The integrated circuit as claimed in claim 1, wherein the voltage VDD of one or more voltages is conducted between the back metallization and the front metallization through the through-hole, the first metal-covered drain contact, and the first through-hole to drain contact.

6. An integrated circuit, comprising: A substrate having a front side and a back side opposite to the front side; The circuit is located on the front side of the substrate; A first front-side metallization layer is disposed on the substrate; A back-side metallization layer is disposed below the back side of the substrate; and a first power-taking cell is located on a first side of the circuit and includes a through-hole, a metal-covered drain contact, and a through-hole-to-drain contact electrically connected from the back-side metallization layer to the first front-side metallization layer, wherein the back-side metallization layer includes a body and a segment, the segment extending from the body and including a micro-shift for connection to the through-hole, the width of the segment being shorter than the width of the body.

7. The integrated circuit of claim 6, comprising a second front metallization layer disposed above the first front metallization layer, a first via and a second via, wherein the first front metallization layer is electrically connected to the second front metallization layer through the first via, and the second front metallization layer is electrically connected to a power rail in the first front metallization layer through the second via.

8. The integrated circuit as claimed in claim 6, including a second power supply cell located on a second side of the circuit, the second side being opposite to a first side of the circuit, and configured to deliver a first voltage VDD or a second voltage VSS from the back metallization layer to the front metallization layer.

9. A method for manufacturing an integrated circuit, comprising: A substrate is provided having a front side and a back side opposite to the front side; An active region is formed on the front side of the substrate; An epitaxial active region is formed in the active region; a metal-covered drain contact electrically connected to the active region is formed; a via-to-drain contact electrically connected to the metal-covered drain contact is formed; a front metallization layer is formed above the via-to-drain contact and electrically connected to the via-to-drain contact; and a back metallization layer is formed below the back side of the substrate and electrically coupled to at least one active region of the active region, wherein a transistor is formed in a circuit on the front side of the substrate, and a first power supply cell is formed on a first side of the circuit to deliver one or more voltages from the back metallization layer to the front metallization layer, wherein forming the back metallization layer includes forming a back metallization layer segment, the back metallization layer including a body and a segment, the segment extending from the body and including a micro-shift for connection to the via, the width of the segment being shorter than the width of the body.

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