Semiconductor device and method of forming thereof

Abstract

This disclosure relates to the structure of a semiconductor device and a method of forming the structure. The structure may include a substrate having an active region and a dummy region on a first side of the substrate. The active region may include an active transistor to ensure proper operation of the semiconductor device; while the dummy region may include dummy structures (e.g., dummy transistors) to avoid denting problems due to loading effects during structure fabrication. The dummy structures may be electrically coupled to the active transistor through embedded contacts in the substrate. The structure may also include a wafer bonded to a second side of the substrate and silicon vias contacting the dummy structures and bonding pads on the second side of the substrate. Each silicon via may contact an array of dummy structures.

Claims

1. A semiconductor device, comprising: A first wafer, wherein the first wafer includes: a plurality of photosensitive sensors located on a first side of the first wafer; and a first interconnect structure located on a second side of the first wafer and electrically coupled to the photosensitive sensors; a second wafer bonded to the first wafer, wherein the second wafer includes: a second interconnect structure located on a first side of the second wafer and electrically coupled to the first interconnect structure; a plurality of active transistors coupled to the second interconnect structure; a plurality of dummy transistors electrically coupled to the active transistors; and a silicon via electrically coupled from a second side of the second wafer to the dummy transistors; and a third wafer bonded to the second wafer, wherein the third wafer includes: an image processor; and a third interconnect structure connecting the image processor and the silicon via.

2. The apparatus as claimed in claim 1, wherein the silicon via is in contact with a gate structure of the dummy transistors.

3. The apparatus as claimed in claim 1, wherein the via is in contact with a source / drain region of the dummy transistors.

4. The apparatus as claimed in claim 1, wherein the silicon via contacts a bonding pad on the second side of the second wafer, wherein the bonding pad is bonded to another bonding pad on the third wafer.

5. A semiconductor device, comprising: A plurality of active transistors are located on a first side of a substrate; A plurality of dummy transistors are located on the first side of the substrate and electrically coupled to the active transistors; an interconnect structure is located on the active transistors; a conductive pad is located on a second side of the substrate; a silicon via is electrically coupled to the dummy transistors and the conductive pad, wherein the silicon via contacts a plurality of gate structures of the dummy transistors, wherein a width of the silicon via is in ratio to a width of each of the gate structures between about 10 and about 15,000; a first wafer is bonded to the substrate on the first side of the substrate, wherein an electronic component on the first wafer is electrically coupled to the interconnect structure; And a second wafer bonded to the substrate on the second side of the substrate, wherein a processing device on the second wafer is electrically coupled to the silicon via.

6. The apparatus of claim 5, wherein the via contacts a plurality of source / drain regions of the dummy transistors, wherein the ratio of the width of the via to the width of each of the source / drain regions is between about 10 and about 10,000.

7. The apparatus as claimed in claim 5, wherein the silicon via comprises tungsten, aluminum, copper or ruthenium.

8. A method of forming a semiconductor device, comprising: A plurality of active transistors and a plurality of dummy transistors are formed on a first side of a substrate; A plurality of buried contacts are formed on the substrate to connect the active transistors and the dummy transistors; a first interconnect structure is formed on the active transistors; an opening is formed from a second side of the substrate to expose the dummy transistors; a conductive material is deposited in the opening to form a silicon via; a first wafer including a second interconnect structure is provided; the substrate is bonded to the first wafer by forming a first contact between the first interconnect structure and the second interconnect structure; a second wafer including a third interconnect structure is provided; and the substrate is bonded to the second wafer by forming a second contact between the TSV and the third interconnect structure.

9. The method as described in claim 8, wherein forming the dummy transistors includes forming a gate structure array of the dummy transistors.

10. The method as described in claim 8, wherein forming the dummy transistors includes forming a source / drain region array of the dummy transistors.

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