Semiconductor structure and its preparation method

Abstract

This invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate comprising a plurality of active regions arranged in an array along a first direction and a second direction; a transistor unit formed on each active region, the transistor unit including a first transistor and a second transistor, the first transistor and the second transistor sharing a drain; a resistive switching unit formed on each drain, each resistive switching unit including a first memristor and a second memristor; and a plurality of word lines extending along the second direction, wherein in each transistor unit, the first transistor is connected to one word line and the second transistor is connected to another word line.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its preparation method. [Previous Technology]

[0002] Resistive Random Access Memory (RRAM) is a non-volatile memory that uses the variable resistance of materials to store information. It has advantages such as low power consumption, high density, fast read and write speed, and good durability.

[0003] However, in the existing 2T2R structure, one transistor controls one R, and there are difficulties in resetting, the required reset operation voltage is high, and the size is difficult to shrink, which will lead to the problem of insufficient transistor drive. [Summary of the Invention]

[0004] The present invention provides a semiconductor structure and a method for preparing the same, so as to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of the present invention, a semiconductor structure is provided, the semiconductor structure comprising:

[0006] A substrate, the substrate comprising a plurality of active regions arranged in an array along a first direction and a second direction;

[0007] A transistor unit is formed on each of the active regions, and the transistor unit includes a first transistor and a second transistor, wherein the first transistor and the second transistor share a drain region;

[0008] A resistive switching unit is formed on each of the drain regions, and each of the resistive switching units includes a first memristor and a second memristor;

[0009] Multiple word lines extending along the second direction, wherein in each of the transistor units, the first transistor is connected to one word line and the second transistor is connected to another word line.

[0010] In one embodiment, the extension direction of the resistive switching unit intersects with the first direction and forms a preset angle, wherein the preset angle is in the range of 30° to 60°.

[0011] In one embodiment, both the first memristor and the second memristor include a lower electrode, a resistive switching layer and an upper electrode arranged from bottom to top, wherein the first memristor and the second memristor share a lower electrode.

[0012] In one embodiment, the semiconductor structure further includes:

[0013] Multiple bit lines extending along the first direction, wherein in each row of resistive switching units on the active region arranged along the first direction, all the first memristors are connected to the same bit line, and all the second memristors are connected to another bit line.

[0014] In one embodiment, the semiconductor structure further includes:

[0015] Multiple source lines extending along the first direction, in each transistor unit, the source region of the first transistor is connected to one source line, and the source region of the second transistor is connected to another source line; wherein, in two adjacent rows of transistor units on the active region arranged along the first direction, the source regions of all the first transistors in one row and the source regions of all the second transistors in the other row are connected to the same source line.

[0016] According to a second aspect of the present invention, a method for preparing a semiconductor structure is provided, the method comprising:

[0017] A substrate is provided, the substrate comprising a plurality of active regions arranged in an array along a first direction and a second direction;

[0018] A transistor unit is formed on each of the active regions, the transistor unit including a first transistor and a second transistor, the first transistor and the second transistor sharing a drain region;

[0019] A plurality of word lines extending along the second direction are formed, wherein in each transistor unit, the first transistor is connected to one word line and the second transistor is connected to another word line;

[0020] A resistive switching unit is formed on each of the drain regions, and each of the resistive switching units includes a first memristor and a second memristor.

[0021] In one embodiment, the extension direction of the resistive switching unit intersects with the first direction and forms a preset angle, wherein the preset angle is in the range of 30° to 60°.

[0022] In one embodiment, both the first memristor and the second memristor include a lower electrode, a resistive switching layer and an upper electrode arranged from bottom to top, wherein the first memristor and the second memristor share a lower electrode.

[0023] In one embodiment, the preparation method further includes:

[0024] After the resistive switching unit is formed, multiple bit lines extending along the first direction are formed, wherein in each row of resistive switching units on the active region arranged along the first direction, all the first memristors are connected to the same bit line, and all the second memristors are connected to another bit line.

[0025] In one embodiment, the preparation method further includes:

[0026] After the transistor unit is formed, a plurality of source lines extending along the first direction are formed. In each transistor unit, the source region of the first transistor is connected to one source line, and the source region of the second transistor is connected to another source line. In the adjacent rows of transistor units on the active region arranged along the first direction, the source regions of all the first transistors in one row and the source regions of all the second transistors in the other row are connected to the same source line.

[0027] The semiconductor structure and its fabrication method of the present invention use two transistors to share a drain region and then form two memristors (R) on the drain region. Therefore, two word lines can control any one of the memristors through two transistors. This is more than the 2T1R structure with one more R. At the same time, any one of the memristors can be controlled by applying excitation through two source lines simultaneously. This improves the driving capability and solves the problem of difficult reset.

[0028] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily apparent from the following description.

Implementation Method

[0036] To make the objectives, features, and advantages of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making progressive changes are within the scope of protection of the present invention.

[0037] An embodiment of the present invention provides a semiconductor structure. FIG1 is a top view of the semiconductor structure provided in the embodiment of the present invention, and FIG2 is a cross-sectional view along the dashed line A-A' in FIG1.

[0038] As shown in Figures 1 and 2, a semiconductor structure includes:

[0039] Substrate 10, the substrate 10 includes a plurality of active regions 11 arranged in an array along a first direction and a second direction;

[0040] A transistor unit is formed on each active region 11. The transistor unit includes a first transistor 21 and a second transistor 22. The first transistor 21 and the second transistor 22 share a drain region 211.

[0041] A resistive switching unit is formed on each drain region 211, and each resistive switching unit includes a first memristor 23 and a second memristor 24;

[0042] Multiple word lines 70 extending along the second direction, wherein in each transistor unit, a first transistor 21 is connected to one word line 70 and a second transistor 22 is connected to another word line 70.

[0043] In one embodiment, the substrate 10 may be a single-element semiconductor material substrate (e.g., silicon substrate, germanium substrate, etc.), a composite semiconductor material substrate (e.g., germanium silicon substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, etc.

[0044] The substrate 10 includes a plurality of active regions 11 arranged in an array along a first direction and a second direction, wherein adjacent active regions 11 are insulated from each other by a shallow trench isolation structure.

[0045] A storage cell is formed on each active region 11. The storage cell has a 2T2R structure and includes a first transistor 21, a second transistor 22, a first memristor 23 and a second memristor 24.

[0046] Figure 3 is a schematic diagram of the structure of the storage unit provided in an embodiment of the present invention.

[0047] As shown in FIG3, the first transistor 21 and the second transistor 22 both include a gate 213 located on the substrate 10 and a drain region 211 and a source region 212 located on both sides of the gate 213 within the substrate 10.

[0048] In this embodiment of the invention, the first transistor 21 and the second transistor 22 share a drain region 211.

[0049] Referring to Figure 3, the first memristor 23 and the second memristor 24 are located on the drain region 211 and are electrically connected to the drain region 211.

[0050] In this embodiment of the invention, two transistors share a drain region, and then two memristors (R) are formed on the drain region. Therefore, two word lines can control any one of the memristors through two transistors. This results in one more R than the 2T1R structure, and improves the driving capability, thus solving the problem of Reset difficulty.

[0051] Referring to Figures 1 and 2 below, the semiconductor structure provided in the embodiments of the present invention will be described in detail.

[0052] In one embodiment, the semiconductor structure further includes a first interlayer dielectric layer 41, a second interlayer dielectric layer 42, a third interlayer dielectric layer 43, a fourth interlayer dielectric layer 44 and a fifth interlayer dielectric layer 45 sequentially stacked on the substrate 10.

[0053] The material of the first interlayer dielectric layer 41 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride; the second interlayer dielectric layer 42 can be a metal interlayer dielectric layer, such as aluminum oxide or zinc oxide; the third interlayer dielectric layer 43 can be a silicon carbide thin film (Nitride Doped Silicon Carbide, NDC); the material of the fourth interlayer dielectric layer 44 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride; the material of the fifth interlayer dielectric layer 45 includes ultra-low K materials.

[0054] As shown in Figure 2, the first transistor 21 and the second transistor 22 are located within the first interlayer dielectric layer 41.

[0055] As shown in Figures 1 and 3, in each transistor unit, the first transistor 21 is connected to one word line 70, and the second transistor 22 is connected to another word line 70. Specifically, as shown in Figure 3, the word line WL is connected to the gate 213 of the transistor.

[0056] The semiconductor structure further includes: a first contact plug 51 located in the first interlayer dielectric layer 41; a metal connection layer 80 located in the second interlayer dielectric layer 42; and a second contact plug 52 located in the third interlayer dielectric layer 43; wherein the metal connection layer 80 is connected to the substrate 10 through the first contact plug 51 and to the first memristor 23 and the second memristor 24 through the second contact plug 52.

[0057] The material of the metal connection layer 80 includes, but is not limited to, metallic copper. The first contact plug 51 and the second contact plug 52 can be a double-layer structure, and the materials of the first contact plug 51 and the second contact plug 52 can include titanium nitride located on the outer layer and metallic tungsten located on the inner layer.

[0058] The first memristor 23 and the second memristor 24 are located within the fourth interlayer dielectric layer 44 and the fifth interlayer dielectric layer 45.

[0059] In one embodiment, the first memristor 23 and the second memristor 24 each include a lower electrode 201, a resistive switching layer 202 and an upper electrode 203 arranged from bottom to top, wherein the first memristor 23 and the second memristor 24 share a lower electrode 201.

[0060] The first memristor 23 and the second memristor 24 share a lower electrode 201, which makes it easy for the two transistors to control either of the memristors.

[0061] The material of the lower electrode 201 includes, but is not limited to, titanium nitride; the material of the resistive switching layer 202 includes, but is not limited to, transition metal oxides, specifically, hafnium oxide, aluminum monoxide, etc.; the material of the upper electrode 203 includes, but is not limited to, titanium nitride.

[0062] In one embodiment, as shown in FIG1, the extending direction of the resistive switching unit intersects with the first direction and forms a preset angle, the preset angle being in the range of 30° to 60°. Preferably, the preset angle is 45°.

[0063] In this embodiment, the resistive switching unit is set in an inclined manner, which allows for the setting of one more R in the same area. In order to improve the driving capability of the transistor, the present invention designs the structure of the shared SL in the prior art as a shared drain region. However, this will reduce the original 2R to 1R. Therefore, in order not to sacrifice the number of R in the same area, the inclined placement method is adopted so that the original 2R can be maintained in the same area. At the same time, the preset angle is set within this range. In this way, when setting the bit lines later, the bit lines connected to the first memristor and the second memristor can be separated so as not to come into contact and cause interference.

[0064] The semiconductor structure further includes: multiple source lines 30 (SL) extending along a first direction, wherein in each transistor unit, the source region 212 of the first transistor 21 is connected to one source line 30, and the source region 212 of the second transistor 22 is connected to another source line 30; wherein, in the transistor units on the active regions 11 arranged in two adjacent rows along the first direction, the source regions 212 of all the first transistors 21 in one row and the source regions 212 of all the second transistors 22 in the other row are connected to the same source line 30.

[0065] In this embodiment of the invention, since two memristors are formed on the shared drain region, either memristor can be controlled by applying excitation simultaneously through two source lines, thus solving the problem of difficult reset.

[0066] As shown in Figure 2, the source line 30 is located within the second interlayer dielectric layer 42.

[0067] The semiconductor structure further includes: multiple bit lines 60 (BL) extending along the first direction, wherein, in each row of active regions 11 arranged along the first direction, all first memristors 23 are connected to the same bit line 60, and all second memristors 24 are connected to another bit line 60.

[0068] Specifically, as shown in Figure 2, the first memristor 23 and the second memristor 24 are connected to the bit line 60 through the third contact plug 53.

[0069] Table 1 below shows a parameter comparison between the semiconductor structure in the prior art and the semiconductor structure in the present invention.

[0070] Table 1 Existing technology This invention Architecture 2T2R 2T2R Unit cell 55F 2 (430*250) 55F 2 (410*262) Drive capability 170 / 40 (170*2) / 40, driving capability doubled.

[0071] As shown in Table 1, when both the semiconductor structure in the prior art and the structure in this invention are 2T2R structures and the size of the storage cell (Unit cell) is 55F2, the driving capability in the prior art is less than that in this invention. As shown in Figure 1, 170nm refers to the width of the active region 11 along the second direction, and 40nm refers to the width of the word line 70 along the first direction. Because this invention can control any one R through two word lines, the driving capability is doubled.

[0072] In this embodiment of the invention, the size of the semiconductor structure can be miniaturized and is not limited by insufficient transistor driving capability caused by size miniaturization.

[0073] Compared with the 2T1R structure, the 2T2R structure in this embodiment of the invention can have one more R under the same driving capability.

[0074] Table 2 below shows the switching states of the word line, bit line and source line of one of the memristors under different conditions.

[0075] Table 2 R BL1 BL2 WL2 WL3 SL1 SL2 Forming 1 0 1 1 0 0 Set 1 0 1 1 0 0 Reset 0 1 1 1 1 1

[0076] Table 2 above shows the switching states of the word line, bit line, and source line of the memristor in the lower left corner of Figure 1 under different conditions. 1 indicates on, and 0 indicates off. As can be seen from the table, the two word lines WL can simultaneously provide excitation to one R, thereby improving the driving capability.

[0077] This embodiment of the invention also provides a method for fabricating a semiconductor structure. Figure 4 is a flowchart of the method for fabricating a semiconductor structure provided in this embodiment of the invention. As shown in Figure 4, the method for fabricating a semiconductor structure includes:

[0078] Step 401: Provide a substrate, the substrate including a plurality of active regions arranged in an array along a first direction and a second direction;

[0079] Step 402: Form a transistor unit on each active region. The transistor unit includes a first transistor and a second transistor. The first transistor and the second transistor share a drain region.

[0080] Step 403: Form multiple word lines extending along the second direction, wherein in each transistor unit, the first transistor is connected to one word line and the second transistor is connected to another word line;

[0081] Step 404: Form a resistive switching unit on each drain region, and each resistive switching unit includes a first memristor and a second memristor.

[0082] The method for preparing the semiconductor structure provided in the embodiments of the present invention will be further described in detail below with reference to specific embodiments. Figures 5a to 5i are schematic diagrams of the semiconductor structure provided in the embodiments of the present invention during the preparation process.

[0083] First, referring to FIG5a, step 401 is performed to provide a substrate 10, which includes a plurality of active regions 11 arranged in an array along a first direction and a second direction.

[0084] In one embodiment, the substrate 10 may be a single-element semiconductor material substrate (e.g., silicon substrate, germanium substrate, etc.), a composite semiconductor material substrate (e.g., germanium-silicon substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, etc.

[0085] As shown in Figure 1, the substrate 10 includes a plurality of active regions 11 arranged in an array along a first direction and a second direction, wherein adjacent active regions 11 are insulated from each other by a shallow trench isolation structure (not shown in the figure).

[0086] Next, referring to FIG5a, step 402 is performed to form a transistor unit on each active region. The transistor unit includes a first transistor 21 and a second transistor 22. The first transistor 21 and the second transistor 22 share a drain region.

[0087] Specifically, referring to Figure 3, both the first transistor 21 and the second transistor 22 include a gate 213 located on the substrate 10 and a drain region 211 and a source region 212 located on both sides of the gate 213 within the substrate 10. The first transistor 21 and the second transistor 22 share a drain region 211.

[0088] Next, referring to FIG5a, a first interlayer dielectric layer 41 is formed, and a first contact plug 51 is formed in the first interlayer dielectric layer 41.

[0089] The material of the first interlayer dielectric layer 41 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. The first contact plug 51 can be a double-layer structure. The material of the first contact plug 51 can include titanium nitride located on the outer layer and tungsten metal located on the inner layer.

[0090] Referring again to FIG5a, a second interlayer dielectric layer 42 is formed on the first interlayer dielectric layer 41, and a metal interconnect layer 80 is formed in the second interlayer dielectric layer 42.

[0091] The second interlayer dielectric layer 42 can be a metal interlayer dielectric layer, such as aluminum oxide, zinc oxide and other materials, and the metal connection layer 80 is made of materials including but not limited to copper.

[0092] Referring again to FIG5a, FIG1 and FIG3, multiple source lines 30 extending along the first direction are formed. In each transistor unit, the source region 212 of the first transistor 21 is connected to one source line 30, and the source region 212 of the second transistor 22 is connected to another source line 30. In the transistor units on the active regions 11 arranged in adjacent rows along the first direction, the source regions 212 of all the first transistors 21 in one row and the source regions 212 of all the second transistors 22 in the other row are connected to the same source line 30.

[0093] Referring again to FIG5a, a third interlayer dielectric layer 43 is formed on the second interlayer dielectric layer 42, and a second contact plug 52 is formed in the third interlayer dielectric layer 43.

[0094] The third interlayer dielectric layer 43 can be a silicon carbide thin film (NDC), and the second contact plug 52 can be a double-layer structure. The material of the second contact plug 52 can include titanium nitride located on the outer layer and tungsten metal located on the inner layer.

[0095] Next, referring to Figures 1 and 3, step 403 is performed to form multiple word lines 70 extending along the second direction. In each transistor unit, the first transistor 21 is connected to one word line 70, and the second transistor 22 is connected to another word line 70. Specifically, as shown in Figure 3, the word line WL is connected to the gate 213 of the transistor.

[0096] Next, step 404 is performed to form a resistive switching unit on each drain region 211, and each resistive switching unit includes a first memristor 23 and a second memristor 24.

[0097] Specifically, referring to Figure 5b, a lower electrode material layer 201' is formed on the third interlayer dielectric layer 43.

[0098] In actual operation, the lower electrode material layer 201' can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods. Preferably, it can be formed by physical vapor deposition process.

[0099] Next, referring to FIG5c, the lower electrode material layer 201' is etched to form the lower electrode 201.

[0100] In actual operation, a mask layer can be formed on the lower electrode material layer 201', and then the mask layer can be patterned to form a lower electrode pattern on the mask layer. The lower electrode material layer 201' can be etched according to the lower electrode pattern to form the lower electrode 201.

[0101] The etching process can be either a wet etching process or a dry etching process.

[0102] Next, referring to Figures 5d and 5e, a fourth interlayer dielectric layer 44 covering the lower electrode 201 is formed, and then the fourth interlayer dielectric layer 44 is subjected to chemical mechanical polishing (CMP) to make the fourth interlayer dielectric layer 44 flush with the surface of the lower electrode 201.

[0103] The fourth interlayer dielectric layer 44 can provide insulation between adjacent lower electrodes 201.

[0104] The material of the fourth interlayer dielectric layer 44 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0105] Next, referring to FIG5f, a resistive switching material layer 202' and an upper electrode material layer 203' are formed on the fourth interlayer dielectric layer 44 and the lower electrode 201.

[0106] In actual operation, the resistive switching layer material layer 202' and the upper electrode material layer 203' can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods. Preferably, they can be formed by physical vapor deposition.

[0107] Next, referring to FIG5g, the resistive switching layer material layer 202' and the upper electrode material layer 203' are etched to form the resistive switching layer 202 and the upper electrode 203.

[0108] In one embodiment, the first memristor 23 and the second memristor 24 each include a lower electrode 201, a resistive switching layer 202 and an upper electrode 203 arranged from bottom to top, wherein the first memristor 23 and the second memristor 24 share a lower electrode 201.

[0109] The first memristor 23 and the second memristor 24 share a lower electrode 201, which makes it easy for the two transistors to control either of the memristors.

[0110] The material of the lower electrode 201 includes, but is not limited to, titanium nitride; the material of the resistive switching layer 202 includes, but is not limited to, transition metal oxides, specifically, hafnium oxide, aluminum monoxide, etc.; the material of the upper electrode 203 includes, but is not limited to, titanium nitride.

[0111] In one embodiment, as shown in FIG1, the extending direction of the resistive switching unit intersects with the first direction and forms a preset angle, the preset angle being in the range of 30° to 60°. Preferably, the preset angle is 45°.

[0112] In this embodiment, the resistive switching unit is set in an inclined manner, which allows for the setting of one more R in the same area. In order to improve the driving capability of the transistor, the present invention designs the structure of the shared SL in the prior art as a shared drain region. However, this will reduce the original 2R to 1R. Therefore, in order not to sacrifice the number of R in the same area, the inclined placement method is adopted so that the original 2R can be maintained in the same area. At the same time, the preset angle is set within this range. In this way, when setting the bit lines later, the bit lines connected to the first memristor and the second memristor can be separated so as not to come into contact and cause interference.

[0113] Next, referring to FIG5h, a fifth interlayer dielectric layer 45 is formed covering the first memristor 23 and the second memristor 24.

[0114] The material of the fifth interlayer dielectric layer 45 includes ultra-low K material.

[0115] Next, referring to FIG5i, a third contact plug 53 is formed within the fifth interlayer dielectric layer 45, wherein the third contact plug 53 is located on the upper electrode 203 and is electrically connected to the upper electrode 203.

[0116] In actual operation, a mask layer is formed on the fifth interlayer dielectric layer 45, the mask layer is patterned, the position of the third contact plug via is formed on the mask layer, and then the fifth interlayer dielectric layer 45 is etched along the position of the third contact plug via to form the third contact plug via. The upper electrode 203 is exposed in the third contact plug via, and the third contact plug 53 is formed in the third contact plug via.

[0117] The third contact plug 53 can be a double-layer structure. The material of the third contact plug 53 may include titanium nitride located on the outer layer and tungsten metal located on the inner layer.

[0118] Next, referring to FIG5i, multiple bit lines 60 extending along the first direction are formed, wherein in each row of active regions 11 arranged along the first direction, all first memristors 23 are connected to the same bit line 60, and all second memristors 24 are connected to another bit line 60.

[0119] Specifically, the first memristor 23 and the second memristor 24 are connected to the bit line 60 through the third contact plug 53.

[0120] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and no limitation is imposed herein.

[0121] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0122] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of protection of the aforementioned patent application. [Simplified Explanation of the Diagram]

[0029] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein:

[0030] In the accompanying drawings, the same or corresponding element symbols represent the same or corresponding parts.

[0031] Figure 1 is a top view of a semiconductor structure provided in an embodiment of the present invention;

[0032] Figure 2 is a cross-sectional view along the direction of the dashed line A-A' in Figure 1;

[0033] Figure 3 is a schematic diagram of the structure of the storage unit provided in an embodiment of the present invention;

[0034] Figure 4 is a flowchart of the semiconductor structure fabrication method provided in the embodiment of the present invention;

[0035] Figures 5a to 5i are schematic diagrams of the semiconductor structure provided in the embodiments of the present invention during the preparation process.

Claims

1. A semiconductor structure, wherein, The semiconductor structure includes: a substrate comprising a plurality of active regions arranged in an array along a first direction and a second direction; a transistor unit formed on each active region, the transistor unit including a first transistor and a second transistor, the first transistor and the second transistor sharing a drain electrode; a resistive switching unit formed on each drain electrode, each resistive switching unit including a first memristor and a second memristor; a plurality of word lines extending along the second direction, wherein in each transistor unit, the first transistor is connected to one word line and the second transistor is connected to another word line; wherein the first memristor and the second memristor each include a lower electrode, a resistive switching layer and an upper electrode arranged from bottom to top, wherein the first memristor and the second memristor share a lower electrode.

2. The semiconductor structure according to claim 1, wherein, The extension direction of the resistive switching unit intersects the first direction and forms a preset angle, which is in the range of 30° to 60°.

3. The semiconductor structure according to claim 1, wherein, The semiconductor structure further includes: multiple bit lines extending along the first direction, wherein in each row of resistive switching cells on the active region arranged along the first direction, all the first memristors are connected to the same bit line, and all the second memristors are connected to another bit line.

4. The semiconductor structure according to claim 1, wherein, The semiconductor structure further includes: multiple source lines extending along the first direction, wherein in each transistor unit, the source region of the first transistor is connected to one source line, and the source region of the second transistor is connected to another source line; wherein, in two adjacent rows of transistor units on the active region arranged along the first direction, the source regions of all the first transistors in one row and the source regions of all the second transistors in the other row are connected to the same source line.

5. A method for fabricating a semiconductor structure, wherein, The fabrication method includes: providing a substrate comprising a plurality of active regions arranged in an array along a first direction and a second direction; forming a transistor unit on each active region, the transistor unit comprising a first transistor and a second transistor, the first transistor and the second transistor sharing a drain electrode; forming a plurality of word lines extending along the second direction, wherein in each transistor unit, the first transistor is connected to one word line and the second transistor is connected to another word line; forming a resistive switching unit on each drain electrode, each resistive switching unit comprising a first memristor and a second memristor; wherein the first memristor and the second memristor each comprise a lower electrode, a resistive switching layer and an upper electrode arranged from bottom to top, wherein the first memristor and the second memristor share a lower electrode.

6. The preparation method according to claim 5, wherein, The extension direction of the resistive switching unit intersects the first direction and forms a preset angle, which is in the range of 30° to 60°.

7. The preparation method according to claim 5, wherein, The fabrication method further includes: after forming the resistive switching unit, forming multiple bit lines extending along the first direction, wherein in each row of resistive switching units on the active region arranged along the first direction, all the first memristors are connected to the same bit line, and all the second memristors are connected to another bit line.

8. The preparation method according to claim 5, wherein, The method further includes: after forming the transistor unit, forming a plurality of source lines extending along the first direction, wherein in each transistor unit, the source region of the first transistor is connected to one source line, and the source region of the second transistor is connected to another source line; wherein, in two adjacent rows of transistor units on the active region arranged along the first direction, the source regions of all the first transistors in one row and the source regions of all the second transistors in the other row are connected to the same source line.

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