Amplifier circuit

Abstract

An amplifier circuit. An input pair circuit is coupled between a current connection terminal and a pair of amplified output terminals, and the amplified output terminals are electrically coupled to a first power supply. The input pair circuit operates according to a pair of input voltages and a reset clock signal to generate a pair of amplified voltages at the amplified output terminals, such that the amplified voltages share a reset level during the reset phase, and have different magnitudes of a first amplification level and a second amplification level during the voltage amplification phase and the voltage amplification completion phase. A tail current circuit is coupled between a second power supply and the current connection terminal, comprising at least two transistors connected in series or parallel, the at least two transistors being controlled by the amplified voltages and configured to be turned on or off together during the reset phase, and having a high-to-low conduction level sequentially during the voltage amplification phase and the voltage amplification completion phase.

Claims

1. An amplifier circuit comprising: an input pair circuit electrically coupled between a current connection terminal and a pair of amplified output terminals, the pair of amplified output terminals being electrically coupled to a first power supply, the input pair circuit configured to operate according to a pair of input voltages and a reset clock signal, thereby generating a pair of amplified voltages at the pair of amplified output terminals such that the pair of amplified voltages share a reset level in a reset phase, and have a first amplification level and a second amplification level of different magnitudes in a voltage amplification phase and a voltage amplification completion phase, wherein the input pair circuit includes: A pair of input transistors, electrically coupled between the current connection terminal and the pair of amplified output terminals, controlled by the pair of input voltages; and a reset switch circuit, disposed between the pair of amplified output terminals and a reset voltage, controlled by the reset clock signal, wherein during the reset phase, the reset clock signal has a reset state that turns on the reset switch circuit to reset the pair of amplified output terminals so that the pair of amplified voltages has a level of the reset voltage, and a level difference between the level of the reset voltage and a level of the first power supply is less than a preset value, and during the voltage amplification phase and the voltage amplification completion phase, the reset clock signal has a non-reset state that turns off the reset switch circuit, so that the pair of input transistors generate the pair of amplified voltages according to the pair of input voltages; and a tail current. The circuit, electrically coupled between a second power source and the current connection terminal, includes at least two transistors connected in series or in parallel. The at least two transistors are controlled by the pair of amplified voltages and configured to be turned on or off together during the reset phase, and have a conduction level from high to low during the voltage amplification phase and the voltage amplification completion phase, respectively.

2. The amplifier circuit as described in claim 1 further includes a connection switch circuit disposed between the tail current circuit and the second power supply or between the tail current circuit and the current connection terminal, controlled by an inverted reset clock signal that is the inverse of the reset clock signal; wherein during the reset phase, the reset clock signal has the reset state causing the connection switch circuit to disconnect; and during the voltage amplification phase and the voltage amplification completion phase, the reset clock signal has the non-reset state causing the connection switch circuit to turn on.

3. The amplifier circuit as claimed in claim 1 further comprises: a first logic operation circuit that performs a logic operation on a first amplified voltage in the pair of amplified voltages and the reset clock signal to generate a first control voltage in the pair of control voltages; and a second logic operation circuit that performs a logic operation on a second amplified voltage in the pair of amplified voltages and the reset clock signal to generate a second control voltage in the pair of control voltages; wherein the at least two transistors included in the tail current circuit are actually controlled by the pair of control voltages.

4. The amplifier circuit as claimed in claim 1, wherein each of the input pair circuit and the tail current circuit is a P-type transistor circuit.

5. The amplifier circuit as claimed in claim 1, wherein each of the input pair circuit and the tail current circuit is an N-type transistor circuit.

6. The amplifier circuit as described in claim 1 further includes a current source circuit electrically coupled between the tail current circuit and the second power supply.

7. The amplifier circuit as described in claim 1 further includes a current source circuit electrically coupled between the tail current circuit and the current connection terminal.

8. The amplifier circuit as claimed in claim 1, wherein the tail current circuit comprises two sub-circuits connected in parallel, each of the two sub-circuits comprising two tail current transistors connected in series, a first tail current transistor being controlled by a first amplification voltage of the pair of amplification voltages, and a second tail current transistor being controlled by a second amplification voltage of the pair of amplification voltages.

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