Semiconductor device and method for fabricating the same

Abstract

This application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a gate structure, a gap structure, and a sealing layer. The gate structure is located on the substrate. The gap structure includes a first spacer, a second spacer, a third spacer, and an air gap. The first spacer is disposed on a sidewall of the gate structure, and the air gap is located between the first spacer and the second spacer. The air gap is sealed through the first spacer, the second spacer, the third spacer, and the sealing layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 981,769 (i.e., priority date "December 16, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to semiconductor devices and methods of manufacturing the same, and more specifically, to semiconductor devices including spacers with air gaps and methods of manufacturing the same. Prior Technology

[0003] Semiconductor components are crucial for many modern applications. With advancements in electronics, semiconductor components have become increasingly smaller while offering more powerful functions and incorporating more integrated circuits. Due to the miniaturization of semiconductor components, different types and sizes of semiconductor components offering different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing operations are required to integrate these different types of semiconductor components.

[0004] As components shrink, the parasitic capacitance between the gate and the contact increases, leading to increased gate delay. To reduce the increase in spacer capacitance, low-dielectric-constant materials can replace oxides and nitrides in the spacer. Low-dielectric-constant materials have a lower dielectric constant, which helps reduce parasitic effects. Among low-dielectric-constant materials, the air gap has the lowest dielectric constant and can be effectively used as a spacer material, thereby improving overall component performance and reliability.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of the "prior art" of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device including a substrate having a top surface, a gate structure disposed on the top surface of the substrate, a gap structure disposed on a sidewall of the gate structure, and a sealing layer covering the substrate, the gap structure, and the gate structure. The gap structure includes a first spacer, a second spacer, a third spacer, and an air gap. The first spacer is disposed on the sidewall of the gate structure, and the air gap is located between the first spacer and the second spacer. The air gap is closed through the first spacer, the second spacer, the third spacer, and the sealing layer.

[0007] In some embodiments, the gate structure includes a first dielectric layer disposed on the top surface of the substrate, a metal compound layer disposed on the first dielectric layer, a second metal layer disposed on the metal compound layer, a third dielectric layer disposed on the second metal layer, and a fourth dielectric layer covering the first dielectric layer, the metal compound layer, the second metal layer and the third dielectric layer.

[0008] In some embodiments, the first dielectric layer comprises silicon oxide; the metal compound layer comprises polysilicon; the second metal layer comprises tungsten; the third dielectric layer comprises silicon nitride; and the fourth dielectric layer also comprises silicon nitride.

[0009] In some embodiments, the semiconductor device further includes a second dielectric layer disposed between the first dielectric layer and the metal compound layer, and a first metal layer disposed between the second dielectric layer and the metal compound layer.

[0010] In some embodiments, the fourth dielectric layer further covers the second dielectric layer and the first metal layer.

[0011] In some embodiments, the second dielectric layer comprises hafnium oxide, hafnium aluminum oxide, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, the like, or combinations thereof; and the first metal layer comprises tungsten, aluminum, tantalum, titanium, platinum, nickel, or alloys or combinations thereof.

[0012] In some embodiments, the air gap is sealed through the sealing layer.

[0013] In some embodiments, the air gap includes a sloping bottom surface.

[0014] In some embodiments, the inclined bottom surface is coplanar with an inclined sidewall of the first spacer.

[0015] In some embodiments, a vertical sidewall of the air gap is coplanar with a vertical sidewall of the second spacer and a vertical sidewall of the third spacer.

[0016] In some embodiments, the vertical level at which the lowest point of the air gap is located is lower than the vertical level at the highest point of the third gap.

[0017] In some embodiments, the sealing layer comprises silicon nitride.

[0018] In some embodiments, a distance between the air gap and the gate structure is positively correlated with a thickness of the fourth dielectric layer.

[0019] Another embodiment of this disclosure provides a semiconductor structure including a substrate, the substrate including a lightly doped drain (LDD) region disposed in a top surface of the substrate and a source / drain (S / D) region disposed in the substrate and adjacent to the LDD region, a gate structure disposed on the substrate, a gap structure disposed on a sidewall of the gate structure, a sealing layer covering the substrate, the gap structure and the gate structure, a dielectric layer covering the sealing layer, and a contact disposed in the dielectric layer and extending into the source / drain region. The gap structure includes a first spacer, a second spacer, a third spacer and an air gap. The air gap is disposed between the first spacer and the second spacer. The air gap is sealed through the sealing layer. The air gap is closed through the first spacer, the second spacer, the third spacer and the sealing layer.

[0020] In some embodiments, the gate structure includes a first dielectric layer disposed on the top surface of the substrate, a second dielectric layer disposed on the first dielectric layer, a first metal layer disposed on the second dielectric layer, a metal compound layer disposed on the first dielectric layer, a second metal layer disposed on the metal compound layer, a third dielectric layer disposed on the second metal layer, and a fourth dielectric layer covering the first dielectric layer, the first metal layer, the second dielectric layer, the metal compound layer, the second metal layer, and the third dielectric layer.

[0021] In some embodiments, the second dielectric layer comprises hafnium oxide, hafnium aluminum oxide, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, the like, or combinations thereof; and the first metal layer comprises tungsten, aluminum, tantalum, titanium, platinum, nickel, or alloys or combinations thereof.

[0022] In some embodiments, the air gap includes a sloping bottom surface.

[0023] In some embodiments, an inclined bottom surface is coplanar with an inclined sidewall of the first spacer.

[0024] In some embodiments, a vertical sidewall of the air gap is coplanar with a vertical side surface of the second spacer and a vertical sidewall of the third spacer.

[0025] In some embodiments, the vertical level at which the lowest point of the air gap is located is lower than the vertical level at the highest point of the third gap.

[0026] In some embodiments, a distance between the air gap and the gate structure is positively correlated with a thickness of the fourth dielectric layer.

[0027] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; sequentially depositing a first dielectric material, a second dielectric material, a first metal layer, a metal compound material, a second metal material, and a third dielectric material on the substrate and covering the substrate; using a photoresist as a photomask to perform a photolithography process on the second dielectric material, the first metal material, the metal compound material, the second metal material, and the third dielectric material, thereby forming a second dielectric layer, a first metal layer, a metal compound layer, a second metal layer, and a third dielectric layer, respectively; depositing a fourth dielectric material to cover the first dielectric material, the second dielectric layer, the first metal layer, the metal compound layer, the second metal layer, and the third dielectric layer; forming a first dielectric layer and a fourth dielectric layer, wherein the first dielectric material... A gate structure is configured with a dielectric layer, a second dielectric layer, a first metal layer, a metal compound layer, a second metal layer, a third dielectric layer, and a fourth dielectric layer; a fifth dielectric material is conformally formed on the fourth dielectric layer and the substrate; a sixth dielectric material is formed on the fifth dielectric material; a seventh dielectric material is formed on the sixth dielectric material; a first gap structure is formed on a sidewall of the gate structure, wherein the first gap structure includes a first gap element, a second gap element, and a third gap element, the third gap element being sandwiched between the first gap element and the second gap element; a second gap structure is formed on the sidewall of the gate structure by removing an upper portion of the first gap structure; and a sealing layer is conformally formed on the substrate, the second gap structure, and the gate structure, wherein the sealing layer seals the air gap.

[0028] In some embodiments, prior to forming the sealing layer, the method further includes performing a trimming process to remove a residual portion of the seventh dielectric material on the gate structure.

[0029] In some embodiments, the finishing process includes an etch-babk process.

[0030] In some embodiments, the second dielectric material includes hafnium oxide, hafnium aluminum oxide, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, the like, or combinations thereof.

[0031] In some embodiments, the formation of the second dielectric material is performed using an atomic layer deposition process.

[0032] In some embodiments, the thickness of the fifth dielectric material is positively correlated with the thickness of the fourth dielectric layer.

[0033] In some embodiments, the thickness of the sixth dielectric material is positively correlated with the deposition rate of the sealing layer.

[0034] Another embodiment of this disclosure provides a method for manufacturing a semiconductor structure, including providing a gate structure on a substrate; forming a lightly doped drain (LDD) region in the substrate; forming a gap structure on a sidewall of the gate structure; forming a source / drain (S / D) region in the substrate; forming a dielectric layer covering the gap structure and the gate structure; forming an opening in the dielectric layer, wherein the opening extends from a top surface of the dielectric layer to the source / drain region of the substrate; and forming a contact by depositing a conductive material in the opening. In some embodiments, the lightly doped drain region and the source / drain region are formed by an ion implantation process.

[0035] In some embodiments, the contact is separated from the gate structure through the gap structure.

[0036] The embodiments disclosed herein provide a semiconductor device including a gap structure having an air gap. Furthermore, a method is proposed to utilize this gap structure to reduce parasitic capacitance between a gate and a contact. By applying the semiconductor device and the associated method, the parasitic capacitance between the gate and the contact is reduced, resulting in improved gate performance.

[0037] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0038] When referring to the drawings in conjunction with the embodiments and the scope of the patent application, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements. Figure 1A is a schematic diagram illustrating a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B is a schematic diagram illustrating a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. Figure 2A is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figures 2B to 2S are schematic diagrams illustrating cross-sectional views of an intermediate stage of a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 3A is a flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure. Figures 3B to 3H are schematic diagrams illustrating cross-sectional views of an intermediate stage of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Implementation

[0039] The following description of this disclosure, accompanied by drawings incorporated into and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0040] The terms "an embodiment," "an embodiment," "an illustrative embodiment," "an other embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0041] To ensure a complete understanding of this disclosure, the following description provides detailed steps and structures. It is clear that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting the disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description but is defined by the claims.

[0042] Figure 1A is a schematic diagram illustrating a cross-sectional view of a semiconductor device 10 according to an embodiment of the present disclosure. The semiconductor device 10 may include a substrate 100, a gate structure 250, a gap structure 270, and a sealing layer 223.

[0043] Referring to FIG1A, in some embodiments, substrate 100 includes a bulk semiconductor substrate. The bulk semiconductor substrate is formed of, for example, an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0044] In some embodiments, substrate 100 includes a semiconductor-insulator structure comprising, from bottom to top, a processing substrate, an insulating layer, and a top semiconductor material layer. The processing substrate and the top semiconductor material layer may be formed of the same material as the host semiconductor substrate material described above. The insulating layer is a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer is a dielectric oxide, such as silicon oxide. Alternatively, the insulating layer is a dielectric nitride, such as silicon nitride or boron nitride. Furthermore, the insulating layer comprises a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide, silicon nitride, and / or boron nitride, arranged in any order.

[0045] Referring to FIG1A, a gate structure 250 is stacked on a substrate 100. In some embodiments, the gate structure 250 includes a dielectric layer 203 on the substrate 100, a metal compound layer 209 on top of the dielectric layer 203, a metal layer 211 on top of the metal compound layer 209, a dielectric layer 213 on top of the metal layer 211, and a dielectric layer 215 covering the dielectric layer 203, the metal compound layer 209, the metal layer 211, and the dielectric layer 213. In an alternative embodiment, the gate structure 250 includes a dielectric layer 205 between the dielectric layer 203 and the metal compound layer 209 and a metal layer 207 on top of the dielectric layer 205. In these embodiments, the dielectric layer 215 also covers the dielectric layer 205 and the metal layer 207. The top surface 215TS of the dielectric layer 215 is referred to as the top surface 250TS of the gate structure 250.

[0046] In some embodiments, the dielectric layer 203 is composed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, similar materials, or combinations thereof. The low dielectric constant material has a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low dielectric constant material exhibits a dielectric constant less than 2.0. In some embodiments, the dielectric material is formed through a deposition process, such as chemical vapor deposition (CVD), followed by an etching process, including isotropic etching, anisotropic etching, or a combination thereof. CVD process temperatures typically range from 600°C to 1000°C, and process pressures are typically equal to or less than one atmosphere (1 atm).

[0047] In some embodiments, the dielectric layer 205 is composed of a high dielectric constant material (e.g., a dielectric material having a dielectric constant greater than 3.9 or 7.0). High dielectric constant materials include hafnium oxide, hafnium aluminum oxide, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, or combinations thereof. In some embodiments, the dielectric material is formed using a deposition process such as atomic layer deposition (ALD), followed by an etching process, including isotropic etching, anisotropic etching, or combinations thereof. ALD process temperatures typically range from 50°C to 300°C, and process pressures typically range from a few millitors (mTorr) to tens of Torr.

[0048] In some embodiments, the metal layer 207 is composed of a metallic material, such as tungsten, titanium, titanium nitride, aluminum, or a combination thereof. In some embodiments, the metallic material is formed through a deposition process and a subsequent etching process. In some embodiments, the deposition process includes physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. In some embodiments, the etching process includes isotropic etching, anisotropic etching, or a combination thereof.

[0049] In some embodiments, the metal compound layer 209 is composed of polycrystalline silicon, metal silicide, polycrystalline silicide, or silicon carbide. Metal silicides include titanium silicide (TiSi₂) or cobalt silicide (CoSi₂). In some embodiments, the metal compound layer 209 is formed using a deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), followed by an etching process, including isotropic etching, anisotropic etching, or a combination thereof.

[0050] In some embodiments, the metal layer 211 comprises tungsten, tantalum, aluminum, alloys thereof (such as aluminum-copper or tungsten-tantalum), or combinations thereof. In some embodiments, the metal layer 211 is formed by a deposition process, such as a physical vapor deposition (PVD) process, followed by an etching process, including isotropic etching, anisotropic etching, or a combination thereof.

[0051] In some embodiments, the dielectric layer 213 is composed of silicon nitride, silicon oxynitride, a low-dielectric-constant material, the like, or a combination thereof. The low-dielectric-constant material has a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low-dielectric-constant material has a dielectric constant of less than 2.0. In some embodiments, the dielectric layer 213 is formed through a deposition process, such as chemical vapor deposition (CVD), followed by an etching process, including isotropic etching, anisotropic etching, or a combination thereof.

[0052] In some embodiments, dielectric layer 215 is composed of the same material as dielectric layer 213. In other words, dielectric layer 215 also includes silicon nitride, silicon oxynitride, low dielectric constant materials, the like, or combinations thereof. Low dielectric constant materials have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, low dielectric constant materials have a dielectric constant of less than 2.0. In some embodiments, dielectric layer 215 is formed through a deposition process, such as chemical vapor deposition (CVD), followed by an etching process, including isotropic etching, anisotropic etching, or a combination thereof.

[0053] Referring to FIG1A, the gap structure 270 is disposed on the top surface 100TS of the substrate 100 and the sidewall 250S of the gate structure 250. The gap structure 270 includes a spacer 217, a spacer 219, an air gap 220, and a spacer 221.

[0054] In some embodiments, the spacer 217 is conformally disposed on the sidewall 250S of the gate structure 250 and extends into the substrate 100. The spacer 217 includes a vertical portion 217-1 on the sidewall 250S of the gate structure 250, an inclined portion 217-2 below the vertical portion 217-1 and connected to the vertical portion 217-1, and a horizontal portion 217-3 below the inclined portion 217-2 and connected to the inclined portion 217-2. In some embodiments, a portion 217-4 of the horizontal portion 217-3 of the spacer 217 is disposed in the substrate 100. In some embodiments, the spacer 217 includes silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass, polyimide, fluorinated silicate glass, or combinations thereof.

[0055] In some embodiments, spacer 219 is disposed above spacer 217 and between spacer 217 and spacer 221. Spacer 219 includes portions 219-1 and 219-2, with portion 219-2 located below and connected to portion 219-1. Portion 219-1 of spacer 219 may be inclined and includes the apex 219T located at vertical level VL2. Portion 219-2 of spacer 219 is horizontal and sandwiched between spacer 217 and spacer 221. In some embodiments, spacer 219 is composed of silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass, polyimide, fluorinated silicate glass, or combinations thereof.

[0056] In some embodiments, an air gap 220 is disposed between spacers 217 and 221. The air gap 220 is perpendicular to and sandwiched between spacers 217 and 221. In some embodiments, the air gap 220 is connected to spacer 219. The air gap 220 includes an inclined bottom surface 220BS and a lowest point 220B located at a vertical level VL1. In some embodiments, the sidewalls 220S1 of the air gap 220 and the sidewalls 219S2 of the spacer 219 are coplanar. Furthermore, the inclined bottom surface 220BS is coplanar with the inclined sidewalls 217-2S2 of the inclined portion 217-2 of the spacer 217. In some embodiments, the vertical level VL1 of the lowest point 220B of the air gap 220 is lower than the vertical level VL2 of the highest point 219T of the spacer 219.

[0057] In some embodiments, spacer 221 is disposed on spacer 217 and spaced apart from spacer 217 through spacer 219 and air gap 220. The sidewalls 221S2 of spacer 221, the sidewalls 220S1 of air gap 220, and the sidewalls 219S2 of spacer 219 are coplanar. In some embodiments, spacer 221 comprises silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass, polyimide, fluorinated silicate glass, or combinations thereof.

[0058] Referring to FIG1A, the sealing layer 223 is configured to cover the substrate 100, the gap structure 270, and the gate structure 250. The sealing layer 223 seals the air gap 220. In other words, the spacers 217, 219, 221, and the sealing layer 223 enclose the air gap 220. In some embodiments, after sealing the air gap 220, the air gap 220 includes a top surface 220TS. In some embodiments, the top surface 220TS of the air gap 220 is lower than the top surface 217TS of the spacer 217 and also lower than the highest point 221T of the spacer 221. In some embodiments, the spacer 221 includes silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass, polyimide, fluorinated silicate glass, or combinations thereof.

[0059] It is worth noting that the width W of the air gap 220 is positively correlated with the deposition rate of the sealing layer 223. In other words, increasing the deposition rate of the sealing layer 223 allows for a larger width W of the air gap 220, while decreasing the deposition rate of the sealing layer 223 results in a smaller width W of the air gap 220. This design primarily aims to prevent the sealing layer 223 from filling the air gap 220. The parameters of the deposition rate of the sealing layer 223 and the width W of the air gap 220 depend on the design requirements of the manufacturing process.

[0060] Furthermore, the distance D1 between the air gap 220 and the gate structure 250 is positively correlated with the thickness T1 of the dielectric layer 215. In other words, increasing the thickness T1 of the dielectric layer 215 allows for a larger distance D1, while decreasing the thickness T1 results in a smaller distance D1. This design primarily aims to prevent parasitic capacitance, reduce gate delay, and achieve better gate control performance. The parameters of the dielectric layer 215 thickness T1 and the distance D1 between the air gap 220 and the gate structure 250 depend on the process design requirements.

[0061] Figure 1B is a schematic diagram illustrating a cross-sectional view of a semiconductor structure 30 according to an embodiment of the present disclosure. The semiconductor structure 30 includes a substrate 300, a gate structure 250, a gap structure 270, a sealing layer 223, a dielectric layer 305, and a contact 309.

[0062] Referring to FIG1B, in some embodiments, substrate 300 is similar to substrate 100 shown in FIG1A, except that substrate 300 further includes a lightly doped drain region 301 and a source / drain region 303. The material of substrate 300 is the same as that of substrate 100, and a repeated description is omitted here.

[0063] In some embodiments, a lightly doped drain region 301 is located below the gate structure 250, close to a drain region (e.g., source / drain region 303) in the substrate 300, and in a channel region between the drain region and the source region (e.g., source / drain region 303). In some embodiments, the lightly doped drain region 301 has a lower doping concentration than the source / drain region 303 to reduce the electric field strength near the drain region. The dopant used in the lightly doped drain region 301 depends on the type of metal-oxide-semiconductor field-effect transistor (MOSFET) formed. For example, in an n-type MOSFET, the substrate 300 is typically formed of n-type silicon, and the lightly doped drain region 301 uses a lightly doped n-type dopant, such as phosphorus or arsenic. Conversely, in a p-type MOSFET, the substrate 300 is typically formed of p-type silicon, and the lightly doped drain region 301 uses a lightly doped p-type dopant, such as boron.

[0064] In some embodiments, the source / drain region 303 is disposed near the lightly doped drain region 301. In some embodiments, the source / drain region 303 and the lightly doped drain region 301 partially overlap. The doping type of the source / drain region 303 is generally the same as that of the lightly doped drain region 301. The doping concentration in the source / drain region 303 is generally higher than that in the lightly doped drain region 301. This means that the concentration of the dopant (such as phosphorus or boron) used in the lightly doped drain region 301 is lower than that in the source / drain region 303.

[0065] Referring to FIG1B, in some embodiments, the gate structure 250, the gap structure 270, and the sealing layer 223 are the same as those shown in FIG1A, and a repeated description is omitted here. It is worth mentioning that the sealing layer 223 completely covers the substrate 300.

[0066] Referring to FIG1B, in some embodiments, dielectric layer 305 is disposed on and covers sealing layer 223. In some embodiments, dielectric layer 305 includes silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass, polyimide, fluorinated silicate glass, or combinations thereof.

[0067] Referring to FIG1B, in some embodiments, contact 309 is located on one side of gate structure 250 and spaced apart from gate structure 250 by a distance d. Contact 309 penetrates dielectric layer 305 and extends into source / drain region 303. In some embodiments, contact 309 is separated from gate structure 250 through gap structure 270 and sealing layer 223. Contact 309 includes an upper portion 309-1 disposed in dielectric layer 305 and a lower portion 309-2 disposed in source / drain region 303. Both upper portion 309-1 and lower portion 309-2 have a tapered profile. In some embodiments, contact 309 includes aluminum, copper, tungsten, cobalt, gold, silver, alloys (such as aluminum-copper alloys), or combinations thereof.

[0068] Figure 2A is a flowchart illustrating a method 10a for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 2B to 2S are schematic diagrams illustrating cross-sectional views of intermediate stages of the method 10a for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0069] Referring to Figures 2A and 2B, in step S101, a substrate 100 is provided. The substrate 100 may have a top surface 100TS.

[0070] In some embodiments, substrate 100 includes a bulk semiconductor substrate. The bulk semiconductor substrate is formed of, for example, an elemental semiconductor, such as silicon or germanium; a composite semiconductor, such as silicon-germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI composite semiconductors; or combinations thereof.

[0071] In some embodiments, substrate 100 includes a semiconductor insulator structure comprising, from bottom to top, a processing substrate, an insulating layer, and a top semiconductor material layer. The processing substrate and the top semiconductor material layer are formed of the same material as the aforementioned host semiconductor substrate material. The insulating layer is a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer is a dielectric oxide, such as silicon oxide. Alternatively, the insulating layer is a dielectric nitride, such as silicon nitride or boron nitride. Furthermore, the insulating layer comprises a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide, silicon nitride, and / or boron nitride, in any order.

[0072] Referring to Figures 2A and 2C to 2H, in step S103, dielectric material 103, dielectric material 105, metal material 107, metal compound material 109, metal material 111 and dielectric material are sequentially deposited on the top surface 100TS to cover the substrate 100.

[0073] Referring to FIG2C, a dielectric material 103 is deposited on a substrate 100, covering the substrate 100. In some embodiments, the dielectric material 103 is composed of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, the like, or a combination thereof. The low dielectric constant material has a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low dielectric constant material has a dielectric constant of less than 2.0. In some embodiments, the dielectric material 103 is formed through a deposition process, such as a chemical vapor deposition (CVD) process, followed by an etching process, which may include isotropic etching, anisotropic etching, or a combination thereof. CVD process temperatures typically range from 600°C to 1000°C, and process pressures are typically equal to or less than one atmosphere (1 atm).

[0074] Referring to FIG2D, dielectric material 105 is deposited on dielectric material 103, covering dielectric material 103. In some embodiments, dielectric material 105 is composed of a high dielectric constant material (e.g., a dielectric material having a dielectric constant greater than 3.9 or 7). High dielectric constant materials may include hafnium oxide, hafnium aluminum oxide, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, or combinations thereof. In some embodiments, dielectric material 105 is formed by a deposition process, such as atomic layer deposition (ALD), followed by an etching process, which may include isotropic etching, anisotropic etching, or combinations thereof. ALD process temperatures typically range from 50°C to 300°C, and process pressures typically range from a few millitors (mTorr) to tens of Torr.

[0075] Referring to FIG2E, a metal material 107 is deposited on the dielectric material 105 to cover the dielectric material 105. In some embodiments, the metal material 107 is composed of a metal material including tungsten, titanium, titanium nitride, aluminum, or combinations thereof. In some embodiments, the metal material 107 is formed through a deposition process and a subsequent etching process. The deposition process includes physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or combinations thereof. The etching process includes isotropic etching, anisotropic etching, or combinations thereof.

[0076] Referring to FIG2F, a metal compound material 109 is deposited on the metal material 107, effectively covering the metal material 107. In some embodiments, the metal compound material 109 is composed of polycrystalline silicon, metal silicides (such as titanium silicide (TiSi₂) or cobalt silicide (CoSi₂)), polysilicides, or silicon carbide. The formation of the metal compound material 109 involves a deposition process, such as a chemical vapor deposition (CVD) process, followed by an etching process. The etching process includes isotropic etching, anisotropic etching, or a combination thereof.

[0077] Referring to Figure 2G, a metal material 111 is deposited on the metal compound material 109, effectively covering the metal compound material 109. In some embodiments, the metal material 111 includes tungsten, tantalum, aluminum, alloys such as aluminum-copper or tungsten-tantalum, or combinations thereof. The metal material 111 is formed using a deposition process, such as physical vapor deposition (PVD), followed by an etching process including isotropic etching, anisotropic etching, or combinations thereof.

[0078] Referring to FIG2H, a dielectric material 113 is deposited on the metal material 111, effectively covering the metal material 111. In some embodiments, the dielectric material 113 is composed of silicon nitride, silicon oxynitride, a low dielectric constant dielectric material, similar materials, or combinations thereof. The low dielectric constant dielectric material has a dielectric constant of less than 3.0, and in some embodiments, less than 2.5, or even less than 2.0. The dielectric material 113 is formed using a deposition process, such as a chemical vapor deposition (CVD) process, followed by an etching process including isotropic etching, anisotropic etching, or a combination thereof.

[0079] Referring to Figures 2A, 2I and 2J, in step S105, dielectric layer 205, metal layer 207, metal compound layer 209, metal layer 211 and dielectric layer 213 are formed.

[0080] Referring to FIG2I, a lithography process 190 is performed on dielectric material 105, metal material 107, metal compound material 109, metal material 111, and dielectric material 113, using a photoresist 115 with an opening 115O as a mask. In some embodiments, the lithography process 190 includes an exposure process, a development process, a post-baking process, and an etching process.

[0081] Referring to FIG2J, after performing lithography process 190, dielectric layer 205, metal layer 207, metal compound layer 209, metal layer 211, and dielectric layer 213 are formed. In some embodiments, dielectric layer 205, metal layer 207, metal compound layer 209, metal layer 211, and dielectric layer 213 have thicknesses H2, H3, H4, H5, and H6, respectively. Furthermore, the top surface 205TS of dielectric layer 205 and the bottom surface 207BS of metal layer 207 are substantially coplanar. Similarly, the top surface 207TS of metal layer 207 and the bottom surface 209BS of metal compound layer 209 are substantially coplanar. The top surface 209TS of metal compound layer 209 and the bottom surface 211BS of metal layer 211 are substantially coplanar, and the top surface 211TS of metal layer 211 and the bottom surface 213BS of dielectric layer 213 are also substantially coplanar.

[0082] The sidewalls 213S1 of dielectric layer 213 and 211S1 of metal layer 211 are substantially coplanar. Furthermore, the sidewalls 213S2 of dielectric layer 213 and 211S2 of metal layer 211 are also substantially coplanar. Additionally, the sidewalls 205S1 of dielectric layer 205 and 207S1 of metal layer 207 are substantially coplanar, and the sidewalls 205S2 of dielectric layer 205 and 207S2 of metal layer 207 are also substantially coplanar.

[0083] Referring to Figures 2A, 2K and 2L, in step S107, dielectric layer 203 and dielectric layer 215 are formed on substrate 100.

[0084] Referring to Figure 2K, a dielectric material 215' is deposited to cover dielectric layer 203, dielectric layer 205, metal layer 207, metal compound layer 209, metal layer 211, and dielectric layer 213. In some embodiments, the dielectric material 215' comprises silicon nitride, silicon oxynitride, a low dielectric constant material, similar materials, or combinations thereof. Low dielectric constant materials have a dielectric constant less than 3.0, even less than 2.5, and some embodiments specify a dielectric constant less than 2.0. The dielectric material 215' is formed through a deposition process, such as a chemical vapor deposition (CVD) process, followed by an etching process including isotropic etching, anisotropic etching, or a combination thereof.

[0085] Referring to FIG2L, an etching process, such as an isotropic etching process, is performed to remove portions 215'-1 of dielectric material 215' and 103-1 of dielectric material 103. After performing the etching process, dielectric layers 203 and 215 are formed, with dielectric layer 203 having a thickness H1 and dielectric layer 215 having a thickness T1. In some embodiments, after forming dielectric layers 203 and 215, portions 101-1 of substrate 100 are also removed. Furthermore, in some embodiments, the top surface 203TS of dielectric layer 203 and the bottom surface 205BS of dielectric layer 205 are substantially coplanar. Additionally, the bottom surface 203BS of dielectric layer 203 and the top surface 100TS of substrate 100 are also substantially coplanar.

[0086] In some embodiments, dielectric layer 203, dielectric layer 205, metal layer 207, metal compound layer 209, metal layer 211, dielectric layer 213, and dielectric layer 215 together form gate structure 250.

[0087] Referring to Figures 2A, 2M, 2N and 2O, in step S109, dielectric materials 217', 219' and 221' are sequentially conformally deposited to cover the gate structure 250 and the substrate 100.

[0088] Referring to Figure 2M, a dielectric material 217' is conformally deposited on the gate structure 250 and the substrate 100. In some embodiments, the dielectric material 217' includes silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, similar materials, or combinations thereof. In some embodiments, the material of the dielectric material 217' is the same as that of the dielectric layer 215, while in other embodiments, the materials of the dielectric material 217' and the dielectric layer 215 are different. The dielectric material 217' has a thickness T2, which determines the location of the air gap (e.g., air gap 220) to be formed in subsequent processes. In some embodiments, the thickness T2 is positively correlated with the thickness T1; that is, increasing the thickness T1 allows for a larger thickness T2, while decreasing the thickness T2 results in a smaller thickness T1. Deposition includes physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or combinations thereof.

[0089] Referring to FIG2N, dielectric material 219' is conformally deposited on dielectric material 217'. In some embodiments, the material of dielectric material 219' is the same as that of dielectric layer 215. In some embodiments, the material of dielectric material 219' is different from that of dielectric material 217'. Dielectric material 219' has a thickness T3, which determines the width of the air gap (e.g., air gap 220) to be formed in subsequent processes. In some embodiments, the thickness T3 is positively correlated with the deposition rate of the sealing layer (e.g., sealing layer 223); that is, increasing the deposition rate allows for a larger thickness T3, while decreasing the deposition rate results in a smaller thickness T3. Deposition processes include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or combinations thereof.

[0090] Referring to Figure 2O, dielectric material 221' is conformally deposited on dielectric material 219'. The material of dielectric material 221' is the same as that of dielectric material 217'. In some embodiments, the material of dielectric material 221' is different from that of dielectric material 219'. The deposition process includes physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof.

[0091] Referring to Figures 2A and 2P, in step S111, a gap structure 260 is formed on the sidewall 250S of the gate structure 250, the sidewall 250S being located on the portion 101-1 of the substrate 100 removed in the previous etching process.

[0092] Referring to Figure 2P, in some embodiments, a lithography process is performed to remove portions of dielectric material 217', dielectric material 219', and dielectric material 221', thereby forming spacers 217, 219, and 221, respectively. The lithography process includes a photoresist coating process, an exposure process, a development process, a post-baking process, and an etching process. Furthermore, in some embodiments, after forming the gap structure 260, portions 101-2 of the substrate 100 are removed.

[0093] After the lithography process is performed, spacer 219 is sandwiched between spacer 217 and spacer 221. Spacer 217 includes a vertical portion 217-1, an inclined portion 217-2 connected to the vertical portion 217-1, and a horizontal portion 217-3 connected to the inclined portion 217-2. A portion 217-4 of the horizontal portion 217-3 is located at a portion 101-1 of the previously removed substrate 100. In some embodiments, spacer 217, spacer 219, and spacer 221 together form a gap structure 260.

[0094] Referring to Figures 2A, 2Q and 2R, in step S113, the gap structure 270 is formed.

[0095] Referring to FIG2Q, in some embodiments, an etching process, such as an anisotropic etching process, is performed to remove the upper portion 219U of spacer 219. For ease of process control, the material of spacer 219 has high etch selectivity relative to the materials of spacers 217 and 221. For example, in some embodiments, during the etching process, the ratio of the etching rate of spacer 219 to the etching rate of spacers 217 and 221 is between about 100:1 and about 1.05:1, between about 50:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, the etching process continues until the surface of the inclined portion 217-2 of spacer 217 (e.g., surface 217-2S2) is exposed.

[0096] After the etching process is performed, the lower portion 219L of the spacer 219 remains in place, forming an air gap 220. In some embodiments, the lower portion 219L includes a portion 219-1 located between the inclined portion 217-2 of the spacer 217 and the spacer 221, and a portion 219-2 located between the horizontal portion 217-3 of the spacer 217 and the spacer 221 and connected to the portion 219-1. The portion 219-1 is inclined and includes a apex 219T at the vertical level VL2, while the portion 219-2 is horizontal and can be sandwiched between the spacer 217 and the spacer 221.

[0097] In some embodiments, air gap 220 is vertically configured and sandwiched between spacer 217 and spacer 221, and connected to spacer 219. In some embodiments, air gap has an inclined bottom surface 220BS and a lowest point 220B located at a vertical level VL1. Furthermore, the sidewalls 220S1 of air gap 220 and the sidewalls 219S2 of spacer 219 are coplanar. The inclined bottom surface 220BS and the inclined portion 217-2 of spacer 217 are also coplanar. Furthermore, the vertical level VL1 of the lowest point 220B of air gap 220 is lower than the vertical level VL2 of the highest point 219T of spacer 219. Air gap 220 and spacer 217, spacer 219 and spacer 221 together form gap structure 270.

[0098] Referring to FIG2R, after the air gap 220 is formed, a trimming process, such as a planarization process or an etching process, is performed to remove the residual portion 221'P of the dielectric material 221' on the top surface 215TS of the dielectric layer 215 (see FIG2Q). In some embodiments, the trimming process includes an etch-back process and is performed until the top surface 215TS of the dielectric layer 215 is exposed.

[0099] Referring to Figures 2A and 2S, in step S115, a conformal sealing layer 223 is deposited to cover the substrate 100, the gate structure 250, and the gap structure 270.

[0100] Referring to Figure 2S, in some embodiments, the material of the sealing layer 223, such as oxynitride, is deposited on the substrate 100, the gate structure 250, and the gap structure 270. The deposition process includes physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or combinations thereof. In some embodiments, a high deposition rate is required to seal the air gap 220. The width W of the air gap 220 is positively correlated with the deposition rate of the sealing layer 223; that is, increasing the deposition rate of the sealing layer 223 allows for a larger width W of the air gap 220, while decreasing the deposition rate of the sealing layer 223 results in a smaller width W of the air gap 220. This design primarily aims to prevent the sealing layer 223 from filling the air gap 220. The parameters of the deposition rate of the sealing layer 223 and the width W of the air gap 220 depend on the process design requirements.

[0101] Figure 3A is a flowchart illustrating a method 30a for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 3B to 3H are schematic diagrams illustrating cross-sectional views of intermediate stages of the method 30a for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0102] Referring to Figures 3A and 3B, in step S301, a gate structure 250 is provided on the substrate 300.

[0103] Referring to Figure 3B, the gate structure 250 is the same as the gate structure 250 in Figure 2L, and the substrate 300 is the same as the substrate 100 in Figure 2B. Repeated descriptions are omitted.

[0104] Referring to Figures 3A and 3C, in step S303, a lightly doped drain (LDD) region 301 is formed in the substrate 300.

[0105] Referring to Figure 3C, in some embodiments, a doping process is performed to form a lightly doped drain (LDD) region 301. The LDD region 301 is typically located below the gate structure 250, close to the drain region, and in the channel region between the drain and source regions. In some embodiments, the LDD region 301 has a lower doping concentration than the source and drain regions to reduce the electric field strength near the drain region. The choice of dopant used in the LDD region 301 depends on the type of MOSFET formed. For example, in an n-type MOSFET, the substrate 300 is typically formed of n-type silicon, and the LDD region 301 utilizes a lightly doped n-type dopant such as phosphorus or arsenic. Conversely, in a p-type MOSFET, the substrate 300 is typically formed of p-type silicon, and the LDD region 301 uses a lightly doped p-type dopant such as boron.

[0106] Referring to Figures 3A and 3D, in step S305, a gap structure 270 is formed on the sidewall 250S of the gate structure 250, and a sealing layer 223 is deposited to cover the substrate 300, the gate structure 250 and the gap structure 270.

[0107] Referring to Figure 3D, the gap structure 270 and the sealing layer 223 are the same as the gap structure 270 in Figures 2R and 2S, and repeated descriptions are omitted.

[0108] Referring to Figures 3A and 3E, in step S307, a source / drain (S / D) region 303 is formed on the sidewall 250S of the gate structure 250.

[0109] Referring to Figure 3E, in some embodiments, a doping process is performed to form a source / drain (S / D) region 303. The S / D region 303 is typically located near a lightly doped drain (LDD) region 301, and in some embodiments, the two regions partially overlap. The doping type of the S / D region 303 is typically the same as that of the LDD region 301; however, the doping concentration in the S / D region 303 is typically higher than the doping concentration in the LDD region 301. This means that the concentration of dopant (such as phosphorus or boron) used in the LDD region 301 is lower than the concentration of dopant in the S / D region 303.

[0110] Referring to Figures 3A and 3F, in step S309, a dielectric layer 305 is configured to cover the sealing layer 223.

[0111] Referring to FIG3F, in some embodiments, a deposition process is performed to form a dielectric layer 305. The deposition process includes physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. The dielectric layer 305 is composed of materials such as silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass, polyimide, fluorinated silicate glass, or a combination thereof.

[0112] Referring to Figures 3A and 3G, in step S311, an opening 307 is formed in the dielectric layer 305.

[0113] Referring to Figure 3G, in some embodiments, the opening 307 is formed using an etching process, such as isotropic etching, anisotropic etching, or a combination thereof. The opening 307 is located on one side of the gate structure 250 and spaced apart from the gate structure 250 by a distance d. In some embodiments, due to etching selectivity in the etching process, excessive silicon consumption may occur during the etching of the contact window, causing the opening 307 to penetrate the dielectric layer 305 and extend into the source / drain (S / D) region 303. In some embodiments, the opening 307 is separated from the gate structure 250 through the gap structure 270 and the sealing layer 223. The opening 307 includes an upper portion 307-1 located in the dielectric layer 305 and a lower portion 307-2 located in the S / D region 303. Both the upper portion 307-1 and the lower portion 307-2 exhibit a tapered profile.

[0114] Referring to Figures 3A and 3H, in step S313, a contact 309 is formed in the dielectric layer 305.

[0115] Referring to Figure 3H, a dielectric layer 305 is deposited in the opening 307 using a chemical vapor deposition (CVD) method. In some embodiments, the material includes aluminum, copper, tungsten, cobalt, gold, silver, alloys (such as aluminum-copper alloys), or combinations thereof. After the deposition process is completed, a contact 309 is formed, including an upper portion 309-1 and a lower portion 309-2, respectively disposed in the upper portion 307-1 and lower portion 307-2 of the opening 307. Since the upper portion 307-1 and lower portion 307-2 of the opening 307 each have a tapered profile, the upper portion 309-1 and lower portion 309-2 of the contact 309 may also exhibit a tapered profile. After the contact 309 is formed, a planarization process is performed to remove portions of the dielectric layer 305 and the contact 309, providing a substantially flat surface for subsequent processing.

[0116] The embodiments disclosed herein provide a semiconductor device 10 including a gap structure 270 having an air gap 220. Furthermore, a method 10a is provided to reduce parasitic capacitance between a gate structure 250 and a contact using the gap structure 270. By applying the semiconductor device 10 and the associated method 10a, the parasitic capacitance between the gate structure 250 and the contact is reduced, resulting in improved gate control performance.

[0117] One embodiment of this disclosure provides a semiconductor device including a substrate having a top surface, a gate structure disposed on the top surface of the substrate, a gap structure disposed on a sidewall of the gate structure, and a sealing layer covering the substrate, the gap structure, and the gate structure. The gap structure includes a first spacer, a second spacer, a third spacer, and an air gap. The first spacer is disposed on the sidewall of the gate structure, and the air gap is located between the first spacer and the second spacer. The air gap is closed through the first spacer, the second spacer, the third spacer, and the sealing layer.

[0118] In some embodiments, the gate structure includes a first dielectric layer disposed on the top surface of the substrate, a metal compound layer disposed on the first dielectric layer, a second metal layer disposed on the metal compound layer, a third dielectric layer disposed on the second metal layer, and a fourth dielectric layer covering the first dielectric layer, the metal compound layer, the second metal layer and the third dielectric layer.

[0119] In some embodiments, the first dielectric layer comprises silicon oxide; the metal compound layer comprises polycrystalline silicon; the second metal layer comprises tungsten; the third dielectric layer comprises silicon nitride; and the fourth dielectric layer also comprises silicon nitride.

[0120] In some embodiments, the semiconductor device further includes a second dielectric layer disposed between the first dielectric layer and the metal compound layer, and a first metal layer disposed between the second dielectric layer and the metal compound layer.

[0121] In some embodiments, the fourth dielectric layer further covers the second dielectric layer and the first metal layer.

[0122] In some embodiments, the second dielectric layer comprises hafnium oxide, hafnium aluminum oxide, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, the like, or combinations thereof; and the first metal layer comprises tungsten, aluminum, tantalum, titanium, platinum, nickel, or alloys or combinations thereof.

[0123] In some embodiments, the air gap is sealed through the sealing layer.

[0124] In some embodiments, the air gap includes a sloping bottom surface.

[0125] In some embodiments, the inclined bottom surface is coplanar with an inclined sidewall of the first spacer.

[0126] In some embodiments, a vertical sidewall of the air gap is coplanar with a vertical sidewall of the second spacer and a vertical sidewall of the third spacer.

[0127] In some embodiments, the vertical level at which the lowest point of the air gap is located is lower than the vertical level at the highest point of the third gap.

[0128] In some embodiments, the sealing layer comprises silicon nitride.

[0129] In some embodiments, a distance between the air gap and the gate structure is positively correlated with a thickness of the fourth dielectric layer.

[0130] Another embodiment of this disclosure provides a semiconductor structure including a substrate, the substrate including a lightly doped drain (LDD) region disposed in a top surface of the substrate and a source / drain (S / D) region disposed in the substrate and adjacent to the LDD region, a gate structure disposed on the substrate, a gap structure disposed on a sidewall of the gate structure, a sealing layer covering the substrate, the gap structure and the gate structure, a dielectric layer covering the sealing layer, and a contact disposed in the dielectric layer and extending into the source / drain region. The gap structure includes a first spacer, a second spacer, a third spacer and an air gap. The air gap is disposed between the first spacer and the second spacer. The air gap is sealed through the sealing layer. The air gap is closed through the first spacer, the second spacer, the third spacer and the sealing layer.

[0131] In some embodiments, the gate structure includes a first dielectric layer disposed on the top surface of the substrate, a second dielectric layer disposed on the first dielectric layer, a first metal layer disposed on the second dielectric layer, a metal compound layer disposed on the first dielectric layer, a second metal layer disposed on the metal compound layer, a third dielectric layer disposed on the second metal layer, and a fourth dielectric layer covering the first dielectric layer, the first metal layer, the second dielectric layer, the metal compound layer, the second metal layer, and the third dielectric layer.

[0132] In some embodiments, the second dielectric layer comprises hafnium oxide, hafnium aluminum oxide, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, the like, or combinations thereof; and the first metal layer comprises tungsten, aluminum, tantalum, titanium, platinum, nickel, or alloys or combinations thereof.

[0133] In some embodiments, the air gap includes a sloping bottom surface.

[0134] In some embodiments, an inclined bottom surface is coplanar with an inclined sidewall of the first spacer.

[0135] In some embodiments, a vertical sidewall of the air gap is coplanar with a vertical side surface of the second spacer and a vertical sidewall of the third spacer.

[0136] In some embodiments, the vertical level at which the lowest point of the air gap is located is lower than the vertical level at the highest point of the third gap.

[0137] In some embodiments, a distance between the air gap and the gate structure is positively correlated with a thickness of the fourth dielectric layer.

[0138] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; sequentially depositing a first dielectric material, a second dielectric material, a first metal layer, a metal compound material, a second metal material, and a third dielectric material on the substrate and covering the substrate; using a photoresist as a photomask to perform a photolithography process on the second dielectric material, the first metal material, the metal compound material, the second metal material, and the third dielectric material, thereby forming a second dielectric layer, a first metal layer, a metal compound layer, a second metal layer, and a third dielectric layer, respectively; depositing a fourth dielectric material to cover the first dielectric material, the second dielectric layer, the first metal layer, the metal compound layer, the second metal layer, and the third dielectric layer; forming a first dielectric layer and a fourth dielectric layer, wherein the first dielectric material... A gate structure is configured with a dielectric layer, a second dielectric layer, a first metal layer, a metal compound layer, a second metal layer, a third dielectric layer, and a fourth dielectric layer; a fifth dielectric material is conformally formed on the fourth dielectric layer and the substrate; a sixth dielectric material is formed on the fifth dielectric material; a seventh dielectric material is formed on the sixth dielectric material; a first gap structure is formed on a sidewall of the gate structure, wherein the first gap structure includes a first gap element, a second gap element, and a third gap element, the third gap element being sandwiched between the first gap element and the second gap element; a second gap structure is formed on the sidewall of the gate structure by removing an upper portion of the first gap structure; and a sealing layer is conformally formed on the substrate, the second gap structure, and the gate structure, wherein the sealing layer seals the air gap.

[0139] In some embodiments, prior to forming the sealing layer, the method further includes performing a trimming process to remove a residual portion of the seventh dielectric material on the gate structure.

[0140] In some embodiments, the finishing process includes an etch-babk process.

[0141] In some embodiments, the second dielectric material includes hafnium oxide, hafnium aluminum oxide, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, the like, or combinations thereof.

[0142] In some embodiments, the formation of the second dielectric material is performed using an atomic layer deposition process.

[0143] In some embodiments, the thickness of the fifth dielectric material is positively correlated with the thickness of the fourth dielectric layer.

[0144] In some embodiments, the thickness of the sixth dielectric material is positively correlated with the deposition rate of the sealing layer.

[0145] Another embodiment of this disclosure provides a method for manufacturing a semiconductor structure, including providing a gate structure on a substrate; forming a lightly doped drain (LDD) region in the substrate; forming a gap structure on a sidewall of the gate structure; forming a source / drain (S / D) region in the substrate; forming a dielectric layer covering the gap structure and the gate structure; forming an opening in the dielectric layer, wherein the opening extends from a top surface of the dielectric layer to the source / drain region of the substrate; and forming a contact by depositing a conductive material in the opening. In some embodiments, the lightly doped drain region and the source / drain region are formed by an ion implantation process.

[0146] In some embodiments, the contact is separated from the gate structure through the gap structure.

[0147] The embodiments disclosed herein provide a semiconductor device including a gap structure having an air gap. Furthermore, a method is proposed to utilize this gap structure to reduce parasitic capacitance between a gate and a contact. By applying the semiconductor device and the associated method, the parasitic capacitance between the gate and the contact is reduced, resulting in improved gate performance.

[0148] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0149] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0150] 10: Semiconductor components 10a: Method 30: Semiconductor Structure 30a: Method 101-2: Part 100: Base 100TS: Top Surface 101-1: Part 103-1: Part 103: Dielectric Materials 105: Dielectric Materials 107: Metallic Materials 109: Metallic Compound Materials 111: Metallic Materials 113: Dielectric materials 115: Photoresist 115O: Opening 190: Microfilm Process 203: Dielectric layer 203BS: Bottom Surface 203TS: Top Surface 205: Dielectric layer 205BS: Bottom Surface 205S1: Sidewall 205S2: Sidewall 205TS: Top Surface 207: Metal layer 207BS: Bottom Surface 207S1: Sidewall 207S2: Sidewall 207TS: Top Surface 209: Metal compound layer 209BS: Bottom Surface 209TS: Top Surface 211: Metal layer 211BS: Bottom Surface 211S1: Sidewall 211S2: Sidewall 211TS: Top Surface 213: Dielectric layer 213BS: Bottom Surface 213S1: Sidewall 213S2: Sidewall 217-4: Part 215'-1: Partial 217-3: Horizontal section 215: Dielectric layer 215TS: Top Surface 215': Dielectric material 217-2: Inclined section 217-2S2: Inclined sidewall 217-1: Vertical section 217: Spacer 217TS: Top Surface 217': Dielectric material 219-2: Partial 219-1: Partial 219: Spacer 219L: Lower Part 219S2: Sidewall 219T: The highest point 219U: Upper Part 219': Dielectric material 220: Air gap 220B: Lowest point 220BS: Sloping bottom surface 220S1: Sidewall 220TS: Top Surface 221: Spacer 221S2: Sidewall 221T: The highest point 221': Dielectric material 221'P: Residual part 223: Sealing layer 250: Gate structure 250S: Sidewall 250TS: Top Surface 260: Gap Structure 270: Gap Structure 300: Base 301: Lightly doped drain region 303: Source / Drain Region 305: Dielectric layer 307-2: Lower Part 307-1: Upper Part 307: Opening 309-2: Lower Part 309-1: Upper Part 309:Contact D1: Distance d: distance H1: Thickness H2: Thickness H3: Thickness H4: Thickness H5: Thickness H6: Thickness VL1: Vertical alignment VL2: Vertical alignment W: Width S101: Steps S103: Steps S105: Steps S107: Steps S109: Steps S111: Steps S113: Steps S115: Steps S301: Steps S303: Steps S305: Steps S307: Steps S309: Steps S311: Steps S313: Steps T1: Thickness T2: Thickness T3: Thickness Z: Axis

Claims

1. A semiconductor element, comprising: A substrate having a top surface; A gate structure disposed on the top surface of the substrate; A gap structure disposed on one sidewall of the gate structure; and a sealing layer covering the substrate, the gap structure and the gate structure, wherein the gap structure includes a first gap element, a second gap element, a third gap element and an air gap; wherein the first gap element is disposed on one sidewall of the gate structure and the air gap is located between the first gap element and the second gap element, wherein the air gap is sealed through the first gap element, the second gap element, the third gap element and the sealing layer, wherein the air gap includes an inclined bottom surface.

2. The semiconductor device as claimed in claim 1, wherein the gate structure comprises: A first dielectric layer disposed on the top surface of the substrate; A metal compound layer disposed on the first dielectric layer; A second metal layer disposed on the metal compound layer; a third dielectric layer disposed on the second metal layer; and a fourth dielectric layer covering the first dielectric layer, the metal compound layer, the second metal layer, and the third dielectric layer.

3. The semiconductor device as claimed in claim 2, wherein the first dielectric layer comprises silicon oxide, the metal compound layer comprises polysilicon, the second metal layer comprises tungsten, the third dielectric layer comprises silicon nitride, and the fourth dielectric layer comprises silicon nitride.

4. The semiconductor device as described in claim 2 further includes: A second dielectric layer disposed between the first dielectric layer and the metal compound layer; And a first metal layer disposed between the second dielectric layer and the metal compound layer.

5. The semiconductor device as claimed in claim 4, wherein the fourth dielectric layer further covers the second dielectric layer and the first metal layer.

6. The semiconductor device as claimed in claim 4, wherein the second dielectric layer comprises hafnium oxide, hafnium aluminum oxide, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, the like or combinations thereof, and the first metal layer comprises tungsten, aluminum, tantalum, titanium, platinum, nickel or alloys thereof or combinations thereof.

7. The semiconductor device as claimed in claim 1, wherein the air gap is sealed through the sealing layer.

8. The semiconductor element as claimed in claim 1, wherein the inclined bottom surface is coplanar with an inclined sidewall of the first spacer.

9. The semiconductor element as claimed in claim 8, wherein a vertical sidewall of the air gap is coplanar with a vertical sidewall of the second spacer and a vertical sidewall of the third spacer.

10. The semiconductor element as claimed in claim 9, wherein a vertical level at which a lowest point of the air gap is located is lower than a vertical level at the highest point of the third gap.

11. The semiconductor device as claimed in claim 1, wherein the sealing layer comprises silicon nitride.

12. The semiconductor device as claimed in claim 2, wherein a distance between the air gap and the gate structure is positively correlated with a thickness of the fourth dielectric layer.

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