Semiconductor structure comprising nanosheets with hidden spacer and method for manufacturing the same

Abstract

Embodiments of the present invention include a semiconductor structure having nanosheets formed above a substrate and connected to source / drain regions, the nanosheets including a bottom nanosheet. Hidden spacers are formed between and below the nanosheets, wherein one of the hidden spacers is a single continuous sheet formed on the substrate and extending upward along the source / drain regions to the bottom nanosheet. Gate material is formed on the nanosheets and the hidden spacers.

Description

[Technical Field]

[0001] The present invention relates generally to a method of manufacturing an integrated circuit (IC) and the resulting structure, and more specifically, to a method of manufacturing a nanosheet configured and arranged to provide a nanosheet having hidden spacers and the resulting structure. [Previous Technology]

[0002] An IC (also known as a chip or microchip) comprises electronic circuitry on a wafer. The wafer is made of semiconductor material, such as silicon or other materials. An IC is formed from a large number of devices, such as transistors, capacitors, resistors, etc., which are formed in layers of the IC and interconnected with wiring in the back-to-upper (BEOL) layer of the wafer. A typical IC is formed by first fabricating individual semiconductor devices using a process commonly known as front-end processing (FEOL). A metal-oxide-semiconductor field-effect transistor (MOSFET) is a transistor used to amplify or switch electronic signals. A MOSFET has source, drain, and metal-oxide gate electrodes. A conventional FET is a planar device in which the entire channel region of the device is formed parallel to and slightly below the planar upper surface of the semiconductor substrate. Compared to planar FETs, there are so-called three-dimensional (3D) devices, such as FinFET devices, which have a three-dimensional structure. One type of device that showcases the future of advanced integrated circuit products is often called a nano-chip transistor. Generally, nanoplate transistors have a finned channel structure comprising a plurality of vertically spaced semiconductor material layers. The gate structure of the device is positioned around each of these spaced-apart channel semiconductor material layers. [Summary of the Invention]

[0003] Embodiments of the present invention pertain to providing nanosheets with hidden spacers. A semiconductor structure includes nanosheets formed above a substrate and connected to source / drain regions, the nanosheets having a bottom nanosheet. The semiconductor structure includes hidden spacers formed between and below the nanosheets, wherein one of the hidden spacers is a single continuous sheet formed on the substrate and extending upward along the source / drain regions to the bottom nanosheet. The semiconductor structure includes a gate material formed on the nanosheets and the hidden spacers.

[0004] According to one or more embodiments, a semiconductor structure includes nanosheets formed above a substrate and connected to source / drain regions, the nanosheets having a bottom nanosheet. The semiconductor structure includes hidden spacers formed between and beneath the nanosheets, wherein one of the hidden spacers is a single continuous sheet formed on the substrate and extending upward along the source / drain regions to the bottom nanosheet, wherein the bottom hidden spacer includes a cavity beneath the bottom nanosheet. The semiconductor structure includes a gate material formed on the nanosheets and the hidden spacers, the gate material filling the cavity of the bottom hidden spacer.

[0005] According to one or more embodiments, a method includes forming a nanosheet having a sacrificial layer and a semiconductor layer, replacing the sacrificial layer with hidden spacers, patterning the nanosheet and the hidden spacers, and forming source / drain regions connected to the nanosheet and the hidden spacers. The method includes etching portions of the hidden spacers and forming a gate material on the nanosheet and the hidden spacers.

[0006] Other embodiments of the present invention implement the features of the apparatus / structure described above in the method and / or implement the features of the method in the apparatus / structure.

[0007] Additional technical features and benefits are achieved by means of the technology of this invention. Embodiments and features of this invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, refer to the embodiments and drawings.

Implementation Method

[0023] The embodiments disclosed herein pertain to a semiconductor structure. The semiconductor structure includes nanosheets formed above a substrate and connected to source / drain regions, the nanosheets having a bottom nanosheet. The semiconductor structure includes hidden spacers formed between and below the nanosheets, wherein the bottom hidden spacer is a single continuous sheet formed on the substrate and extending upward along the source / drain regions to the bottom nanosheet. The semiconductor structure includes a gate material formed on the nanosheets and the hidden spacers. This disclosure provides early release of the sacrificial layer as a technical effect and solution. This removal eliminates the need for recessed inner spacers, as recessed inner spacers and their formation are becoming yield issues for nanosheet transistors. This also provides better performance. The single continuous bottom hidden spacer serving as bottom dielectric isolation reduces source / drain epitaxial etching defects.

[0024] In addition to or as an alternative to one or more of the features described above or below, other embodiments also disclose that the bottom-hidden spacers extend the length of the bottom nanosheet. The technical effect and solution include that the bottom-hidden spacers are continuous sheets used to isolate the nanosheets.

[0025] In addition to or as an alternative to one or more of the features described above or below, other embodiments also disclose that the concealed spacer includes at least one other concealed spacer and a bottom concealed spacer, the bottom concealed spacer having a thickness greater than that of the at least one other concealed spacer. The technical effect and solution include that the bottom concealed spacer can function as both a concealed spacer and an insulating layer.

[0026] In addition to or as an alternative to one or more of the features described above or below, other embodiments also disclose that the hidden spacer includes at least one other hidden spacer and a bottom hidden spacer, the bottom hidden spacer having a length greater than that of the at least one other hidden spacer. The technical effect and solution include that the bottom hidden spacer can function as both a hidden spacer and an isolation layer.

[0027] In addition to or as an alternative to one or more of the features described above or below, other embodiments also disclose that a gate material is formed on the top surface of a bottom-hidden spacer. The technical effect and solution include that the bottom-hidden spacer can act as both a hidden spacer and an isolation layer.

[0028] In addition to or as an alternative to one or more of the features described above or below, other embodiments also disclose that the bottom-hidden spacer includes a cavity, and a gate material is formed in the cavity between the top surface of the bottom-hidden spacer and the bottom surface of the bottom nanosheet. Technical effects and solutions include the bottom-hidden spacer being able to function as both a hidden spacer and an isolation layer.

[0029] In addition to or as an alternative to one or more of the features described above or below, other embodiments also disclose that the hidden spacer includes at least one other hidden spacer and a bottom hidden spacer, the at least one other hidden spacer having a triangular shape extending away from the source / drain region. The technical effect and solution include the early formation of hidden spacers without causing the sacrificial layer to collapse.

[0030] In addition to or as an alternative to one or more of the features described above or below, other embodiments also disclose a bottom-hidden spacer extending between the source / drain regions. The technical effect and solution include the bottom-hidden spacer being a continuous sheet used to isolate nanosheets.

[0031] An embodiment discloses a method comprising forming nanosheets over a substrate, the nanosheets including a bottom nanosheet and connected to source / drain regions. The method includes forming hidden spacers between and beneath the nanosheets, wherein the bottom hidden spacer of the hidden spacers is a single continuous sheet formed on the substrate and extending upward along the source / drain regions to the bottom nanosheet. The method includes forming a gate material on the nanosheets and the hidden spacers. This disclosure provides early release of the sacrificial layer as a technical effect and solution. This removal eliminates the need for recessed inner spacers, as recessed inner spacers and their formation are becoming yield issues for nanosheet transistors. This also provides better performance. The single continuous bottom hidden spacer serving as bottom dielectric isolation reduces source / drain epitaxial etching defects.

[0032] In addition to or as an alternative to one or more of the features described above or below, other embodiments also disclose nanosheets comprising alternating layers of sacrificial and semiconductor layers, and forming hidden spacers between and beneath the nanosheets including completely removing the sacrificial layers to leave cavities in which the hidden spacers are formed. This disclosure provides early release of the sacrificial layers as a technical effect and solution, resulting in the hidden spacers being continuous sheets used to isolate the nanosheets.

[0033] An embodiment discloses a semiconductor structure having nanosheets formed above a substrate and connected to source / drain regions, the nanosheets including a bottom nanosheet. The semiconductor structure includes hidden spacers formed between and below the nanosheets, wherein the bottom hidden spacer is a single continuous sheet formed on the substrate and extending upward along the source / drain regions to the bottom nanosheet, wherein the bottom hidden spacer includes a cavity below the bottom nanosheet. The semiconductor structure includes a gate material formed on the nanosheets and the hidden spacers, the gate material filling the cavity of the bottom hidden spacer. This disclosure provides early release of the sacrificial layer as a technical effect and technical solution. This removal eliminates the need for recessed inner spacers, as recessed inner spacers and their formation are becoming yield problems for nanosheet transistors. This also provides better performance. The single continuous bottom hidden spacer as bottom dielectric isolation reduces source / drain epitaxial etching defects.

[0034] In addition to or as an alternative to one or more of the features described above or below, other embodiments also disclose that the gate material is formed in a cavity between the top surface of the bottom-hidden spacer and the bottom surface of the bottom nanosheet. The technical effects and solutions include the bottom-hidden spacer being able to function as both a hidden spacer and an isolation layer.

[0035] An embodiment discloses a method comprising forming a nanosheet having a sacrificial layer and a semiconductor layer, replacing the sacrificial layer with a hidden spacer, patterning the nanosheet and the hidden spacer, and forming source / drain regions connected to the nanosheet and the hidden spacer. The method includes etching portions of the hidden spacer and forming a gate material on the nanosheet and the hidden spacer. This disclosure provides early release of the sacrificial layer as a technical effect and solution. This removal eliminates the need for recessed inner spacers, as recessed inner spacers and their formation are becoming yield issues for nanosheet transistors. This also provides better performance. A single continuous bottom hidden spacer acting as bottom dielectric isolation reduces source / drain epitaxial etching defects.

[0036] For the sake of brevity, the known techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process with additional steps or functionality not described in detail herein. Specifically, the various steps involved in manufacturing semiconductor devices and semiconductor-based ICs are well-known, and therefore, for the sake of brevity, many known steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0037] A MOSFET is a transistor used to amplify or switch electronic signals. A MOSFET has source, drain, and metal gate electrodes. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material (e.g., silicon dioxide or glass), which makes the MOSFET's input resistance relatively high. The gate voltage controls whether the current path from the source to the drain is open ("off") or resistive ("on"). n-type field-effect transistors (NFETs) and p-type field-effect transistors (PFETs) are two complementary types of MOSFETs. An NFET includes an n-doped source and drain junction and uses electrons as current carriers. A PFET includes a p-doped source and drain junction and uses holes as current carriers.

[0038] A nanowire or nanosheet MOSFET is a type of MOSFET that uses multiple stacked nanowires / nanosheets to form multiple channel regions. The gate region of a nanosheet MOSFET is formed by covering the gate stack material around the multiple nanowire / nanosheet channels. This configuration is called a gate-all-around (GAA) FET structure. Nanowire / nanosheet MOSFET devices reduce short-channel effects and reduce drain-induced barrier loss.

[0039] The GAA nanosheet FET structure provides excellent electrostatic discharge (ESD). Compared to the known FinFET structure where the transistor's fins extend "upwards" from the transistor, the nanosheet FET design implements the fins as silicon nanosheets / nanowires. In the known configuration of GAA nanosheet FETs, a relatively small FET footprint is provided by forming a channel region as a series of nanosheets (i.e., silicon nanowires). The known GAA configuration includes a source region, a drain region, and a stacked nanosheet channel between the source and drain regions. The gate surrounds the stacked nanosheet channel and modulates the electron flow through the nanosheet channel between the source and drain regions. GAA nanosheet FETs are fabricated by forming alternating layers of channel nanosheets and sacrificial nanosheets. The sacrificial nanosheets are released from the channel nanosheets before the FET device is completed.

[0040] One or more embodiments provide a transistor having a nanosheet with hidden spacers. A stack of nanosheets and a silicon-germanium sacrificial layer is formed, and a dummy gate is formed. Early release of the silicon-germanium sacrificial layer is performed, and the sacrificial layer is replaced with an insulating layer as a hidden spacer. After patterning, source / drain regions are formed, and the dummy gate is removed. Anisotropic etching is performed to selectively remove portions of the hidden spacers, and gate material is deposited in the cavity formed after the portions of the hidden spacers have been removed.

[0041] As a technical benefit and solution, this removal eliminates the need for recessed internal spacers, as the recessing and formation of internal spacers has become a yield problem and limits the adjustment of the contacted gate (multi) pitch (CPP). This also provides better performance. Furthermore, the formation of hidden spacers after channel release reduces source / drain epitaxial etch defects. The single continuous bottom hidden spacer, acting as a bottom dielectric isolation layer, reduces source / drain epitaxial etch defects. Moreover, due to the absence of hidden spacer deposition and etchback, there are no recessed hidden spacers.

[0042] Turning now to a more detailed description of the present invention, FIG1A depicts a simplified top view of a portion of an integrated circuit (IC) 100, and FIG1B depicts a cross-sectional view taken along line A of the IC 100. For ease of understanding, some layers may be omitted from the top view to avoid confusion and to view the layers below. Thus, the top view is intended to provide a simplified illustration and general orientation, but is not intended to be a complete representation of the device. Standard semiconductor manufacturing techniques can be used to manufacture the IC 100 as understood by one generally skilled in the art. Any suitable lithography process, including deposition and etching techniques, may be used herein.

[0043] Figures 1A and 1B depict an IC 100 having undergone several manufacturing processes on a wafer. The figures illustrate the IC 100 after the growth of an alternating stack of nanosheets. The nanosheet stack is formed on a substrate 102 (or wafer). The substrate 102 may be formed of (pure) silicon. Other suitable semiconductor materials may be used for the substrate 102. As seen in Figure 1B, the nanosheet stack has alternating layers of semiconductor layer 110 and sacrificial layers 112 and 112A. Semiconductor layer 110 may comprise substantially pure silicon. Semiconductor layer 110 is a channel region for a nanosheet FET device. Semiconductor layer 110 is a nanosheet, and the nanosheet may have a thickness of, for example, 5 nanometers. The thickness of the nanosheet may be in the range of about 2 nm to 10 nm, and other ranges are possible. Sacrificial layers 112 and 112A are formed of silicon-germanium (SiGe), wherein the atomic percentage (%) of germanium is about 25% and silicon is the remainder. In one or more embodiments, the atomic percentage of germanium may be in the range of about 15% to 30%, and silicon is the remainder in sacrificial layers 112 and 112A.

[0044] A hard mask layer 120 is formed on top of the semiconductor layer 110. Examples of materials for the hard mask layer 120 may include nitride materials, such as silicon nitride.

[0045] Figures 2A, 2B and 2C depict the IC 100 after the nanosheets are patterned into fins and shallow trench isolation is formed. Except for the cross-sectional view taken along A in Figure 2B, Figure 2C depicts a cross-sectional view taken along B of the IC 100.

[0046] The hard mask layer 120 is patterned, and the patterned hard mask layer 120 is used to etch a portion of the semiconductor layer 110, the sacrificial layers 112 and 112A, and the substrate 102. Wet etching or dry etching can be used.

[0047] A shallow trench isolation (STI) region 202 is formed in the substrate 102. The material of the STI region 202 may include low-k dielectric materials, ultra-low-k dielectric materials, etc. As best seen in Figure 2C, the fin width W can be in the range of about 6 nm to 14 nm. Although a single fin is shown in Figure 2C, multiple fins may exist as shown by the dashed lines in Figure 2A.

[0048] Figures 3A and 3B depict the IC 100 after the formation of the dummy gate. A sacrificial gate material is formed on the IC 100, ultimately creating a dummy gate 302, and a hard masking layer 304 is formed on top of the sacrificial gate material. The hard masking layer 304 is patterned and is used to etch the sacrificial gate material into the dummy gate 302. The etching terminates on the hard masking layer 120 and the STI region 202, exposing the hard masking layer 120 and the STI region 202. Examples of materials for the dummy gate 302 may include amorphous silicon, polycrystalline silicon, etc. Examples of materials for the hard masking layer 304 may include nitride materials, such as silicon nitride, silicon oxynitride, etc.

[0049] Figures 4A and 4B depict IC 100 after all sacrificial layers have been released. This is an earlier release of the entire silicon-germanium material used to fabricate sacrificial layers 112 and 112A, thereby creating cavities 402 and 402A, respectively. The height H1 of cavity 402A is greater than the height H2 of cavity 402 because the thickness / height of sacrificial layer 112A is greater than that of sacrificial layer 112. Unlike current state-of-the-art manufacturing processes, it is not necessary to recess the sacrificial layers to form the internal spacers that are later released during the SiGe process. This reduces the number of processing steps.

[0050] Figures 5A and 5B depict the IC 100 after the cavity is refilled with insulating material. Deposition is performed to simultaneously form hidden spacers 502 and 502A to fill the cavities 402 and 402A. Examples of materials for the hidden spacers 502 and 502A may include silicon carbide (SiOC), SiBCN, SiOCN, SiC, SiOCN, SiN, etc.

[0051] An etchback is performed to remove excess hidden spacer material. The bottom hidden spacer 502A is the lowest hidden spacer and has a thickness or height H1, while the hidden spacer 502 has a thickness or height H2. Height H1 is greater than height H2. In one or more embodiments, height H2 is approximately twice (2×) the height H1. In one or more embodiments, height H2 is approximately three, four, five, etc., the height H1.

[0052] Figures 6A and 6B depict the IC 100 after gate spacer deposition and etching. Gate spacer material is deposited and etched to form gate spacer 602 on the dummy gate 302 and hard masking layer 304. Reactive ion etching (RIE) can be used to etch the deposited gate spacer material to form gate spacer 602. Examples of materials for gate spacer 602 may include nitride materials such as SiN, SiBCN, SiOCN, SiOC, etc.

[0053] Figures 7A and 7B depict the IC 100 after the fin recess. Directional etching is performed using a hard mask layer 304 and gate spacers 602 as protective masks to etch the fins, thereby creating cavities 702. Reactive ion etching (RIE) can be used to etch through the hard mask layer 120, the semiconductor layer 110, and the hidden spacers 502 and 502A. Different etching chemicals can be used to etch through different layers of the nanosheet stack, terminating on the substrate 102.

[0054] Figures 8A and 8B depict the IC 100 after epitaxial growth of the source and drain regions. Semiconductor material is epitaxially grown from semiconductor layer 110 and substrate 102. The deposited semiconductor material may be doped with n-type or p-type dopants depending on whether an n-type or p-type transistor is formed to generate source / drain regions 802. Unlike current state-of-the-art technologies, there is no longer a manufacturing process for recessing the silicon-germanium sacrificial layer and filling it with spacer material, because the hidden spacers 502 and 502A now act as insulators.

[0055] Figures 9A and 9B depict the IC 100 after the formation of the interlayer / intralayer dielectric (ILD). The filler material is deposited and repolished (e.g., using chemical mechanical polishing / planarization (CMP)) to produce the ILD layer 902. The ILD layer 902 may include low-k dielectric materials, ultra-low-k dielectric materials, etc.

[0056] Figures 10A and 10B depict IC 100 after the pseudo-pull. The pseudo gate 302 is etched after the hard mask layer 304 is removed, thereby creating cavity 1002. The hard mask layer 120 is also removed.

[0057] Figures 11A and 11B depict IC 100 after channel release. Etching is performed to remove a portion of the hidden spacers 502 and 502A. The result of the etching is that a portion of the hidden spacers 502 and 502A remains intact. The etching causes a cavity 1150 to form in the bottom hidden spacer 502A below the bottom semiconductor layer 110A of the semiconductor layer 110. The bottom semiconductor layer 110A is the bottommost semiconductor layer.

[0058] Directional etching (e.g., RIE) can be performed to etch the interior and exterior of the screen / page. Anisotropic etching can be performed, where gas-based etching or wet-based etching can be used. Furthermore, an example supplier of systems for etching is Applied Materials®, which supplies the Applied Centura® Sculpta® patterning system. The Applied Centura® Sculpta® patterning system enables a capability known as pattern plasticity, defined as the ability to precisely and unidirectionally modify the dimensions of features on a wafer to improve the performance of EUV patterning. The shapes of the hidden spacers 502 and 502A can be adjusted using the etching system to produce near-square or arrowhead shapes.

[0059] Figures 12A and 12B depict the IC 100 after the replacement gate (RMG) is formed. A gate material 1202 is formed around the semiconductor layer 110 and on the hidden spacers 502 and 502A. The gate material 1202 is in contact with the source / drain region 802. The gate material 1202 includes one or more high-k dielectric layers wound around the semiconductor layer 110. The gate material 1202 includes a work function material surrounding the high-k dielectric layers and a gate metal filler.

[0060] A gate cap 1204 is formed on a gate material 1202. The gate cap 1204 may include a nitride material.

[0061] FIG13 is a flowchart of a method 1300 for forming an IC 100 with hidden spacers according to one or more embodiments. Reference may be made to any of the diagrams discussed herein. At block 1302, method 1300 includes forming a nanosheet (e.g., semiconductor layer 110 and sacrificial layers 112 and 112A) over a substrate 102, the nanosheet including a bottom nanosheet (e.g., sacrificial layer 112A) and connected to a source / drain region 802. At block 1304, method 1300 includes forming hidden spacers 502 (including a bottom hidden spacer 502A) between and below the nanosheets, wherein the bottom hidden spacer 502A of the hidden spacers 502 is a single continuous wafer formed on the substrate 102 and extending upward along the source / drain region 802 to the bottom nanosheet (e.g., bottom semiconductor layer 110A). At block 1306, method 1300 includes forming a gate material 1202 on a nanosheet (e.g., semiconductor layer 110) and a hidden spacer 502.

[0062] Furthermore, the bottom hidden spacer 502A extends the length of the bottom nanosheet (e.g., the bottom semiconductor layer 110A). The hidden spacer 502 includes at least one other hidden spacer (e.g., hidden spacer 502) and the bottom hidden spacer 502A, the bottom hidden spacer 502A having a thickness greater than that of at least one other hidden spacer (e.g., hidden spacer 502) (e.g., height / thickness H1 is greater than height / thickness H2). The hidden spacer 502 includes at least one other hidden spacer and the bottom hidden spacer 502A, the bottom hidden spacer 502A having a length greater than that of at least one other hidden spacer (e.g., hidden spacer 502). For example, the length L1 of the bottom hidden spacer 502A (which is a continuous wafer from (one) source / drain region 802 to (another) source / drain region 802) is greater than the decreasing length L2 of the hidden spacer 502.

[0063] In addition, the nanosheet includes alternating layers of sacrificial layers 112 and 112A and semiconductor layer 110; and forming hidden spacers 502 between or beneath the nanosheets includes completely removing the sacrificial layers 112 and 112A to leave cavities 402 and 402A, such that hidden spacers 502 (including bottom hidden spacers 502A) are formed in cavities 402 and 402A. Gate material 1202 is formed on the top surface of the bottom hidden spacer 502A.

[0064] Furthermore, a cavity 1150 is formed in the bottom-hidden spacer 502A, and a gate material 1202 is formed in the cavity 1150 between the top surface of the bottom-hidden spacer 502A and the bottom surface of the bottom nanosheet (e.g., the bottom semiconductor layer 110A). The hidden spacer 502 includes at least one other hidden spacer and the bottom-hidden spacer 502A, and the at least one other hidden spacer has a square or triangular shape extending away from the source / drain region 802. The bottom-hidden spacer 502A extends between the source / drain regions 802.

[0065] FIG14 is a flowchart of a method 1400 for forming an IC 100 with hidden spacers according to one or more embodiments. Reference may be made to any of the diagrams discussed herein. Method 1400 includes: forming a nanosheet of sacrificial layers 112 and 112A and a semiconductor layer 110 at block 1402; replacing sacrificial layers 112 and 112A with hidden spacers 502 (including bottom hidden spacers 502A) at block 1404; patterning the nanosheet and hidden spacers 502 (including bottom hidden spacers 502A) at block 1406; and forming a source / drain region 802 connected to the nanosheet and hidden spacers 502 (including bottom hidden spacers 502A) at block 1408. Method 1400 includes: etching a portion of the hidden spacer 502 (including the bottom hidden spacer 502A) at block 1410; and forming a gate material 1202 on the nanosheet and the hidden spacer 502 (including the bottom hidden spacer 502A) at block 1412.

[0066] As discussed herein, gate materials are formed around semiconductor layers. Gate materials include high-k materials and work function materials commonly referred to as high-k metal gates (HKMGs). Techniques for forming HKMGs in gate openings are well known in this art, and therefore, details have been omitted to allow the reader to focus on the prominent features of the disclosed method. However, it should be understood that this HKMG will generally include forming one or more gate dielectric layers (e.g., interlayer (IL) oxide and high-k gate dielectric layers) deposited to line the gate opening, and forming one or more metal layers deposited onto one or more gate dielectric layers to fill the gate opening. Given the conductivity type of the FET, the materials and thicknesses of the dielectric and metal layers used for the HKMG can be pre-selected to achieve the desired work function. To avoid confusion in the diagrams and to allow the reader to focus on the prominent features of the disclosed method, the different layers within the HKMG stack are not shown. For illustrative purposes, as an example, a high-k gate dielectric layer may be a dielectric material having a dielectric constant greater than that of silicon dioxide (i.e., greater than 3.9). Exemplary high-k dielectric materials include, but are not limited to, hafnium (Hf)-based dielectrics (e.g., hafnium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium aluminum oxide, etc.) or other suitable high-k dielectrics (e.g., aluminum oxide, tantalum oxide, zirconium oxide, etc.). Depending on the application, one or more metal layers may include work function metals adjacent to the gate dielectric layer and preselected, based on the conductivity type of the nanosheet-FET, to achieve an optimal gate conductor work function. For example, the optimal gate conductor work function of a PFET may be, for instance, between approximately 4.9 eV and approximately 5.2 eV. Exemplary metals (and metal alloys) having a work function in or near this range include, but are not limited to, ruthenium, palladium, platinum, cobalt, and nickel, as well as metal oxides (aluminum oxycarbide, titanium aluminate oxycarbide, etc.) and metal nitrides (e.g., titanium nitride, silicon titanium nitride, silicon tantalum nitride, aluminum titanium nitride, aluminum tantalum nitride, etc.). The optimal gate conductor work function of an NFET may be, for example, between 3.9 eV and about 4.2 eV. Exemplary metals (and metal alloys) having a work function in or near this range include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and their alloys, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. One or more metal layers may further include filler metals or filler metal alloys, such as tungsten, tungsten alloys (e.g., tungsten silicon or titanium tungsten), cobalt, aluminum, or any other suitable filler metal or filler metal alloy.

[0067] Although not shown, contact formation and ILD formation are performed. An ILD material can be deposited, source / drain contact openings can be patterned using conventional photolithography, and then metal can be deposited to fill the cavities, thereby forming metal contacts. A portion of the metal contacts may include silicate, which is generated from the interface between the metal material and the semiconductor material. The metal contacts are source / drain contacts respectively connected to the epitaxial source / drain regions.

[0068] The ILD material can be SiO2, SiN, a low-k dielectric material, or an ultra-low-k dielectric material. Low-k dielectric materials typically include dielectric materials with a k-value of about 3.9 or less. Ultra-low-k dielectric materials typically include dielectric materials with a k-value less than 2.5. Unless otherwise stated, all k-values ​​mentioned in this application are measured relative to vacuum. Exemplary ultra-low-k dielectric materials typically include porous materials such as porous organic silicate glasses, porous polyamide nanofoams, silica dry gels, porous silsesquioxanes (HSQ), porous methylsilsesquioxanes (MSQ), porous inorganic materials, porous CVD materials, porous organic materials, or combinations thereof. Ultra-low-k dielectric materials can be produced using templated processes or sol-gel processes commonly known in this art. In templated processes, the precursor typically contains a complex of thermally unstable and stable materials. After film deposition, thermally unstable materials can be removed by heating, leaving pores in the dielectric film. In sol-gel processes, porous low-k dielectric films can be formed by the hydrolysis and polycondensation of one or more alkoxides, such as tetraethoxysilane (TEOS).

[0069] Various embodiments of the present invention are described herein with reference to the accompanying drawings. Alternative embodiments may be designed without departing from the scope of the invention. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) are depicted between elements in the following description and in the drawings, those skilled in the art will recognize that many of the positional relationships described herein are oriented independently, while maintaining the described functionality even if the orientation is changed. Unless otherwise specified, such connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limited in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, referring to the present description, a layer "A" is formed above layer "B" including one or more intermediate layers (e.g., layer "C") between layer "A" and layer "B," provided that the relevant characteristics and functions of layers "A" and "B" are not substantially altered by the one or more intermediate layers.

[0070] The phrase “selective to”, such as “the first element is selective to the second element”, means that the first element can be etched and the second element can act as an etch terminator.

[0071] As used herein, "p-type" refers to the addition of impurities to a pure semiconductor that produces defects that generate valence electrons. Examples of p-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium.

[0072] As used herein, "n-type" refers to the addition of impurities that contribute free electrons to a pure semiconductor. Examples of n-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus.

[0073] As previously noted herein, for the sake of brevity, prior art related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, with the aid of the background, a more general description of semiconductor device manufacturing processes that can be used to implement one or more embodiments of the present invention will now be provided. Although specific manufacturing operations used in implementing one or more embodiments of the present invention may be individually known, the described combination of operations and / or resulting structures of the present invention is unique. Therefore, the unique combination of operations described in the manufacture of a semiconductor device according to the present invention utilizes a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0074] Generally speaking, the various processes used to form microchips to be packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP) and similar processes. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and / or by ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopant. Films of both conductors (e.g., polycrystalline silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by applying voltage. By creating the structures of these various components, millions of transistors can be built and wired together to form the complex circuit systems of modern microelectronic devices.

[0075] As noted above, atomic layer etching (ALE) processes can be used in this invention for purposes such as removing via residues caused by via misalignment. ALE processes use plasma-based or electrochemical methods to provide precise etching of metals. An ALE process is generally defined by two independently controllable, well-defined, sequential, self-limiting reaction steps. This process typically includes passivation followed by selective removal of the passivation layer and can be used to remove thin metal layers of approximately several nanometers. An illustrative plasma-based method typically includes a two-step process that typically involves exposing a metal (such as copper) to a chlorine and hydrogen plasma at low temperatures (below 20°C). This process produces volatile etching products that minimize surface contamination. In another example, cyclic exposure to an oxidant and hexafluoroacetylene (Hhfac) at high temperatures (such as 275°C) can be used to selectively etch metals such as copper. An illustrative electrochemical method may also include two steps. The first step involves limited sulfidation of the surface of a metal such as copper to form a metal sulfide, such as Cu₂S, followed by selective wet etching of the metal sulfide, for example, etching Cu₂S in HCl. Atomic-layer etching is a relatively new technique, and optimization for a specific metal is entirely within the skill of someone proficient in this technique. The reaction at the surface provides high selectivity and minimally or not at all corrodes the exposed dielectric surface.

[0076] Semiconductor lithography is the process of forming a three-dimensional raised image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called photoresist. To construct the complex structure of transistors and the numerous wires of millions of transistors connecting circuits, the lithography and etching pattern transfer steps are repeated multiple times. The patterns printed on the wafer are aligned with the previously formed patterns, and conductors, insulators, and selectively doped regions are slowly built in to form the final device.

[0077] Photoresist can be formed using conventional deposition techniques, such as chemical vapor deposition, plasma vapor deposition, sputtering, dip coating, spin coating, brush coating, spraying, and other similar deposition techniques. After the photoresist is formed, it is exposed to radiation such as X-ray radiation, extreme ultraviolet (EUV) radiation, electron beam radiation, or similar radiation to form the desired pattern. Next, the exposed photoresist is developed using a conventional resist development process.

[0078] After the development step, an etching step may be performed to transfer the pattern from the patterned photoresist to the interlayer dielectric. The etching step for forming at least one opening may include dry etching processes (including, for example, reactive ion etching, ion beam etching, plasma etching or laser ablation), wet chemical etching processes or any combination thereof.

[0079] For the sake of brevity, the prior art related to the implementation and use of the present invention may or may not be described in detail herein. Specifically, various forms of computing systems and specific computer programs used to implement the various technical features described herein are well known. Therefore, for the sake of brevity, many prior art implementation details are only briefly mentioned or completely omitted herein without providing well known system and / or process details.

[0080] In some embodiments, various functions or actions may occur at a given location and / or in combination with the operation of one or more devices or systems. In some embodiments, a portion of a given function or action may be performed at a first device or location, and the remainder of the function or action may be performed at one or more additional devices or locations.

[0081] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. It should be further understood that the terms "comprises" and / or "comprising," when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0082] All components or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent for performing functions in conjunction with other claimed elements as specifically claimed. This disclosure is presented for illustrative and descriptive purposes but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. Embodiments have been chosen and described to best explain the principles and practical application of this disclosure and to enable others skilled in the art to understand this disclosure with respect to various embodiments having various modifications suitable for the particular purpose considered.

[0083] The diagrams depicted herein are illustrative. Many variations may exist in the diagrams or the steps (or operations) described therein without departing from the spirit of this disclosure. For example, actions may be performed in different orders, or actions may be added, deleted, or modified. Furthermore, the term "coupled" describes a signal path between two elements and does not imply a direct connection between the elements without any intervening elements / connections. All such variations are considered part of this disclosure.

[0084] The following definitions and abbreviations will be used to interpret the scope of the patent application and this specification. As used herein, the terms "comprises / comprising," "includes / including," "has / having," "contains or containing," or any other variations thereof are intended to cover non-exclusive inclusions. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0085] Additionally, the term "illustrative" is used herein to mean "serving as an example, illustration, or diagram." Any embodiment or design described herein as "illustrative" is not necessarily to be construed as superior or advantageous to other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plural" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" may include both indirect "connection" and direct "connection."

[0086] The terms “about,” “substantially,” “approximately,” and variations thereof are intended to include a degree of error associated with a measurement based on a specific quantity of equipment available at the time of filing this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value.

[0087] Various embodiments of the invention have been described for illustrative purposes, but such description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments described herein. [Simplified Explanation of the Diagram]

[0008] The details of the proprietary rights described herein are specifically pointed out and clearly claimed in the claims at the end of this specification. The foregoing and other features and advantages of embodiments of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] FIG1A and FIG1B respectively depict a top view and a cross-sectional view of a portion of an integrated circuit (IC) under manufacturing after manufacturing operations, according to one or more embodiments of the present invention;

[0010] Figures 2A, 2B and 2C depict a top view and a cross-sectional view of a portion of an IC under manufacturing after a manufacturing operation, according to one or more embodiments of the present invention.

[0011] FIG3A and FIG3B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention;

[0012] FIG4A and FIG4B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention;

[0013] FIG5A and FIG5B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention;

[0014] FIG6A and FIG6B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention;

[0015] FIG7A and FIG7B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention;

[0016] FIG8A and FIG8B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention;

[0017] FIG9A and FIG9B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention;

[0018] FIG10A and FIG10B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention.

[0019] FIG11A and FIG11B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention.

[0020] FIG12A and FIG12B depict a top view and a cross-sectional view of a portion of an IC under manufacturing after manufacturing operations, according to one or more embodiments of the present invention;

[0021] FIG13 depicts a flowchart of a method for forming a semiconductor structure according to one or more embodiments of the present invention; and

[0022] FIG14 depicts a flowchart of a method for forming a semiconductor structure according to one or more embodiments of the present invention.

Claims

1. A semiconductor structure comprising: nanosheets formed above a substrate and connected to source / drain regions, the nanosheets including a bottom nanosheet; hidden spacers formed between and below the nanosheets, wherein the hidden spacers include a bottom hidden spacer and at least one other hidden spacer, the bottom hidden spacer being a single continuous sheet formed on the substrate and extending upward along the source / drain regions to the bottom nanosheet, the at least one other hidden spacer having a triangular shape extending away from the source / drain regions; and a gate material formed on the nanosheets and the hidden spacers.

2. The semiconductor structure of claim 1, wherein the spacer hidden on the substrate extends a length of the substrate nanosheet.

3. The semiconductor structure of claim 1, wherein the bottom-hidden spacer has a thickness greater than that of the at least one other hidden spacer.

4. The semiconductor structure of claim 1, wherein the bottom-hidden spacer has a length greater than that of the at least one other hidden spacer.

5. The semiconductor structure of claim 1, wherein the gate material is formed on a top surface of the spacer hidden on the bottom.

6. The semiconductor structure as described in claim 5, wherein: The bottom-hidden spacer includes a cavity; and the gate material is formed in the cavity between the top surface of the bottom-hidden spacer and one of the bottom surfaces of the bottom nanosheet.

7. The semiconductor structure of claim 1, wherein the spacer hidden on the substrate extends between the source / drain regions.

8. A method for manufacturing a semiconductor structure, comprising: forming nanosheets over a substrate, the nanosheets including a bottom nanosheet and connected to source / drain regions; forming hidden spacers between and below the nanosheets, wherein the hidden spacers include a bottom hidden spacer and at least one other hidden spacer, the bottom hidden spacer being a single continuous sheet formed on the substrate and extending upward along the source / drain regions to the bottom nanosheet, the at least one other hidden spacer having a triangular shape extending away from the source / drain regions; and forming a gate material on the nanosheets and the hidden spacers.

9. The method of claim 8, wherein the spacer hidden on the substrate extends a length of the substrate nanosheet.

10. As in request item 8, wherein: The bottom hidden spacer has a thickness greater than that of the at least one other hidden spacer; and the bottom hidden spacer has a length greater than that of the at least one other hidden spacer.

11. As in request item 8, where: The nanosheets comprise alternating layers of sacrificial and semiconductor layers; and forming the hidden spacers between and beneath the nanosheets comprises completely removing the sacrificial layers to leave cavities in which the hidden spacers are formed.

12. The method of claim 8, wherein the gate material is formed on a top surface of the spacer hidden at the bottom.

13. As in request item 12, wherein: A cavity is formed in the spacer hidden at the bottom; and the gate material is formed in the cavity between the top surface of the spacer hidden at the bottom and one of the bottom surfaces of the bottom nanosheet.

14. The method of claim 8, wherein the spacer hidden beneath the bottom extends between the source / drain regions.

15. A semiconductor structure comprising: nanosheets formed above a substrate and connected to source / drain regions, the nanosheets including a bottom nanosheet; hidden spacers formed between and below the nanosheets, wherein the hidden spacers include a bottom hidden spacer and at least one other hidden spacer, the bottom hidden spacer being a single continuous sheet formed on the substrate and extending upward along the source / drain regions to the bottom nanosheet, the at least one other hidden spacer having a triangular shape extending away from the source / drain regions, wherein the bottom hidden spacer includes a cavity below the bottom nanosheet; and a gate material formed on the nanosheets and the hidden spacers, the gate material filling the cavity of the bottom hidden spacer.

16. The semiconductor structure of claim 15, wherein the spacer hidden on the substrate extends a length of the substrate nanosheet.

17. The semiconductor structure of claim 15, wherein the bottom-hidden spacer has a thickness greater than that of the at least one other hidden spacer.

18. The semiconductor structure of claim 15, wherein the bottom-hidden spacer has a length greater than that of the at least one other hidden spacer.

19. The semiconductor structure of claim 15, wherein the gate material is formed on a top surface of the spacer hidden on the bottom.

20. The semiconductor structure of claim 19, wherein the gate material is formed in the cavity between the top surface of the bottom-hidden spacer and one of the bottom surfaces of the bottom nanosheet.

21. The semiconductor structure of claim 15, wherein the spacer hidden on the substrate extends between the source / drain regions.

22. A method for manufacturing a semiconductor structure, comprising: forming a nanosheet including a sacrificial layer and a semiconductor layer; replacing the sacrificial layer with hidden spacers; patterning the nanosheet and the hidden spacers; forming source / drain regions connected to the nanosheet and the hidden spacers; etching portions of the hidden spacers, wherein the hidden spacers include a bottom hidden spacer and at least one other hidden spacer such that the at least one other hidden spacer has a triangular shape extending away from the source / drain regions; and forming a gate material on the nanosheet and the hidden spacers.

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