Electronic device and method of shifting a signal from one voltage domain to another

Abstract

An electronic device includes a first stage and a second stage. The first stage includes a first device circuit and a second device circuit. The first device circuit operates in a first voltage domain, selects an input signal in response to a first selection signal, and generates a first intermediate output signal based on the selected input signal. The second device circuit operates in a second voltage domain, selects an input signal in response to a second selection signal, and generates a second intermediate output signal based on the selected input signal. The second stage operates in the second voltage domain, receives the first intermediate output signal and the second intermediate output signal, and generates an output signal. The invention also discloses a method for shifting a signal from one voltage domain to another.

Description

Technical Field

[0001] The embodiments of the present invention relate to an electronic device and a method of operating the same, particularly to an electronic device having a level shifter and a method of shifting a signal from one voltage domain to another. Prior Technology

[0002] A level shifter is a circuit that enables signal transitions between different voltage levels or voltage domains, allowing communication between components operating in different voltage domains. Level shifters can be used in devices where components with many different voltage requirements coexist. A level shifter receives an input signal at one voltage level and uses a switching element, such as a transistor, to convert the input signal into an output signal at another voltage level. Furthermore, level shifters can be combined with other circuits, such as a multiplexer and a latch, to improve signal routing and synchronization. Applications of level shifters include mobile devices, microcontrollers, memory interfaces, power management systems, and other systems operating at multiple voltage levels. Summary of the Invention

[0003] One embodiment of the present invention provides an electronic device, including a first stage and a second stage. The first stage includes a first device circuit and a second device circuit. The first device circuit is configured to operate in a first voltage domain to receive a pair of input signals and a complementary plurality of first selection signals, select one of the input signals in response to the first selection signals, and generate a first intermediate output signal based on the selected input signal. The second device circuit is configured to operate in a second voltage domain to receive the input signals and a complementary plurality of second selection signals, select one of the input signals in response to the second selection signals, and generate a second intermediate output signal based on the selected input signal. The second stage is configured to operate in the second voltage domain to receive the first intermediate output signal and the second intermediate output signal, and generate an output signal.

[0004] Another embodiment of the present invention provides an electronic device, including: a first stage, a second stage, and a third stage. The first stage includes a first device circuit and a second device circuit. The first device circuit is configured to operate in a first voltage domain to receive an input signal in the first voltage domain and generate a first intermediate output signal based on the input signal. The second device circuit is configured to operate in a second voltage domain to receive the input signal and generate a second intermediate output signal based on the input signal. The second stage is configured to operate in the second voltage domain to receive the first intermediate output signal, the second intermediate output signal, and complementary complex clock signals, and generate a third intermediate output signal based on the first intermediate output signal, the second intermediate output signal, and the clock signals. The third stage is configured to operate in the second voltage domain to receive the third intermediate output signal and the clock signals and generate an output signal.

[0005] Another embodiment of the present invention provides a method for shifting a signal from one voltage domain to another voltage domain. The method includes: receiving a first input signal and a second input signal; selecting one of the first input signal and the second output signal in response to complementary complex first selection signals and complementary complex second selection signals; generating a first intermediate output signal and a second intermediate output signal based on the selected first input signal and the second output signal; shifting one of the selected first input signal and the second output signal from a first voltage domain to a second voltage domain based on the first intermediate output signal, the second intermediate output signal and complementary clock signals; and generating an output signal based on a third intermediate output signal corresponding to the second voltage domain. Simple Explanation of the Diagram

[0006] The various aspects of this disclosure can be better understood through the accompanying illustrations and the following detailed description: Figure 1A is a schematic unit diagram of an exemplary device according to various embodiments of the present disclosure; Figure 1B is a schematic unit diagram of another exemplary device according to various embodiments of the present disclosure; Figure 1C is a schematic timing diagram illustrating an exemplary relationship between input signals and output signals according to various embodiments disclosed herein; Figure 2 is a schematic circuit diagram of another exemplary device according to various embodiments of the present disclosure; Figure 3 is a schematic circuit diagram of another exemplary device according to various embodiments of the present disclosure; Figure 4 is a schematic circuit diagram of another exemplary device according to various embodiments of the present disclosure; Figure 5 is a schematic circuit diagram of another exemplary device according to various embodiments of the present disclosure; Figure 6 is a schematic circuit diagram of another exemplary device according to various embodiments of the present disclosure; Figure 7 is a schematic circuit diagram of another exemplary device according to various embodiments of the present disclosure; Figure 8 is a flowchart of an exemplary method for shifting a signal from one voltage domain to another according to various embodiments of the present disclosure; Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. To simplify this disclosure, specific examples of elements and arrangements will be described below. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature on or above a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or symbols may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0008] Level shifting circuits can be implemented in various forms. Often, a single level shifting circuit is implemented using a series of circuit stages, including a multiplexer, a level shifter (e.g., using switching elements such as p-type metal-oxide-semiconductor (PMOS) and / or n-type metal-oxide-semiconductor (NMOS)), and a latch operating between different voltage domains. For example, the multiplexer selects an input signal, the level shifter adjusts the voltage level of the selected input signal to match the required operating voltage domain, and then the latch stabilizes and maintains the adjusted signal before providing the output signal, ensuring synchronization. In some cases, a large number of circuit stages (four or more) can cause unwanted delays due to factors such as signal transition time. A significant number of circuit stages can also increase power consumption and cause signal degradation. Some circuit levels may further introduce synchronization complexity into the circuit, making it difficult to align signals between different clock domains. Implementing multi-stage level shifters may also require a large amount of circuit area.

[0009] To address these specific and / or other issues, in the particular paradigm described herein, the system and method integrate multiplexers, level shifters, and latches into a single, unified structure, reducing the number of circuit stages to fewer than four. This optimization can improve efficiency, increasing operating speed by up to 35% in some cases, while also reducing power consumption, enhancing signal quality, and improving synchronization.

[0010] Figure 1A is a schematic unit diagram of an exemplary device 100A according to various embodiments of the present disclosure. As shown in Figure 1A, the exemplary device 100A includes a first stage 110 and a second stage 120. The first stage 110 operates in the voltage domains VDD and VDDM. For example, the voltage domain VDD = 0.6 Ford (V) and the voltage domain VDDM = 1.0 V. In this exemplary embodiment, the first stage 110 receives a complex number of input signals (e.g., input signals INPUT_A and INPUT_B), selects one of the input signals INPUT_A and INPUT_B, and shifts the selected input signal INPUT_A or INPUT_B, for example, from the voltage domain VDD to the voltage domain VDDM. The second stage 120 operates in the voltage domain VDDM and generates an output signal LS_OUT in the voltage domain VDDM.

[0011] In the above description, because device 100A includes fewer than four circuit stages, device 100A operates relatively faster. Reducing the number of circuit stages minimizes transmission delay, making device 100A suitable for high-speed applications.

[0012] Figure 1B is a schematic unit diagram of an exemplary device 100B according to various embodiments of the present disclosure. As shown in Figure 1B, the exemplary device 100B includes a first stage 130, a second stage 140, and a third stage 150. The first stage 130 operates in voltage domains VDD and VDDM. For example, voltage domain VDD = 0.6V and voltage domain VDDM = 1.0V. In this exemplary embodiment, the first stage 130 receives an input signal INPUT and shifts the input signal INPUT, for example, from voltage domain VDD to voltage domain VDDM. In a particular embodiment, the second stage 140 and the third stage 150 maintain and generate an output signal LATCH_OUT in voltage domain VDDM. In this particular embodiment, at least one of the second stage 140 and the third stage 150 operates between voltage domains VDDM and VSS and receives one or more clock signals, causing latching.

[0013] In the above description, because device 100B includes fewer than four circuit stages, its operating speed is relatively fast. Reducing the number of circuit stages minimizes transmission delay, making device 100B suitable for high-speed applications. For example, FIG1C is a schematic timing diagram illustrating a relationship between the input signal INPUT and the output signal LATCH_OUT according to various embodiments of the present disclosure. As shown in FIG1C, corresponding to the input signal INPUT, the transition state of the output signal LATCH_OUT of the present disclosure occurs earlier than that of the prior art output signal LATCH_OUT'.

[0014] Figure 2 is a schematic circuit diagram of another exemplary device 200 according to various embodiments of the present disclosure. As shown in Figure 2, the exemplary device 200 (e.g., device 100A) receives a first input signal INPUT_A and a second input signal INPUT_B. Corresponding to complementary selection signals SEL_A and SEL_B, it selects one of the first input signal INPUT_A and the second input signal INPUT_B, shifts the selected first input signal INPUT_A to the second input signal INPUT_B from the voltage domain VDD to the voltage domain VDDM, and generates an output signal LS_OUT in the voltage domain VDDM. In this exemplary embodiment, device 200 includes a first stage 210 and a second stage 220. The first stage 210 includes a first device circuit 230 and a second device circuit 240, each operating in a corresponding voltage domain (voltage domain VDD, voltage domain VDDM). For example, the first device circuit 230 operates between voltage domains VDD and VSS, and includes a pair of inverters (inverter 250 and inverter 260), a pair of PMOS transistors (PMOS transistor P1 and PMOS transistor P2), and a pair of NMOS transistors (NMOS transistor N1 and NMOS transistor N2). Inverter 250 receives the input signal INPUT_A at its input terminal. Transistors P1 and N1 connect inverter 250 to the corresponding voltage domains (voltage domain VDD and voltage domain VSS). PMOS transistor P1 has a gate terminal that receives the selection signal SEL_B, while the gate terminal of NMOS transistor N1 receives the selection signal SEL_A.

[0015] Similarly, inverter 260 has an input terminal that receives the input signal INPUT_B, and an output terminal that is connected to the output terminal of inverter 250. Transistors P2 and N2 connect inverter 260 to the corresponding voltage domains (voltage domain VDD, voltage domain VSS). PMOS transistor P2 has a gate terminal that receives the selection signal SEL_A, while the gate terminal of NMOS transistor N2 receives the selection signal SEL_B.

[0016] The second device circuit 240 operates between the voltage domain VDDM and the voltage domain VSS. The second device circuit includes a pair of inverters (inverter 270 and inverter 280), two pairs of PMOS transistors (PMOS transistors P3 to PMOS transistor P6), and a pair of NMOS transistors (NMOS transistors N3 and NMOS transistor N4). Inverter 270 receives the input signal INPUT_A at its input terminal. PMOS transistors P3 and PMOS transistor P4 are connected in series between the voltage domain VDDM and inverter 270. PMOS transistor P4 is connected between PMOS transistor P3 and inverter 270, and PMOS transistor P4 has a gate terminal that receives the selection signal SEL1_B. NMOS transistor N3 connects inverter 270 to the voltage domain VSS, and NMOS transistor N3 has a gate terminal that receives the selection signal SEL1_A.

[0017] Similarly, inverter 280 has an input terminal that receives the input signal INPUT_B, and an output terminal that is connected to the output terminal of inverter 270. PMOS transistors P5 and PMOS transistor P6 are connected in series between the voltage domain VDDM and inverter 280. PMOS transistor P5 is connected between the voltage domain VDDM and PMOS transistor P6, and PMOS transistor P5 has a gate terminal that is connected to the gate terminal of PMOS transistor P3. PMOS transistor P6 is connected between PMOS transistor P5 and inverter 280, and PMOS transistor P6 has a gate terminal that receives the selection signal SEL1_A. NMOS transistor N4 connects inverter 280 to the voltage domain VSS, and NMOS transistor N4 has a gate terminal that receives the selection signal SEL1_B.

[0018] The second stage 220 operates between the voltage domains VDDM and VSS, and includes an inverter 290 and a PMOS transistor P7. Inverter 290 has an input terminal connected to the output terminals of inverters 250 and 260, and an output terminal connected to the gate terminals of PMOS transistors P3 and P5. PMOS transistor P7 connects inverter 290 to the voltage domain VDDM, and has a gate terminal connected to the output terminals of inverters 270 and 280.

[0019] In an exemplary operation, device circuit 230 receives a first input signal INPUT_A and a second input signal INPUT_B, and selects one of the first input signal INPUT_A and the second input signal INPUT_B in response to complementary selection signals SEL_A and SEL_B. Then, device circuit 230 generates a first intermediate output signal INT_OUT1 based on the selected first input signal INPUT_A and the second input signal INPUT_B. For example, with voltage domain VDD=0.6V, voltage domain VDDM=1.0V, voltage domain VSS=0V, first input signal INPUT_A=0.6V, and second input signal INPUT_B=0V, when selection signal SEL_A is at a high level (i.e., selection signal SEL_B is at a low level), transistors P1 and N1 are turned on, activating inverter 250. Therefore, the first input signal INPUT_A (0.6V or voltage domain VDD) is selected, generating the first intermediate output signal INT_OUT1 in the voltage domain VSS. At this time, transistors P2 and N2 remain off, and inverter 260 is not activated, ensuring that the second input signal INPUT_B is not selected.

[0020] Subsequently, device circuit 240 receives the same input signals (first input signal INPUT_A, second input signal INPUT_B) and selects one of the first input signal INPUT_A and the second input signal INPUT_B in response to complementary selection signals (selection signal SEL1_A, selection signal SEL1_B). Then, device circuit 240 generates a second intermediate output signal INT_OUT2 based on the selected first input signal INPUT_A and second input signal INPUT_B. For example, when selection signal SEL1_A is at a high level (i.e., selection signal SEL1_B is at a low level), transistors P4 and N3 are turned on, and assuming PMOS transistor P3 is also turned on, inverter 270 is activated. Therefore, the first input signal INPUT_A is selected, generating the second intermediate output signal INT_OUT2 in the voltage domain VSS. At this time, transistors P6 and N4 remain off, inverter 280 is not activated, ensuring that the second input signal INPUT_B is not selected.

[0021] Next, the second stage 220 receives the intermediate output signals (first intermediate output signal INT_OUT1 and second intermediate output signal INT_OUT2) and generates the output signal LS_OUT in the voltage domain VDDM, shifting the first input signal INPUT_A from the voltage domain VDD to the voltage domain VDDM. For example, because the intermediate output signals (first intermediate output signal INT_OUT1 and second intermediate output signal INT_OUT2) are in the voltage domain VSS, the PMOS transistor P7 is turned on and the inverter 290 is activated, generating the output signal LS_OUT in the voltage domain VDDM.

[0022] Figure 3 is a schematic circuit diagram of another exemplary device 300 according to various embodiments of the present disclosure. As shown in Figure 3, the exemplary device 300 (e.g., device 100A) receives a first input signal INPUT_A and a second input signal INPUT_B. Corresponding to complementary selection signals SEL_A and SEL_B, it selects one of the first input signal INPUT_A and the second input signal INPUT_B, shifts the selected first input signal INPUT_A to the second input signal INPUT_B from the voltage domain VDD to the voltage domain VDDM, and generates an output signal LS_OUT in the voltage domain VDDM. In this exemplary embodiment, device 300 includes a first stage 310 and a second stage 320. The first stage 310 includes a first device circuit 330 and a second device circuit 340, each operating in a corresponding voltage domain (voltage domain VDD, voltage domain VDDM).

[0023] For example, the first device circuit 330 includes a pair of inverters (inverter 350 and inverter 360) and a pair of transmission gates (transmission gate 370 and transmission gate 380). Inverters 350 and 360 operate between voltage domains VDD and VSS, and each receives a corresponding input signal (a first input signal INPUT_A and a second input signal INPUT_B) at its input terminal. Transmission gate 370 has one input terminal connected to the output terminal of inverter 350, and an n-type terminal and a p-type terminal, respectively, receiving a corresponding selection signal (selection signal SEL_A and selection signal SEL_B). Similarly, inverter 360 operates between voltage domains VDD and VSS, and receives the second input signal INPUT_B at its input terminal. The transmission gate 380 has an input terminal connected to the output terminal of the inverter 360, an output terminal connected to the output terminal of the transmission gate 370, and an n-type terminal and a p-type terminal, respectively, for receiving a corresponding selection signal (selection signal SEL_B, selection signal SEL_A).

[0024] The second device circuit 340 includes two pairs of PMOS transistors (PMOS transistors P1 to PMOS transistor P4) and two pairs of NMOS transistors (NMOS transistors N1 to PMOS transistor N4). Transistors P1, P2, N1, and N2 are connected in series between voltage domain VDDM and voltage domain VSS. PMOS transistor P1 is connected between voltage domain VDDM and PMOS transistor P2. PMOS transistor P2 is connected between transistors P1 and N1, and receives the selection signal SEL1_B at its gate. NMOS transistor N1 is connected between transistors P2 and N2, and receives the input signal INPUT_A at its gate. NMOS transistor N2 is connected between NMOS transistor N1 and voltage domain VSS, and receives the selection signal SEL1_A at its gate.

[0025] Transistors P3, P4, N3, and N4 are connected in series between voltage domains VDDM and VSS. PMOS transistor P3 is connected between voltage domain VDDM and PMOS transistor P4, and has a gate terminal connected to the gate terminal of PMOS transistor P1. PMOS transistor P4 is connected between transistors P3 and N3, and receives the selection signal SEL1_A at its gate terminal. NMOS transistor N3 is connected between transistors P4 and N4, and receives the input signal INPUT_B at its gate terminal. The junction of transistors P4 and N3 is connected to the junction of transistors P2 and N1. NMOS transistor N4 is connected between NMOS transistor N3 and voltage domain VSS, and receives the selection signal SEL1_B at its gate terminal.

[0026] The second stage 320 operates between voltage domains VDDM and VSS, and includes a PMOS transistor P5 and an NMOS transistor N5. The PMOS transistor P5 is connected between voltage domain VDDM and NMOS transistor N5, and has a gate terminal connected to the junction of transistors P2 and N1, and the junction of transistors P4 and N3. The NMOS transistor N5 is connected between voltage domain VSS and PMOS transistor P5, and has a gate terminal connected to the output of transmission gate 370 and the output of transmission gate 380.

[0027] In an exemplary operation, device circuit 330 receives a first input signal INPUT_A and a second input signal INPUT_B, and selects one of the first input signal INPUT_A and the second input signal INPUT_B in response to complementary selection signals SEL_A and SEL_B. Then, device circuit 330 generates a first intermediate output signal INT_OUT1 based on the selected first input signal INPUT_A and the second input signal INPUT_B. For example, with voltage domain VDD=0.6V, voltage domain VDDM=1.0V, voltage domain VSS=0V, first input signal INPUT_A=0.6V, and second input signal INPUT_B=0V, when selection signal SEL_A is at a high level (i.e., selection signal SEL_B is at a low level), transmission gate 370 is activated, allowing the output of inverter 350 (i.e., 0V or voltage domain VSS) to pass. Therefore, the first input signal INPUT_A (0.6V or voltage domain VDD) is selected, generating the first intermediate output signal INT_OUT1 in the voltage domain VSS. At this time, the transmission gate 380 remains closed, blocking the output of the inverter 360, ensuring that the second input signal INPUT_B is not selected.

[0028] Subsequently, device circuit 340 receives the same input signals (first input signal INPUT_A, second input signal INPUT_B) and selects one of the first input signal INPUT_A and the second input signal INPUT_B in response to complementary selection signals (selection signal SEL1_A, selection signal SEL1_B). Then, device circuit 340 generates a second intermediate output signal INT_OUT2 based on the selected first input signal INPUT_A and second input signal INPUT_B. For example, when selection signal SEL1_A is at a high level (i.e., selection signal SEL1_B is at a low level), transistors N1 and N2 are turned on, pulling down the junction of transistors P2 and N1 to the voltage domain VSS. Therefore, the first input signal INPUT_A is selected, generating the second intermediate output signal INT_OUT2 in the voltage domain VSS.

[0029] Next, the second stage 320 receives the intermediate output signals (first intermediate output signal INT_OUT1 and second intermediate output signal INT_OUT2) and generates an output signal LS_OUT in the voltage domain VDDM. The input signal INPUT_A is shifted from the voltage domain VDD to the voltage domain VDDM. For example, since the intermediate output signals (first intermediate output signal INT_OUT1 and second intermediate output signal INT_OUT2) are in the voltage domain VSS, the PMOS transistor P5 is turned on, while the NMOS transistor remains off. The junction of transistor P5 and transistor N5 is pulled up to the voltage domain VDDM, and an output signal LS_OUT is generated in the voltage domain VDDM.

[0030] Figure 4 is a schematic circuit diagram of another exemplary device 400 according to various embodiments of the present disclosure. As shown in Figure 4, the exemplary device 400 (e.g., device 100B) receives an input signal INPUT, shifts the input signal INPUT from the voltage domain VDD to the voltage domain VDDM, maintains and generates an output signal LATH_OUT in the voltage domain VDDM. In this exemplary embodiment, the device circuit (i.e., device 400) includes a first stage 410, a second stage 420, and a third stage 430. The first stage 410 includes a first device circuit 410a and a second device circuit 410b, each operating in a corresponding voltage domain (voltage domain VDD, voltage domain VDDM).

[0031] For example, the first device circuit 410a includes an inverter 440, operating between voltage domains VDD and VSS, and receiving an input signal INPUT at its input terminal. The second device circuit 410b includes a pair of inverters (inverter 450 and inverter 460) and a pair of PMOS transistors (PMOS transistor P1 and PMOS transistor P2). Inverter 450 is connected to voltage domain VSS and has an input terminal connected to the input terminal of inverter 440. Inverter 460 is connected to voltage domain VSS and has an input terminal connected to the output terminal of inverter 440. PMOS transistors P1 and PMOS transistor P2 connect the corresponding inverters 450 and 460 to voltage domain VDDDM, respectively, and each has a gate terminal connected to the output terminal of the corresponding inverter 450 and inverter 460.

[0032] The second stage 420 operates between the voltage domains VDDM and VSS, and includes an inverter 470, a pair of PMOS transistors (transistor P3 and transistor P4), and an NMOS transistor N1. Inverter 470 has an input terminal connected to the output terminal of inverter 440. PMOS transistors P3 and P4 are connected in series between the voltage domain VDDM and inverter 470. PMOS transistor P3 is connected between the voltage domain VDDM and PMOS transistor P4, and receives a clock signal CLK at its gate. PMOS transistor P4 is connected between PMOS transistor P3 and inverter 470, and has a gate terminal connected to the output terminal of inverter 450. NMOS transistor N1 connects inverter 470 to the VSS voltage domain and receives the inverted version of the clock signal CLK at its gate terminal.

[0033] The third stage 430 includes an inverter 480, a pair of PMOS transistors (PMOS transistor P4 and PMOS transistor P5), and a pair of NMOS transistors (NMOS transistor N2 and NMOS transistor N3). Inverter 480 operates between voltage domains VDDM and VSS and has an input terminal connected to the output terminal of inverter 470, generating an output signal LATCH_OUT at its output terminal. Transistors P5, P6, N2, and N3 are connected in series between voltage domains VDDM and VSS. PMOS transistor P5 is connected between voltage domain VDDM and PMOS transistor P6 and has a gate terminal connected to the output terminal of inverter 480. PMOS transistor P6 is connected between transistors P5 and N2 and receives the inverted version of the clock signal CLK at its gate terminal. Transistor N2 is connected between transistors P6 and N2 and receives the clock signal CLK at its gate terminal. The junctions of PMOS transistor P6 and NMOS transistor N2 are connected to the input terminal of inverter 480. NMOS transistor N3 is connected between NMOS transistor N2 and voltage domain VSS, and has one gate terminal connected to the output terminal of inverter 480.

[0034] In a demonstration operation, with voltage domain VDD=0.8V, voltage domain VDDM=1.2V, voltage domain VSS=0V, and input signal INPUT=0V, device circuit 410a receives an input signal INPUT and then generates a first intermediate output signal INT_OUT1 in the voltage domain VDD. Subsequently, device circuit 410b receives the same input signal INPUT, assuming PMOS transistor P1 is turned on, inverter 450 is activated, and generates a second intermediate output signal INT_OUT2 in the voltage domain VDDM.

[0035] Next, the second stage 420 and the third stage 430 receive the first intermediate output signal INT_OUT1 and the second intermediate output signal INT_OUT2, respectively. Based on the clock signal CLK and the inverted clock signal CLKB, they maintain and generate the output signal LATCH_OUT in the voltage domain VDDM, and shift the input signal INPUT to the voltage domain VDDM. For example, when the clock signal CLK transitions from a high level to a low level (i.e., the inverted clock signal CLKB transitions from a low level to a high level), transistors P3 and N1 are turned on. Assuming that the PMOS transistor P4 is turned on, the inverter 470 is activated and generates a third intermediate output signal INT_OUT3 in the voltage domain VSS.

[0036] Subsequently, inverter 480 receives the third intermediate output signal INT_OUT3 and generates an output signal LATCH_OUT in the voltage domain VDDM. For example, when the pulse signal CLK transitions from a low level to a high level, NMOS transistors N2 and NMOS transistors N3 are turned on, pulling down the input of inverter 480 to the voltage domain VSS, thus strengthening the output signal LATCH_OUT in the voltage domain VDDM. At this time, PMOS transistors P5 and P6 remain off, ensuring that the output signal LATCH_OUT remains stable in the voltage domain VDDM.

[0037] Figure 5 is a schematic circuit diagram of another exemplary device 500 according to various embodiments of the present disclosure. As shown in Figure 5, the exemplary device 500 (e.g., device 100B) receives an input signal INPUT, shifts the input signal INPUT from the voltage domain VDD to the voltage domain VDDM, maintains and generates an output signal LATH_OUT in the voltage domain VDDM. In this exemplary embodiment, the device circuit (i.e., device 500) includes a first stage 510, a second stage 520, and a third stage 530. The first stage 510 includes a first device circuit 540 and a second device circuit 550, each operating in a corresponding voltage domain (voltage domain VDD, voltage domain VDDM).

[0038] For example, the first device circuit 540 includes an inverter 560 operating between voltage domains VDD and VSS, and receiving an input signal INPUT at its input terminal. The second device circuit 550 includes a pair of PMOS transistors (PMOS transistor P1 and PMOS transistor P2) and a pair of NMOS transistors (NMOS transistor N1 and NMOS transistor N2). Transistors P1 and N1 are connected in series between voltage domains VDD and VSS. NMOS transistor N1 receives the input signal INPUT at its gate terminal. Transistors P2 and N2 are connected in series between voltage domains VDD and VSS. PMOS transistor P1 has a gate terminal connected to the junction of transistors P2 and N2. PMOS transistor P2 has a gate terminal connected to the junction of transistors P1 and N1. The NMOS transistor has a gate terminal connected to the output terminal of inverter 560.

[0039] The second stage 520 includes a pair of PMOS transistors (PMOS transistor P3 and PMOS transistor P4) and a pair of NMOS transistors (NMOS transistor N3 and NMOS transistor N4). Transistors P3, P4, N3, and N4 are connected in series between voltage domain VDDM and voltage domain VSS. PMOS transistor P3 is connected between voltage domain VDDM and PMOS transistor P4, and receives a clock signal CLK at its gate. PMOS transistor P4 is connected between transistors P3 and N3, and has a gate connected to the junction of transistors P1 and N1. NMOS transistor N3 is connected between transistors P4 and N4, and has a gate connected to the output of inverter 560. NMOS transistor N4 is connected between NMOS transistor N3 and voltage domain VSS, and receives an inverted version of the clock signal CLK at its gate.

[0040] The third stage 530 includes an inverter 570, a pair of PMOS transistors (PMOS transistor P5 and PMOS transistor P6), and a pair of NMOS transistors (NMOS transistor N5 and NMOS transistor N6). Inverter 570 operates between voltage domains VDDM and VSS and has an input terminal connected to the junction of transistors P4 and N3, generating an output signal LATCH_OUT at its output terminal. Transistors P5, P6, N5, and N6 are connected in series between voltage domains VDDM and VSS. PMOS transistor P5 is connected between voltage domain VDDM and PMOS transistor P6 and has a gate terminal connected to the output terminal of inverter 570. PMOS transistor P6 is connected between transistors P5 and N5 and receives the inverted version of the clock signal CLK at its gate terminal. NMOS transistor N5 is connected between transistors P6 and N6 and receives the clock signal CLK at its gate terminal. The junctions of transistors P6 and N5 are connected to the input of inverter 570. NMOS transistor N6 is connected between NMOS transistor N5 and voltage domain VSS, and has a gate terminal connected to the output of inverter 570.

[0041] In an exemplary operation, with voltage domain VDD=0.8V, voltage domain VDDM=1.2V, voltage domain VSS=0V, and input signal INPUT=0V, device circuit 540 receives the input signal INPUT and then generates a first intermediate output signal INT_OUT1 in the voltage domain VDD. Next, device circuit 550 receives the output signal INPUT, assuming PMOS transistor P1 is turned on, and the junction of transistor P1 and transistor N1 is pulled up to VDDM, generating a second intermediate output signal INT_OUT2 in the voltage domain VDDM.

[0042] Next, the second stage 520 and the third stage 530 receive the first intermediate output signal INT_OUT1 and the second intermediate output signal INT_OUT2, respectively, and maintain and generate the output signal LATCH_OUT in the voltage domain VDDM according to the clock signal CLK and the inverted clock signal CLKB, shifting the input signal INPUT to the voltage domain VDDM. For example, when the clock signal CLK transitions from a high level to a low level (i.e., the inverted clock signal CLKB transitions from a low level to a high level), NMOS transistors N3 and NMOS transistor N4 are turned on. Assuming that PMOS transistor P4 remains off, the junction of transistors P4 and N3 is pulled down to the voltage domain VSS, generating an intermediate output signal INT_OUT3 in the voltage domain VSS.

[0043] Subsequently, inverter 570 receives the intermediate output signal INT_OUT3 and generates an output signal LATCH_OUT in the voltage domain VDDM. For example, when the pulse signal CLK transitions from a low level to a high level, NMOS transistors N5 and N6 are turned on, pulling down the input of inverter 570 to the voltage domain VSS, thus strengthening the output signal LATCH_OUT in the voltage domain VDDM. At this time, PMOS transistors P5 and P6 remain off, ensuring that the output signal LATCH_OUT remains stable in the voltage domain VDDM.

[0044] Figure 6 is a schematic circuit diagram of another exemplary device 600 according to various embodiments of the present disclosure. As shown in Figure 6, the exemplary device 600 (e.g., device 100B) receives a first input signal INPUT_A and a second output signal INPUT_B. Corresponding to complementary selection signals SEL_A and SEL_B, it selects one of the first input signal INPUT_A and the second output signal INPUT_B, shifts the selected first input signal INPUT_A and the second output signal INPUT_B from the voltage domain VDD to the voltage domain VDDM, and maintains and generates an output signal LATH_OUT in the voltage domain VDDM. In this exemplary embodiment, the device circuit (i.e., device 600) includes a first stage 610, a second stage 620, and a third stage 630. The first stage 610 includes a first device circuit 640 and a second device circuit 650, each operating in a corresponding voltage domain (voltage domain VDD, voltage domain VDDM).

[0045] For example, the first device circuit 640 operates between the voltage domain VDD and the voltage domain VSS, and the first device circuit 640 includes a pair of inverters (inverter 640a and inverter 640b), a pair of PMOS transistors (PMOS transistor P1 and PMOS transistor P2), and a pair of NMOS transistors (NMOS transistor N1 and NMOS transistor N2). Inverter 640a and inverter 640b receive an output signal (first input signal INPUT_A and second output signal INPUT_B) at their input terminals, respectively. PMOS transistor P1 connects inverter 640a to the voltage domain VDD and receives a selection signal SEL_B at its gate terminal. NMOS transistor N1 connects inverter 640a to the voltage domain VSS and receives a selection signal SEL_A at its gate terminal. PMOS transistor P2 connects inverter 640b to the voltage domain VDD and receives a selection signal SEL_A at its gate terminal. The NMOS transistor N2 connects the inverter 640b to the voltage domain VSS and receives the selection signal SEL_B at the gate terminal.

[0046] Next, the second stage 620 and the third stage 630 receive the first intermediate output signal INT_OUT1 and the second intermediate output signal INT_OUT2, respectively, and lock and generate the output signal LATCH_OUT in the voltage domain VDDM according to the clock signal CLK and the inverted clock signal CLKB, shifting the input signal INPUT to the voltage domain VDDM. The second device circuit 650 operates between the voltage domain VDDM and the voltage domain VSS, and the second device circuit 650 includes complex inverters (inverters 650a to 650c), complex PMOS transistors (PMOS transistors P3 to PMOS transistors P7), and complex NMOS transistors (NMOS transistors N3 and NMOS transistors N4). Inverters 650a and 650b have input terminals, receiving the input signal INPUT_A and the input signal INPUT_B, respectively. PMOS transistors P3 and PMOS transistors P4 are connected in series between the voltage domain VDDM and inverter 650a. PMOS transistor P3 is connected between the VDDM voltage domain and PMOS transistor P4. PMOS transistor P4 is connected between PMOS transistor P3 and inverter 650a, and receives the selection signal SEL1_B at its gate terminal.

[0047] PMOS transistors P3 and P4 are connected in series between the voltage domain VDDM and inverter 650a. PMOS transistor P3 is connected between the VDDM voltage domain and PMOS transistor P4. PMOS transistor P4 is connected between PMOS transistor P3 and inverter 650a, and receives the selection signal SEL1_B at its gate. NMOS transistor N3 connects inverter 650a to the voltage domain VSS, and receives the selection signal SEL1_A at its gate.

[0048] Similarly, PMOS transistors P5 and P6 are connected in series between the voltage domain VDDM and inverter 650b. PMOS transistor P5 is connected between the VDDM voltage domain and PMOS transistor P6, and has a gate terminal connected to the gate terminal of PMOS transistor P3. PMOS transistor P6 is connected between PMOS transistor P5 and inverter 650b, and receives the selection signal SEL1_A at its gate terminal. NMOS transistor N4 connects inverter 650b to the voltage domain VSS, and receives the selection signal SEL1_B at its gate terminal.

[0049] Inverter 650c is connected to the voltage domain VSS and has an input terminal connected to the output terminals of inverters 640a and 640b, and an output terminal connected to the gate terminals of PMOS transistors P3 and PMOS transistor P5. PMOS transistor P7 connects inverter 650c to the voltage domain VDDM and has a gate terminal connected to the output terminals of inverters 650a and 650b.

[0050] The second stage 620 operates between the voltage domains VDDM and VSS, and includes an inverter 660, a first PMOS transistor P8, a second PMOS transistor P9, and an NMOS transistor N5. Inverter 660 has an input terminal connected to the output terminals of inverters 640a and 640b. PMOS transistors P8 and P9 are connected in series between the voltage domain VDDM and inverter 660. PMOS transistor P8 is connected between the voltage domain VDDM and PMOS transistor P9, and receives the clock signal CLK at its gate. PMOS transistor P9 is connected between PMOS transistor P8 and inverter 660, and has a gate terminal connected to the output terminals of inverters 650a and 650b. NMOS transistor N5 connects inverter 660 to the VSS voltage domain and receives the inverted version of the clock signal CLK at its gate.

[0051] The third stage 630 operates between the voltage domains VDDM and VSS, and includes an inverter 670, a first PMOS transistor P10, a second PMOS transistor P11, a first NMOS transistor N6, and a second NMOS transistor N7. Inverter 670 has an input terminal connected to the output terminal of inverter 660, and generates an output signal LATCH_OUT at its output terminal. Transistors P10, P11, N6, and N7 are connected in series between the voltage domains VDDM and VSS. PMOS transistor P10 is connected between voltage domain VDDM and PMOS transistor P11, and has a gate terminal connected to the output terminal of inverter 670. PMOS transistor P11 is connected between transistors P10 and N6, and receives an inverted clock signal CLKB at its gate terminal. The junctions of transistors P11 and N6 are connected to the input terminal of inverter 670. NMOS transistor N6 is connected between transistors P11 and N7, and receives the clock signal CLK at its gate. NMOS transistor N7 is connected between NMOS transistor N6 and the voltage domain VSS, and has a gate connected to the output of inverter 670.

[0052] In an exemplary operation, device circuit 640 receives a first input signal INPUT_A and a second output signal INPUT_B, and selects one of the first input signal INPUT_A and the second output signal INPUT_B in response to complementary selection signals SEL_A and SEL_B. Then, device circuit 640 generates a first intermediate output signal INT_OUT1 based on the selected first input signal INPUT_A and second output signal INPUT_B. For example, with voltage domain VDD=0.8V, voltage domain VDDM=1.2V, first input signal INPUT_A=0V, and second input signal INPUT_B=0.8V, when selection signal SEL_A is at a high level (i.e., selection signal SEL_B is at a low level), transistors P1 and N1 are turned on, activating inverter 640a. Therefore, the input signal INPUT_A (0V or voltage domain VSS) is selected, generating the first intermediate output signal INT_OUT1 in the voltage domain VDD. At this time, transistors P2 and N2 remain off, and inverter 640b is not activated, ensuring that the second input signal INPUT_B is not selected.

[0053] Subsequently, device circuit 650 receives the same input signals (first input signal INPUT_A, second input signal INPUT_B) and selects one of the first input signal INPUT_A and the second input signal INPUT_B in response to complementary selection signals SEL1_A and SEL1_B. Next, device circuit 650 generates a second intermediate output signal INT_OUT2 based on the selected first input signal INPUT_A and the second input signal INPUT_B. For example, when selection signal SEL1_A is at a high level (i.e., selection signal SEL1_B is at a low level), transistors P4 and N3 are turned on. Assuming PMOS transistor P3 is turned on, inverter 650a is activated. Therefore, INPUT_A is selected, generating the second intermediate output signal INT_OUT2 in the voltage domain VDDM. At this time, transistors P6 and N4 remain off, inverter 650b is not activated, ensuring that INPUT_B is not selected.

[0054] Next, the second stage 620 and the third stage 630 receive the first intermediate output signal INT_OUT1 and the second intermediate output signal INT_OUT2, respectively. Based on the clock signal CLK and the inverted clock signal CLKB, they lock and generate the output signal LATCH_OUT in the voltage domain VDDM, and shift the output signal INPUT to the VDDM voltage domain. For example, when the clock signal CLK transitions from a high level to a low level (i.e., the inverted clock signal CLKB transitions from a low level to a high level), transistors P8 and N5 are turned on. Assuming that the PMOS transistor P9 is turned on, the inverter 660 is activated and generates the third intermediate output signal INT_OUT3 in the voltage domain VSS.

[0055] Subsequently, inverter 670 receives the third intermediate output signal INT_OUT3 and generates the output signal LATCH_OUT in the voltage domain VDDM. For example, when the pulse signal CLK transitions from a low level to a high level, NMOS transistors N6 and N7 are turned on, pulling down the input of inverter 670 to the voltage domain VSS, thus strengthening the output signal LATCH_OUT in the voltage domain VDDM. At this time, PMOS transistors P10 and P11 remain off, ensuring that the output signal LATCH_OUT remains stable in the voltage domain VDDM.

[0056] Figure 7 is a schematic circuit diagram of another exemplary device 700 according to various embodiments of the present disclosure. As shown in Figure 7, the exemplary device 700 (e.g., device 100B) receives a first input signal INPUT_A and a second output signal INPUT_B, and selects one of the first input signal INPUT_A and the second output signal INPUT_B in response to complementary selection signals SEL_A and SEL_B. It then shifts the selected first input signal INPUT_A and the second output signal INPUT_B from the voltage domain VDD to the voltage domain VDDM, maintaining and generating an output signal LATH_OUT in the voltage domain VDDM. In this exemplary embodiment, the device circuit (i.e., device 700) includes a first stage 710, a second stage 720, and a third stage 730. The first stage 710 includes a first device circuit 740 and a second device circuit 750, each operating in a corresponding voltage domain (voltage domain VDD, voltage domain VDDM).

[0057] For example, the first device circuit 740 includes a pair of inverters (inverter 740a and inverter 740b) and a pair of transmission gates (transmission gate 740c and transmission gate 740d). Inverters 740a and 740b operate in the voltage domain between VDD and VSS, and receive input signals INPUT_A and INPUT_B at their respective input terminals. Transmission gate 740c has an input terminal connected to the output terminal of inverter 740a, and n-type and p-type terminals, each receiving selection signals SEL_A and SEL_B respectively. Transmission gate 740d has an input terminal connected to the output terminal of inverter 740b, an output terminal connected to the output terminal of transmission gate 740c, and n-type and p-type terminals, each receiving selection signals SEL_B and SEL_A respectively.

[0058] The second device circuit 750 includes a complex number of PMOS transistors (PMOS transistors P1 to PMOS transistors P5) and a complex number of NMOS transistors (NMOS transistors N1 to NMOS transistors N5). Transistors P1, P2, N1, and N2 are connected in series between voltage domain VDDM and voltage domain VSS. PMOS transistor P1 is connected between voltage domain VDDM and PMOS transistor P2. PMOS transistor P2 is connected between transistors P1 and N1, and receives the selection signal SEL1_B at its gate. NMOS transistor N1 is connected between transistors P2 and N2, and receives the input signal INPUT_A at its gate. NMOS transistor N2 is connected between NMOS transistor N1 and voltage domain VSS, and receives the selection signal SEL1_A at its gate.

[0059] Transistors P3, P4, N3, and N4 are connected in series between voltage domains VDDM and VSS. PMOS transistor P3 is connected between voltage domain VDDM and PMOS transistor P4, and has a gate terminal connected to the gate terminal of PMOS transistor P1. PMOS transistor P4 is connected between transistors P3 and N3, and receives the selection signal SEL1_A at its gate terminal. NMOS transistor N3 is connected between transistors P4 and N4, and receives the input signal INPUT_B at its gate terminal. The junctions of transistors P4 and N3 are connected to the junctions of transistors P2 and N1. NMOS transistor N4 is connected between NMOS transistor N3 and voltage domain VSS, and receives the selection signal SEL1_B at its gate terminal.

[0060] Transistors P5 and N5 are connected in series between voltage domain VDDM and voltage domain VSS. The junctions of transistors P5 and N5 are connected to the gate terminals of PMOS transistor P1 and PMOS transistor P3. PMOS transistor P5 is connected between voltage domain VDDM and NMOS transistor N5, and has a gate terminal connected to the junctions of transistors P2 and N1 and transistors P4 and N3. NMOS transistor N5 is connected between PMOS transistor P5 and voltage domain VSS, and has a gate terminal connected to the output terminals of transmission gate 740c and transmission gate 740d.

[0061] The second stage 720 operates between the voltage domain VDDM and the voltage domain VSS, and includes a pair of PMOS transistors (PMOS transistor P6 and PMOS transistor P7) and a pair of NMOS transistors (NMOS transistor N6 and NMOS transistor N7). PMOS transistor P6 is connected between the voltage domain VDDM and PMOS transistor P7, and receives the clock signal CLK at its gate. PMOS transistor P7 is connected between PMOS transistor P6 and NMOS transistor N6, and has a gate connected to the junction of transistors P2 and N1 and the junction of transistors P4 and N3. NMOS transistor N6 is connected between transistors P7 and N7, and has a gate connected to the output of transmission gate 740c and the output of transmission gate 740d. NMOS transistor N7 is connected between NMOS transistor N6 and the voltage domain VSS, and receives the inverted version of the clock signal CLK at its gate.

[0062] The third stage 730 includes an inverter 760, a pair of PMOS transistors (PMOS transistor P8 and PMOS transistor P9), and a pair of NMOS transistors (NMOS transistor N8 and NMOS transistor N9). The inverter 760 operates between voltage domains VDDM and VSS. Transistors P8, P9, N8, and N9 are connected in series between voltage domains VDDM and VSS. PMOS transistor P8 is connected between voltage domain VDDM and PMOS transistor P9 and has a gate terminal connected to the output of inverter 760. PMOS transistor P9 is connected between transistors P8 and N8 and receives the inverted clock signal CLKB at its gate terminal. The junctions of transistors P9 and N8 are connected to the input of inverter 760. NMOS transistor N8 is connected between transistors P9 and N8 and receives the clock signal CLK at its gate terminal. NMOS transistor N9 is connected between NMOS transistor N8 and voltage domain VSS, and has a gate terminal connected to the output of inverter 760.

[0063] In an exemplary operation, device circuit 740 receives a first input signal INPUT_A and a second output signal INPUT_B, and selects one of the first input signal INPUT_A and the second output signal INPUT_B in response to complementary selection signals SEL_A and SEL_B. Then, device circuit 740 generates a first intermediate output signal INT_OUT1 based on the selected first input signal INPUT_A and second output signal INPUT_B. For example, with voltage domain VDD=0.8V, voltage domain VDDM=1.2V, voltage domain VSS=0V, input signal INPUT_A=0V, and input signal INPUT_B=0.8V, when selection signal SEL_A is at a high level (i.e., selection signal SEL_B is at a low level), transmission gate 740c is activated, allowing the output of inverter 740a (i.e., voltage domain VDD or 0.8V) to pass. Therefore, the input signal INPUT_A (0V or voltage domain VSS) is selected, generating the first intermediate output signal INT_OUT1 in the voltage domain VDD. At this time, the transmission gate 740d remains closed, blocking the output of the inverter 740b, ensuring that the second input signal INPUT_B is not selected.

[0064] Subsequently, the device circuit 750 receives the same input signals (first input signal INPUT_A and second input signal INPUT_B) and selects one of the first input signal INPUT_A and the second input signal INPUT_B in response to the complementary selection signals SEL1_A and SEL1_B. Then, the device circuit 750 generates a second intermediate output signal INT_OUT2 based on the selected first input signal INPUT_A and second input signal INPUT_B. For example, when the selection signal SEL1_A is at a high level (i.e., the selection signal SEL1_B is at a low level), PMOS transistor P2 is turned on. Assuming PMOS transistor P1 is turned on, the junction of transistors P2 and N1 is pulled up to the VDDM voltage domain. Therefore, the first input signal INPUT_A is selected, generating the second intermediate output signal INT_OUT2 in the VDDM voltage domain.

[0065] Next, the second stage 720 and the third stage 730 receive the first intermediate output signal INT_OUT1 and the second intermediate output signal INT_OUT2, respectively, and maintain and generate the output signal LATCH_OUT in the VDDM voltage domain according to the clock signal CLK and the inverted clock signal CLKB, shifting the input signal INPUT_A to the VDDM voltage domain. For example, when the clock signal CLK transitions from a high level to a low level (i.e., the inverted clock signal CLKB transitions from a low level to a high level), transistors N6 and N7 are turned on. Assuming that the PMOS transistor P7 remains off, the junction of transistors P7 and N6 is pulled down to the voltage domain VSS, generating the third intermediate output signal INT_OUT3 in the voltage domain VSS.

[0066] Subsequently, inverter 760 receives the third intermediate output signal INT_OUT3 and generates the output signal LATCH_OUT in the voltage domain VDDM. For example, when the pulse signal CLK transitions from a low level to a high level, NMOS transistors N8 and N9 are turned on, pulling down the input of inverter 760 to the voltage domain VSS, thus strengthening the output signal LATCH_OUT in the voltage domain VDDM. At this time, PMOS transistors P8 and P9 remain off, ensuring that the output signal LATCH_OUT remains stable in the voltage domain VDDM.

[0067] Figure 8 is a flowchart of an exemplary method for shifting a signal from one voltage domain to another according to various embodiments of the present disclosure. For ease of understanding, exemplary method 800 will be described with reference to Figures 1A-1C and Figures 2-7. It should be understood that method 800 can be applied to structures other than those shown in Figures 1A-1C and Figures 2-7. Furthermore, it should be understood that additional operations may be provided before, during, or after method 800, and in alternative embodiments of method 800, some of the operations described below may be replaced or omitted.

[0068] In operation 810, the device receives a first input signal INPUT_A and a second input signal INPUT_B, and selects one of the first input signal INPUT_A and the second input signal INPUT_B in response to complementary selection signals SEL_A and SEL_B. For example, the selected first input signal INPUT_A and the second input signal INPUT_B are received (e.g., received in a voltage domain VDD). In operation 820, the device processes the selected first input signal INPUT_A and the second input signal INPUT_B, and generates a first intermediate output signal INT_OUT1 and a second intermediate output signal INT_OUT2. For example, the first intermediate output signal INT_OUT1 is in the voltage domain VDD, and the second intermediate output signal INT_OUT2 is in the voltage domain VSS. These intermediate output signals collectively prepare for the voltage domain transition of the selected first input signal INPUT_A and the second input signal INPUT_B.

[0069] In operation 830, the device receives a clock signal CLK and an inverted clock signal CLKB, and generates a third intermediate output signal INT_OUT3 based on the first intermediate output signal INT_OUT1, the second intermediate output signal INT_OUT2, the clock signal CLK, and the inverted clock signal CLKB. This signal acts as the control node in the level shifter, determining whether to drive the output to the voltage domain VDDM or the voltage domain VSS. For example, the third intermediate output signal INT_OUT3 in the voltage domain VSS initiates a pull-up path towards the voltage domain VDDM. Therefore, this operation can perform a voltage level shift, converting the voltage level from the voltage domain VDD to the voltage domain VDDM.

[0070] During operation 840, the device maintains and generates an output signal LATCH_OUT in the voltage domain VDDM, ensuring a stable output compatible with circuitry operating in the voltage domain VDDM.

[0071] In an alternative embodiment, the device includes a first stage, a second stage, and a third stage. The first stage receives an input signal INPUT (e.g., received in a voltage domain VDD) and generates a first intermediate output signal INT_OUT1 and a second intermediate output signal INT_OUT2. The second and third stages receive complementary clock signals (clock signal CLK and inverted clock signal CLKB), maintain, and generate an output signal LATCH_OUT in the voltage domain VDDM. For example, the second stage generates a third intermediate output signal INT_OUT3 (e.g., in the voltage domain VSS) based on the first intermediate output signal INT_OUT1, the second intermediate output signal INT_OUT2, the clock signal CLK, and the inverted clock signal CLKB. The third stage generates the output signal LATCH_OUT based on the third intermediate output signal INT_OUT3, the clock signal CLK, and the inverted clock signal CLKB.

[0072] In one embodiment, a device includes a first stage and a second stage. The first stage includes a first device circuit and a second device circuit. The first device circuit operates in a first voltage domain, receives a pair of input signals and a complementary first selection signal, selects one of the input signals in response to the first selection signal, and generates a first intermediate output signal based on the selected input signal. The second device circuit operates in a second voltage domain, receives the input signals and a complementary second selection signal, selects one of the input signals in response to the second selection signal, and generates a second intermediate output signal based on the selected input signal. The second stage operates in the second voltage domain, receives the first intermediate output signal and the second intermediate output signal, and generates an output signal.

[0073] In one embodiment, the first device circuit includes: a first inverter configured to receive one of the input signals; a second inverter configured to receive the other of the input signals, wherein the second inverter has an output terminal connected to one output terminal of the first inverter; and one or more switching elements configured to connect the first inverter and the second inverter to the first voltage domain in response to the first selection signal and the second selection signal.

[0074] In one embodiment, the first device circuit includes: a first inverter and a second inverter, each configured to receive a corresponding input signal; a first transmission gate configured to transmit an output signal of the first inverter in response to the first selection signals and the second selection signals; and a second transmission gate having an output terminal connected to an output terminal of the first transmission gate, and the second transmission gate configured to transmit an output signal of the second inverter in response to the first selection signals and the second selection signals.

[0075] In one embodiment, the second device circuit includes: a first inverter configured to receive one of the input signals; a second inverter configured to receive the other of the input signals, wherein the second inverter has an output terminal connected to one output terminal of the first inverter; and one or more switching elements configured to connect the first inverter and the second inverter to the second voltage domain in response to the first selection signal and the second selection signal.

[0076] In one embodiment, the second device circuit includes a switching module configured to connect the first intermediate output signal to the second voltage domain based on one of the selected input signals and in response to the first selection signal and the second selection signal.

[0077] In one embodiment, the second stage includes: an inverter configured to receive the first intermediate output signal and output an output signal according to the first intermediate output signal; and one or more switching elements configured to connect the inverter to the second voltage domain in response to the second intermediate output signal.

[0078] In one embodiment, the second stage includes one or more switching elements configured to connect the output signal in response to the first intermediate output signal and the second intermediate output signal.

[0079] In another embodiment, the device includes a first stage, a second stage, and a third stage. The first stage includes a first device circuit and a second device circuit. The first device circuit operates in a first voltage domain, receives an input signal in the first voltage domain, and generates a first intermediate output signal based on the input signal. The second device circuit operates in a second voltage domain, receives the input signal, and generates a second intermediate output signal based on the input signal. The second stage operates in the second voltage domain, receives the first intermediate output signal, the second intermediate output signal, and a complementary clock signal, and generates a third intermediate output signal based on the first intermediate output signal, the second intermediate output signal, and the clock signal. The third stage operates in the second voltage domain, receives the third intermediate output signal and the clock signal, and generates an output signal.

[0080] In one embodiment, the first device circuit includes an inverter configured to receive the input signal and output the first intermediate output signal.

[0081] In one embodiment, the second device circuit includes: a first inverter configured to receive the input signal; a second inverter configured to output the second intermediate output signal; and one or more switching elements configured to connect the first inverter or the second inverter to the second voltage domain in response to an output signal of the first inverter and an output signal of the second inverter.

[0082] In one embodiment, the second device circuit includes a switching element configured to connect the first intermediate output signal to the first voltage domain or the second voltage domain in response to the input signal and the first intermediate output signal.

[0083] In one embodiment, the second stage includes: an inverter configured to receive the first intermediate output signal; and one or more switching elements configured to connect the inverter to the second voltage domain in response to the second intermediate output signal and the clock signals.

[0084] In one embodiment, the second stage includes one or more switching elements configured to connect to the third intermediate output signal in response to the first intermediate output signal, the second intermediate output signal, and the clock signals.

[0085] In one embodiment, the third stage includes: an inverter having an input terminal configured to receive the third intermediate output signal and configured to generate the output signal at an output terminal; and one or more switching elements connected between the input terminal and the output terminal of the inverter, the switching elements being configured to connect the input terminal of the inverter to the first voltage domain in response to the output signal and the clock signals.

[0086] In another embodiment, a method for shifting a signal from one voltage domain to another includes: receiving a first input signal and a second input signal; selecting one of the first input signal and a second output signal in response to a complementary first selection signal and a complementary second selection signal; generating a first intermediate output signal and a second intermediate output signal based on the selected first input signal and the second input signal; generating a third intermediate output signal based on the first intermediate output signal, the second intermediate output signal and a complementary clock signal; and generating an output signal based on the third intermediate output signal and the clock signal.

[0087] In another embodiment, a method for shifting a signal from one voltage domain to another includes: receiving a first input signal and a second input signal; selecting one of the first input signal and the second input signal in response to a complementary first selection signal and a complementary second selection signal; generating a first intermediate output signal and a second intermediate output signal based on the selected first input signal and the second input signal; shifting the selected first input signal and the second input signal from the first voltage domain to the second voltage domain based on the first intermediate output signal, the second intermediate output signal and a complementary clock signal; and generating an output signal based on a third intermediate output signal corresponding to the second voltage domain.

[0088] In one embodiment, the method further includes: connecting an inverter to the first voltage domain in response to the first selection signals; and generating the first intermediate output signal by the inverter based on one of the first input signal and the second input signal.

[0089] In one embodiment, the method further includes: connecting an inverter to the second voltage domain in response to the second selection signals; and generating the second intermediate output signal from the inverter based on the first input signal and the second input signal.

[0090] In one embodiment, the method further includes: connecting an inverter to the second voltage domain in response to the second intermediate output signal; and generating the third intermediate output signal by the inverter based on the first intermediate output signal.

[0091] In one embodiment, the method further includes: connecting an inverter to the second voltage domain in response to the first intermediate output signal and the second intermediate output signal; and generating the third intermediate output signal by the inverter based on the first intermediate output signal.

[0092] In one embodiment, the method further includes generating the output signal by an inverter based on the third intermediate output signal.

[0093] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations to this disclosure without departing from its spirit and scope.

[0094] 100A, 100B, 200, 300, 400, 500, 600, 700: Devices 110, 130, 210, 310, 410, 510, 610, 710: Level 1 120, 140, 220, 320, 420, 520, 620, 720: Level 2 150, 430, 530, 630, 730: Level 3 230, 240, 330, 340, 410a, 410b, 540, 550, 640, 650, 740, 750: Device circuit 250, 260, 270, 280, 290, 350, 360, 440, 450, 460, 470, 480, 560, 570, 640a, 640b, 650a, 650b, 650c, 660, 670, 740a, 740b, 760: Inverters VDD, VDDM, VSS: Voltage Domain P1~P11, N1~N7: Transistors INPUT_A, INPUT_B, INPUT: Input signals SEL_A, SEL_B, SEL1_A, SEL1_B: Selection signals INT_OUT1, INT_OUT2, INT_OUT3: Intermediate output signals LS_OUT, LATCH_OUT, LATCH_OUT: Output signals CLK: Clock signal CLKB: Reverse Clock Signal 370, 380, 740c, 740d: Transmission gates 800: Method 810, 820, 830, 840: Operation

Claims

1. An electronic device comprising: A first stage includes: a first device circuit configured to operate in a first voltage domain to receive a pair of input signals and a complementary pair of first selection signals, select one of the input signals in response to the first selection signals, and generate a first intermediate output signal based on the selected input signal; a second device circuit configured to operate in a second voltage domain to receive the input signals and a complementary pair of second selection signals, select one of the input signals in response to the second selection signals, and generate a second intermediate output signal based on the selected input signal; and a second stage configured to operate in the second voltage domain to receive the first intermediate output signal and the second intermediate output signal, and generate an output signal.

2. The electronic device as claimed in claim 1, wherein the first device circuitry includes: A first inverter configured to receive one of the input signals; a second inverter configured to receive the other of the input signals, wherein the second inverter has an output terminal connected to one of the output terminals of the first inverter; and one or more switching elements configured to connect the first inverter and the second inverter to the first voltage domain in response to the first selection signal and the second selection signal.

3. The electronic device as claimed in claim 1, wherein the first device circuitry includes: A first inverter and a second inverter, each configured to receive a corresponding input signal; a first transmission gate configured to transmit an output signal of the first inverter in response to the first selection signal and the second selection signal; and a second transmission gate having an output terminal connected to an output terminal of the first transmission gate, and the second transmission gate configured to transmit an output signal of the second inverter in response to the first selection signal and the second selection signal; and wherein the second device circuit includes a switching module configured to connect a first intermediate output signal to the second voltage domain based on one of the selected input signals and in response to the first selection signal and the second selection signal.

4. The electronic device as claimed in claim 1, wherein the second device circuitry includes: A first inverter configured to receive one of the input signals; a second inverter configured to receive the other of the input signals, wherein the second inverter has an output terminal connected to one of the output terminals of the first inverter; and one or more switching elements configured to connect the first inverter and the second inverter to the second voltage domain in response to the first selection signal and the second selection signal.

5. The electronic device as claimed in claim 1, wherein the second level includes: An inverter configured to receive the first intermediate output signal and output an output signal based on the first intermediate output signal; And one or more switching elements configured to connect the inverter to the second voltage domain in response to the second intermediate output signal, or configured to connect the output signal in response to the first intermediate output signal and the second intermediate output signal.

6. An electronic device comprising: A first stage includes: a first device circuit configured to operate in a first voltage domain to receive an input signal in the first voltage domain and generate a first intermediate output signal based on the input signal; and a second device circuit configured to operate in a second voltage domain to receive the input signal and generate a second intermediate output signal based on the input signal; a second stage configured to operate in the second voltage domain to receive the first intermediate output signal, the second intermediate output signal, and a complementary pair of clock signals, and generate a third intermediate output signal based on the first intermediate output signal, the second intermediate output signal, and the clock signals; and a third stage configured to operate in the second voltage domain to receive the third intermediate output signal and the clock signals and generate an output signal.

7. The electronic device as claimed in claim 6, wherein the third level includes: An inverter having an input terminal configured to receive the third intermediate output signal and configured to generate the output signal at an output terminal; And one or more switching elements connected between the input and output of the inverter, the switching elements being configured to connect the input of the inverter to the second voltage domain in response to the output signal and the clock signals.

8. A method for shifting a signal from one voltage domain to another, comprising: The system receives a first input signal and a second input signal; selects one of the first input signal and the second input signal in response to complementary complex first selection signals and complementary complex second selection signals; generates a first intermediate output signal and a second intermediate output signal based on the selected first input signal and the second input signal; shifts the selected first input signal and the second input signal from a first voltage domain to a second voltage domain based on the first intermediate output signal, the second intermediate output signal and complementary complex clock signals; and generates an output signal based on a third intermediate output signal corresponding to the second voltage domain.

9. The method for shifting a signal from one voltage domain to another as described in claim 8, further comprising: In response to these first selection signals, an inverter is connected to the first voltage domain; And based on the first input signal and the second input signal, the inverter generates the first intermediate output signal.

10. The method for shifting a signal from one voltage domain to another as described in claim 8, further comprising: In response to these second selection signals, an inverter is connected to the second voltage domain; And based on the first input signal and the second input signal, the inverter generates the second intermediate output signal.

11. The method for shifting a signal from one voltage domain to another as described in claim 8, further comprising: An inverter is connected to the second voltage domain in response to the second intermediate output signal or in response to both the first and second intermediate output signals; and the third intermediate output signal is generated by the inverter based on the first intermediate output signal.

12. The method for shifting a signal from one voltage domain to another as described in claim 8, further comprising: The output signal is generated by an inverter based on the third intermediate output signal.

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