Package structure including heat sink structure and method for manufacturing the same

Abstract

This application discloses a packaging structure and a method for manufacturing the packaging structure. The packaging structure includes an electronic device and a heat sink structure. The heat sink structure is disposed on the electronic device and includes a base portion, a plurality of thermal vias, and a thermally conductive layer. The plurality of thermal vias extend through the base portion. The thermally conductive layer is disposed between the base portion and the electronic device. The plurality of thermal vias are thermally connected to the electronic device through the thermally conductive layer to dissipate heat generated by the electronic device.

Description

Technical Field

[0001] This application is a division of U.S. Application No. 113132865, filed August 30, 2024, which claims priority and benefits from U.S. Official Application No. 18 / 670,912, filed May 22, 2024, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a packaging structure and a method for manufacturing the same, and more specifically, to a packaging structure including a heat sink structure and a method for manufacturing the same. Prior Technology

[0003] Semiconductor packaging structures are used in a variety of electronic applications, and their size continues to shrink to meet current application requirements. However, various problems arise during the size reduction process, affecting the final electrical characteristics, quality, cost, and yield. For example, heat dissipation.

[0004] The discussion in the preceding technical paragraphs is for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes the prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a packaging structure including an electronic device and a heat sink structure. The heat sink structure is disposed on the electronic device and includes a base portion, a plurality of thermal vias, and a thermally conductive layer. The plurality of thermal vias extend through the base portion. The thermally conductive layer is disposed between the base portion and the electronic device. The plurality of thermal vias are thermally connected to the electronic device through the thermally conductive layer to dissipate heat generated by the electronic device.

[0006] Another aspect of this disclosure provides a packaging structure including an electronic device and a heat sink structure. The heat sink structure is disposed on the electronic device and includes a thermally conductive layer, a plurality of thermal vias, and a plurality of pads. The plurality of thermal vias are connected to a second surface of the thermally conductive layer. The plurality of pads are connected to a first surface of the thermally conductive layer. The plurality of pads are thermally connected to the electronic device to dissipate heat generated by the electronic device through the thermally conductive layer to the thermal vias.

[0007] Another aspect of this disclosure provides a method for manufacturing a packaging structure, comprising: providing an electronic device; providing a heat sink structure, wherein the heat sink structure includes a thermally conductive layer, a plurality of heat-perforated holes disposed in the electronic device, and a thermally conductive layer connecting the plurality of heat-perforated holes; and thermally connecting the heat sink structure to the electronic device, wherein the thermally conductive layer is disposed between a base portion and the electronic device.

[0008] Due to the design of the package structure disclosed herein, the heat generated by the electronic device can be easily and quickly dissipated or transferred to the heat dissipation via through the thermal path. Therefore, the reliability and lifespan of the package structure can be improved.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0010] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings that combine the embodiments with the scope of the patent application. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased. Figure 1 is a flowchart illustrating a method for manufacturing a packaging structure according to an embodiment of the present disclosure; Figures 2 to 24 are cross-sectional views illustrating the manufacturing process of a packaging structure according to an embodiment of the present disclosure; Figure 25 is a cross-sectional view illustrating an assembly structure according to an embodiment of the present disclosure. Implementation

[0011] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used in this document to describe the relative relationship between one element or feature depicted in the diagram and another. In addition to the orientations shown in the diagram, spatially related terms are intended to cover different orientations of the element during use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0013] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intermediate components or intermediate layers.

[0014] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one component from another. Thus, for example, the first component, first member, or first part discussed below may be referred to as the second component, second member, or second part without departing from the teachings of this disclosure.

[0015] Unless the context otherwise indicates, terms such as “identical,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure when referring to orientation, layout, location, shape, size, quantity, or other measure, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, quantities, or other measures within an acceptable range of possible variations (e.g., due to manufacturing processes). The term “substantially” may be used herein to reflect this meaning. For example, articles described as “substantially identical,” “substantially equal,” or “substantially coplanar” may be exactly the same, equal, or coplanar, or may be substantially identical, equal, or coplanar within an acceptable range of possible variations (e.g., due to manufacturing processes).

[0016] In this disclosure, packaging structure, electronic device, semiconductor electronic device or semiconductor electronic structure can generally refer to a device that can operate using semiconductor characteristics.

[0017] Figure 1 is a flowchart illustrating a manufacturing method 900 of a packaging structure 6' according to an embodiment of the present disclosure. Figures 2 to 24 are cross-sectional views illustrating the manufacturing process of a packaging structure 6' according to an embodiment of the present disclosure.

[0018] Referring to Figures 2 to 12, in step S901, electronic device 6a may be provided.

[0019] Referring to Figure 2, a first wafer 1' may be provided. The first wafer 1' may include a first base portion 10, a first conductive structure 14, a first lower structure 15, and a plurality of first conductive vias 17. The first wafer 1' may have a plurality of dividing lines 19 to define a plurality of cells 18. The first base portion 10 may have a first surface 101 (e.g., a bottom surface) and a second surface 102 (e.g., a top surface) opposite to the first surface 101.

[0020] The first base portion 10 may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the first base portion 10 may include an insulator-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the first base portion 10 may be a host semiconductor substrate composed entirely of at least one semiconductor material; this host semiconductor substrate does not contain any dielectric material, insulating layer, or conductive features.

[0021] A first conductive structure 14 may be disposed on a first surface 101 (e.g., a bottom surface) of the first base portion 10. In some embodiments, the first conductive structure 14 may include a plurality of front-end-of-line (FEOL) devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally-diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable integrated circuit (IC) components, or combinations thereof. In some embodiments, the first conductive structure 14 may further include at least one back-end-of-line (BEOL) interconnect pattern, such as a plurality of patterned circuit layers electrically connected to the front-end-of-line (FEOL) device. In some embodiments, the first conductive structure 14 may further include at least one dielectric layer or at least one dielectric structure covering the front-end-of-line (FEOL) device and the back-end-of-line (BEOL) interconnect pattern.

[0022] The first conductive structure 14 may include a first dielectric layer 141, a first circuit layer (including a plurality of traces and a plurality of pads 142), a second dielectric layer 143, a second circuit layer (including a plurality of traces and a plurality of pads 144), a plurality of internal vias 146, and a third dielectric layer 145. The first dielectric layer 141 may be disposed on a first surface 101 (e.g., a bottom surface) of the first base portion 10. The first dielectric layer 141 may be an interlayer dielectric (ILD) layer and may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN). The first circuit layer (including traces and pads 142) may be disposed on the first dielectric layer 141.

[0023] A second dielectric layer 143 can be disposed on the first dielectric layer 141 to cover the first circuit layer. The second dielectric layer 143 can be an inter-metal dielectric (IMD) layer and can include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN). A second circuit layer (including traces and pads 144) can be disposed on the second dielectric layer 143.

[0024] An internal via 146 may be disposed in the second dielectric layer 143 and may connect the first circuit layer (e.g., pad 142) and the second circuit layer (e.g., pad 144). A third dielectric layer 145 may surround the second circuit layer (e.g., pad 144). The third dielectric layer 145 may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN).

[0025] A first lower structure 15 may be disposed on the first conductive structure 14. The first lower structure 15 may include a first lower dielectric layer 151 and a plurality of first lower pads 152. The first lower pads 152 may be disposed on a second circuit layer (e.g., pad 144) and may be embedded in the first lower dielectric layer 151. Each first lower pad 152 may be a hybrid bonding (HB) pad and may include copper (Cu) or aluminum (Al). The first lower pads 152 may be exposed by the first lower dielectric layer 151. The first lower dielectric layer 151 may be a hybrid bonding (HB) dielectric layer and may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN).

[0026] A first conductive via 17 may be disposed in the first base portion 10 and may extend beyond the first surface 101 (e.g., bottom surface) of the first base portion 10. The first conductive via 17 may extend through the first dielectric layer 141 to connect to or contact the first circuit layer (e.g., pad 142). Therefore, the first conductive via 17 may extend into the first conductive structure 14 and may be electrically connected to the first conductive structure 14. Thus, the first lower pad 152 may be electrically connected to the first conductive via 17 through the first conductive structure 14.

[0027] In each unit 18, the first conductive via 17 may include a plurality of first central vias 171 disposed in the central portion of the unit 18, and a plurality of first peripheral vias 172 disposed in the peripheral portion of the unit 18. The peripheral portion of the unit 18 may surround the central portion of the unit 18. In some embodiments, the first central vias 171 may be configured for signal transmission. The first peripheral vias 172 may be configured for heat dissipation. The gap between the first central vias 171 may be larger than the gap between the first peripheral vias 172.

[0028] Referring to Figure 3, the first wafer 1' can be attached or bonded to the carrier 92. The first lower structure 15 of the first wafer 1' can contact the carrier 92. Therefore, the first surface 101 (e.g., the bottom surface) of the first base portion 10 can face the carrier 92.

[0029] Referring to Figure 4, the first base portion 10 can be thinned from its second surface 102 (e.g., the top surface) by grinding, chemical-mechanical polishing (CMP), and etching to expose the first conductive via 17. Therefore, the first conductive via 17 can extend beyond the second surface 102 (e.g., the top surface) of the first base portion 10. The first conductive via 17 can extend through the first base portion 10.

[0030] Referring to Figure 5, a first upper structure 16 can be formed on the second surface 102 (e.g., the top surface) of the first base portion 10. The first upper structure 16 may include a first upper dielectric layer 161 and a plurality of first upper pads 162. The first upper dielectric layer 161 may be disposed on the second surface 102 (e.g., the top surface) of the first base portion 10 and may cover the top portion of the first conductive via 17. The first upper dielectric layer 161 may be a hybrid bonding (HB) dielectric layer and may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN).

[0031] The first upper pad 162 may be embedded in the first upper dielectric layer 161 and may be exposed through the first upper dielectric layer 161. The first upper pad 162 may be electrically connected to the first conductive via 17. In some embodiments, the first upper pad 162 may directly contact the first conductive via 17. Each first upper pad 162 may be a hybrid bonding (HB) pad and may comprise copper or aluminum.

[0032] Referring to Figure 6, the carrier 92 can be removed from the first wafer 1'. The first wafer 1' can then be diced along the dicing line 19 to form a plurality of first semiconductor wafers 1. Each first semiconductor wafer 1 corresponds to each cell 18. The first semiconductor wafer 1 has a first surface 11 (e.g., a bottom surface), a second surface 12 (e.g., a top surface), and a side surface 13 extending between the first surface 11 (e.g., the bottom surface) and the second surface 12 (e.g., the top surface). The length L1 of the first conductive via 17 can be greater than the thickness T1 of the first base portion 10.

[0033] Referring to Figure 7, a fifth wafer 5' may be provided. The fifth wafer 5' may include a fifth base portion 50, a fifth conductive structure 54, a fifth upper structure 55, and a plurality of fifth conductive vias 57. The fifth wafer 5' may have a plurality of dividing lines 59 to define a plurality of cells 58. The fifth base portion 50 may have a first surface 501 (e.g., a bottom surface) and a second surface 502 (e.g., a top surface) opposite to the first surface 501.

[0034] The fifth base portion 50 may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the fifth base portion 50 may include an insulator-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the fifth base portion 50 may be a host semiconductor substrate composed entirely of at least one semiconductor material; this host semiconductor substrate does not contain any dielectric material, insulating layer, or conductive features.

[0035] A fifth conductive structure 54 may be disposed on a second surface 502 (e.g., a top surface) of the fifth base portion 50. In some embodiments, the fifth conductive structure 54 may include a plurality of front-end-of-line (FEOL) devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally-diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable integrated circuit (IC) components, or combinations thereof. In some embodiments, the fifth conductive structure 54 may further include at least one back-end-of-line (BEOL) interconnect pattern, such as a plurality of patterned circuit layers electrically connected to the front-end-of-line (FEOL) device. In some embodiments, the fifth conductive structure 54 may further include at least one dielectric layer or at least one dielectric structure covering the front-end-of-line (FEOL) device and the back-end-of-line (BEOL) interconnect pattern.

[0036] The fifth conductive structure 54 may include a first dielectric layer 541, a first circuit layer (including a plurality of traces and a plurality of pads 542), a second dielectric layer 543, a second circuit layer (including a plurality of traces and a plurality of pads 544), a plurality of internal vias 546, and a third dielectric layer 545. The first dielectric layer 541 may be disposed on the second surface 502 (e.g., the top surface) of the fifth base portion 50. The first dielectric layer 541 may be an interlayer dielectric (ILD) layer and may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN). The first circuit layer (including traces and pads 542) may be disposed on the first dielectric layer 541.

[0037] A second dielectric layer 543 can be disposed on the first dielectric layer 541 to cover the first circuit layer. The second dielectric layer 543 can be an intermetallic dielectric (IMD) layer and can include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN). A second circuit layer (including traces and pads 544) can be disposed on the second dielectric layer 543.

[0038] An internal via 546 may be disposed in the second dielectric layer 543 and may connect the first circuit layer (e.g., pad 542) and the second circuit layer (e.g., pad 544). A third dielectric layer 545 may surround the second circuit layer (e.g., pad 544). The third dielectric layer 545 may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN).

[0039] A fifth upper structure 55 may be disposed on the fifth conductive structure 54. The fifth upper structure 55 may include a fifth upper dielectric layer 551 and a plurality of fifth upper pads 552. The fifth upper pads 552 may be disposed on a second circuit layer (e.g., pad 544) and may be embedded in the fifth upper dielectric layer 551. Each fifth upper pad 552 may be a hybrid bonding (HB) pad and may include copper or aluminum. The fifth upper pads 552 may be exposed by the fifth upper dielectric layer 551. The fifth upper dielectric layer 551 may be a hybrid bonding (HB) dielectric layer and may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN).

[0040] A fifth conductive via 57 may be disposed in the fifth base portion 50 and may extend beyond the second surface 502 (e.g., top surface) of the fifth base portion 50. The fifth conductive via 57 may extend through the first dielectric layer 541 to connect to or contact the first circuit layer (e.g., pad 542). Therefore, the fifth conductive via 57 may extend into the fifth conductive structure 54 and may be electrically connected to the fifth conductive structure 54. Thus, the fifth upper pad 552 may be electrically connected to the fifth conductive via 57 through the fifth conductive structure 54.

[0041] In each unit 58, the fifth conductive via 57 may include a plurality of fifth central vias 571 disposed in the central portion of the unit 58, and a plurality of fifth peripheral vias 572 disposed in the peripheral portion of the unit 58. The peripheral portion of the unit 58 may surround the central portion of the unit 58. In some embodiments, the fifth central vias 571 may be configured for signal transmission. In some embodiments, the fifth peripheral vias 572 may be configured for heat dissipation. The gap between the fifth central vias 571 may be larger than the gap between the fifth peripheral vias 572.

[0042] Referring to Figure 8, an enlarged view of region "A" in Figure 7 is illustrated. The fifth conductive via 57 (e.g., a fifth central via 571 or a fifth peripheral via 572) may include a conductive material 573, a barrier layer 574, and a liner 575. The conductive material 573 may include a metal, such as copper (Cu) or other suitable materials. The barrier layer 574 may include tantalum (Ta) or titanium (Ti) and may surround the conductive material 573. The liner 575 may include an oxide material, such as silicon oxide (SiO2), and may surround the barrier layer 574. The thickness of the barrier layer 574 may be substantially equal to the thickness of the liner 575.

[0043] Referring to Figure 9, a plurality of first semiconductor wafers 1 can be attached to the cell 58 of the fifth wafer 5' by hybrid bonding. The first surface 11 of the first semiconductor wafer 1 can directly contact the fifth upper structure 55 of the fifth wafer 5'. The first lower dielectric layer 151 of the first lower structure 15 of the first semiconductor wafer 1 can be bonded to the fifth upper dielectric layer 551 of the fifth upper structure 55 of the fifth wafer 5'. The first lower pad 152 of the first lower structure 15 of the first semiconductor wafer 1 can be attached to the fifth upper pad 552 of the fifth upper structure 55 of the fifth wafer 5' by metal-to-metal bonding.

[0044] Referring to Figure 10, a plurality of second semiconductor wafers 2 can be attached to the first semiconductor wafer 1 by hybrid bonding. The structure of the second semiconductor wafers 2 can be the same as or similar to the structure of the first semiconductor wafer 1. The second semiconductor wafer 2 has a first surface 21 (e.g., bottom surface), a second surface 22 (e.g., top surface), and a side surface 23 extending between the first surface 21 (e.g., bottom surface) and the second surface 22 (e.g., top surface).

[0045] The second semiconductor wafer 2 may include a second base portion 20, a second conductive structure 24, a second lower structure 25, a second upper structure 26, and a plurality of second conductive vias 27, which are the same as the first base portion 10, the first conductive structure 14, the first lower structure 15, the first upper structure 16, and the first conductive vias 17 of the first semiconductor wafer 1.

[0046] The second conductive via 27 may include a plurality of second central vias disposed in the central portion of the second semiconductor wafer 2, and a plurality of second peripheral vias disposed in the peripheral portion of the second semiconductor wafer 2. In some embodiments, the second central vias may be configured for signal transmission and may correspond to the first central via 171. The second peripheral vias may be configured for heat dissipation and may correspond to the first peripheral via 172.

[0047] The first surface 21 of the second semiconductor wafer 2 can directly contact the second surface 12 of the first semiconductor wafer 1. The second lower dielectric layer 251 of the second lower structure 25 of the second semiconductor wafer 2 can be bonded to the first upper dielectric layer 161 of the first upper structure 16 of the first semiconductor wafer 1. The second lower pad 252 of the second lower structure 25 of the second semiconductor wafer 2 can be attached to the first upper pad 162 of the first upper structure 16 of the first semiconductor wafer 1 by metal-to-metal bonding.

[0048] Subsequently, a plurality of third semiconductor wafers 3 can be attached to the second semiconductor wafer 2 by hybrid bonding. The structure of the third semiconductor wafer 3 can be the same as or similar to the structure of the first semiconductor wafer 1. The third semiconductor wafer 3 has a first surface 31 (e.g., bottom surface), a second surface 32 (e.g., top surface), and a side surface 33 extending between the first surface 31 (e.g., bottom surface) and the second surface 32 (e.g., top surface).

[0049] The third semiconductor wafer 3 may include a third base portion 30, a third conductive structure 34, a third lower structure 35, a third upper structure 36, and a plurality of third conductive vias 37, which are the same as the first base portion 10, the first conductive structure 14, the first lower structure 15, the first upper structure 16, and the first conductive vias 17 of the first semiconductor wafer 1.

[0050] The third conductive via 37 may include a plurality of third central vias disposed in the central portion of the third semiconductor wafer 3, and a plurality of third peripheral vias disposed in the peripheral portion of the third semiconductor wafer 3. In some embodiments, the third central via may be configured for signal transmission and may correspond to the second central via and the first central via 171. The third peripheral vias may be configured for heat dissipation and may correspond to the second peripheral via and the first peripheral via 172.

[0051] The first surface 31 of the third semiconductor wafer 3 can directly contact the second surface 22 of the second semiconductor wafer 2. The third lower dielectric layer 351 of the third lower structure 35 of the third semiconductor wafer 3 can be bonded to the second upper dielectric layer 261 of the second upper structure 26 of the second semiconductor wafer 2. The third lower pad 352 of the third lower structure 35 of the third semiconductor wafer 3 can be attached to the second upper pad 262 of the second upper structure 26 of the second semiconductor wafer 2 by metal-to-metal bonding.

[0052] Subsequently, a plurality of fourth semiconductor wafers 4 can be attached to the third semiconductor wafer 3 by hybrid bonding. The structure of the fourth semiconductor wafer 4 can be similar to that of the first semiconductor wafer 1. The fourth semiconductor wafer 4 has a first surface 41 (e.g., bottom surface), a second surface 42 (e.g., top surface), and a side surface 43 extending between the first surface 41 (e.g., bottom surface) and the second surface 42 (e.g., top surface).

[0053] The fourth semiconductor wafer 4 may include a fourth base portion 40, a fourth conductive structure 44, a fourth lower structure 45, a fourth upper structure 46, and a plurality of fourth conductive vias 47, which are the same as the first base portion 10, the first conductive structure 14, the first lower structure 15, the first upper structure 16, and the first conductive vias 17 of the first semiconductor wafer 1.

[0054] The fourth conductive via 47 may include a plurality of fourth peripheral vias disposed on the peripheral portion of the fourth semiconductor wafer 4. In some embodiments, the fourth peripheral vias may be configured for heat dissipation and may correspond to the third peripheral via, the second peripheral via, and the first peripheral via 172.

[0055] The first surface 41 of the fourth semiconductor wafer 4 can directly contact the second surface 32 of the third semiconductor wafer 3. The fourth lower dielectric layer 451 of the fourth lower structure 45 of the fourth semiconductor wafer 4 can be bonded to the third upper dielectric layer 361 of the third upper structure 36 of the third semiconductor wafer 3. The fourth lower pad 452 of the fourth lower structure 45 of the fourth semiconductor wafer 4 can be attached to the third upper pad 362 of the third upper structure 36 of the third semiconductor wafer 3 by metal-to-metal bonding.

[0056] Referring to Figure 11, an encapsulant 65 can be formed on the fifth wafer 5' to cover and encapsulate the stacked first semiconductor wafer 1, second semiconductor wafer 2, third semiconductor wafer 3, and fourth semiconductor wafer 4. The encapsulant 65 may include a molding compound with or without fillers. The encapsulant 65 may have a top surface 652. Simultaneously, a molding structure 5a can be formed.

[0057] Referring to Figure 12, the encapsulant 65 can be thinned from its top surface 652. Simultaneously, the fourth base portion 40 can be thinned from its second surface 402 (e.g., the top surface) by grinding, chemical mechanical polishing (CMP), and etching to expose the fourth conductive via 47. Therefore, the fourth conductive via 47 can extend beyond the second surface 402 (e.g., the top surface) of the fourth base portion 40, and the top surface 652 of the encapsulant 65 can be substantially coplanar with the second surface 402 (e.g., the top surface).

[0058] Subsequently, a fourth upper structure 46 can be formed on the second surface 402 (e.g., top surface) of the fourth base portion 40 and the top surface 652 of the encapsulant 65. The fourth upper structure 46 may include a fourth upper dielectric layer 461 and a plurality of fourth upper pads 462. The fourth upper dielectric layer 461 may be disposed on the second surface 402 (e.g., top surface) of the fourth base portion 40 and the top surface 652 of the encapsulant 65, and may cover the top portion of the fourth conductive via 47. The fourth upper dielectric layer 461 may be a hybrid bonding (HB) dielectric layer and may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN).

[0059] The fourth upper pad 462 may be embedded in the fourth upper dielectric layer 461 and may be exposed through the fourth upper dielectric layer 461. The fourth upper pad 462 may be electrically connected to the fourth conductive via 47. In some embodiments, the fourth upper pad 462 may directly contact the fourth conductive via 47. Each fourth upper pad 462 may be a hybrid bonding (HB) pad and may comprise copper or aluminum.

[0060] Meanwhile, the molded structure 5a may include a plurality of electronic devices 6a (corresponding to unit 58) defined by the dividing line 59. Each electronic device 6a may be an electronic device 6a having a first surface 61 (e.g., bottom surface) and a second surface 62 (e.g., top surface) opposite to the first surface 61.

[0061] Referring to Figures 1 and 13 to 18, in step S902, a heat sink structure 7 can be provided. Referring to Figure 13, a sixth wafer 7' can be provided. The sixth wafer 7' may include a sixth base portion 70 and a first dielectric layer 761. The sixth wafer 7' may have a plurality of dividing lines 79 to define a plurality of cells 7a. The sixth base portion 70 may also be referred to as "base portion 70". The sixth base portion 70 may have a first surface 701 (e.g., a bottom surface) and a second surface 702 (e.g., a top surface), which is opposite to the first surface 701.

[0062] The sixth base portion 70 may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the sixth base portion 70 may include an insulator-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the sixth base portion 70 may be a host semiconductor substrate composed entirely of at least one semiconductor material; this host semiconductor substrate does not contain any dielectric material, insulating layer, or conductive features.

[0063] A first dielectric layer 761 may be disposed on a first surface 701 (e.g., a bottom surface) of the sixth base portion 70. The first dielectric layer 761 may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN).

[0064] Referring to Figure 14, a plurality of thermal vias 77 can be formed extending through the first dielectric layer 761 and into the sixth base portion 70. The thermal vias 77 can be configured for heat dissipation.

[0065] Referring to Figure 15, an enlarged view of region "B" in Figure 14 is shown. The thermal via 77 may include a conductive material 773 and a barrier layer 774. The conductive material 773 may include a metal, such as copper (Cu) or other suitable material. The barrier layer 774 may include tantalum (Ta) or titanium (Ti) and may surround the conductive material 773.

[0066] Referring to Figure 16, a thermally conductive layer 74 and a second dielectric layer 762 can be formed on the first dielectric layer 761. The thermally conductive layer 74 may include a metal, such as copper (Cu) or other suitable materials. The material of the thermally conductive layer 74 may be the same as or different from the material of the thermal via 77. The thermally conductive layer 74 may cover and contact the thermal via 77. Therefore, the thermal via 77 can directly contact the thermally conductive layer 74.

[0067] The second dielectric layer 762 may surround the thermally conductive layer 74. The first dielectric layer 761 and the second dielectric layer 762 may together form a dielectric structure 76. The dielectric structure 76 may be disposed on the first surface 701 of the sixth base portion 70 and may encapsulate the thermally conductive layer 74. The thermally conductive layer 74 may be separated from the sixth base portion 70 by the first dielectric layer 761 of the dielectric structure 76. Therefore, a portion of the dielectric structure 76 is disposed between the thermally conductive layer 74 and the sixth base portion 70.

[0068] Referring to Figure 17, a lower structure 75 (e.g., a sixth lower structure 75) may be formed or disposed on the thermally conductive layer 74 and the dielectric structure 76. The lower structure 75 may include a lower dielectric layer 751 (e.g., a sixth lower dielectric layer 751) and a plurality of lower pads 752 (e.g., a plurality of sixth lower pads 752). The lower pads 752 may be disposed on the thermally conductive layer 74 and may be embedded in the lower dielectric layer 751. Each lower pad 752 may be a hybrid bonding (HB) pad and may include copper or aluminum. The lower pads 752 may be exposed by the lower dielectric layer 751. The lower dielectric layer 751 may be a hybrid bonding (HB) dielectric layer and may include silicon oxide (SiO2), silicon nitride (SiN), and / or silicon carbide (SiCN).

[0069] A heat-perforated hole 77 is connected to a second surface 742 (e.g., top surface) of the thermally conductive layer 74. A lower pad 752 is connected to a first surface 741 (e.g., bottom surface) of the thermally conductive layer 74 opposite to the second surface 742.

[0070] Meanwhile, the structure corresponding to each unit 7a is a heat sink structure 7. Therefore, the sixth wafer 7' may include a plurality of heat sink structures 7 defined by the dividing line 79.

[0071] Referring to Figure 18, a partial perspective view of the thermally conductive layer 74 and heat-perforating via 77 of Figure 17 is shown. The thermally conductive layer 74 may have a mesh shape. That is, the thermally conductive layer 74 may include a plurality of intersecting lines 743 to form a plurality of intersecting portions 744. The heat-perforating via 77 is connected to the intersecting portions 744 of the thermally conductive layer 74. However, in some embodiments, the thermally conductive layer 74 may have a plate-like or sheet-like shape.

[0072] Referring to Figures 1 and 19 to 24, in step S903, the heat sink structure 7 can be thermally connected to the electronic device 6, and the thermally conductive layer 74 can be disposed between the sixth base portion 70 and the electronic device 6. Referring to Figures 19 and 20, the sixth wafer 7' of Figure 17 is attached to the molded structure 5a of Figure 12 by hybrid bonding.

[0073] The bottom surface 71 of the heat sink structure 7 of the sixth wafer 7' can directly contact the second surface 62 (e.g., top surface) of the electronic device 6a of the molded structure 5a. The lower dielectric layer 751 (e.g., the sixth lower dielectric layer 751) of the lower structure 75 of the heat sink structure 7 can be bonded to the fourth upper dielectric layer 461 of the fourth upper structure 46 of the electronic device 6a of the molded structure 5a. The lower pad 752 (e.g., the sixth lower pad 752) of the lower structure 75 of the heat sink structure 7 can be attached and thermally connected to the fourth upper pad 462 of the fourth upper structure 46 of the electronic device 6a of the molded structure 5a by metal-to-metal bonding. The cleaving line 79 of the sixth wafer 7' can be aligned with the cleaving line 59 of the molded structure 5a to jointly form the cleaving line 59a.

[0074] Referring to Figure 21, the sixth base portion 70 (e.g., base portion 70) can be thinned from its second surface 702 (e.g., top surface) by grinding, chemical mechanical polishing (CMP), and etching to expose the thermal via 77. Therefore, the thermal via 77 can extend beyond the second surface 702 (e.g., top surface) of the sixth base portion 70 (e.g., base portion 70). The thermal via 77 can extend through the sixth base portion 70 (e.g., base portion 70). In some embodiments, the barrier layer 774 may not be removed and may remain on the conductive material 773. That is, the protruding portion of the thermal via 77 protruding from the second surface 702 of the sixth base 70 may include the barrier layer 774.

[0075] Referring to Figure 22, a protective material 78 may be formed or disposed on a second surface 702 (e.g., a top surface) of the sixth base portion 70 (e.g., the base portion 70) and may encapsulate the heat passage 77. The protective material 78 may include a molding compound with or without filler. The protective material 78 may cover and contact the barrier layer 774 of the heat passage 77.

[0076] Referring to Figure 23, the fifth base portion 50 can be thinned from its first surface 501 (e.g., the top surface) by grinding, chemical mechanical polishing (CMP), and etching to expose the fifth conductive via 57. Therefore, the fifth conductive via 57 can extend beyond the first surface 501 (e.g., the bottom surface) of the fifth base portion 50. The fifth conductive via 57 can extend through the fifth base portion 50. The length of the fifth conductive via 57 can be greater than the thickness of the fifth base portion 50.

[0077] Subsequently, dielectric layer 56 may be formed or disposed on the first surface 501 (e.g., bottom surface) of the fifth base portion 50, and may encapsulate the fifth conductive via 57. Then, a plurality of external connectors 68 may be formed in dielectric layer 56 to connect to the fifth conductive via 57 for external connection.

[0078] Referring to Figure 24, a segmentation process can be performed along the segmentation line 59a to form a plurality of package structures 6'.

[0079] Referring to Figure 24, a cross-sectional view of a package structure 6' illustrating some embodiments of this disclosure is shown. The package structure 6' may include an electronic device 6 and a heat sink structure 7. The electronic device 6 may be a stacked structure comprising a plurality of stacked memory devices (e.g., dynamic random access memory (DRAM)). For example, the electronic device 6 may be high bandwidth memory (HBM).

[0080] In some embodiments, the electronic device 6 may include a first semiconductor wafer 1, a second semiconductor wafer 2, a third semiconductor wafer 3, a fourth semiconductor wafer 4, a base semiconductor wafer 5, an encapsulant 65, a fourth superstructure 46, and a plurality of external connectors 68.

[0081] The first semiconductor wafer 1 may have a bottom surface 11 (e.g., a first surface), a top surface 12 (e.g., a second surface), and a side surface 13 extending between the bottom surface 11 and the top surface 12. The first semiconductor wafer 1 may include a first base portion 10, a first conductive structure 14, a first lower structure 15, a first upper structure 16, and a plurality of first conductive vias 17. The first semiconductor wafer 1 may be a memory wafer, such as a dynamic random access memory (DRAM) wafer.

[0082] A first conductive structure 14 may be provided on a first surface 101 (e.g., a bottom surface) of the first base portion 10. A first conductive via 17 may extend through the first base portion 10 and may be electrically connected to the first conductive structure 14. In some embodiments, the bottom end of the first conductive via 17 may extend beyond the first surface 101 (e.g., the bottom surface) of the first base portion 10 and may extend into the first conductive structure 14. Therefore, the first conductive via 17 may be an integral structure, and the length of the first conductive via 17 may be greater than the thickness of the first base portion 10. In some embodiments, the first conductive via 17 may extend beyond a second surface 102 (e.g., a top surface) of the first base portion 10.

[0083] A first lower structure 15 may be disposed on the first conductive structure 14. The first lower structure 15 may be a hybrid bond (HB) structure or a solder bond structure, and may include a first lower dielectric layer 151 and a plurality of first lower pads 152. The first lower dielectric layer 151 may be a hybrid bond (HB) dielectric layer. Each first lower pad 152 may be a hybrid bond (HB) pad. The first lower pads 152 may be embedded in the first lower dielectric layer 151 and may be exposed by the first lower dielectric layer 151. The first lower pads 152 may be surrounded by the first lower dielectric layer 151. The first lower pads 152 may be electrically connected to the first conductive via 17 through the first conductive structure 14.

[0084] In some embodiments, the bottom surface of the first lower pad 152 may be substantially aligned with the bottom surface of the first lower dielectric layer 151. Therefore, the bottom surface of the first lower pad 152 may be exposed via the bottom surface of the first lower dielectric layer 151. In some embodiments, the top surface of the first lower pad 152 may be substantially aligned with the top surface of the first lower dielectric layer 151. Therefore, the top surface of the first lower pad 152 may contact the first conductive structure 14. In some embodiments, the thickness of the first lower pad 152 may be substantially equal to the thickness of the first lower dielectric layer 151.

[0085] A first upper structure 16 may be provided on a second surface 102 (e.g., top surface) of the first base portion 10. The first upper structure 16 may be a hybrid bonding (HB) structure and may include a first upper dielectric layer 161 and a plurality of first upper pads 162.

[0086] The first upper dielectric layer 161 may be a hybrid bonding (HB) dielectric layer. Each first upper pad 162 may be a hybrid bonding (HB) pad. The first upper pad 162 may be embedded in the first upper dielectric layer 161 and may be exposed by the first upper dielectric layer 161. The first upper pad 162 may be surrounded by the first upper dielectric layer 161. The first upper pad 162 may be electrically connected to the first conductive via 17. In some embodiments, the first upper pad 162 may directly contact the first conductive via 17. The first upper pad 162 may be electrically connected to the first lower pad 152 through the first conductive via 17 and the first conductive structure 14.

[0087] In some embodiments, the top surface of the first upper pad 162 may be substantially aligned with the top surface of the first upper dielectric layer 161. Therefore, the top surface of the first upper pad 162 may be exposed via the top surface of the first upper dielectric layer 161. The bottom surface of the first upper pad 162 may contact the first conductive via 17. In some embodiments, the thickness of the first upper pad 162 may be less than the thickness of the first upper dielectric layer 161.

[0088] The second semiconductor wafer 2 may be stacked on the first semiconductor wafer 1 and may be electrically connected to the first semiconductor wafer 1 by hybrid bonding or metal-to-metal bonding. The second semiconductor wafer 2 may have a bottom surface 21 (e.g., a first surface), a top surface 22 (e.g., a second surface), and a side surface 23 extending between the bottom surface 21 and the top surface 22. The bottom surface 21 (e.g., the first surface) of the second semiconductor wafer 2 may directly contact the top surface 12 of the first semiconductor wafer 1. The side surface 23 of the second semiconductor wafer 2 may be substantially aligned or aligned with the side surface 13 of the first semiconductor wafer 1.

[0089] The second semiconductor chip 2 may include a second base portion 20, a second conductive structure 24, a second lower structure 25, a second upper structure 26, and a plurality of second conductive vias 27. The second semiconductor chip 2 may be a memory chip, such as a dynamic random access memory (DRAM) chip.

[0090] A second conductive structure 24 may be provided on a first surface (e.g., a bottom surface) of the second base portion 20. A second conductive via 27 may extend through the second base portion 20 and may be electrically connected to the second conductive structure 24. In some embodiments, the bottom end of the second conductive via 27 may extend beyond the first surface (e.g., the bottom surface) of the second base portion 20 and may extend into the second conductive structure 24. Therefore, the second conductive via 27 may be an integral structure, and the length of the second conductive via 27 may be greater than the thickness of the second base portion 20. In some embodiments, the second conductive via 27 may extend beyond a second surface (e.g., a top surface) of the second base portion 20.

[0091] A second lower structure 25 can be disposed on the second conductive structure 24. The second lower structure 25 can be a hybrid bonding (HB) structure and can include a second lower dielectric layer 251 and a plurality of second lower pads 252. The second lower dielectric layer 251 can be a hybrid bonding (HB) dielectric layer. Each second lower pad 252 can be a hybrid bonding (HB) pad. The second lower pads 252 can be embedded in the second lower dielectric layer 251 and can be exposed by the second lower dielectric layer 251. The second lower pads 252 can be surrounded by the second lower dielectric layer 251. The second lower pads 252 can be electrically connected to the second conductive via 27 through the second conductive structure 24.

[0092] In some embodiments, the bottom surface of the second lower pad 252 may be substantially aligned with the bottom surface of the second lower dielectric layer 251. Therefore, the bottom surface of the second lower pad 252 may be exposed via the bottom surface of the second lower dielectric layer 251. In some embodiments, the top surface of the second lower pad 252 may be substantially aligned with the top surface of the second lower dielectric layer 251. Therefore, the top surface of the second lower pad 252 may contact the second conductive structure 24. In some embodiments, the thickness of the second lower pad 252 may be substantially equal to the thickness of the second lower dielectric layer 251.

[0093] The second lower structure 25 of the second semiconductor wafer 2 can be bonded to and electrically connected to the first upper structure 16 of the first semiconductor wafer 1 via hybrid bonding. Therefore, the second lower pad 252 of the second semiconductor wafer 2 can directly contact the first upper pad 162 of the first semiconductor wafer 1. The width of the second lower pad 252 of the second semiconductor wafer 2 can be substantially equal to the width of the first upper pad 162 of the first semiconductor wafer 1.

[0094] A second upper structure 26 may be provided on a second surface (e.g., top surface) of the second base portion 20. The second upper structure 26 may be a hybrid bonding (HB) structure or a solder bonding structure, and may include a second upper dielectric layer 261 and a plurality of second upper pads 262.

[0095] The second upper dielectric layer 261 may be a hybrid bonding (HB) dielectric layer. Each second upper pad 262 may be a hybrid bonding (HB) pad. The second upper pad 262 may be embedded in the second upper dielectric layer 261 and may be exposed by the second upper dielectric layer 261. The second upper pad 262 may be surrounded by the second upper dielectric layer 261. The second upper pad 262 may be electrically connected to the second conductive via 27. In some embodiments, the second upper pad 262 may directly contact the second conductive via 27. The second upper pad 262 may be electrically connected to the second lower pad 252 through the second conductive via 27 and the second conductive structure 24.

[0096] In some embodiments, the top surface of the second upper pad 262 may be substantially aligned with the top surface of the second upper dielectric layer 261. Therefore, the top surface of the second upper pad 262 may be exposed via the top surface of the second upper dielectric layer 261. The bottom surface of the second upper pad 262 may contact the second conductive via 27. In some embodiments, the thickness of the second upper pad 262 may be less than the thickness of the second upper dielectric layer 261.

[0097] In some embodiments, the bottom surface 21 of the second semiconductor wafer 2 may include the bottom surface of the second lower pad 252 and the bottom surface of the second lower dielectric layer 251. The top surface 22 of the second semiconductor wafer 2 may include the top surface of the second upper pad 262 and the top surface of the second upper dielectric layer 261. The side surface 23 of the second semiconductor wafer 2 may include the side surface of the second base portion 20, the side surface of the second conductive structure 24, the side surface of the second lower structure 25, and the side surface of the second upper structure 26.

[0098] The third semiconductor wafer 3 can be stacked on and electrically connected to the second semiconductor wafer 2 by hybrid bonding or metal-to-metal bonding. The third semiconductor wafer 3 may have a bottom surface 31 (e.g., a first surface), a top surface 32 (e.g., a second surface), and a side surface 33 extending between the bottom surface 31 and the top surface 32. The bottom surface 31 (e.g., the first surface) of the third semiconductor wafer 3 can contact the top surface 22 of the second semiconductor wafer 2.

[0099] The third semiconductor chip 3 may include a third base portion 30, a third conductive structure 34, a third lower structure 35, a third upper structure 36, and a plurality of third conductive vias 37. The third semiconductor chip 3 may be a memory chip, such as a dynamic random access memory (DRAM) chip.

[0100] The third base portion 30 may have a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface) opposite to the first surface. A third conductive structure 34 may be provided on the first surface (e.g., the bottom surface) of the third base portion 30.

[0101] The third conductive via 37 may extend through the third base portion 30 and may be electrically connected to the third conductive structure 34. In some embodiments, the bottom end of the third conductive via 37 may extend beyond the first surface (e.g., the bottom surface) of the third base portion 30 and may extend into the third conductive structure 34. In some embodiments, the third conductive via 37 may extend beyond the second surface (e.g., the top surface) of the third base portion 30.

[0102] A third lower structure 35 may be disposed on the third conductive structure 34. The third lower structure 35 may be a hybrid bond (HB) structure or a solder bond structure, and may include a third lower dielectric layer 351 and a plurality of third lower pads 352. The third lower dielectric layer 351 may be a hybrid bond (HB) dielectric layer. Each third lower pad 352 may be a hybrid bond (HB) pad. The third lower pads 352 may be embedded in the third lower dielectric layer 351 and may be exposed by the third lower dielectric layer 351. The third lower pads 352 may be electrically connected to the third conductive via 37 through the third conductive structure 34.

[0103] The third lower pad 352 of the third lower structure 35 of the third semiconductor wafer 3 can be attached to the second upper pad 262 of the second upper structure 26 of the second semiconductor wafer 2 by metal-to-metal bonding.

[0104] A third upper structure 36 may be provided on the second surface (e.g., the top surface) of the third base portion 30. The third upper structure 36 may be a hybrid bonding (HB) structure and may include a third upper dielectric layer 361 and a plurality of third upper pads 362.

[0105] The third upper dielectric layer 361 may be a hybrid bonding (HB) dielectric layer. Each third upper pad 362 may be a hybrid bonding (HB) pad. The third upper pad 362 may be embedded in the third upper dielectric layer 361 and may be exposed by the third upper dielectric layer 361. The third upper pad 362 may be electrically connected to the third conductive via 37. In some embodiments, the third upper pad 362 may be electrically connected to the third lower pad 352 through the third conductive via 37 and the third conductive structure 34.

[0106] The fourth semiconductor wafer 4 can be stacked on and electrically connected to the third semiconductor wafer 3 by hybrid bonding or metal-to-metal bonding. The fourth semiconductor wafer 4 may have a bottom surface 41 (e.g., a first surface), a top surface 42 (e.g., a second surface), and a side surface 43 extending between the bottom surface 41 and the top surface 42. The bottom surface 41 (e.g., the first surface) of the fourth semiconductor wafer 4 can directly contact the top surface 32 of the third semiconductor wafer 3.

[0107] The fourth semiconductor chip 4 may include a fourth base portion 40, a fourth conductive structure 44, a fourth lower structure 45, and a plurality of third conductive vias 37. The fourth semiconductor chip 4 may be a memory chip, such as a dynamic random access memory (DRAM) chip.

[0108] A fourth conductive structure 44 may be disposed on a first surface (e.g., a bottom surface) of the fourth base portion 40. A fourth lower structure 45 may be disposed on the fourth conductive structure 44. The fourth lower structure 45 may be a hybrid bond (HB) structure and may include a fourth lower dielectric layer 451 and a plurality of fourth lower pads 452. The fourth lower dielectric layer 451 may be a hybrid bond (HB) dielectric layer. Each fourth lower pad 452 may be a hybrid bond (HB) pad. The fourth lower pads 452 may be embedded in the fourth lower dielectric layer 451 and may be exposed by the fourth lower dielectric layer 451.

[0109] The fourth lower structure 45 of the fourth semiconductor wafer 4 can be bonded to and electrically connected to the third upper structure 36 of the third semiconductor wafer 3 by hybrid bonding. For example, the fourth lower dielectric layer 451 of the fourth semiconductor wafer 4 can be bonded to the third upper dielectric layer 361 of the third semiconductor wafer 3 by dielectric-to-dielectric bonding.

[0110] The fourth lower pad 452 of the fourth semiconductor wafer 4 can be attached to, bonded to or electrically connected to the third upper pad 362 of the third semiconductor wafer 3 by metal-to-metal bonding.

[0111] The base semiconductor wafer 5 (or the fifth semiconductor wafer 5) may have a bottom surface 51 (e.g., a first surface), a top surface 52 (e.g., a second surface), and a side surface 53 extending between the bottom surface 51 and the top surface 52. The base semiconductor wafer 5 may include a fifth base portion 50, a fifth conductive structure 54, a fifth upper structure 55, a plurality of fifth conductive vias 57, and a dielectric layer 56. The base semiconductor wafer 5 may be a controller wafer, such as an application processor (AP) wafer.

[0112] A fifth conductive structure 54 may be provided on a first surface (e.g., a top surface) of the fifth base portion 50. A fifth conductive via 57 may extend through the fifth base portion 50 and may be electrically connected to the fifth conductive structure 54. In some embodiments, one end of the fifth conductive via 57 may extend into the fifth conductive structure 54.

[0113] A fifth upper structure 55 may be disposed on the fifth conductive structure 54. The fifth upper structure 55 may be a hybrid bond (HB) structure or a solder bond structure, and may include a fifth upper dielectric layer 551 and a plurality of fifth upper pads 552. The fifth upper dielectric layer 551 may be a hybrid bond (HB) dielectric layer. Each fifth upper pad 552 may be a hybrid bond (HB) pad. The fifth upper pads 552 may be embedded in the fifth upper dielectric layer 551 and may be exposed by the fifth upper dielectric layer 551.

[0114] The dielectric layer 56 may be formed or disposed on the first surface (e.g., the bottom surface) of the fifth base portion 50 and may encapsulate the fifth conductive via 57.

[0115] The first lower pad 152 of the first lower structure 15 of the first semiconductor wafer 1 can be bonded to and electrically connected to the fifth upper pad 552 of the fifth upper structure 55 of the base semiconductor wafer 5 by hybrid bonding.

[0116] The encapsulant 65 may be a molding compound with or without filler. The encapsulant 65 may encapsulate the top surface 52 of the first semiconductor wafer 1, the second semiconductor wafer 2, the third semiconductor wafer 3, the fourth semiconductor wafer 4, and the base semiconductor wafer 5. The encapsulant 65 may cover the side surface 13 of the first semiconductor wafer 1, the side surface 23 of the second semiconductor wafer 2, the side surface 33 of the third semiconductor wafer 3, the side surface 43 of the fourth semiconductor wafer 4, and the top surface 52 of the base semiconductor wafer 5.

[0117] An external connector 68 can be formed in the dielectric layer 56 to connect to the fifth conductive via 57 for external connection. The external connector 68 may include a reflowable material, such as a silver-tin alloy (AgSn). Therefore, the external connector 68 may include solder balls, solder bumps, or microbumps. The external connector 68 may be disposed on the fifth conductive via 57.

[0118] A fourth upper structure 46 may be disposed on the second surface (e.g., top surface) of the fourth base portion 40 and the top surface of the encapsulant 65. The fourth upper structure 46 may include a fourth upper dielectric layer 461 and a plurality of fourth upper pads 462. The fourth upper dielectric layer 461 may be disposed on the second surface (e.g., top surface) of the fourth base portion 40 and the top surface of the encapsulant 65, and may cover the top portion of the fourth conductive via 47. The fourth upper dielectric layer 461 may be a hybrid bonding (HB) dielectric layer.

[0119] The fourth upper pad 462 may be embedded in the fourth upper dielectric layer 461 and may be exposed through the fourth upper dielectric layer 461. The fourth upper pad 462 may be electrically connected to the fourth conductive via 47. In some embodiments, the fourth upper pad 462 may directly contact the fourth conductive via 47. Each fourth upper pad 462 may be a hybrid bonding (HB) pad.

[0120] A heat sink structure 7 can be disposed on the electronic device 6. The heat sink structure 7 may have a bottom surface 71 (e.g., a first surface), a top surface 72 (e.g., a second surface), and a side surface 73 extending between the bottom surface 71 and the top surface 72. The heat sink structure 7 may include a base portion 70, a thermally conductive layer 74, a lower structure 75, a dielectric structure 76, a plurality of thermal vias 77, and a protective material 78. The heat sink structure 7 may be a wafer structure.

[0121] The base portion 70 may have a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface) opposite to the first surface. The dielectric structure 76 may include a first dielectric layer 761 and a second dielectric layer 762. The first dielectric layer 761 may be disposed on the first surface (e.g., the bottom surface) of the base 70. A thermal via 77 may extend through the first dielectric layer 761 and the base 70. The length of the thermal via 77 may be greater than the thickness of the base 70.

[0122] A thermally conductive layer 74 and a second dielectric layer 762 may be formed on the first dielectric layer 761. The thermally conductive layer 74 may include a metal, such as copper (Cu) or other suitable material. The thermally conductive layer 74 may cover and contact the thermal via 77. Therefore, the thermal via 77 may directly contact and connect to the second surface (e.g., the top surface) of the thermally conductive layer 74. The thermally conductive layer 74 may be disposed between the base 70 and the electronic device 6. The thermal via 77 may be thermally connected to the electronic device 6 through the thermally conductive layer 74 to dissipate heat generated by the electronic device 6. The length L7 of the thermal via 77 may be greater than the thickness T7 of the sixth base portion 70 (e.g., the base portion 70).

[0123] The second dielectric layer 762 may surround the thermally conductive layer 74. Therefore, the dielectric structure 76 may be disposed on the first surface 701 of the base portion 70 and may encapsulate the thermally conductive layer 74. The thermally conductive layer 74 may be separated from the base portion 70 by the first dielectric layer 761 of the dielectric structure 76. Therefore, a portion of the dielectric structure 76 is disposed between the thermally conductive layer 74 and the sixth base portion 70.

[0124] A lower structure 75 can be disposed on the thermally conductive layer 74 and the dielectric structure 76. The lower structure 75 may include a lower dielectric layer 751 and a plurality of lower pads 752. The lower pads 752 may be disposed on and connected to the first surface (e.g., the bottom surface) of the thermally conductive layer 74, and may be embedded in the lower dielectric layer 751. Each lower pad 752 may be a hybrid bonding (HB) pad. The lower pads 752 may be exposed by the lower dielectric layer 751. The lower dielectric layer 751 may be a hybrid bonding (HB) dielectric layer. The lower pads 752 may be thermally connected to the electronic device 6 to dissipate the heat generated by the electronic device 6 through the thermally conductive layer 74 to the heat via 77.

[0125] In some embodiments, the bottom surface of the lower pad 752 may be substantially aligned with the bottom surface of the lower dielectric layer 751. Therefore, the bottom surface of the lower pad 752 may be exposed via the bottom surface of the lower dielectric layer 751. In some embodiments, the thickness of the lower pad 752 may be substantially equal to the thickness of the lower dielectric layer 751.

[0126] Protective material 78 may be disposed on a second surface (e.g., top surface) of the base portion 70 and may encapsulate the thermal via 77. Protective material 78 may include a molding compound with or without filler. Protective material 78 does not contact encapsulant 65.

[0127] The heat sink structure 7 can be attached to the electronic device 6 via a hybrid bonding process. Therefore, the thermally conductive layer 74 can be thermally connected to the electronic device 6 via the lower pad 752, the fourth upper pad 462, and the fourth conductive via 47. Furthermore, the side surface 73 of the heat sink structure 7 can be substantially aligned with the side surface 63 of the electronic device 6. The side surface 783 of the protective material 78, the side surface 703 of the base portion 70, and the side surface of the encapsulant 65 of the electronic device 6 (i.e., the side surface 63 of the electronic device 6) can be substantially aligned with each other. Furthermore, the thermally conductive layer 74 of the heat sink structure 7 can be perpendicularly overlapped with the encapsulant 65 of the electronic device 6.

[0128] In the embodiment shown in FIG24, the thermal path 94 (or thermal conduction path, or heat dissipation path) can be formed as including a fifth peripheral through hole 572, a fifth conductive structure 54, a fifth upper pad 552, a first lower pad 152, a first conductive structure 14, a first peripheral through hole 172, a first upper pad 162, a second lower pad 252, a second conductive structure 24, a second peripheral through hole 272, a second upper pad 262, a third lower pad 352, a third conductive structure 34, a third peripheral through hole 372, a third upper pad 362, a fourth lower pad 452, a fourth conductive structure 44, a fourth peripheral through hole 472, a fourth upper pad 462, a lower pad 752, a thermally conductive layer 74, and a thermal through hole 77.

[0129] Therefore, the heat generated by the electronic device 6 can be easily and quickly dissipated or transferred to the heat port 77 through the thermal path 94. This improves the reliability and lifespan of the package structure 6'.

[0130] Referring to Figure 25, a cross-sectional view of an assembly structure 8 illustrating some embodiments of this disclosure is shown. The assembly structure 8 may be a semiconductor structure and may include an interposer 80 (or substrate 80), a package structure 6', a semiconductor device 82, and a plurality of external connectors 84.

[0131] Intermediate layer 80 may include a base portion, a conductive structure, and a plurality of conductive vias. The base portion may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, substrate 80 may be a printed circuit board (PCB).

[0132] A conductive structure may be provided on the base portion. In some embodiments, the conductive structure may include a redistribution layer (RDL) structure. Conductive vias may extend through the base portion and may be electrically connected to the conductive structure.

[0133] An external connector 84 may be disposed on the bottom surface of the interposer 80 for external connection. The external connector 84 may include a reflowable material, such as silver tin (AgSn). Therefore, the external connector 84 may include solder balls, solder bumps, or microbumps. The external connector 84 may be disposed on a conductive via.

[0134] The package structure 6' in Figure 25 can be the package structure 6' in Figure 24. The package structure 6' can be coupled to and electrically connected to the interposer 80 via an external connector 68.

[0135] Semiconductor device 82 can be a logic chip or logic die. Semiconductor device 82 can be bonded to and electrically connected to interposer 80 by a plurality of solders 83. Therefore, package structure 6' can be electrically connected to or communicate with semiconductor device 82 through interposer 80.

[0136] One aspect of this disclosure provides a packaging structure including an electronic device and a heat sink structure. The heat sink structure is disposed on the electronic device and includes a base portion, a plurality of thermal vias, and a thermally conductive layer. The plurality of thermal vias extend through the base portion. The thermally conductive layer is disposed between the base portion and the electronic device. The plurality of thermal vias are thermally connected to the electronic device through the thermally conductive layer to dissipate heat generated by the electronic device.

[0137] Another aspect of this disclosure provides a packaging structure including an electronic device and a heat sink structure. The heat sink structure is disposed on the electronic device and includes a thermally conductive layer, a plurality of thermal vias, and a plurality of pads. The plurality of thermal vias are connected to a second surface of the thermally conductive layer. The plurality of pads are connected to a first surface of the thermally conductive layer. The plurality of pads are thermally connected to the electronic device to dissipate heat generated by the electronic device through the thermally conductive layer to the thermal vias.

[0138] Another aspect of this disclosure provides a method for manufacturing a packaging structure, comprising: providing an electronic device; providing a heat sink structure, wherein the heat sink structure includes a thermally conductive layer, a plurality of heat-perforated holes disposed in the electronic device, and a thermally conductive layer connecting the plurality of heat-perforated holes; and thermally connecting the heat sink structure to the electronic device, wherein the thermally conductive layer is disposed between a base portion and the electronic device.

[0139] Due to the design of the package structure disclosed herein, the heat generated by the electronic device can be easily and quickly dissipated or transferred to the heat dissipation via through the thermal path. Therefore, the reliability and lifespan of the package structure can be improved.

[0140] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0141] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0142] 1: First Semiconductor Wafer 1': First wafer 2: Second semiconductor wafer 3: Third semiconductor wafer 4: Fourth Semiconductor Wafer 5: Base semiconductor wafer 5': Fifth wafer 5a: Molded structure 6: Electronic devices 6': Packaging structure 6a: Electronic devices 7: Heat sink structure 7': Sixth wafer 7a: Unit 8: Assembly Structure 10: First base section 11: First Surface 12: Second Surface 13: Side surface 14: First conductive structure 15: First lower structure 16: First superstructure 17: First conductive via 18: Unit 19: Divider 20: Second base section 21: First Surface 22: Second Surface 23: Side surface 24: Second conductive structure 25: Second lower structure 26: Second superstructure 27: Second conductive via 30: Third base section 31: First Surface 32: Second surface 33: Side surface 34: Third conductive structure 35: Third lower structure 36: Third superstructure 37: Third conductive via 40: Fourth base section 41: First Surface 42: Second surface 43: Side surface 44: Fourth conductive structure 45: Fourth lower structure 46: Fourth upper structure 47: Fourth conductive via 50: Fifth base section 51: Bottom surface 52: Top surface 53: Side surface 54: Fifth conductive structure 55: Fifth upper structure 56: Dielectric layer 57: Fifth conductive via 58: Unit 59: Divider line 59a: Divider 61: First Surface 62: Second surface 63: Side surface 65: Encapsulant 68: External connector 70: The Sixth Base Section 71: Bottom surface 72: Top surface 73: Side surface 74: Thermal conductive layer 75: Substructure 76: Dielectric Structure 77: Heat port 78: Protective materials 79: Divider 80: Intermediary layer 82: Semiconductor Devices 83: Solder 84: External Connector 92: Carrier 94: Heat Path 101: First Surface 102: Second Surface 141: First dielectric layer 142: Pad 143: Second dielectric layer 144: Pad 145: Third dielectric layer 146: Internal through hole 151: First lower dielectric layer 152: First lower pad 161: First upper dielectric layer 162: First upper pad 171: First central through hole 172: First peripheral through hole 251: Second lower dielectric layer 252: Second lower pad 261: Second upper dielectric layer 262: Second upper pad 351: Third lower dielectric layer 352: Third lower pad 361: Third upper dielectric layer 362: Third upper pad 402: Second Surface 451: Fourth lower dielectric layer 452: Fourth lower pad 461: Fourth upper dielectric layer 462: Fourth upper pad 501: First Surface 502: Second Surface 541: First dielectric layer 542: Pad 543: Second dielectric layer 544: Pad 545: Third dielectric layer 546: Internal through hole 551: Fifth upper dielectric layer 552: Fifth upper pad 571: Fifth center through hole 572: Fifth peripheral through hole 573: Conductive Materials 574: Barrier Layer 575: Lining 652: Top surface 701: First Surface 702: Second Surface 703: Side surface 741: First Surface 742: Second Surface 743: Line 744: Intersection 751: Lower dielectric layer 752: Lower pad 761: First dielectric layer 762: Second dielectric layer 773: Conductive Materials 774: Barrier Layer 783: Side surface 900: Method A: Area B: Area L1: Length L7: Length S901: Steps S902: Steps S903: Steps T1: Thickness T7: Thickness

Claims

1. A packaging structure, comprising: An electronic device; The device also includes a heat sink structure disposed on the electronic device, comprising: a base portion including a first surface and a second surface opposite to the first surface; a thermally conductive layer including a first surface and a second surface opposite to the first surface; a dielectric structure disposed on the first surface of the base portion and encapsulating the thermally conductive layer, wherein a portion of the dielectric structure is disposed between the thermally conductive layer and the base portion; a plurality of thermal vias connected to the second surface of the thermally conductive layer and extending beyond the second surface of the base portion; and a plurality of pads connected to the first surface of the thermally conductive layer, wherein the plurality of pads are thermally connected to the electronic device to dissipate the heat generated by the electronic device through the thermally conductive layer to the plurality of thermal vias.

2. The packaging structure as described in claim 1, wherein the heat sink structure is attached to the electronic device by hybrid bonding.

3. The packaging structure as described in claim 1, wherein the thermally conductive layer has a mesh shape.

4. The packaging structure as described in claim 3, wherein the thermally conductive layer comprises a plurality of lines intersecting each other to form a plurality of intersecting portions.

5. The packaging structure as described in claim 4, wherein the plurality of thermal vias are connected to the plurality of intersections of the thermally conductive layer.

6. The packaging structure as described in claim 1, wherein the heat sink structure further includes: A protective material is used to encapsulate the plurality of thermal vias.

7. The packaging structure as described in claim 1, wherein one side surface of the heat sink structure is substantially aligned with one side surface of the electronic device.

8. The packaging structure as described in claim 1, wherein the electronic device further includes: The first semiconductor chip; A second semiconductor wafer, stacked on and electrically connected to the first semiconductor wafer; a third semiconductor wafer, stacked on and electrically connected to the second semiconductor wafer; a fourth semiconductor wafer, stacked on and electrically connected to the third semiconductor wafer; and an encapsulant for encapsulating the first semiconductor wafer, the second semiconductor wafer, the third semiconductor wafer, and the fourth semiconductor wafer.

9. A method for manufacturing a packaging structure, comprising: Provide an electronic device; A heat sink structure is provided, wherein the steps of providing the heat sink structure include: providing a base portion including a first surface and a second surface opposite to the first surface; forming a plurality of thermal vias in the base portion; forming a thermally conductive layer on the base portion to connect the plurality of thermal vias; forming a dielectric structure on the first surface of the base portion and encapsulating the thermally conductive layer, wherein a portion of the dielectric structure is disposed between the thermally conductive layer and the base portion; and thermally connecting the heat sink structure to an electronic device, wherein the thermally conductive layer is disposed between the base portion and the electronic device, wherein the step of thermally connecting the heat sink structure to the electronic device includes: thinning the base portion to expose the plurality of thermal vias, such that the plurality of thermal vias extend beyond the second surface of the base portion.

10. The manufacturing method of claim 9, wherein the plurality of thermal vias are connected to a second surface of the thermally conductive layer, and the heat sink structure includes a plurality of pads connected to a first surface of the thermally conductive layer, wherein the step of thermally connecting the heat sink structure to the electronic device further includes: The plurality of pads are thermally connected to the electronic device.

11. The manufacturing method as claimed in claim 9, wherein the step of thermally connecting the heat sink structure to the electronic device further comprises: The heat sink structure is attached to the electronic device by hybrid bonding.

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