Semiconductor device with t-shaped buried gate electrode

Abstract

This disclosure provides a semiconductor device with a T-shaped buried gate electrode and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of long active regions; a first gate electrode disposed in a dielectric layer above the semiconductor substrate and extending into the semiconductor substrate; and a first source / drain region and a second source / drain region disposed in the long active regions and located on opposite sides of the first gate electrode. The equally long active regions extend along a first direction and are parallel to each other. The first gate electrode has a first portion extending through the long active regions and a second portion extending into the first source / drain regions.

Claims

1. A semiconductor element, comprising: A semiconductor substrate having a plurality of long active regions, wherein the equally long active regions extend along a first direction and are parallel to each other; A first gate electrode is disposed in a dielectric layer above the semiconductor substrate and extends into the semiconductor substrate; a first source / drain region and a second source / drain region are disposed in the long active region and located on opposite sides of the first gate electrode; and a plurality of virtual active regions are located between the equally long active regions, wherein the first gate electrode has a first portion extending through the long active region and a second portion extending into the first source / drain region.

2. The semiconductor device as claimed in claim 1, wherein the long active region is implemented in a test element group (TEG).

3. The semiconductor element as claimed in claim 1, wherein the virtual active regions located between two adjacent long active regions are arranged continuously and separated from each other in the first direction.

4. The semiconductor element as claimed in claim 1, wherein the virtual active regions located in different pairs of equal-length active regions are arranged alternately.

5. The semiconductor element as claimed in claim 4, wherein the virtual active regions located in different pairs of equal-length active regions are arranged along a second direction, wherein the second direction is a mirror image of the first direction relative to a reference direction.

6. The semiconductor device as claimed in claim 1, wherein the second portion of the first gate electrode is located within the long active region.

7. The semiconductor device as claimed in claim 6, wherein the first portion and the second portion of the first gate electrode form a right angle.

8. The semiconductor device as described in claim 1, further comprising: A second gate electrode is disposed in the semiconductor substrate; And a third source / drain region is disposed in the long active region, wherein the second source / drain region and the third source / drain region are located on opposite sides of the second gate electrode, wherein the second gate electrode has a third portion extending through the long active region and a fourth portion extending into the third source / drain region.

9. The semiconductor device as claimed in claim 8, wherein the second source / drain region is located between the first gate electrode and the second gate electrode, and the second portion of the first gate electrode and the fourth portion of the second gate electrode extend parallel to each other.

10. A semiconductor element, comprising: A semiconductor substrate; Multiple long active regions are disposed in the semiconductor substrate, wherein the equally long active regions extend along a first direction and are parallel to each other; A first gate structure is disposed in a dielectric layer above the semiconductor substrate and extends into the semiconductor substrate. The first gate structure includes a first word line insulating layer, a first word line barrier layer, a first word line conductive layer, and a first word line capping layer. A first source / drain region and a second source / drain region are disposed in the long active region and located on opposite sides of the first gate structure. The first word line conductive layer has a first portion extending through the long active region and a second portion extending into the first source / drain region.

11. The semiconductor device as claimed in claim 10, wherein the first word line barrier layer is disposed between the first word line insulating layer and the first word line conductive layer.

12. The semiconductor device as claimed in claim 10, wherein the first word line conductive layer includes a nucleation portion and a body portion surrounded by the nucleation portion.

13. The semiconductor device as claimed in claim 12, wherein the nucleation portion and the bulk portion comprise tungsten.

14. The semiconductor device as claimed in claim 10, wherein the second portion of the first word line conductive layer is located within a long active region.

15. The semiconductor element as claimed in claim 14, wherein the first portion of the first character line conductive layer forms a right angle with the second portion.

16. The semiconductor device as described in claim 10, further comprising: A second gate structure is disposed in the dielectric layer above the semiconductor substrate and extends into the semiconductor substrate; A third source / drain region is disposed in the long active region, wherein the second source / drain region and the third source / drain region are located on opposite sides of the second gate structure, wherein the second gate structure includes a second word line insulating layer, a second word line barrier layer, a second word line conductive layer and a second word line cover layer.

17. The semiconductor device as claimed in claim 16, wherein the second word line conductive layer includes a nucleation portion and a body portion surrounded by the nucleation portion.

18. The semiconductor device as claimed in claim 16, wherein the second word line conductive layer includes a third portion extending through the long active region and a fourth portion extending into the third source / drain region.

19. The semiconductor device as claimed in claim 17, wherein the nucleation portion and the bulk portion comprise tungsten.

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