Vertically charge transferring pixel sensor and manufacturing method thereof

Abstract

This invention relates to a vertical charge transfer imaging sensor and its manufacturing method. In the vertical charge transfer imaging sensor, a plurality of substrate pixel units are formed by separating the substrate using a deep trench isolation structure (DTI). By allowing the DTI to penetrate the substrate to physically isolate each substrate pixel unit, photoelectric crosstalk between corresponding pixels of each substrate pixel unit can be avoided, improving device performance. Furthermore, each substrate pixel unit is divided into a photosensitive area, a charge readout area, and a substrate lead-out area using a shallow trench isolation structure. Corresponding to the pixel formed by the substrate pixel unit, the substrate pixel unit and the gate structure constitute a MOS capacitor. The substrate pixel unit is the substrate electrode of the MOS capacitor, and the substrate lead-out area is the connection terminal of the substrate pixel unit. External signals can be connected to the substrate lead-out area from the front side of the substrate to apply voltage to the substrate electrode through the substrate lead-out area.

Description

Technical Field

[0001] This invention relates to the field of photosensitive technology, and more particularly to a vertical charge transfer imaging sensor and a method for manufacturing a vertical charge transfer imaging sensor. Prior Technology

[0002] Vertically charge-transferring (VCT) imaging sensors utilize a substrate and a floating-gate transistor structure for imaging. Figure 1 is a planar schematic of the pixels in a VCT. Figure 2 is a cross-sectional schematic of the VCT along the XX' direction in Figure 1. Referring to Figures 1 and 2, a vertical charge transfer imaging sensor typically includes multiple pixels formed on a substrate 10. Each pixel has a photosensitive area 11 and a charge readout area 12 formed in the substrate 10 and separated by a shallow trench isolation structure (STI). A gate structure is formed on the photosensitive area 11 and the charge readout area 12 and includes a gate dielectric layer GOX, a floating gate FG, an inter-gate dielectric layer 13, and a control gate CG stacked sequentially. A source region S and a drain region D are formed on the charge readout area 12 and are located on both sides of the control gate (CG), respectively. The gate structure and the substrate 10 below it form a MOS capacitor, wherein the control gate (CG) and the substrate 10 are the two electrodes of the MOS capacitor, respectively. The gate structure, the source region S, and the drain region D form a readout transistor with a floating gate transistor structure. When light enters the substrate 10 from the side away from the gate structure, it will collide with the lattice of the substrate 10 to generate photoelectrons. By applying a suitable bias voltage to the MOS capacitor, the photoelectrons can move toward the control gate CG and gather on the surface of the photosensitive area 11 or cross the energy barrier to enter the floating gate (FG), thereby causing the drain current and / or threshold voltage of the read transistor to change. By detecting this change, photoelectric sensing and imaging can be realized.

[0003] Compared to traditional photodiode-based sensing devices (such as CMOS image sensors), vertical charge transfer imaging sensors can achieve higher full-well charge (or potential well capacity) with the same pixel area, resulting in a higher signal-to-noise ratio and facilitating pixel miniaturization.

[0004] As shown in Figure 2, existing technology forms deep trench isolation structures (DTI) between different pixels to reduce photoelectric crosstalk between adjacent pixels. A substrate layer 14 of appropriate thickness is maintained between the bottom surface of the DTI and the back surface of the substrate 10. This substrate layer 14 connects to the substrate portion corresponding to each pixel. During operation, a voltage can be applied to this substrate layer 14 from the back surface of the substrate 10 to apply voltage to the substrate electrode of the aforementioned MOS capacitor. However, photoelectrons formed by incident light within the substrate 10 can generate crosstalk through the substrate layer 14, affecting device performance. Furthermore, to reduce the thickness of the substrate layer 14 and thus reduce crosstalk, part of the bottom surface of the DTI may be exposed from the back surface of the substrate 10 while another part is not exposed, resulting in an uneven back surface of the substrate 10. This is detrimental to processes requiring flatness on one side of the back surface of the substrate 10. Summary of the Invention

[0005] To facilitate the application of voltage to the substrate corresponding to the pixels of a vertical charge transfer imaging sensor while improving the isolation performance between pixels and avoiding photoelectric crosstalk, this invention provides a vertical charge transfer imaging sensor and a method for manufacturing a vertical charge transfer imaging sensor.

[0006] On one hand, the present invention provides a vertical charge transfer imaging sensor, the vertical charge transfer imaging sensor comprising:

[0007] A substrate having a first doping type and comprising a front side and a back side opposite to each other;

[0008] A deep trench isolation structure penetrating the substrate, wherein the deep trench isolation structure separates the substrate to form a plurality of substrate pixel units;

[0009] A shallow trench isolation structure is formed on the front side of the substrate, which divides each substrate pixel unit into a photosensitive area, a charge readout area, and a substrate lead-out area;

[0010] A readout transistor includes a gate structure formed on the front side of the charge readout region and a first source / drain region and a second source / drain region formed on both sides of the charge readout region, wherein the gate structure extends from the charge readout region to the photosensitive region; and

[0011] A MOS capacitor is formed by the gate structure and the corresponding substrate pixel unit, wherein the substrate pixel unit is the substrate electrode of the MOS capacitor, and the substrate lead-out region is the voltage application region of the substrate electrode.

[0012] Optionally, the vertical charge transfer imaging sensor further includes:

[0013] An interlayer dielectric layer covers the plurality of substrate pixel units, the deep trench isolation structure, the shallow trench isolation structure, the read transistor, and the MOS capacitor from the front side;

[0014] A first source / drain plug penetrates the interlayer dielectric layer to connect to the first source / drain region;

[0015] A second source / drain plug, penetrating the interlayer dielectric layer to connect to the second source / drain region; and

[0016] Substrate electrode plugs penetrate the interlayer dielectric layer to connect to the substrate lead-out region.

[0017] Optionally, the gate structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate stacked on the surfaces of the photosensitive area and the charge readout area of ​​the substrate pixel unit.

[0018] Optionally, the vertical charge transfer imaging sensor includes:

[0019] At least one word line is formed by connecting the control gates in the gate structure on at least two of the substrate pixel units.

[0020] Optionally, the concentration of a first doping type on the surface of the substrate lead-out region is greater than that of the surrounding substrate, and the first source / drain region and the second source / drain region have a second doping type.

[0021] Optionally, the end face of the deep trench isolation structure that faces the same direction as the back surface of the substrate pixel unit is flush with the back surface of the substrate pixel unit.

[0022] Optionally, the vertical charge transfer imaging sensor further includes:

[0023] The back dielectric layer includes a high dielectric constant layer covering the deep trench isolation structure and the substrate pixel unit from the back side of the substrate, and an oxide layer covering the high dielectric constant layer.

[0024] On one hand, the present invention provides a method for manufacturing a vertical charge transfer imaging sensor, the method comprising:

[0025] A substrate is provided, the substrate having a first doping type and including a front side and a back side opposite to each other;

[0026] A deep trench isolation structure and a shallow trench isolation structure are formed on the front side of the substrate. The deep trench isolation structure and the shallow trench isolation structure extend from one side of the front side into the substrate. The deep trench isolation structure separates the substrate to form a plurality of substrate pixel units, and the shallow trench isolation structure divides each substrate pixel unit into a photosensitive area, a charge readout area, and a substrate lead-out area.

[0027] A gate structure is formed on the surface of each substrate pixel unit corresponding to the front side of the substrate, and a first source / drain region and a second source / drain region are formed on the charge readout regions on both sides of the gate structure to form a readout transistor, wherein the gate structure extends from the charge readout region to the photosensitive region and forms a MOS capacitor with the corresponding substrate pixel unit; and

[0028] The substrate is thinned from the back side to expose the deep trench isolation structure and the plurality of substrate pixel units separated by the deep trench isolation structure.

[0029] Optionally, before thinning the substrate from the back side, the manufacturing method further includes:

[0030] A patterned mask layer is formed on the substrate, and openings in the mask layer expose lead-out areas of the substrate; and

[0031] The surface of the substrate lead-out region is implanted with first-type doped ions, such that the concentration of the first-type doping on the surface of the substrate lead-out region is greater than that of the surrounding substrate.

[0032] Optionally, before thinning the substrate from the back side, the manufacturing method further includes:

[0033] An interlayer dielectric layer is formed on the front side of the substrate; and

[0034] A first source / drain plug, a second source / drain plug, and a substrate electrode plug are formed that penetrate the interlayer dielectric layer. The first source / drain plug is connected to the first source / drain region, the second source / drain plug is connected to the second source / drain region, and the substrate electrode plug is connected to the substrate lead-out region.

[0035] Optionally, thinning the substrate from the back side includes:

[0036] The back side of the substrate is polished using a CMP process to expose the deep trench isolation structure and the plurality of substrate pixel units from the back side of the substrate; and

[0037] A back dielectric layer is formed, the back dielectric layer comprising a high dielectric constant layer covering the deep trench isolation structure and the substrate pixel unit from the back side of the substrate, and a low dielectric constant layer covering the high dielectric constant layer.

[0038] Optionally, after the CMP process is completed, wet etching is performed to remove damage to the surface of the substrate pixel unit.

[0039] In the vertical charge transfer imaging sensor and its manufacturing method provided by the present invention, a plurality of substrate pixel units are formed by separating the substrate using the deep trench isolation structure (DTI). By allowing the DTI to penetrate the substrate to physically isolate each substrate pixel unit, photoelectric crosstalk between corresponding pixels of each substrate pixel unit can be avoided, thereby improving device performance. Furthermore, each substrate pixel unit is divided into a photosensitive area, a charge readout area, and a substrate lead-out area using the shallow trench isolation structure. Corresponding to the pixel formed by the substrate pixel unit, the substrate pixel unit and the gate structure constitute a MOS capacitor. The substrate pixel unit is the substrate electrode of the MOS capacitor, and the substrate lead-out area is the connection terminal of the substrate pixel unit. The substrate lead-out area can be connected to a corresponding external signal from the front side of the substrate to apply a voltage to the substrate electrode through the substrate lead-out area. Simple Explanation of the Diagram

[0040] Figure 1 is a planar schematic diagram of the pixels of the vertical charge transfer imaging sensor. Figure 2 is a cross-sectional schematic diagram of the vertical charge transfer imaging sensor along the XX' direction in Figure 1. Figure 3 is a planar schematic diagram of a vertical charge transfer imaging sensor according to an embodiment of the present invention. Figures 4 and 5 are schematic cross-sectional views along lines A-A' and B-B' in Figure 3, respectively. Figure 6 is a flowchart illustrating a method for manufacturing a vertical charge transfer imaging sensor according to an embodiment of the present invention. Figures 7 to 28 are schematic cross-sectional views of a method for manufacturing a vertical charge transfer imaging sensor according to an embodiment of the present invention. Implementation

[0041] The vertical charge transfer imaging sensor and its manufacturing method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. The embodiments of the present invention should not be considered as limited to the specific shapes of the areas shown in the drawings, but may include actual shapes, such as those caused by manufacturing deviations.

[0042] Referring to Figures 3, 4, and 5, according to an embodiment of the present invention, a vertical charge transfer imaging sensor includes a substrate (or base plate) 100, a deep trench isolation structure (DTI), a shallow trench isolation structure (STI), a readout transistor, and a MOS capacitor. Detailed description follows.

[0043] The substrate 100 can be made of various suitable substrates in the art, and its material may include silicon, germanium, silicon-germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide, etc. The substrate 100 has a first doping type, such as p-type or n-type; this embodiment uses p-type as an example. The substrate 100 is, for example, a silicon substrate doped with boron or boron difluoride. The substrate 100 has a front side 100a and a back side 100b that are opposite to each other.

[0044] A deep trench isolation structure (DTI) penetrates the substrate 100, separating the substrate 100 to form multiple substrate pixel units 110. The DTI may include deep trenches penetrating the substrate 100 along its thickness direction and an isolation dielectric (such as silicon oxide or silicon nitride) filling the deep trenches. By making the DTI penetrate the substrate 100, each substrate pixel unit 110 is physically isolated, avoiding photoelectric crosstalk between corresponding pixels of each substrate pixel unit 110, thereby improving device performance.

[0045] As an example, the deep trench isolation structure (DTI) includes a deep trench penetrating a substrate 100, a linear dielectric layer (or linear oxide layer) 103 formed within the deep trench, a trench electrode 104a, and a capping layer 105. The linear dielectric layer 103 covers the sidewalls of the deep trench. The trench electrode 104a and the capping layer 105 fill the deep trench and are isolated from the substrate 100 by the linear dielectric layer 103. The capping layer 105 is located on the side of the trench electrode 104a closest to the front surface 100a of the substrate 10. The trench electrode 104a provides an operable electrode terminal for the vertical charge transfer imaging sensor. Combined with other electrode terminals in the sensor, diverse operating modes can be achieved. For example, by applying a positive bias voltage between the substrate 100 and the trench electrode 104a, the potential energy barrier at the interface between the deep trench isolation structure (DTI) and the substrate 100 can be increased, reducing the probability of photoelectrons being trapped at this interface, thus helping to improve photoelectric conversion efficiency and alleviate dark current and white pixel problems. The trench electrode 104a can extend laterally along the deep trench to the peripheral region of the substrate 100 to connect with external electrical signals.

[0046] As an example, the end face of the deep trench isolation structure DTI, which faces the back surface 100b of the substrate pixel unit 110, is flush with the back surface 100b of the substrate pixel unit 110 (i.e., the height difference between the end face and the back surface of the substrate pixel unit 110 is within a set requirement range). This means that the end face and the back surface 100b of the substrate pixel unit 110 have better flatness, which makes it more convenient to carry out processes based on this vertical charge transfer imaging sensor that require flatness on one side of the back surface 100b of the substrate 100.

[0047] A shallow trench isolation structure (STI) is formed on the front side 100a of the substrate 100. It may include shallow trenches formed from one side of the front side 100a of the substrate 100 and an isolation dielectric (such as silicon oxide or silicon nitride) filling the shallow trenches. As shown in FIG3, according to an embodiment of the present invention, the shallow trench isolation structure (STI) divides each substrate pixel unit 110 into a photosensitive area 110a, a charge readout area 110b, and a substrate lead-out area 110c. As an example, the cross-sectional shape of the substrate pixel unit 110, the photosensitive area 110a, the charge readout area 110b, and the substrate lead-out area 110c are all rectangular, and a pair of parallel sides of each of the charge readout area 110b and the substrate lead-out area 110c are parallel to a pair of parallel sides of the substrate pixel unit 110.

[0048] Referring to Figure 3, as an example, the substrate pixel unit 110 is, for example, square. The photosensitive area 110a, the charge readout area 110b, and the substrate lead-out area 110c have the same length and width directions. The length of the photosensitive area 110a is equal to the side length of the substrate pixel unit 110, and the sum of the width of the photosensitive area 110a, the width of the charge readout area 110b, and the width of the shallow trench isolation structure STI is equal to the side length of the substrate pixel unit 110. The widths of the charge readout area 110b and the substrate lead-out area 110c are equal, and the sum of the lengths of the charge readout area 110b, the substrate lead-out area 110c, and the shallow trench isolation structure STI is equal to the side length of the substrate pixel unit 110. It is understood that the present invention is not limited thereto. The cross-sectional shape of the substrate pixel unit 110, the photosensitive area 110a, the charge reading area 110b, and the substrate lead-out area 110c can also be other shapes or have other dimensional relationships. The positional distribution of the photosensitive area 110a, the charge reading area 110b, and the substrate lead-out area 110c can be adjusted according to the actual situation. As an example, referring to Figure 3, multiple substrate pixel units 110 are arranged in rows and columns, with the column direction parallel to line AA' for example and the row direction parallel to line BB' for example. In at least two adjacent substrate pixel units 110 in the same column, the charge readout area 110b and substrate lead-out area 110c of one substrate pixel unit 110 are adjacent to the photosensitive area 110a of another substrate pixel unit 110. In at least two adjacent substrate pixel units 110 in the same row, the substrate lead-out area 110c of one substrate pixel unit 110 is adjacent to the substrate lead-out area 110c of another substrate pixel unit 110, and the substrate lead-out area 110c and the charge readout area 110b in the substrate pixel unit 110 are aligned in the row direction. However, the present invention is not limited to this, and the arrangement of the photosensitive area 110a, charge readout area 110b, and substrate lead-out area 110c in different substrate pixel units 110 can be adjusted according to actual conditions.

[0049] Each substrate pixel unit 110 has the readout transistor formed on it. Referring to Figures 4 and 5, the readout transistor includes a gate structure 120 formed on the front side 100a of the charge readout region 110b and a first source / drain region and a second source / drain region (both represented by S / D in the figures) formed on both sides of the charge readout region 110b of the gate structure 120. In each substrate pixel unit 110, the gate structure 120 extends from the charge readout region 110b to the photosensitive region 110a (refer to Figure 3).

[0050] Referring to Figures 4 and 5, the gate structure 120 may include a gate dielectric layer 106, a floating gate FG, an inter-gate dielectric layer 108, and a control gate CG stacked on the surfaces of the photosensitive area 110a and the charge readout area 110b of the substrate pixel unit 110. In this embodiment, the floating gate FG, the inter-gate dielectric layer 108, and the control gate CG in the gate structure 120 extend from the photosensitive area 110a to the charge readout area 110b, and the first source / drain region and the second source / drain region are exposed on both sides of the extension direction, respectively. The vertical charge transfer imaging sensor may include multiple word lines (WL1 and WL2 as shown in Figure 3), each word line being formed by connecting at least two control gate CGs in the gate structure 110 on the substrate pixel unit 100.

[0051] The MOS capacitor is formed corresponding to each substrate pixel unit 110. Specifically, the MOS capacitor is formed by a gate structure 120 and the substrate pixel unit 110 below it, wherein the substrate pixel unit 110 is the substrate electrode of the MOS capacitor, and the control gate CG constitutes the other electrode of the MOS capacitor. The substrate lead-out region 110c is the voltage application region of the substrate electrode. In order to reduce the contact resistance of the substrate lead-out region 110c, optionally, the first doping type concentration of the top of the substrate lead-out region 110c facing the front side 100a is greater than the first doping type concentration of the surrounding substrate 100, for example, having p-type heavy doping (p+).

[0052] The aforementioned substrate pixel unit 110, along with the readout transistor and MOS capacitor formed on the substrate pixel unit 110, constitute the pixel of the vertical charge transfer imaging sensor. During operation, pressure can be applied to the two electrodes of the MOS capacitor, causing the control gate CG to be positively biased relative to the substrate pixel unit 110, thus forming a depletion region in the substrate pixel unit 110. When light is incident from the back surface 100b of the substrate 100, it collides with the substrate lattice to generate photoelectrons. Under the influence of the electric field in the depletion region, the photoelectrons accumulate on the surface of the photosensitive area 110a or cross the energy barrier to enter the floating gate FG. Since the photosensitive area 110a and the floating gate FG of the charge readout area 110b are connected, the accumulation of photoelectrons causes a change in the state of the floating gate FG of the charge readout area 110b, which in turn causes a change in the drain current and / or threshold voltage of the readout transistor. The vertical charge transfer imaging sensor detects this change to achieve photoelectric sensing and imaging. This article uses an N-type readout transistor in a vertical charge transfer imaging sensor pixel as an example, where the source region S and drain region D are n-type doped. It can be understood that in the case of a p-type readout transistor, the source region S and drain region D are p-type doped.

[0053] Referring to Figures 4 and 5, on the front side 100a of the substrate 100, the vertical charge transfer imaging sensor may further include an interlayer dielectric layer 130, a first source / drain plug CT1, a second source / drain plug CT2, and a substrate electrode plug CT3. The interlayer dielectric layer 130 covers multiple substrate pixel units 110, a deep trench isolation structure (DTI), a shallow trench isolation structure (STI), the readout transistor, and the MOS capacitor from the front side 100a. The first source / drain plug CT1 penetrates the interlayer dielectric layer 130 to connect to the first source / drain region, the second source / drain plug CT2 penetrates the interlayer dielectric layer 130 to connect to the second source / drain region, and the substrate electrode plug CT3 penetrates the interlayer dielectric layer 130 to connect to the substrate lead-out region 110c. Metal interconnect structures and multiple metal pads (not shown) may also be formed on the interlayer dielectric layer 130. The first source / drain region can be connected to the corresponding metal pads through the metal interconnect structure. As an example, when the device is working, the metal pads are connected to an external power supply to apply voltage to the first source / drain region, the second source / drain region, and the substrate lead-out region 110c. In this embodiment, since each substrate pixel unit 110 has a substrate lead-out region 110c, the voltage applied to each substrate pixel unit 110 is more uniform, which helps to improve the performance of the vertical charge transfer imaging sensor.

[0054] Referring to Figures 4 and 5, on the back side 100b of the substrate 100, the vertical charge transfer imaging sensor may further include a back dielectric layer 140. Specifically, the back dielectric layer 140 may include a high dielectric constant layer 141 covering the deep trench isolation structure (DTI) and each substrate pixel unit 110 from the back side 100b of the substrate 100, and an oxide layer 142 (such as silicon oxide) covering the high dielectric constant layer 141. The high dielectric constant layer 141 is formed using a material with a high dielectric constant (e.g., greater than 3.9) (such as Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), or TiO2, etc.). By utilizing the high dielectric constant layer 141, the potential energy barrier of the back side 100b of the substrate 100 can be improved, reducing the probability of photoelectrons being trapped near the back side 100b of the substrate 100, which helps to improve the photoelectric conversion efficiency.

[0055] This invention also relates to a method for manufacturing a vertical charge transfer imaging sensor, which can be used to fabricate the vertical charge transfer imaging sensor described in the above embodiments. Figures 7 to 28 are schematic cross-sectional views of a method for manufacturing a vertical charge transfer imaging sensor according to an embodiment of the present invention. The method for manufacturing the vertical charge transfer imaging sensor will be described below with reference to Figures 3, 6, and 7 to 28.

[0056] Figures 7 and 8 are cross-sections along lines A-A' and B-B' in Figure 3, respectively, after the deep trench DT is formed in the substrate 100. Referring to Figures 3, 6, 7, and 8, step S1 is performed to provide a substrate 100, which has a first doping type and includes a front side 100a and a back side 100b facing away from each other. As an example, the substrate 100 is, for example, a silicon substrate and has p-type doping. The surface of the substrate 100 used to form the floating transistor structure is the front side 100a, and the surface facing away from the front side 100a is the back side 100b.

[0057] Referring to Figure 6, step S2 is performed, forming a deep trench isolation structure (DTI) and a shallow trench isolation structure (STI) on the front side 100a of the substrate 100. The deep trench isolation structure (DTI) and the shallow trench isolation structure (STI) extend from the front side 100a into the substrate 100. The deep trench isolation structure (DTI) separates the substrate 100 to form a plurality of substrate pixel units 110. The shallow trench isolation structure (STI) divides each substrate pixel unit 110 into a photosensitive area 110a, a charge readout area 110b, and a substrate lead-out area 110c.

[0058] The shallow trench isolation structure (STI) may include a shallow trench formed from one side of the front side 100a of the substrate 100 and an isolation dielectric filling the shallow trench. The deep trench isolation structure (DTI) may include a deep trench formed from one side of the front side 100a of the substrate 100 and an isolation dielectric filling the deep trench. The isolation dielectric in the deep trench isolation structure (DTI) and the shallow trench isolation structure (STI) may include silicon oxide and / or silicon nitride, etc. The shallow trench isolation structure (STI) and the deep trench isolation structure (DTI) can be formed using conventional trench isolation fabrication processes, and this application does not impose any special limitations on the specific formation process of the shallow trench isolation structure (STI) and the deep trench isolation structure (DTI). As an example, the deep trench isolation structure (DTI) includes a deep trench formed on the front side 100a of the substrate 100, an isolation dielectric filling the deep trench, and a trench electrode, which provides an operable electrode terminal for a vertical charge transfer imaging sensor. The following example illustrates the fabrication process for forming a shallow trench isolation structure (STI) and a deep trench isolation structure (DTI) including the trench electrodes, wherein the same dielectric deposition process is used to fill the shallow trench with an isolation dielectric and to fill the top of the deep trench with an isolation dielectric. The invention is not limited thereto; for example, in another embodiment, the shallow trench is first filled with an isolation dielectric to form the STI, and then the deep trench and the deep trench isolation structure (DTI) are fabricated.

[0059] In step S2, as an example, referring to Figures 3, 7, and 8, a pad oxide layer 101, at least one hard mask (such as hard mask layer 102), an anti-reflective film (not shown), and a photoresist layer (not shown) can be formed on the surface of the substrate 100. A dry etching process is then performed according to the deep trench pattern to form a deep trench DT extending from the front side 100a into the substrate 100. The pad oxide layer 101 is, for example, made of silicon oxide, and the hard mask layer 102 is, for example, made of silicon nitride. At this time, the bottom surface of the deep trench DT is located within the substrate 100, forming a plurality of substrate pixel units 110 isolated by the deep trench DT.

[0060] Figures 9 and 10 show cross-sections along lines A-A' and B-B' in Figure 3 after filling the deep trench DT. Referring to Figures 3, 9, and 10, a linear oxide layer (or linear dielectric layer 103) can be formed on the surface of the deep trench DT using processes such as thermal oxidation, chemical vapor deposition, or atomic layer deposition. Then, conductive material is deposited to fill the deep trench DT and cover it with a hard masking layer 102. The upper surface of the conductive material is then planarized to expose the hard masking layer 102, and the remaining conductive material forms a trench conductive layer 104 within the deep trench DT. The trench conductive layer 104 can be made of a conductive material with good light-shielding properties. Optionally, the trench conductive layer 104 includes one or more of tungsten, tungsten silicide, titanium, titanium nitride, and doped polycrystalline silicon. In this embodiment, the trench conductive layer 104 is, for example, doped polycrystalline silicon. After the conductive material deposition is completed, annealing can be performed to recrystallize the doped polycrystalline silicon to obtain a suitable grain size.

[0061] Figures 11 and 12 show cross-sections along lines A-A' and B-B' in Figure 3 after the shallow trench ST is formed. Referring to Figures 3, 11, and 12, the hard mask layer 102, the pad oxide layer 101, and the substrate 100 are then etched to form a shallow trench ST extending from the front side 100a into the substrate 100. The shallow trench ST is formed within each substrate pixel unit 110, and its depth is less than the depth of the deep trench DT. In this embodiment, the shallow trench ST within each substrate pixel unit 110 divides the substrate pixel unit 110 into a photosensitive area 110a, a charge readout area 110b, and a substrate lead-out area 110c.

[0062] Figures 13 and 14 show cross-sections along lines A-A' and B-B' in Figure 3 after part of the trench conductive layer 104 has been removed. Referring to Figures 3, 13, and 14, the trench conductive layer 104 within the deep trench DT is then etched, making the trench conductive layer 104 lower than the front surface 100a of the substrate 100, thus forming an unfilled space above the deep trench DT. The remaining trench conductive layer 104 forms the trench electrode 104a. At this point, the unfilled space communicates with the shallow trench ST at the top of the substrate 100, with the communication point located at the intersection of the shallow trench ST and the deep trench DT.

[0063] Figures 15 and 16 show cross-sections along lines A-A' and B-B' in Figure 3 after the capping layer 105 is formed in the unfilled space above the deep trench DT and in the shallow trench ST. Referring to Figures 3, 15, and 16, an isolation dielectric, such as one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, and nitrogen-doped silicon carbide, is deposited on the substrate 100. The isolation dielectric fills the upper part of the deep trench DT and the shallow trench ST and covers the surface of the hard masking layer 102. Then, the surface of the hard masking layer 102 is exposed by a planarization process (such as CMP). The remaining isolation dielectric fills the upper part of the deep trench DT and the shallow trench ST, forming the capping layer 105.

[0064] After the above process, a deep trench isolation structure (DTI) and a shallow trench isolation structure (STI) are formed on the front side 100a of the substrate 100 corresponding to the deep trench DT and the shallow trench ST, respectively. The deep trench isolation structure DTI includes a deep trench DT and a linear oxide layer (or linear dielectric layer 103) filling the deep trench DT, a trench electrode 104a, and a capping layer 105. The shallow trench isolation structure STI includes a shallow trench ST and a capping layer 105 filling the shallow trench ST. Furthermore, the deep trench isolation structure DTI separates the substrate 100 to form a plurality of substrate pixel units 110, and the shallow trench isolation structure STI divides each substrate pixel unit 110 into a photosensitive area 110a, a charge readout area 110b, and a substrate lead-out area 110c. The arrangement of the photosensitive area 110a, the charge readout area 110b, and the substrate lead-out area 110c can be referred to the vertical charge transfer imaging sensor described in the above embodiment.

[0065] Referring to Figure 6, step S3 is performed, forming a gate structure on the surface of each substrate pixel unit 110 corresponding to the front surface 100a of the substrate 100, and forming a first source / drain region and a second source / drain region on the charge readout regions 110b on both sides of the gate structure to form a readout transistor. The gate structure extends from the charge readout region 110b to the photosensitive region 110a and forms a MOS capacitor with the corresponding substrate pixel unit 110. The following is an example illustrating the process of forming the gate structure in step S3.

[0066] Figures 17 and 18 show cross-sections along lines A-A' and B-B' in Figure 3 after removing part of the capping layer 105 and hard masking layer 102 in the shallow trench isolation structure (DTI). Referring to Figures 3, 17, and 18, the capping layer 105 in the shallow trench (ST) is first etched so that its top surface is lower than the top surface of the hard masking layer 102 but not lower than the front side 100a of the substrate 100. Then, the hard masking layer 102 is removed. At this point, part of the side surface of the capping layer 105 in the deep trench isolation structure (DTI) is exposed. The pad oxide layer 101 on the surface of the substrate 100 can then be removed, and a gate dielectric layer 106 is formed on the surface of the substrate 100 exposed by the removal of the pad oxide layer 101.

[0067] Figures 19 and 20 show cross-sections along lines A-A' and B-B' in Figure 3 after the floating gate material layer 107 is formed. Referring to Figures 3, 19, and 20, polysilicon is deposited on substrate 100 to cover the gate dielectric layer 106, the shallow trench isolation structure (STI), and the deep trench isolation structure (DTI). The top surface of the polysilicon is then planarized to expose the top surface of the DTI. The remaining polysilicon is stacked on the gate dielectric layer 106 to form the floating gate material layer 107.

[0068] Figures 21 and 22 show cross-sections along lines A-A' and B-B' in Figure 3 after etching away part of the capping layer 105 in the deep trench isolation structure (DTI) and forming the inter-gate dielectric layer 108. Referring to Figures 3, 21, and 22, the capping layer 105 in the DTI is etched such that the top surface of the capping layer 105 is lower than the top surface of the floating gate material layer 107 and higher than the front surface 100a of the substrate 100, thereby forming a groove above the DTI. Then, the inter-gate dielectric layer 108 is formed on the substrate 100, covering the inner surface of the groove and the surface of the floating gate material layer 108. The inter-gate dielectric layer 108 may employ an ONO (oxide-nitride-oxide) structure, for example.

[0069] Figures 23 and 24 show cross-sections along lines A-A' and B-B' in Figure 3 after the gate structure is formed by depositing the control gate material layer and performing an etching process. Referring to Figures 3, 23, and 24, polycrystalline silicon material is first deposited on substrate 100 as the control gate material layer. The control gate material layer fills the groove above the deep trench isolation structure (DTI) and covers each substrate pixel unit 110. Then, the control gate material layer and the lower inter-gate dielectric layer 108 and floating gate material layer 107 are etched to form a gate structure 120 on each substrate pixel unit 110, including a gate dielectric layer 106, a floating gate FG (formed by the floating gate material layer 107), an inter-gate dielectric layer 108, and a control gate FG (formed by the control gate material layer). As shown in Figure 3, in this embodiment, during the etching process to form the gate structure 120, at least one word line (WL1 and WL2 as shown in Figure 3) can be formed by connecting the control gates CG on the substrate pixel units 110 in the same column. As shown in Figure 3, after the gate structure 120 is formed, a portion of the charge readout area 110b in the substrate pixel unit 110 is exposed from both sides of the control gate CG.

[0070] Next, a spacer wall process can be performed to form a spacer wall (not shown) on the side of the gate structure 120; then, source / drain ion implantation is performed on the exposed charge readout region 110b to form a first source / drain region and a second source / drain region (S / D in Figures 25 and 26) on both sides of the gate structure 120, respectively. The source / drain ion implantation is, for example, a second doping type (e.g., n-type) ion implantation, so that the source region S and the drain region D have n-type doping (e.g., n+).

[0071] Before performing the source / drain ion implantation, a first masking layer can be formed on the substrate 100, covering the substrate lead-out region 110c and exposing the readout region 110a and charge readout region 110b. This prevents n-type ions from being implanted into the substrate lead-out region 110c during the source / drain ion implantation. After completing the source / drain ion implantation, the first masking layer can be removed, and a second masking layer can be formed on the substrate 100, covering the area outside the substrate lead-out region 110c and exposing only the substrate lead-out region 110c. Then, a first doping type (e.g., p-type) ion implantation is performed on the substrate lead-out region 110c, making the concentration of the first doping type on the surface of the substrate lead-out region 110c greater than that of the surrounding substrate 100, which helps to reduce the contact resistance of the substrate lead-out region 110c. For example, a heavily p-type doped (p+) layer can be formed on the top of the substrate lead-out region 110c.

[0072] Figures 25 and 26 are cross-sections along lines A-A' and B-B' in Figure 3 after the formation of the interlayer dielectric layer 130 and the plugs. Referring to Figures 3, 25, and 26, after forming the gate structure, the following process can be further performed on the front side 10a of the substrate 10: First, an interlayer dielectric layer 130 is formed on the front side 100a of the substrate 100. The interlayer dielectric layer 130 includes, for example, a contact hole etch stop layer (not shown) covering the front side 100a of the substrate 100 and an oxide layer covering the contact hole etch stop layer; then, a first source / drain plug CT1, a second source / drain plug CT2, and a substrate electrode plug CT3 are formed through the interlayer dielectric layer 130. The first source / drain plug CT1 is connected to the first source / drain region, the second source / drain plug CT2 is connected to the second source / drain region, and the substrate electrode plug CT3 is connected to the substrate lead-out region 110c. The first source / drain plug CT1, the second source / drain plug CT2, and the substrate electrode plug CT3 may include metals formed in contact holes through the interlayer dielectric layer 130, such as copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, ruthenium, copper alloys, or aluminum alloys.

[0073] Furthermore, a metal interconnect structure and metal pads (not shown) can be formed on the interlayer dielectric layer 130. The first source / drain plug CT1, the second source / drain plug CT2, and the substrate electrode plug CT3 can be connected to the corresponding metal pads through the metal interconnect structure. This allows a voltage to be applied from the front side 100a of the substrate 100 to the substrate lead-out region 110c in each substrate pixel unit 110 through the corresponding metal pads, thus achieving the purpose of applying a voltage to the substrate electrode of the aforementioned MOS capacitor. Optionally, after forming the metal interconnect structure and the metal pads, a circuit board (not shown) can be bonded to the front side 100a of the substrate 100, connecting the metal pads to the devices in the circuit board.

[0074] Figures 27 and 28 are cross-sections along lines A-A' and B-B' in Figure 3, respectively, after the deep trench isolation structure (DTI) and substrate pixel units 110 are exposed from the back side 100b of the substrate 100. Referring to Figures 3, 27, and 28, and referring to Figure 6, step S4 is performed to thin the substrate 100 from the back side 100b, exposing the deep trench isolation structure (DTI) and the plurality of substrate pixel units 110 separated by the deep trench isolation structure (DTI).

[0075] In step S4, the back surface 100b can be ground using a CMP process to expose the deep trench isolation structure (DTI) and the multiple substrate pixel units 110 separated by the DTI. Optionally, after completing the CMP process, wet etching can be performed to remove damage to the surface of the substrate pixel units 110 caused by the CMP process. By exposing the deep trench isolation structure (DTI) and the multiple substrate pixel units 110 separated by the DTI from the back surface 100b of the substrate 100, the multiple substrate pixel units 110 are completely physically isolated, which can effectively reduce photoelectric crosstalk between pixels.

[0076] Referring to Figures 4 and 5, after completing the above steps, a back dielectric layer 140 may be further formed on the back side 100a of the substrate 100. As an example, the back dielectric layer 140 may include a high dielectric constant layer 141 covering the deep trench isolation structure DTI and the substrate pixel unit 110 from the back side 100b of the substrate 100, and an oxide layer 142 (such as silicon oxide) covering the high dielectric constant layer 141.

[0077] In the vertical charge transfer imaging sensor and its manufacturing method described in the above embodiments, a plurality of substrate pixel units 110 are formed by separating the substrate 100 using a deep trench isolation structure (DTI). By allowing the deep trench isolation structure (DTI) to penetrate the substrate 100 to physically isolate each substrate pixel unit 110, photoelectric crosstalk between corresponding pixels of each substrate pixel unit 110 can be avoided, thereby improving device performance. Furthermore, a shallow trench isolation structure (STI) is used to separate each substrate pixel unit 110 into a photosensitive area 110a and an electrical... The charge readout area 110b and the substrate lead-out area 110c correspond to the pixel formed by the substrate pixel unit 110. The substrate pixel unit 110 and the gate structure 120 constitute a MOS capacitor. The substrate pixel unit 110 is the substrate electrode of the MOS capacitor. The substrate lead-out area 110c is the connection terminal of the substrate pixel unit 110. The substrate lead-out area 110c can be connected to the corresponding external signal from the front side 100a of the substrate 100 by means of connecting the source / drain region to the external signal, so as to apply voltage to the substrate electrode through the substrate lead-out area 110c.

[0078] It should be noted that the embodiments in this specification are described in a progressive manner, with each part focusing on the differences from the preceding parts, and the similarities and similarities between the parts can be referred to each other.

[0079] The above description is merely a description of preferred embodiments of the present invention and is not intended to define the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

[0080] 100: Substrate 100a: Front 100b: Back 101: Pad Oxide Layer 102: Hard mask layer 103: Linear dielectric layer 104: Trench conductive layer 104a: Trench electrode 105: Covering layer 106: Gate dielectric layer 107: Floating gate electrode material layer 108: Intergate dielectric layer 110: Substrate pixel unit 110a: Photosensitive area 110b: Charge Readout Area 110c: Substrate lead-out region 120: Gate structure 130: Interlayer dielectric layer 140: Backside dielectric layer 141: High dielectric constant layer 142: Oxide layer CG: Control Gate CT1: First source / drain plug CT2: Second source / drain plug CT3: Substrate Electrode Plug D: Duct region DT: Deep Trench DTI: Deep Trench Isolation Structure FG: Floating gate S: Source region S / D: Source / Drain Region ST: Shallow trench STI: Shallow Trench Isolation Structure S1, S2, S3, S4: Steps WL1, WL2: Word lines

Claims

1. A vertical charge transfer imaging sensor, characterized in that it comprises: A substrate having a first doping type and including a front side and a back side opposite to each other; a deep trench isolation structure penetrating the substrate, the deep trench isolation structure separating the substrate to form a plurality of substrate pixel units; a shallow trench isolation structure formed on the front side of the substrate, the shallow trench isolation structure dividing each of the substrate pixel units into a photosensitive area, a charge readout area, and a substrate lead-out area; a readout transistor including a gate structure formed on the front side of the charge readout area and a first source / drain area and a second source / drain area formed on both sides of the gate structure by the charge readout area, wherein the gate structure extends from the charge readout area to the photosensitive area; and a metal-oxide-semiconductor (MOS) capacitor formed by the gate structure and the corresponding substrate pixel units, the substrate pixel units being the substrate electrodes of the MOS capacitor, the substrate lead-out areas being the voltage application areas of the substrate electrodes, wherein the vertical charge transfer imaging sensor further includes: An interlayer dielectric layer covers the plurality of substrate pixel units, the deep trench isolation structure, the shallow trench isolation structure, the read transistor, and the metal-oxide-semiconductor (MOS) capacitor from the front side; a first source / drain plug penetrates the interlayer dielectric layer to connect to the first source / drain region; a second source / drain plug penetrates the interlayer dielectric layer to connect to the second source / drain region; and a substrate electrode plug penetrates the interlayer dielectric layer to connect to the substrate lead-out region.

2. The vertical charge transfer imaging sensor as claimed in claim 1, wherein the gate structure comprises a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate stacked on the surfaces of the photosensitive area and the charge readout area of ​​the substrate pixel unit.

3. The vertical charge transfer imaging sensor as claimed in claim 2, characterized in that it comprises: At least one word line is formed by connecting the control gates in the gate structures on at least two of the substrate pixel units.

4. The vertical charge transfer imaging sensor as claimed in claim 1, characterized in that the concentration of a first doping type on the surface of the substrate lead-out region is greater than the concentration of a first doping type on the surrounding substrate, and the first source / drain region and the second source / drain region have a second doping type.

5. The vertical charge transfer imaging sensor as claimed in claim 1, wherein the end face of the deep trench isolation structure facing the same direction as the back face of the substrate pixel unit is flush with the back face of the substrate pixel unit.

6. The vertical charge transfer imaging sensor as claimed in claim 1, characterized in that it comprises: A back dielectric layer includes a high dielectric constant layer covering the deep trench isolation structure and the substrate pixel unit from the back side of the substrate, and an oxide layer covering the high dielectric constant layer.

7. A method for manufacturing a vertical charge transfer imaging sensor, characterized in that it comprises: A substrate is provided, the substrate having a first doping type and including a front side and a back side opposite to each other; a deep trench isolation structure and a shallow trench isolation structure are formed on the front side of the substrate, the deep trench isolation structure and the shallow trench isolation structure extending from the front side into the substrate, the deep trench isolation structure separating the substrate to form a plurality of substrate pixel units, the shallow trench isolation structure separating each substrate pixel unit into a photosensitive area, a charge readout area and a substrate lead-out area; a gate structure is formed on the surface of each substrate pixel unit corresponding to the front side of the substrate, and a first source / drain region and a second source / drain region are formed on both sides of the charge readout area to form a readout transistor, wherein the gate structure extends from the charge readout area to the photosensitive area and forms a metal-oxide-semiconductor (MOS) capacitor with the corresponding substrate pixel unit; and the substrate is thinned from the back side to expose the deep trench isolation structure and the plurality of substrate pixel units separated by the deep trench isolation structure, the manufacturing method further comprising: An interlayer dielectric layer is formed on the front side of the substrate; and a first source / drain plug, a second source / drain plug, and a substrate electrode plug are formed through the interlayer dielectric layer, wherein the first source / drain plug is connected to the first source / drain region, the second source / drain plug is connected to the second source / drain region, and the substrate electrode plug is connected to the substrate lead-out region.

8. The manufacturing method as claimed in claim 7, characterized in that, before thinning the substrate from the back side, the manufacturing method further comprises: A patterned mask layer is formed on the substrate, and openings in the mask layer expose the substrate lead-out area; And implanting first-type doping ions on the surface of the substrate lead-out region, such that the concentration of the first-type doping on the surface of the substrate lead-out region is greater than that of the surrounding substrate.

9. The manufacturing method as claimed in claim 7, characterized in that thinning the substrate from the back side comprises: The back side of the substrate is polished using a chemical mechanical polishing (CMP) process to expose the deep trench isolation structure and the plurality of substrate pixel units from the back side of the substrate; And forming a back dielectric layer, the back dielectric layer comprising a high dielectric constant layer covering the deep trench isolation structure and the substrate pixel unit from the back side of the substrate, and a low dielectric constant layer covering the high dielectric constant layer.

10. The manufacturing method as claimed in claim 9, characterized in that, after completing the chemical mechanical polishing (CMP) process, wet etching is performed to remove damage to the surface of the substrate pixel unit.

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