Structure for packaging an optical component and method for fabricating the same

TWI939197BActive Publication Date: 2026-09-11AITRONICS INC
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Patent Information

Application Number
TW114134572
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-09-09
Publication Date
2026-09-11
Estimated Expiration
2045-09-08

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  • Figure TWG2TB001910765_003
    Figure TWG2TB001910765_003
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Abstract

An optical element packaging structure and its fabrication method are disclosed. The optical element packaging structure includes a wiring substrate, a light-emitting diode (LED) chip, a first photoelectric conversion chip, a second photoelectric conversion chip, an optical adhesive layer, and a transparent substrate. The top surface of the wiring substrate extends upward to form a light-shielding barrier. The LED chip, the first photoelectric conversion chip, and the second photoelectric conversion chip are disposed on and coupled to the wiring substrate. The LED chip and the second photoelectric conversion chip are located on the same side of the light-shielding barrier, and the first photoelectric conversion chip is located on the other side of the light-shielding barrier. The optical adhesive layer covers the LED chip, the first photoelectric conversion chip, and the second photoelectric conversion chip, and the transparent substrate is disposed on the optical adhesive layer.
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Claims

1. An optical element packaging structure, comprising: a wiring substrate extending upward from its top surface to form a light-shielding barrier, the top surface having a first surface and a second surface, the first surface and the second surface being located on opposite sides of the light-shielding barrier; the first surface having a plurality of first conductive pads coupled to the wiring substrate; the second surface having a plurality of second conductive pads and a plurality of third conductive pads coupled to the wiring substrate; one side of each of the plurality of second conductive pads having a plurality of third conductive pads; and the other side of each of the plurality of second conductive pads having the light-shielding barrier opposite to the plurality of third conductive pads, the light-shielding barrier being located between the plurality of first conductive pads and the plurality of second conductive pads, the positions of the plurality of first conductive pads and the plurality of second conductive pads corresponding to each other; a plurality of light-emitting diode chips, respectively coupled to the plurality of second conductive pads; a plurality of first photoelectric conversion chips, respectively coupled to the plurality of first conductive pads; and a plurality of second photoelectric conversion chips, respectively coupled to the plurality of third conductive pads. Two optical adhesive layers are respectively disposed on the first surface and the second surface to cover the plurality of light-emitting diode chips, the plurality of first photoelectric conversion chips and the plurality of second photoelectric conversion chips; and two transparent substrates are respectively disposed on the two optical adhesive layers.

2. The optical element packaging structure as described in claim 1, wherein each of the transparent substrates has an anti-reflective layer on its top surface.

3. The optical element packaging structure as described in claim 2, wherein the plurality of light-emitting diode (LED) chips, the plurality of first photoelectric conversion chips, and the plurality of second photoelectric conversion chips are coupled to a processing circuit. When the anti-reflective layer is attached to an object under test (AUT), the processing circuit sequentially drives the plurality of LED chips. When the processing circuit drives each LED chip to emit light to be measured, the processing circuit enables the first photoelectric conversion chip and the second photoelectric conversion chip corresponding to the driven LED chip to receive the light to be measured, thereby obtaining a first brightness value and a second brightness value respectively. The processing circuit calculates the brightness difference between the first brightness value and the second brightness value corresponding to the plurality of LED chips and their average value, and uses... This process calculates a standard deviation and defines a normal variation range, an abnormal variation range, and a stop-operation range based on the average value and the standard deviation. After defining the normal variation range, the abnormal variation range, and the stop-operation range, the processing circuit drives the light-emitting diode chip to emit measurement light and activates its corresponding first photoelectric conversion chip and second photoelectric conversion chip to receive the measurement light, thereby obtaining a first measurement brightness value and a second measurement brightness value, respectively. The processing circuit calculates the measurement brightness difference between the first measurement brightness value and the second measurement brightness value. When the processing circuit determines that the measurement brightness difference value falls within the normal variation range, the processing circuit calculates the measurement parameter of the object to be measured corresponding to the first measurement brightness value.

4. The optical element packaging structure as described in claim 3, wherein when the processing circuit determines that the measured brightness difference value falls within the abnormal variation range, the processing circuit increases the current value supplied to the light-emitting diode chip.

5. The optical element packaging structure as described in claim 3, wherein when the processing circuit determines that the measured brightness difference value falls within the stop operating range multiple times consecutively, the processing circuit stops driving the plurality of light-emitting diode chips and disables the plurality of first photoelectric conversion chips and the plurality of second photoelectric conversion chips.

6. The optical element packaging structure as described in claim 3, wherein the first photoelectric conversion chip and the second photoelectric conversion chip respectively convert the first measured brightness value and the second measured brightness value into a first voltage value V1 and a second voltage value V2, and transmit them to the processing circuit. The processing circuit calculates the signal-to-noise ratio based on V1 / (V2-V1). When the signal-to-noise ratio is less than or equal to a preset value, the processing circuit stops driving the plurality of light-emitting diode chips and disables the plurality of first photoelectric conversion chips and the plurality of second photoelectric conversion chips.

7. The optical element packaging structure as described in claim 1, wherein the plurality of light-emitting diode chips are near-infrared light-emitting diode chips.

8. The optical element packaging structure as described in claim 1, wherein the plurality of first photoelectric conversion chips and the plurality of second photoelectric conversion chips are photodiode chips.

9. The optical element packaging structure as described in claim 1, wherein the plurality of light-emitting diode wafers, the plurality of first photoelectric conversion wafers and the plurality of second photoelectric conversion wafers are horizontal wafers, vertical wafers or flip-chip wafers.

10. The optical element packaging structure as claimed in claim 1, wherein the bottom surface of the wiring substrate is provided with a plurality of electrodes thereto.

11. The optical element packaging structure as described in claim 1, wherein the wiring substrate is further provided with a thermistor.

12. The optical element packaging structure as described in claim 1, wherein the two transparent substrates are glass substrates.

13. A method for manufacturing an optical element packaging structure, comprising the following steps: providing a wiring substrate having a groove, wherein the bottom surface of the groove has a plurality of regions arranged parallel to each other, each region extending upward to form a light-shielding barrier to divide the groove into a plurality of sub-grooves, each region having a plurality of first conductive pads, a plurality of second conductive pads and a plurality of third conductive pads coupled to the wiring substrate, each of the plurality of second conductive pads having a plurality of third conductive pads respectively on one side, and the light-shielding barrier being located opposite the plurality of third conductive pads on the other side, the light-shielding barrier being located between the plurality of first conductive pads and the plurality of second conductive pads, the positions of the plurality of first conductive pads and the plurality of second conductive pads respectively corresponding; mounting a plurality of light-emitting diode chips on the plurality of regions respectively, wherein each of the plurality of light-emitting diode chips includes a plurality of light-emitting diode chips, the plurality of light-emitting diode chips being coupled to a set of the second conductive pads; Multiple sets of first photoelectric conversion chips are respectively installed on the multiple regions, wherein each set of first photoelectric conversion chips includes multiple first photoelectric conversion chips, and the multiple first photoelectric conversion chips are coupled to a set of first conductive pads; multiple sets of second photoelectric conversion chips are respectively installed on the multiple regions, wherein each set of second photoelectric conversion chips includes multiple second photoelectric conversion chips, and the multiple second photoelectric conversion chips are coupled to a set of third conductive pads; multiple optical adhesive layers are respectively formed in the multiple sub-grooves to cover the multiple sets of light-emitting diode chips, the multiple sets of first photoelectric conversion chips, and the multiple sets of second photoelectric conversion chips; multiple transparent substrates are respectively formed in the multiple sub-grooves to cover the multiple optical adhesive layers; and the wiring substrate, the light-shielding barrier, the multiple optical adhesive layers, and the multiple transparent substrates are cut to form multiple optical element package structures, wherein each optical element package structure includes a set of light-emitting diode chips, a set of first photoelectric conversion chips, and a set of second photoelectric conversion chips.

14. A method for manufacturing an optical element packaging structure as described in claim 13, wherein before the step of forming the plurality of transparent substrates in the plurality of sub-grooves, a plurality of anti-reflective layers are formed on the plurality of transparent substrates; and in the step of cutting the wiring substrate, the light-shielding barrier, the plurality of optical adhesive layers and the plurality of transparent substrates to form the plurality of optical element packaging structures, the wiring substrate, the light-shielding barrier, the plurality of optical adhesive layers, the plurality of transparent substrates and the plurality of anti-reflective layers are cut to form the plurality of optical element packaging structures.

15. A method for manufacturing an optical element packaging structure as described in claim 13, wherein the plurality of light-emitting diode chips are near-infrared light-emitting diode chips.

16. A method for manufacturing an optical element packaging structure as described in claim 13, wherein the plurality of first photoelectric conversion chips and the plurality of second photoelectric conversion chips are photodiode chips.

17. A method for manufacturing an optical element packaging structure as described in claim 13, wherein the plurality of light-emitting diode wafers, the plurality of first photoelectric conversion wafers, and the plurality of second photoelectric conversion wafers are horizontal wafers, vertical wafers, or flip-chip wafers.

18. A method for manufacturing an optical element packaging structure as described in claim 13, wherein the bottom surface of the wiring substrate is provided with a plurality of electrodes coupled thereto.

19. A method for manufacturing an optical element packaging structure as described in claim 13, wherein the wiring substrate is further provided with a plurality of thermistors, and each of the chip modules includes the thermistors.

20. A method for manufacturing an optical element packaging structure as described in claim 13, wherein the plurality of transparent substrates are glass substrates.

Citation Information

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