Manufacturing method of semiconductor structure

Abstract

This disclosure provides a method for manufacturing a semiconductor structure. A substrate is provided. A bitline conductive layer is formed on the substrate. A bitline dielectric layer is formed on the bitline conductive layer. A first hard mask layer and a second hard mask layer are formed on the bitline dielectric layer. A first trench is formed to define the bitline dielectric layer and the bitline conductive layer as a bitline structure, wherein the second hard mask layer on the bitline dielectric layer is removed, while the first hard mask layer on the bitline dielectric layer is retained. A sacrificial layer is formed within the first trench. The sacrificial layer is removed to form a second trench, and the first hard mask layer is removed to expose the top surface of the bitline dielectric layer. Cell contacts are formed within the second trench.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Provide a substrate; A bit-line conductive layer is formed on the substrate; a bit-line dielectric layer is formed on the bit-line conductive layer; a first hard mask layer and a second hard mask layer are sequentially formed on the bit-line dielectric layer, wherein the first hard mask layer comprises polysilicon and the second hard mask layer comprises carbon; a first trench is formed to define the bit-line dielectric layer and the bit-line conductive layer as a bit-line structure, wherein the second hard mask layer is removed and the first hard mask layer is retained; a sacrificial layer is formed in the first trench; the sacrificial layer is removed to form a second trench, and the first hard mask layer is removed to expose a top surface of the bit-line dielectric layer; and a cell contact is formed in the second trench.

2. The method as described in claim 1, wherein the bit-line conductive layer comprises: A first conductive layer is located on the substrate; And a second conductive layer, located on the first conductive layer.

3. The method as described in claim 2, wherein the first conductive layer and the first hard mask layer are made of the same material.

4. The method as described in claim 1, further comprising: Before forming the first trench, a photoresist is formed on the second hard mask layer.

5. The method as described in claim 1, further comprising: A portion of the sacrificial layer is removed to form an isolation trench.

6. The method as described in claim 5, further comprising: Before forming the second trench, a contact isolation layer is filled in the isolation trench.

7. The method as described in claim 1, further comprising: Before forming the sacrificial layer, a spacer layer is formed on the bit line structure.

8. The method as described in claim 7, wherein the spacer layer comprises: A first spacer layer is located on the sidewall of the bit line structure; and a second spacer layer located on the sidewall of the first spacer layer, wherein the first spacer layer and the second spacer layer are made of different materials.

9. A method for manufacturing a semiconductor structure, comprising: Provide a substrate; A bit-line conductive layer is formed on the substrate, wherein the bit-line conductive layer includes a first conductive layer and a second conductive layer; a bit-line dielectric layer is formed on the bit-line conductive layer, wherein the bit-line dielectric layer has a first thickness; a first hard mask layer and a second hard mask layer are sequentially formed on the bit-line dielectric layer, wherein the first hard mask layer and the first conductive layer are made of the same material; a first trench is formed to define the bit-line dielectric layer and the bit-line conductive layer as a bit-line structure, wherein the second hard mask layer is removed while the first hard mask layer is retained; a sacrificial layer is formed in the first trench; the sacrificial layer is removed to form a second trench and the first hard mask layer is removed to expose a top surface of the bit-line dielectric layer, wherein the bit-line dielectric layer has a second thickness, the second thickness being the same as the first thickness; and a cell contact is formed in the second trench.

10. The method as described in claim 9, wherein the first trench is parallel to the bit line structure.

11. The method as described in claim 9, wherein the sacrificial layer comprises an oxide.

12. The method as described in claim 9, wherein the first hard mask layer and the first conductive layer comprise polysilicon.

13. The method as described in claim 9, wherein the second hard mask layer comprises carbon.

14. The method as described in claim 9, further comprising: A portion of the sacrificial layer is removed to form an isolation trench.

15. The method as described in claim 14, further comprising: Before forming the second trench, a contact isolation layer is filled in the isolation trench.

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