Integrated circuit device

Abstract

This invention discloses various structures for implementing nanosheet transistors. These structures include nanosheet transistors with different widths within the transistor device. Variations in the width of the nanosheet transistors within the transistor device allow for different designs of the input and output stages, which can improve the power utilization and performance of the transistor device. In some cases, the input stage has nanosheet transistors with nanosheet fins that are narrower than those in the output stage. Variations in the width of the nanosheet transistors can also be implemented within the input or output stage by merging the nanosheet fins.

Description

Technical Field

[0001] The embodiments described herein relate to transistor structures for semiconductor devices. More specifically, the embodiments described herein relate to structures for nanosheet transistors in integrated circuit devices. Prior Technology

[0002] Nanochip (e.g., gate-all-around) transistors are increasingly used in integrated circuits. Due to the increased gate control of the channels provided by the geometry of nanochip transistor designs, nanochip transistors can offer more efficient characteristics for turn-on / turn-off transistors compared to planar FETs or FinFETs. This increased efficiency in turn-on or turn-off transistors provides reduced leakage and better power utilization (e.g., voltage reduction) for integrated circuits utilizing nanochip transistors. Nanochip transistors can have more complex designs than planar FETs or FinFETs. As integrated circuit designs evolve, more avenues for utilizing more complex nanochip transistor designs are conceivable. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The features and advantages of the methods and apparatus of the embodiments described in this disclosure will be more fully understood by referring to the following detailed description of the currently preferred but illustrative embodiments according to this disclosure, together with the accompanying drawings, wherein: [Figure 1] A perspective view depicting a nanosheet transistor according to some embodiments. [Figure 2] depicts an end view representation of a channel area according to some embodiments. [Figure 3] A top plan view depicting a standard cell layout with nanosheet transistors according to some embodiments. [Figure 4] A top plan view depicting the layout of a transistor device with nanosheet transistors according to some embodiments. [Figure 5] A top plan view depicting the layout of a transistor device having nanosheet transistors with integrated nanosheet fins in the output stage according to some embodiments. [Figure 6] A top plan view depicting the layout of a transistor device having nanosheet transistors with integrated nanosheet fins in both the input and output stages, according to some embodiments. [Figure 7] is a block diagram of an embodiment of the instance system.

[0005] While the embodiments disclosed herein may be subject to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the scope of the claims to the specific forms disclosed. Rather, this application is intended to encompass all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined in the appended claims. Implementation

[0006] Priority Claim This application claims priority to U.S. Provisional Patent Application No. 63 / 585,404, filed September 26, 2023, entitled “Nanosheet Sizing for Power Delivery,” the disclosure of which is incorporated herein by reference in its entirety.

[0007] As used herein, the term "standard cell" refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide standard logic or storage functionality for various implementations. For example, an individual standard cell may be one cell from a library of cells from which various suitable cells can be selected to implement a particular cell design. As a further example, a standard cell may be a cell design that has been established (e.g., designed) and subsequently implemented multiple times to produce integrated circuit devices via, for example, synthesis or automated processes. Integrated circuit cells may also include custom circuit design cells individually designed for a particular implementation. Embodiments of the circuit design cells described herein can be implemented in various implementations of logic integrated circuits or memory integrated circuits.

[0008] Figure 1 depicts a perspective view of a nanosheet transistor according to some embodiments. In the illustrated embodiment, a nanosheet transistor 100 is formed on a substrate 150. In some embodiments, the transistor 100 includes a gate 110 and a channel region 120. The gate 110 may be a polysilicon gate or a metal gate. The channel region 120 includes nanofins 130 and a substrate channel 140. The nanofins 130 are fins made of silicon, another semiconductor, or a combination of semiconductors, which pass through the structure (e.g., material) of the gate 110. In various embodiments, the nanofins 130 are relatively thin (in the vertical dimension), rectangular semiconductor material sheets aligned parallel to the substrate 150 (e.g., the horizontal plane of the nanofins 130 is parallel to the horizontal plane of the substrate 150). The transistor 100 generally includes a plurality of nanofins 130 passing through the gate 110. For example, as shown in Figure 1, transistor 100 includes three nanofins 130 passing through gate 110.

[0009] In various embodiments, a substrate channel 140 is formed in a substrate 150 beneath the nanofins 130. The substrate channel 140 may be formed by forming shallow trench isolation (STI) 145 on either side of the substrate channel in the substrate 150. Thus, the substrate channel 140 is part of the substrate 150 between the STIs 145. In some embodiments, the substrate channel 140 is aligned with the nanofins 130 and has similar horizontal dimensions (e.g., length or width) to those nanofins. In some embodiments, the substrate channel 140 is made of the same semiconductor material as the nanofins 130. For example, both the nanofins 130 and the substrate channel 140 may be silicon.

[0010] Figure 2 depicts an end view representation of a channel region 120 according to some embodiments. In the illustrated embodiment, the channel region 120 includes a nanofin 130 above a substrate channel 140 and inside a gate 110. In some embodiments, the gate 110 substantially surrounds (e.g., "all-around") the nanofin 130. It should be noted that at least some gate dielectric material (not shown) may be present between the nanofin 130 and the gate 110. Using the gate 110 to surround the nanofin 130 provides better control over gate operation and reduces current leakage from the gate, resulting in more efficient characteristics for turning the gate on and off.

[0011] Figure 3 depicts a top plan view representation of a standard cell layout with a nanosheet transistor according to some embodiments. In the illustrated embodiment, the standard cell 300 includes enabled gate structures 310A to 310C and dummy (e.g., disabled) gate structures 320A to 320B. In various embodiments, the enabled gate structures 310A to 310C and the dummy gate structures 320A to 320B are formed of the same material and are structurally similar. In such embodiments, the determination of whether the gate structure is "active" or "dummy" can be made by whether the gate is connected in the layout and design of the cell 300.

[0012] In some embodiments, dummy gate structures 320A to 320B are implemented to demarcate (e.g., isolate) the layout of structures or units within a cell from other structures. For example, as shown in FIG3, dummy gate structure 320A is positioned at the left edge of cell 300 in the gate pitch direction 302 (e.g., the horizontal direction of the cell), and dummy gate structure 320B is positioned at the right edge of cell 300. Therefore, dummy gate structures 320A to 320B isolate enabled gate structures 310A to 310C from the cells or other structures to the left and right of cell 300 in the gate pitch direction 302.

[0013] In various embodiments, the enabled gate structures 310A to 310C and the dummy gate structures 320A to 320B are fingers or lines of gate material that cross (e.g., extend) across the cell 300 in the cell height direction 304 (e.g., the vertical direction of the cell). Examples of gate materials include, but are not limited to, polycrystalline silicon or metal. In some embodiments, the gate material of the gate structures 310A to 310C may extend beyond the boundary of the cell 300. For example, the gate structures 310A to 310C may include gate material extending in the cell height direction 304 into adjacent cells above or below the cell 300.

[0014] In various embodiments, unit 300 includes channel regions 330A to 300B. In some embodiments, channel regions 330A to 330B include nanofins 340A to 340B. Nanofins 340A to 340B may include multiple stacked nanofins, such as nanofins 130 shown in Figures 1 and 2. Therefore, in the top plan view of Figure 3, only the top nanofins are shown as nanofins 340A and 340B. In various embodiments, as shown in Figure 3, nanofins 340A to 340B extend across the width of unit 300 in the gate pitch direction 302. For example, nanofins 340A to 340B extend between dummy gate structures 320A and dummy gate structures 320B.

[0015] In some embodiments, the enable gate 350 (dashed box) is formed at the region where the nanofins 340A to 340B (oriented in the gate pitch direction 302) intersect with the enable gate structures 310A to 310C (oriented in the cell height direction 304). For example, in the embodiment illustrated in FIG3, the enable gates 350A to 350C are formed at the region where the nanofins 340A intersect with the enable gate structures 310A to 310C, and the enable gates 350D to 350F are formed at the region where the nanofins 340B intersect with the enable gate structures 310A to 310C. Accordingly, the cell 300 includes six enable gates (gates 350A to 350F) within the boundary of the standard cell. The enable gates 350A to 350F may have a structure similar to that of the gate 110 shown in FIG1 and 2.

[0016] In current embodiments of the standard unit (such as unit 300), nanofins 340A to 340B have the same horizontal width (e.g., a fixed width determined by the design and size of the unit). For example, the width 342A of nanofin 340A is approximately the same as the width 342B of nanofin 340B. It should be noted that widths 342A and 342B are shown vertically in the illustration of FIG3, but represent the horizontal width of the nanofins (e.g., the horizontal width of nanofin 130 shown in FIG1 and FIG2). In various embodiments, the transistor device based on unit 300 may have an input stage and an output stage. For example, as shown in FIG3, unit 300 may include an input stage 360 ​​and an output stage 370 (dashed box).

[0017] In unit 300, because gates 350A to 350F have substantially the same operating characteristics (e.g., drive current capacity, capacitance, and power) due to the same width of nanofins 340A to 340B, the desired different operating characteristics of input stage 360 ​​and output stage 370 can be implemented by selecting the number of gates used in the output stage from the input stage. For example, in the illustrated embodiment of unit 300, input stage 360 ​​includes two enable gates (enable gates 350A and 350D), while output stage 370 includes four enable gates (enable gates 350B, 350C, 350E, and 350F). Output stage 370 has more enable gates to achieve a larger drive output, while input stage 360 ​​has fewer enable gates to have lower capacitance in the input. Because the width of the nanofins 340 in cell 300 is substantially the same, there is limited flexibility in designing the input and output stages of the transistor device for cell 300. For example, variations in stage design are typically implemented only by changing the number of enabled gates in each stage.

[0018] This disclosure recognizes that additional design flexibility in transistor devices can be achieved by varying the width of the nanosheet fins provided by the transistor within the transducer, offering greater flexibility in the design of the input and output stages of the transistor device. Compared to transistor devices with nanosheet transistors of the same width as the transducer, this increased flexibility provides improved power efficiency and enhanced performance. For example, flexibility in the input / output stage design allows the transistor device to have a greater current drive capability from the output stage to other devices, while having lower capacitance in the input stage (as seen in other devices).

[0019] Some embodiments disclosed herein have four generalized elements: 1) a plurality of gate structures oriented along a first direction; 2) a plurality of elongated channel regions oriented along a second direction, wherein the elongated channel regions include two or more stacked nanofins; 3) an input stage including elongated channel regions having nanofins with a first width along the first direction; and 4) an output stage including elongated channel regions having nanofins with a second width along the first direction greater than the first width. In some embodiments, the elongated channel regions extend through the gate structures, wherein an enabled gate is located at the intersection of the nanofins and the gate structures. In some embodiments, the input and output stages are in separate cells separated in the cell height direction, wherein the gate structures extend across the two stages.

[0020] Various descriptions of embodiments having such generalized elements are now described in this disclosure. It should be noted that the illustrated embodiments of this disclosure depict design templates having cells of various nanochip transistors that can be implemented in the input and output stages of transistor devices. These design templates provide basic building blocks from which many different types of devices can be constructed based on the interconnection schemes of the transistors in the design templates. For example, simple devices (such as inverters, NAND devices, multiplexers (MUX)) and more complex devices (e.g., complex FETs) can be constructed based on the basic building blocks of this disclosure.

[0021] Figure 4 depicts a top plan view illustrating the layout of a transistor device with nanosheet transistors according to some embodiments. In the illustrated embodiment, transistor device 400 is a device having a cell width of a standard cell width in the gate pitch direction 402 and a cell height twice the standard cell height in the cell height direction 404 (e.g., 2 x standard cell heights 406A to 406B). In some embodiments, the standard cell height is the cell height that accommodates two rows of channel regions and nanosheet transistor fins (e.g., two channel regions 430 with nanosheet fins 440).

[0022] In some embodiments, device 400 includes enabled gate structures 410A to 410B and deactivated (e.g., disabled) gate structures 420A to 420B. The deactivated gate structures 420A to 420B define the edges of device 400 in the gate pitch direction 402 and isolate device 400 from other devices in the gate pitch direction, wherein deactivated gate structure 420A defines the left edge and deactivated gate structure 420B defines the right edge. In various embodiments, the enabled gate structures 410A to 410B and the deactivated gate structures 420A to 420B are fingers or lines of gate material that cross (e.g., extend) across device 400 in the cell height direction 404 (e.g., the direction perpendicular to the device in the illustration). The gate material may be, for example, polycrystalline silicon or metal. In some embodiments, the gate material of the gate structures 410A to 410B or the dummy gate structures 420A to 420B may extend beyond the boundary of the device 400.

[0023] In some embodiments, device 400 is divided into an input stage 460 in the top portion of the device (as defined by standard cell height 406A) and an output stage 470 in the bottom portion of the device (as defined by standard cell height 406B). Various wirings in the layers above the structure shown in FIG4 can be implemented to define the connection between the input stage 460 and the output stage 470.

[0024] In some embodiments, input stage 460 includes channel regions 430A to 430B, while output stage 470 includes channel regions 430C to 430D. In various embodiments, channel regions 430A to 430B include nanofins 440A to 440B, and channel regions 430C to 430D include nanofins 440C to 440D. Each of nanofins 440A to 440D may include stacked nanofins, such as nanofin 130 shown in Figures 1 and 2. Nanofins 440A to 440D extend across the width of device 400 in the gate pitch direction 402. For example, nanofins 440A to 440D extend between dummy gate structures 420A and dummy gate structures 420B.

[0025] In various embodiments, input stage 460 includes enable gates 450A to 450D. Enable gates 450A to 450D (dashed box) may be formed at the region where nanofins 440A to 440B (oriented in the gate pitch direction 402) intersect with enable gate structures 410A to 410B (oriented in the cell height direction 404). For example, enable gates 450A to 450B are formed at the region where nanofins 440A intersect with enable gate structures 410A to 410B, while enable gates 450C to 450D are formed at the region where nanofins 440B intersect with enable gate structures 410A to 410B.

[0026] In various embodiments, output stage 470 includes enable gates 450E to 450H. Enable gates 450E to 450H (dashed boxes) may be formed at the region where nanofins 440C to 440D (oriented in the gate pitch direction 402) intersect with enable gate structures 410A to 410B (oriented in the cell height direction 404). For example, enable gates 450E to 450F are formed at the region where nanofins 440C intersect with enable gate structures 410A to 410B, while enable gates 450G to 450H are formed at the region where nanofins 440D intersect with enable gate structures 410A to 410B. Accordingly, both input stage 460 and output stage 470 may include the same number of enable gates (e.g., four in device 400).

[0027] In the embodiment illustrated in Figure 4, nanofins 440A to 440B in input stage 460 have a width of 442A, and nanofins 440C to 440D in output stage 470 have a width of 442B. In some embodiments, width 442A differs from width 442B. For example, width 442A may be smaller than width 442B, and nanofins 440A to 440B are heterogeneous relative to nanofins 440C to 440D. Variations in the width of nanofins 440 between input stage 460 and output stage 470 can be implemented to provide varying properties in the enable gate 450 associated with the nanofins. For example, in device 400, input stage 460 includes enable gates 450A to 450D with nanofins 440A to 440B, which have a smaller width (width 442A) than the enable gates 450E to 450H with nanofins 440C to 440D in output stage 470. The smaller width of the nanofins can be implemented in input stage 460 to reduce the capacitance that other devices around device 400 may experience. Conversely, the larger width of the nanofins implemented in output stage 470 increases the drive current capacity of device 400, allowing as much drive output as possible to be provided to other devices outside device 400. Reducing the capacitance of device 400 as seen by other devices while providing as much drive output as possible increases the performance and power utilization of device 400 (along with other devices associated with device 400).

[0028] An example of a transistor device that can benefit from reduced capacitance in the input stage and increased drive output to other devices is a clock implemented in a flip-flop circuit. A clock with reduced capacitance in the input stage reduces the impact of its capacitance on other devices connected to the clock, while providing a high signal output from the clock that can be easily received by other devices. This clock device can also be implemented in a flip-flop circuit with a smaller area, reducing the area penalty of the clock in the flip-flop circuit.

[0029] Additional embodiments of the device are conceivable, wherein the width of the device is increased to place the input and output stages side-by-side within the device (e.g., side-by-side in the gate pitch direction). Placing the input and output stages side-by-side in the gate pitch direction allows for further variations in the design of the channel region and the gate formed by the channel region. For example, the width of the channel region may vary between the gates in the input or output stages, or a larger channel region may be created by merging channel regions. Various exemplary embodiments are described now to understand that the elements in the examples can be applied to other embodiments conceived herein, including those explicitly depicted.

[0030] Figure 5 depicts a top plan view illustrating the layout of a transistor device having nanosheet transistors with integrated nanosheet fins in an output stage, according to some embodiments. In the illustrated embodiment, transistor device 500 is a device having a cell width in the gate pitch direction 502 that is wider than the cell width in Figures 3 and 4. Device 500 has a cell height in the cell height direction 504 that is twice the standard cell height (e.g., 2 x standard cell heights 506A to 506B) and similar in height to device 400 shown in Figure 4.

[0031] In some embodiments, device 500 includes enabled gate structures 510A to 510C and deactivated (e.g., disabled) gate structures 520A to 520C. In various embodiments, the enabled gate structures 510A to 510C and the deactivated gate structures 520A to 520C are fingers or lines of gate material that cross (e.g., extend) across device 500 in the cell height direction 504 (e.g., the vertical direction of the device in the illustration). The gate material may be, for example, polycrystalline silicon or metal. In some embodiments, the gate material of the gate structures 510A to 510C or the deactivated gate structures 520A to 520C may extend beyond the boundary of device 500.

[0032] In various embodiments, dummy gate structures 520A to 520B define the edges of device 500 in the gate pitch direction 502 and isolate device 500 from other devices in the gate pitch direction, wherein dummy gate structure 520A defines the left edge and dummy gate structure 520B defines the right edge. In some embodiments, dummy gate structure 520C divides device 500 into an input stage 560 and an output stage 570. For example, device 500 is divided by dummy gate structure 520C into an input stage 560 (in the gate pitch direction 502) in the left portion of the device and an output stage 570 in the right portion of the device. Various wirings in the layers above the structure shown in FIG5 can be implemented to define the connection between input stage 560 and output stage 570.

[0033] In some embodiments, input stage 560 includes channel regions 530A to 530D, while output stage 570 includes channel regions 530E to 530G. Channel regions 530A to 530G may include corresponding nanofins 540A to 540G. Each of nanofins 540A to 540G may include stacked nanofins, such as nanofin 130 shown in Figures 1 and 2. In various embodiments, nanofins 540A to 540D extend across the width of input stage 560 in the gate pitch direction 502. For example, nanofins 540A to 540D extend between dummy gate structures 520A and dummy gate structures 520C. Nanofins 540E to 540G extend across the width of output stage 570 in the gate pitch direction 502 between dummy gate structures 520C and dummy gate structures 520B.

[0034] In various embodiments, input stage 560 includes enable gates 550A to 550H. Enable gates 550A to 550D (dashed boxes) may be formed at the region where nanofins 540A to 540B (oriented in the gate pitch direction 502) intersect with enable gate structures 510A to 510B (oriented in the cell height direction 504). Additionally, enable gates 550E to 550H (dashed boxes) may be formed at the region where nanofins 540C to 540D (oriented in the gate pitch direction 502) intersect with enable gate structures 510A to 510B (oriented in the cell height direction 504). For example, the activation gates 550A to 550B are formed in the region where the nanofin 540A intersects with the activation gate structures 510A to 510B, the activation gates 550C to 550D are formed in the region where the nanofin 540B intersects with the activation gate structures 510A to 510B, the activation gates 550E to 550F are formed in the region where the nanofin 540C intersects with the activation gate structures 510A to 510B, and the activation gates 550G to 550H are formed in the region where the nanofin 540D intersects with the activation gate structures 510A to 510B.

[0035] In the embodiment illustrated in Figure 5, nanofins 540A to 540B in the input stage 560 have a width of 542A, and nanofins 540C to 540D in the output stage have a width of 542B. In some embodiments, the width 542A is different from the width 542B. For example, the width 542A may be smaller than the width 542B, and nanofins 540A to 540B are heterogeneous relative to nanofins 540C to 540D. The variation in the width of the nanofins 540 in the input stage 560 allows for the availability of connections to gates of different sizes within the input stage. Accordingly, the input stage 560 increases the design flexibility of the device 500 by providing gate properties and corresponding gate connectivity that can be implemented in various types of transistor devices.

[0036] In some embodiments, the output stage 570 includes enable gates 550I to 550K formed between dummy gate structures 520C and dummy gate structures 520B in the region where nanofins 540E to 540G (oriented in the gate pitch direction 502) intersect with the enable gate structure 510C (oriented in the cell height direction 504). For example, enable gate 550I (dashed box) is formed in the region where nanofins 540E and enable gate structure 510C intersect, enable gate 550J (dashed box) is formed in the region where nanofins 540F and enable gate structure 510C intersect, and enable gate 550K (dashed box) is formed in the region where nanofins 540G and enable gate structure 510C intersect.

[0037] In various embodiments, output stage 570 is based on a layout comprising four nanosheets of similar size (e.g., similar width), wherein two of these nanosheets are merged to form a single nanosheet. For example, in the embodiment illustrated in FIG5, nanosheet fin 540E (in channel region 530E) and nanosheet fin 540G (in channel region 530G) are individual nanosheet fins, wherein nanosheet fin 540F (in channel region 530F) is formed by merging two individual nanosheet fins. Merging nanosheet fins to form nanosheet fin 540F can be implemented by designing the formation of the two individual nanosheet fins to be substantially adjacent or have some overlap in the layout.

[0038] Therefore, in the embodiment illustrated in Figure 5, nanofins 540E and 540G both have a width of 542C, while nanofin 540F has a width of 542D, which is approximately twice the width of 542C. Thus, nanofin 540F in the output stage 570 is larger than nanofin 540E or nanofin 540G, and the enabled gate 550J (corresponding to nanofin 540F) has a higher drive current capacity than the enabled gate 550I (corresponding to nanofin 540E) or enabled gate 550K (corresponding to nanofin 540G). In some embodiments, the width 542D is approximately twice the width of 542C, and therefore the enabled gate 550J has approximately twice the drive current capacity of the enabled gate 550I or enabled gate 550K. Although nanofins 540E and 540G are shown to have the same width in Figure 5, it is conceivable that some embodiments of nanofins 540E and 540G may have different widths.

[0039] With variations in the width (and drive current capacity) of the enabled gates 550I to 550K in the output stage 570, the design of device 500 can have increased flexibility because different outputs can be implemented based on providing different connections to the enabled gates. For example, in one envisioned embodiment, enabled gate 550J (which has the largest drive current capacity) can be connected to another device that requires a higher drive output from device 500, while enabled gates 550I and 550K can be connected to other devices that have lower requirements for drive output from device 500.

[0040] Device 500 also has the design benefits of the input stage 560 provided by device 400 shown in FIG. 4 for the output stage 570. For example, smaller nanofins in the input stage 560 can be used to reduce the capacitance that can be experienced by other devices around device 500, while larger nanofins in the output stage 570 can be used to increase the drive current capacity of device 500 and provide as much drive output as possible to other devices outside device 500.

[0041] Figure 6 depicts a top plan view of the layout of a transistor device according to some embodiments, having nanoplate transistors with integrated nanoplate fins in both the input and output stages. In the illustrated embodiment, transistor device 600 is substantially similar to device 500 shown in Figure 5, except for a change in the input stage. For example, input stage 560' shown in Figure 6 is substantially similar to input stage 560 shown in Figure 5, except that the channel region (along with the nanoplate fins) in the vertical central portion of the input stage is integrated.

[0042] In various embodiments, input stage 560' includes a merged channel region 630BC having merged nanofins 640BC. Channel region 630BC can be formed, for example, by moving individual channel regions 530B and 530C, which are adjacent (or partially overlapping) to each other at or near the boundaries of standard cell heights 506A and 506B as shown in FIG. 5, to merge the individual channel regions and form a single channel region 630BC. Nanofins 640BC are formed accordingly using the merging of channel regions as a merging between individual nanofins 530B and 530C.

[0043] Utilizing the merged channel region 630BC and merged nanofin 640BC formed in the input stage 560', the enable gate 650CE (dashed box) and enable gate 650DF (dashed box) can be formed as merged enable gates associated with the enable gates 550C to 550F shown in FIG. 5. For example, the enable gate 650CE can be formed at the region where the merged nanofin 640BC (oriented in the gate pitch direction 502) intersects with the enable gate structure 510A (oriented in the cell height direction 504), and the merged enable gate 650DF (dashed box) can be formed at the region where the merged nanofin 640BC intersects with the enable gate structure 510B (oriented in the cell height direction 504).

[0044] In the illustrated embodiment, the merged nanofin 640BC has a width of 642AB. Width 642AB can be, for example, the sum of widths 542A and 542B (shown in both Figures 5 and 6). Accordingly, the formation of the merged nanofin 640BC establishes a third width size for the nanofins in the input stage (input stage 560'). For example, width 642AB is a third usable width added to a first usable width (width 542A) and a second usable width (width 542B), which are widths of different sizes, as described above.

[0045] The varying widths of the nanofins in input stage 560' provide different gate enable capabilities within the input stage. Furthermore, the merging of the channel region and nanofins reduces the total number of enable gates in input stage 560' while maintaining the total area of ​​the enable gates in the input stage (e.g., current drive capability). For example, input stage 560' shown in Figure 6 has six enable gates, while input stage 560 shown in Figure 5 has eight enable gates, but the total enable gate area (and therefore the current drive capability) is approximately the same. Additional variation in the width of the nanofins in input stage 560' provides additional flexibility in the design of device 600 by offering three options for gate characteristics and corresponding gate connectivity that can be implemented in various types of transistor devices. Example computer system

[0046] Turning to Figure 7, a block diagram of one embodiment of system 700 is shown, which may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 700 includes at least one instance of a system-on-chip (SoC) 706, which may include various types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise, communication mesh architecture, and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 706 include multiple execution lanes and instruction dispatch queues. In various embodiments, SoC 706 is coupled to external memory 702, peripheral devices 704, and a power supply 708.

[0047] A power supply 708 is also provided, which supplies supply voltage to the SoC 706 and one or more supply voltages to memory 702 and / or peripheral devices 704. In various embodiments, the power supply 708 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SoC 706 is included (and more than one external memory 702 is also included).

[0048] Memory 702 refers to any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3, and / or low-power versions of SDRAM such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the devices are mounted using a SoC or integrated circuit in a chip-on-chip configuration, package-on-package configuration, or multi-chip module configuration.

[0049] Peripheral device 704 may include any desired circuitry depending on the type of system 700. For example, in one embodiment, peripheral device 704 includes means for various types of wireless communication (such as WiFi, Bluetooth, cellular, GPS, etc.). In some embodiments, peripheral device 704 may also include additional storage, including RAM, solid-state storage, or disk storage. Peripheral device 704 includes user interface devices such as a display screen (including a touch screen or multi-touch screen), a keyboard or other input device, a microphone, a speaker, etc.

[0050] As illustrated, system 700 is shown to have applications in a wide range of fields. For example, system 700 can be used as part of a chip, circuit system, component, etc., of a desktop computer 710, laptop computer 720, tablet computer 730, cellular or mobile phone 740, or television 750 (or a set-top box coupled to a television). A smartwatch and health monitoring device 760 are also illustrated. In some embodiments, the smartwatch may include a variety of general computing-related functions. For example, the smartwatch may provide email, mobile phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functions. For example, the health monitoring device may monitor a user's vital signs, track the user's proximity to other users for the purpose of social distancing during an epidemic, contact tracing, and provide communication to emergency services in the event of a health crisis. Epidemiological functions (such as contact tracing), providing communication to emergency medical services, etc. In various embodiments, the smartwatches mentioned above may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0051] System 700 can be further used as part of (multiple) cloud-based services 770. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 700 can be used in one or more devices in a home 780, different from those previously mentioned. For example, appliances in the home can monitor and detect conditions of concern. For example, various devices in the home (e.g., refrigerators, air conditioning systems, etc.) can monitor the status of the devices and provide alerts to the homeowner when specific events are detected (or, for example, repair facilities). Alternatively, a thermostat can monitor the temperature in the home and automatically adjust the heating / cooling system based on the homeowner's historical responses to various conditions. Figure 7 also illustrates the application of System 700 to various transportation modes 790. For example, system 700 can be used in the control and / or entertainment systems of airplanes, trains, buses, taxis, private cars, surface vessels ranging from private boats to cruise ships, locomotives (for rental or personal use), etc. In various cases, system 700 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, and other aspects. Many other embodiments are possible and contemplated. It should be noted that the apparatus and applications illustrated in Figure 7 are illustrative only and are not intended to be limiting. Other apparatuses are possible and contemplated. ***

[0052] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiment" or "various embodiments"). An embodiment is a different implementation or example of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," and the like do not necessarily refer to the same embodiment. Numerous possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives falling within the spirit or scope of this disclosure.

[0053] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all embodiments of these embodiments will necessarily exhibit any or all of the potential advantages. Whether the advantages realized for a particular embodiment depend on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why embodiments falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure (in conjunction with one of the disclosed embodiments) that renders one or more of the disclosed advantages ineffective or diminished. Furthermore, suboptimal design implementation of a particular embodiment (e.g., the embodiment technique or tooling) may also render the disclosed advantages ineffective or diminished. Even assuming a skilled embodiment, the realization of advantages may still depend on other factors, such as the environmental conditions in which the embodiment is deployed. For example, inputs applied to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, resulting in the inability to achieve the benefits of its solution. Given the existence of possible factors outside this disclosure, it is expressly intended that any potential advantages described herein not be construed as requiring compliance with the claims to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the (multiple) types of improvements available to designers who have the benefits of this disclosure. Such advantages described permissibly (e.g., stating that a particular advantage "may cause") are not intended to convey any doubt as to whether such advantages are actually achievable, but rather to acknowledge that the technical reality of achieving such advantages often depends on additional factors.

[0054] Unless otherwise stated, the embodiments are not limiting. That is, the disclosed embodiments are not intended to limit the scope of the draft claims based on this disclosure, even if only a single instance with respect to a particular feature is described. The disclosed embodiments are intended to be illustrative and not limiting, and there is no statement to the contrary in this disclosure. Therefore, this application is intended to allow the scope of the claims to cover the disclosed embodiments and such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to which this disclosure pertains.

[0055] For example, the features in this application can be combined in any suitable manner. Accordingly, during the examination of this application (or the application claiming priority), a new claim may be made for any such combination of features. Specifically, referring to the claims of the accompanying patent application, features from independent claims may be combined with features from other independent claims, including, where appropriate, claims attached to other subsidiary claims. Similarly, features from individual subsidiary claims may be combined, where appropriate.

[0056] Accordingly, while the accompanying subsidiary claims may be drafted such that each is dependent on a single other claim, additional dependencies are also contemplated. Any combination of features of the subsidiary claims consistent with this disclosure is contemplated and may be claimed in this application or another application. In short, combinations are not limited to those specifically enumerated in the scope of the appended patent application.

[0057] Where appropriate, it is also envisioned that a request drafted in one format or statutory type (e.g., device) is intended to support a corresponding request in another format or statutory type (e.g., method). ***

[0058] Because this disclosure is a legal document, all terms and phrases used are subject to administrative and judicial interpretation. The following paragraphs and the definitions provided throughout this disclosure are intended to determine how to interpret the scope of any patent application drafted based on this disclosure.

[0059] Unless the context explicitly specifies otherwise, the singular form of an item (i.e., a noun or noun phrase preceded by "a / an" or "the") is intended to mean "one or more" (or "one or more"). Therefore, mentioning "an item" in a claim does not exclude additional instances of that item without accompanying context. "Plurality" refers to a set of one of two or more items.

[0060] In this article, the word "may" is used in the sense of permission (i.e., having the possibility or ability to) and not in the sense of mandatory (i.e., being required to).

[0061] The terms “comprising” and “including” and their forms are open-ended, meaning “including, but not limited to”.

[0062] When the term "or" is used in this disclosure with respect to a list of options, it is generally understood to be used in an inclusive sense unless the context otherwise provides. Therefore, the statement "x or y" is equivalent to "x or y, or both," thus: 1) covering x but not y; 2) covering y but not x; and 3) covering both x and y. On the other hand, phrases such as "either x or y, but not both" clearly indicate that "or" is used in an exclusive sense.

[0063] The statements "w, x, y, or z, or any combination thereof" or "... at least one of ... w, x, y, and z" are intended to cover all possibilities involving a single element or at most a total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element of the set (e.g., w but not x, y, or z)), any two elements (e.g., w and x, but not y or z)), any three elements (e.g., w, x, and y, but not z)), and all four elements. Therefore, the phrase "...w, x, y, and z at least one" refers to at least one element of the set [w, x, y, z], thereby encompassing all possible combinations of this list of elements. This phrase is not interpreted as requiring at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0064] In this disclosure, various "labels" may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for a feature (e.g., "first circuit," "second circuit," "specific circuit," "given circuit," etc.) refer to different instances of that feature. Additionally, unless otherwise stated, the labels "first," "second," and "third," when applied to a feature, do not imply any type of order (e.g., spatial, temporal, logical, etc.).

[0065] The phrase "based on" is used to describe one or more factors that influence a decision. This term does not preclude the possibility that additional factors may influence the decision. That is, a decision may be based solely on a particular factor, or on that particular factor and other unspecified factors. Consider the phrase "determine A based on B." This phrase indicates that B is a factor used to determine A, or that B influences the decision of A. This phrase does not preclude the possibility that A may also be determined based on other factors, such as C. This phrase is also intended to encompass an embodiment where A is determined solely based on B. As used herein, the term "based on" is synonymous with the term "based at least in part on."

[0066] The phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with or independently of any of the specified factors. That is, an effect may be a response to these factors alone, or it may be a response to these specified factors and other unspecified factors. Consider the phrase "perform A in response to B." This phrase specifies that B is a factor that triggers the execution of A or a specific result of A. This phrase does not exclude the possibility that A may also be performed in response to another factor (such as C). This phrase also does not exclude the possibility that A may be performed in conjunction with responses to B and C. This phrase is also intended to cover instances where A is performed in response to B alone. As used herein, the phrase "responsive to" is synonymous with the phrase "responsive at least in part to." Similarly, the phrase "in response to" is synonymous with the phrase "at least in part in response to". ***

[0067] In this disclosure, different entities (which may be referred to differently as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This notation ("entity" configured to "perform one or more tasks") is used herein to refer to a structure (i.e., a physical object). Specifically, this notation indicates that the structure is configured to perform the one or more tasks during operation. Even if a structure is not currently being operated, it may still be said that the structure is "configured to" perform a task. Therefore, an entity described or stated as being "configured to" perform a task refers to a physical object, such as a device, circuit, system with a processing unit, or memory storing executable program instructions to perform that task. This phrase is not used herein to refer to intangible things.

[0068] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform such tasks / operations, even if not specifically mentioned.

[0069] The term "configured to" does not imply "configurable to". For example, an unprogrammed FPGA will not be considered "configured to" performing a specific function. However, this unprogrammed FPGA may be "configurable to" performing that function. After proper programming, the FPGA can then claim to be "configured to" performing a specific function.

[0070] For the purposes of this disclosed U.S. patent application, it is expressly intended that a structure be described in a claim as being "configured to" perform one or more tasks. [Not] invoke 35 USC § 112(f) to interpret the claim element. If the applicant intends to invoke section 112(f) during the examination of a U.S. patent application based on this disclosure, the claim element will be stated using the phrase "a component for 'performing a function'".

[0071] Different “circuit” may be described in this disclosure. These circuits or “circuitry” constitute hardware comprising various types of circuit elements, such as combinational logic, time-controlled storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuit systems may be custom-designed or taken from standard libraries. In various implementations, circuit systems may include digital components, analog components, or a combination of both, as needed. Certain types of circuits are often referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit systems.

[0072] Therefore, the disclosed circuits / units / components and other elements illustrated herein include hardware elements, such as those described in the preceding paragraphs. In many instances, the internal configuration of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" can be described as having the function of "processing an opcode of an instruction and routing that instruction to one or more of a plurality of functional units," meaning that the decoder unit is "configured to" perform this function. This description of function is sufficient for those skilled in the art of computer science to indicate a feasible set of structures for that circuit.

[0073] In various embodiments, as discussed in the preceding paragraphs, circuits, units, and other elements defined by the functions or operations implemented therefrom through configuration, this configuration, and the manner in which such circuits / units / components interact with each other, form a micro-level definition of hardware, which is ultimately manufactured in integrated circuits or programmed into an FPGA to form a physical implementation of the micro-level definition. Therefore, this micro-level definition is a structure from which many physical implementations are recognized by those skilled in the art, all of which fall within the broad structure described by the micro-level definition. That is, those skilled in the art who propose the micro-level definition provided according to this disclosure can implement this structure without excessive experimentation and by applying common knowledge, by encoding the description of the circuits / units / components in a hardware description language (HDL) (such as Verilog or VHDL). HDL descriptions are often expressed in a functional manner. However, for those with ordinary knowledge in the relevant technical field, this HDL description is used to transform the structure of a circuit, unit, or component into the details of a next-level implementation. This HDL description can take the form of behavioral code (which is generally not synthesizable), register transfer language (RTL) code (which is generally synthesizable, as opposed to behavioral code), or structured code (e.g., a wiring lookup table specifying logic gates and their connections). Subsequently, the HDL description can be synthesized based on a component library designed for a given integrated circuit manufacturing technique, and can be modified for timing, power, and other reasons to produce a final design database, which is transferred to a manufacturing plant to create a mask, ultimately producing the integrated circuit. Some hardware circuitry or portions thereof can also be customized in a schematic editor and transferred to the integrated circuit design along with the synthesized circuit system. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnections between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement hardware circuitry, and / or discrete components may be used in some embodiments. Alternatively, HDL designs may be synthesized into a programmable logic array, such as a field-programmable gate array (FPGA), and implemented within the FPGA. The decoupling between the design of this group of circuits and subsequent lower-level implementations of these circuits typically results in a situation where, when this process is executed at a different stage of the circuit implementation, the circuit or logic designer never specifies a particular set of structures for the lower-level implementation that goes beyond the description of the actions the circuit is configured to perform.

[0074] In fact, many different lower-level combinations of circuit elements can be used to implement circuits of the same specifications, resulting in a large number of equivalent structures. As mentioned, these lower-level circuit implementations can vary depending on changes in manufacturing technology, the choice of manufacturer to produce integrated circuits, and the component library provided for a particular project. In many cases, the choice of different design tools or methodologies to produce these different implementations can be arbitrary.

[0075] Furthermore, for a single implementation of a circuit with a specific functional specification, it is common to include a large number of devices (e.g., millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete description of the underlying structure for implementing a single embodiment, let alone an equivalent feasible implementation of a massive array. For this reason, this disclosure describes circuit structures using functional shorthand commonly used in the industry.

[0076] 100: Nano-plate transistor; transistor 110: Gate 120: Passage Area 130: Nanofin 140: Substrate Channel 145: Shallow Trench Isolation (STI) 150: Substrate 300: Unit 302: Gate pitch direction 304: Unit height direction 310A, 310B, 310C: Gate structure enabled; Gate structure 320A, 320B: Virtual gate structure 330A, 330B: Passage Area 340A, 340B: Nanofins 342A, 342B: Width 350, 350A, 350B, 350C, 350D, 350E, 350F: Gate enabled; Gate 360: Input Level 370: Output stage 400: Transistor device; apparatus 402: Gate Pitch Direction 404: Element height direction 406A, 406B: Standard unit height 410A, 410B: Gate structure enabled 420A, 420B: Virtual gate structure 430, 430A, 430B, 430C, 430D: Passage Area 440, 440A, 440B, 440C, 440D: Nanofins 442A, 442B: Width 450A, 450B, 450C, 450D, 450E, 450F, 450G, 450H: Enable gate 460: Input Level 470: Output stage 500: Transistor device; apparatus 502: Gate pitch direction 504: Unit height direction 506A, 506B: Standard unit height 510A, 510B, 510C: Gate structure enabled 520A, 520B, 520C: Virtual gate structure 530A, 530B, 530C, 530D, 530E, 530F, 530G: Channel Area 540A, 540B, 540C, 540D, 540E, 540F, 540G: Nanofins 542A, 542B, 542C, 542D: Width 550A, 550B, 550C, 550D, 550E, 550F, 550G, 550H, 550I, 550J, 550K: Enable gate 560: Input Level 560': Input level 570: Output stage 600: Transistor Device 630BC: Area via merged corridor 640BC: Combined nanofin 642AB: Width 650CE: Gate Enabled 650DF: Enable gate 700: Display System 702: External Memory 704: Peripheral Equipment 706: System-on-a-Chip (SoC) 708: Power Supply 710: Desktop computer 720: Laptop 730: Tablet PC 740: Cellular or mobile phone 750: Television 760: Smartwatches and Health Monitoring Devices 770: Cloud-based services 780: Home 790: Transportation Mode

Claims

1. An integrated circuit device comprising: a substrate; a plurality of gate structures oriented in a horizontal dimension along a first direction above the substrate; a plurality of elongated channel regions oriented in the horizontal dimension along a second direction perpendicular to the first direction, wherein the elongated channel regions pass through at least one of the gate structures, and wherein the elongated channel regions include two or more nanofins stacked in a vertical dimension above the substrate; A first stage comprising at least two of the elongated channel regions, wherein the nanofins in one of the at least two elongated channel regions of the first stage have a first width in the horizontal dimension along the first direction, and the nanofins in one of the at least two elongated channel regions of the first stage have a second width in the horizontal dimension along the first direction, the second width being greater than the first width; and a second stage comprising at least one of the elongated channel regions, wherein the nanofins in the at least one other elongated channel region of the second stage have a third width in the horizontal dimension along the first direction, the third width being greater than the first width.

2. The apparatus of claim 1, wherein the nanosheets are aligned parallel to the substrate in the vertical dimension.

3. The apparatus of claim 1, wherein an active gate is formed at an intersection of at least one of the elongated channel regions and at least one of the gate structures.

4. The apparatus of claim 1, wherein the elongated channel regions extend between a first dummy gate structure on a first side of the apparatus in the horizontal dimension and a second dummy gate structure on a second side of the apparatus in the horizontal dimension.

5. The apparatus of claim 1, wherein the nanofins are substantially surrounded by a portion of the at least one gate structure, wherein the nanofins pass through the at least one gate structure.

6. The apparatus of claim 1, wherein the first stage includes at least one additional elongated channel region, wherein the nanofin in the at least one additional elongated channel region of the first stage has the first width.

7. The apparatus of claim 1, wherein the second stage includes at least two of the elongated channel regions, and the nanofins in the at least two elongated channel regions of the second stage have the third width.

8. The apparatus of claim 1, wherein the second stage includes at least two of the elongated channel regions, and the nanofins in the at least two elongated channel regions of the second stage are combined.

9. The apparatus of claim 1, wherein the apparatus includes one or more integrated circuit units, and wherein the first direction in the horizontal dimension is a unit height direction, and the second direction in the horizontal dimension is a gate pitch direction.

10. The apparatus of claim 9, wherein at least one of the gate structures extends across both the first stage and the second stage in the height direction of the unit.

11. The apparatus of claim 9, wherein the second stage is separated from the first stage in the gate pitch direction by at least one dummy gate structure oriented in the unit height direction.

12. The apparatus of claim 1, wherein the first stage includes at least one additional elongated channel region, wherein the nanofin in the at least one additional elongated channel region of the first stage has the second width.

13. The apparatus of claim 1, wherein the third width and the second width are the same width.

14. An integrated circuit device comprising: a plurality of gate structures oriented above a substrate in a horizontal dimension along a first direction, wherein the plurality of gate structures includes: A first dummy gate structure positioned on a first side of the device along a second direction perpendicular to the first direction in the horizontal dimension; a second dummy gate structure positioned on a second side of the device along the second direction; and at least one enable gate structure positioned between the first dummy gate structure and the second dummy gate structure; a plurality of elongated channel regions oriented along the second direction and extending between the first dummy gate structure and the second dummy gate structure, wherein the elongated channel regions pass through the at least one enable gate structure, and wherein the elongated channel regions include two or more nanofins stacked in a vertical dimension above the substrate; A first stage comprising at least one of the elongated channel regions, wherein the nanofins in the at least one elongated channel region of the first stage have a first width in the horizontal dimension along the first direction; and a second stage comprising at least two other elongated channel regions, wherein the nanofins in at least one of the other two elongated channel regions of the second stage have a second width in the horizontal dimension along the first direction, the second width being greater than the first width, and wherein the nanofins in the at least two other elongated channel regions of the second stage are merged.

15. The apparatus of claim 14, wherein the second stage is separated from the first stage in the first direction.

16. The apparatus of claim 14, wherein the gate structures extend across both the first stage and the second stage.

17. The apparatus of claim 14, wherein the first stage includes at least two of the elongated channel regions, the nanofins in the at least two elongated channel regions of the first stage having the first width, and wherein the second stage includes at least two of the elongated channel regions, the nanofins in the at least two elongated channel regions of the second stage having the second width.

18. An integrated circuit device comprising: a plurality of gate structures oriented above a substrate in a horizontal dimension along a first direction, wherein the plurality of gate structures includes: A first dummy gate structure positioned on a first side of the device along a second direction perpendicular to the first direction in the horizontal dimension; a second dummy gate structure positioned on a second side of the device along the second direction; two or more enabled gate structures positioned between the first dummy gate and the second dummy gate. and a third dummy gate structure, which is positioned between at least two of the activated gate structures; A first stage comprising: a plurality of first elongated channel regions oriented along the second direction and extending between the first dummy gate structure and the third dummy gate structure, wherein the first elongated channel regions pass through at least one of the enabled gate structures, wherein the first elongated channel regions include two or more first nanofins stacked in a vertical dimension above the substrate, the first nanofins in at least one of the first elongated channel regions of the first stage having a first width in the horizontal dimension along the first direction; and a second stage comprising: A plurality of second elongated channel regions oriented along the second direction and extending between the third dummy gate structure and the second dummy gate structure, wherein the second elongated channel regions pass through at least one of the enabled gate structures, wherein the second elongated channel regions include two or more second nanofins stacked above the substrate in the vertical dimension, wherein the second nanofins in at least one of the second elongated channel regions of the second stage have a second width in the horizontal dimension along the first direction, the second width being greater than the first width, and wherein the second nanofins in at least two of the second elongated channel regions are merged.

19. The apparatus of claim 18, wherein the second stage is separated from the first stage by the third dummy gate structure.

20. The apparatus of claim 18, wherein the first stage further includes at least one first nanofin of at least another of the first elongated channel regions of the first stage having the second width.

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