Low-power voltage regulator with fast transient response

Abstract

In some embodiments, a voltage regulator includes a transmission means coupled between an input and an output of the voltage regulator. The voltage regulator also includes an amplifier circuit having a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to the gate of the transmission means. The voltage regulator further includes a first current source coupled between a power supply rail and the amplifier circuit, and a capacitor coupled between the first current source and the output of the voltage regulator.

Description

Technical Field

[0001] This case asserts priority and interest in non-provisional application No. 17 / 154,865 filed with the U.S. Patent and Trademark Office on January 21, 2021.

[0002] In summary, the contents of this application pertain to voltage regulators, and more specifically, to low dropout (LDO) regulators. Prior Technology

[0003] Voltage regulators are used in a variety of systems to provide regulated voltages to the power supply circuits within those systems. A commonly used voltage regulator is the low-dropout (LDO) regulator. An LDO regulator typically includes a pass-through device and an amplifier coupled in a feedback loop to provide a regulated output voltage based on a reference voltage. Summary of the Invention

[0004] The following provides a simplified overview of one or more implementations to offer a basic understanding of such implementations. This invention is not an exhaustive summary of all anticipated implementations, nor is it intended to identify key or essential elements of all implementations, nor to illustrate the scope of any or all implementations. Its sole purpose is to provide, in a simplified form, some concepts of one or more implementations as a prelude to the more detailed description that follows.

[0005] The first embodiment relates to a voltage regulator. The voltage regulator includes a transfer device coupled between an input and an output of the voltage regulator. The voltage regulator also includes an amplifier circuit having a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to the gate of the transfer device. The voltage regulator further includes a first current source coupled between a power supply rail and the amplifier circuit; and a capacitor coupled between the first current source and the output of the voltage regulator.

[0006] The second aspect relates to a method of operating a voltage regulator. The voltage regulator includes a transmission device coupled between the input and output of the voltage regulator, and an amplifier circuit coupled to the gate of the transmission device. The method includes: detecting a transient voltage drop at the output of the voltage regulator via a capacitor; and increasing a bias current to the amplifier circuit based on the detected transient voltage drop.

[0007] A supplier relates to a chip. The chip includes: pads; a power rail; a reference circuit configured to generate a reference voltage; and a voltage regulator. The voltage regulator includes: a transfer device coupled between an input of the voltage regulator and an output of the voltage regulator, wherein the input of the voltage regulator is coupled to the power rail. The voltage regulator also includes: an amplifier circuit having a first input, a second input, and an output, wherein the first input is coupled to the reference circuit, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to the gate of the transfer device. The voltage regulator also includes: a first current source coupled between the power rail and the amplifier circuit; and a capacitor coupled between the first current source and the output of the voltage regulator. Simple Explanation of the Diagram

[0008] Figure 1 illustrates an example of a low-dropout (LDO) regulator.

[0009] Figure 2 illustrates an example of the fluctuation of the output voltage of an LDO regulator caused by changes in load current, according to certain conditions described in this case.

[0010] Figure 3 illustrates an example of an LDO regulator with self-adjusting current bias, according to certain aspects of the present case.

[0011] Figure 4 illustrates an exemplary implementation of a self-adjusting current source in certain states according to the content of this case.

[0012] Figure 5 illustrates an example of the response time for self-adjusting current bias in certain states according to the content of this case.

[0013] Figure 6 illustrates an LDO regulator with dynamic current bias and self-adjusting current bias, according to certain aspects of the case.

[0014] Figure 7 illustrates an exemplary implementation of a current source for dynamic current biasing according to certain states of the present case.

[0015] Figure 8 illustrates an exemplary implementation of an amplifier circuit of certain types according to the contents of this case.

[0016] Figure 9 illustrates an exemplary implementation of a bias circuit, error amplifier, and buffer according to certain states of the present case.

[0017] Figure 10 illustrates an example of a chip including an LDO regulator according to certain states of the present case.

[0018] Figure 11 is a flowchart of a method for operating a voltage regulator in certain states according to the content of this case. Implementation

[0019] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations, and not as representing the only configuration in which the concepts described herein can be implemented. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art to which this invention pertains that these concepts can be implemented without these specific details. In some instances, well-known structures and components are illustrated in block diagram form to avoid obscuring such concepts.

[0020] Voltage regulators can be used to provide circuit blocks with a power supply voltage different from the main power supply voltage and / or to convert noisy power supply voltages into clean power supply voltages.

[0021] A commonly used voltage regulator is the low dropout (LDO) regulator, an example of which is illustrated in Figure 1. The exemplary LDO regulator 110 shown in Figure 1 has an input 105 coupled to a voltage supply rail 112 and an output 130 coupled to a circuit block 170. The LDO regulator 110 is configured to convert the supply voltage VDD on the supply rail 112 into a regulated output voltage Vout at the output 130 of the LDO regulator 110.

[0022] LDO regulator 110 includes a transfer device 115 coupled between input 105 and output 130 of LDO regulator 110. In the example in FIG1, transfer device 115 is implemented using a p-type field-effect transistor (PFET) having a source coupled to input 105 and a drain coupled to output 130. However, it will be understood that in other implementations, transfer device 115 may be implemented using another type of transistor (e.g., an n-type field-effect transistor (NFET)). It will also be understood that transfer device 115 may be implemented using multiple transistors coupled in parallel.

[0023] LDO regulator 110 also includes amplifier circuit 120 having an output 126 coupled to a gate of transfer device 115, a first input 122 coupled to a reference voltage Vref, and a second input 124 coupled to output 130 via feedback path 150. The reference voltage Vref can be provided by a bandgap reference circuit or another type of circuit. LDO regulator 110 may also include a voltage divider 160 coupled between output 130 and ground. In the example in FIG1, voltage divider 160 includes a first feedback resistor R1 and a second feedback resistor R2 coupled in series between output 130 and ground. In this example, the second input 124 of amplifier circuit 120 is coupled to node 165 between the first feedback resistor R1 and the second feedback resistor R2. Voltage divider 160 is configured to generate a feedback voltage Vfb at node 165, which is fed to the second input 124 of amplifier circuit 120. The feedback voltage Vfb is proportional to the output voltage Vout of the LDO regulator 110 and is provided by the following: (1) Where R1 is the resistance of the first feedback resistor R1, and R2 is the resistance of the second feedback resistor R2.

[0024] In operation, the amplifier circuit 120 adjusts the gate voltage of the transmission device 115 in the direction of reducing the difference (i.e., error) between the reference voltage Vref and the feedback voltage Vfb. This forces the output voltage Vout of the LDO regulator 110 to be approximately equal to the following: (2) Therefore, the output voltage Vout can be set to the desired voltage by setting the resistance of the feedback resistors R1 and R2 and / or setting the reference voltage Vref accordingly.

[0025] The output voltage Vout fluctuates during changes in the load current ILoad (i.e., the current drawn by circuit block 170). Figure 2 illustrates an example of the fluctuation in output voltage Vout caused by changes in the load current ILoad. In this example, the load current ILoad rises to ∆ILoad and then falls back to ∆ILoad. This can happen, for example, when circuit block 170 transitions from a standby state to an active state and then back to a standby state.

[0026] As shown in Figure 2, an increase in the load current ILoad causes an undershoot 210 in the output voltage Vout, and a decrease in the load current ILoad causes an overshoot 220 in the output voltage Vout. It is desirable to reduce the undershoot and overshoot in the output voltage Vout (i.e., reduce the fluctuations in the output voltage Vout) to ensure the accurate performance of circuit block 170.

[0027] One approach to reducing output voltage Vout fluctuations is to couple a large off-chip capacitor to the output 130 of the LDO regulator 110 to absorb load current variations. However, this approach increases area and cost. A second approach is to provide a large, constant bias current to the amplifier circuit 120 to increase the loop bandwidth of the LDO regulator 110, thereby giving the LDO regulator 110 a faster transient response. A faster transient response allows the LDO regulator 110 to quickly reduce fluctuations in the output voltage Vout. However, the large constant bias current results in higher power consumption.

[0028] In another approach, the LDO regulator 110 uses a self-adjusting current bias, where the bias current to the amplifier circuit 120 is adjusted based on the load current. In this regard, Figure 3 illustrates an example of an LDO regulator 110 with a self-adjusting current bias according to certain configurations. In this example, the LDO regulator 110 includes a current source 310 coupled between the power supply rail 112 and the amplifier circuit 120, wherein the current source 310 is configured to provide a bias current to the amplifier circuit 120. The current source 310 is also coupled to the gate of the transfer device 115. The current source 310 is configured to sense the load current from the gate voltage of the transfer device 115 and adjust the bias current to the amplifier circuit 120 based on the sensed load current. In some configurations, the current source 310 is configured to increase the bias current when the sensed load current increases and decrease the bias current when the sensed load current decreases. By increasing the bias current when the sensed load current is high (i.e., heavy), the current source 310 increases the loop bandwidth of the LDO regulator 110 when the sensed load current is high (and thus reduces the transient response time).

[0029] Figure 4 illustrates an exemplary implementation of a current source 310 according to certain states. In this example, the current source 310 includes a transistor 410 coupled between the power supply rail 112 and the amplifier circuit 120. In the example in Figure 4, the transistor 410 is implemented using a PFET having a source coupled to the power supply rail 112 and a drain coupled to the amplifier circuit 120. However, it will be understood that the transistor 410 may be implemented using another type of transistor in other implementations. It will also be understood that the transistor 410 may include multiple transistors coupled between the power supply rail 112 and the amplifier circuit 120. In this example, the gate of the transistor 410 is coupled to the gate of the transfer device 115, which allows the transistor 410 to sense the load current from the gate voltage of the transfer device 115 and adjust the bias current based on the sensed load current.

[0030] Compared to the first method, self-adjusting current bias is advantageous by eliminating the need for the large off-chip capacitors used in the first method. Furthermore, self-adjusting current bias reduces the bias current when the sensed load current is light (this can occur, for example, when circuit block 170 is in standby mode). Compared to the second method using a large, constant bias current, the reduced bias current during light load current periods lowers power consumption.

[0031] However, self-adjusting current bias may not provide sufficient reduction in voltage downsurge due to changes in load current from light to heavy load. An example of this is illustrated in Figure 5, showing an instance of bias current IBias and load current ILoad. In this example, the load current ILoad rises at time T1 and falls at time T2.

[0032] Before time T1, the load current ILoad is low (i.e., light). As a result, the bias current IBias is also low, which reduces the loop bandwidth of the LDO regulator 110 (and thus increases the transient response time). At time T1, the load current ILoad rises, causing a voltage undershoot in the output voltage Vout (e.g., undershoot 210). As shown in Figure 5, at the start of the voltage undershoot, the bias current IBias is initially low, and therefore the loop bandwidth of the LDO regulator 110 is initially small. This is because the current source 310 senses changes in the load current ILoad from the gate voltage of the transmission device 115. Since the response of the gate voltage to changes in the load current ILoad is limited by the loop bandwidth of the LDO regulator 110 (which is initially small), there is a relatively long delay TDelay between the rise in the load current ILoad and the increase in the bias current IBias. The initially small loop bandwidth of the LDO regulator 110 (and therefore, the initially slow transient response) can lead to a large output voltage undershoot.

[0033] At time T2, the load current ILoad decreases, causing a voltage overshoot in the output voltage Vout (e.g., overshoot 220). As shown in Figure 5, at the start of the voltage overshoot, the bias current IBias is initially high, and therefore the loop bandwidth of the LDO regulator 110 is initially large. As a result, the LDO regulator 110 can respond quickly to the decrease in the load current ILoad, and thus significantly reduce the voltage overshoot.

[0034] Therefore, when the load current ILoad changes from a light load to a heavy load, although the self-adjusting current bias significantly reduces voltage overshoot, it may not provide sufficient reduction for voltage undershoot due to the initial small loop bandwidth of the LDO regulator 110.

[0035] To address this issue, the various states of this application provide dynamic current bias to reduce undershoot in the output voltage Vout caused by changes in load current ILOAD from light to heavy load, as discussed further below. The dynamic current bias of the various states of this application can be used in conjunction with a self-adjusting current bias, or it can be used without a self-adjusting current bias.

[0036] Figure 6 illustrates an example of an LDO regulator 110 with dynamic current bias according to certain configurations. In this example, the LDO regulator 110 also includes the current source 310 for self-adjusting current bias discussed above. However, it will be understood that the current source 310 may be omitted in some implementations.

[0037] In this example, the LDO regulator 110 also includes a bias current source 610 and a feedback capacitor 615 for providing dynamic current bias. In the following discussion, the bias current source 610 is referred to as the first bias current source 610, and the bias current source 610 is referred to as the second bias current source 610.

[0038] A first current source 610 is coupled between the power supply rail 112 and the amplifier circuit 120, wherein the first current source 610 is configured to provide bias current to the amplifier circuit 120. A feedback capacitor 615 is coupled between the first current source 610 and the output 130 of the LDO regulator 110. Thus, the first bias current source 610 is capacitively coupled to the output 130 of the LDO regulator 110 via the feedback capacitor 615. This capacitive coupling couples a transient voltage drop in the output voltage Vout to the first bias current source 610 during voltage downswing. This allows the first bias current source 610 to detect the transient voltage drop in the output voltage Vout caused by changes in the load current ILoad from a light load to a heavy load. In some cases, the transient voltage drop may have a duration between 10 nanoseconds and 1 microsecond. The first bias current source 610 can quickly detect transient voltage drops in the output voltage Vout because it is capacitively coupled to the output 130 of the LDO regulator 110 via the feedback capacitor 615, which is not limited by the initial small loop bandwidth of the LDO regulator 110 discussed above. In contrast, the response time of the self-adjusting current bias is limited by the loop bandwidth of the LDO regulator 110 (which is initially small) because the second current source 310 detects increases in load current from the gate voltage of the transmission device 115.

[0039] In response to a transient voltage drop detected in the output voltage Vout, the first current source 610 boosts (i.e. increases) the bias current of the amplifier circuit 120. The boosted bias current increases the loop bandwidth of the LDO regulator 110 (i.e., reduces the transient response time), which allows the LDO regulator 110 to respond quickly to voltage undershoot and reduces voltage undershoot.

[0040] Therefore, the first bias current source 610 and the feedback capacitor 615 are rapidly increased to the bias current of the amplifier circuit 120 in response to a transient drop in the output voltage Vout, thereby providing the LDO regulator 110 with a fast transient response to voltage undershoot. Self-adjusting current bias can also be helpful during voltage undershoot. This is because, during the transition from light load current to heavy load current, as the load current increases, self-adjusting bias helps to improve loop bandwidth.

[0041] In the example shown in Figure 6, dynamic current biasing is used in combination with self-adjusting current biasing. In this example, dynamic current biasing can be used to reduce voltage undershoot caused by changes in load current from light load to heavy load, and self-adjusting current biasing can be used to reduce voltage overshoot caused by changes in load current from heavy load to light load. However, it will be understood that in some implementations, dynamic current biasing can be used without self-adjusting current biasing (e.g., where voltage overshoot is not a problem or where voltage overshoot is mitigated by another technique). In such implementations, the second current source 310 can be omitted.

[0042] Figure 7 illustrates an exemplary implementation of a first current source 610 according to certain configurations. In this example, the first current source 610 includes a transistor 710 coupled between the power supply rail 112 and the amplifier circuit 120. In the example in Figure 7, the transistor 710 is implemented by a PFET having a source coupled to the power supply rail 112 and a drain coupled to the amplifier circuit 120. However, it will be understood that the transistor 710 can be implemented using another type of transistor in other implementations. It will also be understood that the transistor 710 may include multiple transistors coupled between the power supply rail 112 and the amplifier circuit 120. Furthermore, in this example, the second current source 310 is implemented by the transistor 410 discussed above with reference to Figure 4.

[0043] In the example shown in Figure 7, the LDO regulator 110 also includes a voltage bias circuit 725 coupled to the gate of transistor 710. In this example, the voltage bias circuit 725 is configured to generate a DC bias voltage Vb, which is applied to the gate of transistor 710 to bias the gate of transistor 710.

[0044] In this example, a feedback capacitor 615 is coupled between the gate of transistor 710 and the output 130 of LDO regulator 110. Therefore, the gate of transistor 710 is capacitively coupled to the output 130 of LDO regulator 110 via the feedback capacitor 615. This capacitive coupling couples a transient voltage drop in the output voltage Vout to the gate of transistor 710, while blocking the bias voltage Vb from the output 130 of LDO regulator 110. The transient voltage drop coupled to the gate of transistor 710 via the feedback capacitor 615 causes the gate voltage of transistor 710 to decrease from the bias voltage Vb. This decrease in gate voltage causes transistor 710 (implemented using a PFET in this example) to increase the bias current to amplifier circuit 120. Therefore, in response to the transient voltage drop at the output 130 of LDO regulator 110 caused by a change in load current from light to heavy load, transistor 710 increases the bias current to amplifier circuit 120.

[0045] Figure 8 illustrates an exemplary implementation of an amplifier circuit 120 according to certain aspects of the present invention. In this example, the amplifier circuit 120 includes an error amplifier 820 and an output buffer 830. The error amplifier 820 is configured to provide high gain to the amplifier circuit 120 and may have high output impedance. The error amplifier 820 may be implemented using a common-source common-gate amplifier or another type of amplifier. The output buffer 830 is configured to provide low output impedance at the output 126 of the amplifier circuit 120 to drive the gate of the transmission device 115. The output buffer 830 may be implemented using a source follower or another type of buffer circuit.

[0046] In the example shown in Figure 8, the error amplifier 820 has a first input 822 (e.g., a negative input) coupled to a reference voltage Vref, a second input 824 (e.g., a positive input) coupled to an output 130 via a feedback path 150, and an output 826. The output buffer 830 has an input 832 coupled to the output 826 of the error amplifier 820 and an output 834 coupled to the gate of the transfer device 115.

[0047] In the example of Figure 8, the transistor 410 shown in Figure 7 includes a first transistor 410-1 coupled between the power supply rail 112 and the error amplifier 820, and a second transistor 410-2 coupled between the power supply rail 112 and the output buffer 830. In this example, the first transistor 410-1 is implemented by a PFET having a source coupled to the power supply rail 112 and a drain coupled to the error amplifier 820, and the second transistor 410-2 is implemented by a PFET having a source coupled to the power supply rail 112 and a drain coupled to the output buffer 830. However, it will be understood that each of transistors 410-1 and 410-2 can be implemented using a different type of transistor in other implementations. The gate of each of transistors 410-1 and 410-2 is gate-coupled to the gate of the transfer device 115 to sense load current from the gate voltage of the transfer device 115. In response to the sensed increase in load current, the first transistor 410-1 increases the bias current of the error amplifier 820, and the second transistor 410-2 increases the bias current of the output buffer 830. Therefore, in this example, the first transistor 410-1 provides a self-adjusting current bias for the error amplifier 820, and the second transistor 410-2 provides a self-adjusting current bias for the output buffer 830.

[0048] In the example of Figure 8, the transistor 710 shown in Figure 7 includes a first transistor 710-1 coupled between the power supply rail 112 and the error amplifier 820, and a second transistor 710-2 coupled between the power supply rail 112 and the output buffer 830. In the example of Figure 8, the first transistor 710-1 is implemented using a PFET having a source coupled to the power supply rail 112 and a drain coupled to the error amplifier 820, and the second transistor 710-2 is implemented using a PFET having a source coupled to the power supply rail 112 and a drain coupled to the output buffer 830. However, it will be understood that each of transistors 710-1 and 710-2 can be implemented using a different type of transistor in other implementations. In this example, a voltage biasing circuit 725 is coupled to the gate of each of transistors 710-1 and 710-2 to bias the gates of transistors 710-1 and 710-2.

[0049] A feedback capacitor 615 is coupled between the output 130 and the gate of each of transistors 710-1 and 710-2. Therefore, the gate of each of transistors 710-1 and 710-2 is capacitively coupled to the output 130 via the feedback capacitor 615. This capacitive coupling couples a transient voltage drop in the output voltage Vout to the gates of transistors 710-1 and 710-2 during a voltage downswing. In response to the transient voltage drop, the first transistor 710-1 increases the bias current to the error amplifier 820, and the second transistor 710-2 increases the bias current to the output buffer 830. Therefore, in this example, the first transistor 710-1 provides a dynamic current bias to the error amplifier 820, and the second transistor 710-2 provides a dynamic current bias to the output buffer 830.

[0050] Figure 9 illustrates an exemplary implementation of a bias circuit 725, an error amplifier 820, and an output buffer 830 according to certain configurations. In this example, the bias circuit 725 includes a transistor 910 (e.g., a PFET) and a resistor 912. The source of the transistor 910 is coupled to a power supply rail 112, and the drain and gate of the transistor 910 are coupled (i.e., connected) together. The resistor 912 is coupled between the drain of the transistor 910 and ground. In this example, a bias voltage Vb is generated at the gate of the transistor 910.

[0051] Error amplifier 820 includes a first input transistor 920 and a second input transistor 922. The gate of the first input transistor 920 is coupled to the first input 822 of error amplifier 820, and the gate of the second input transistor 922 is coupled to the second input 824 of error amplifier 820. Therefore, a reference voltage Vref is applied to the gate of the first input transistor 920, and a feedback voltage Vfb is applied to the gate of the second input transistor 922. In the example in FIG9, each of input transistors 920 and 922 is implemented using a PFET. However, it will be understood that each of input transistors 920 and 922 can be implemented using another type of transistor (e.g., an NFET).

[0052] Error amplifier 820 also includes transistors 924, 926, 930, 932, 934, 940, 942, and 944. Transistors 924 and 934 are coupled in a current mirror configuration, wherein the drain of transistor 924 is coupled to the drain of the first input transistor 920, and the gate of transistor 924 is coupled to the gate and drain of transistor 934. The sources of transistors 924 and 934 are coupled to ground. The source of transistor 932 is coupled to the drain of transistor 934, and the gate of transistor 932 is biased by a bias voltage Vcas. Transistors 930 and 940 are coupled in a current mirror configuration, wherein the drain of transistor 930 is coupled to the drain of transistor 932, and the gate of transistor 930 is coupled to the gate and drain of transistor 940. The drain of transistor 940 is coupled to the output 826 of error amplifier 820.

[0053] Transistors 926 and 944 are coupled in a current mirror configuration, wherein the drain of transistor 926 is coupled to the drain of the second input transistor 922, and the gate of transistor 926 is coupled to the gate of transistor 944 and the drain of transistor 926. The sources of transistors 926 and 944 are coupled to ground. The source of transistor 942 is coupled to the drain of transistor 944, the gate of transistor 942 is biased by a bias voltage Vcas, and the drain of transistor 942 is coupled to the output 826 of error amplifier 820.

[0054] In operation, the current from the first input transistor 920 flows through transistor 924 and is mirrored at the drain of transistor 934. The current from transistor 934 flows through transistors 932 and 930 and is mirrored at the drain of transistor 940, which is coupled to the output 826. The current from the second input transistor 922 flows through transistor 926 and is mirrored at the drain of transistor 944. The current from transistor 944 flows through transistor 942, which is coupled to the output 826. In this example, transistor 942 is coupled to transistor 944 in a common-source, common-gate configuration, which increases the output impedance and gain of the error amplifier 820.

[0055] In this example, the LDO regulator 110 includes a bias generation circuit 915 configured to generate a bias voltage Vcas according to certain conditions. The bias generation circuit 915 includes a bias transistor 914, a resistor Rb, and a capacitor Cb. The resistor Rb and capacitor Cb are coupled in parallel between nodes 916 and 918, where the bias voltage Vcas is generated at node 916. The drain of transistor 914 is coupled to node 918 and the gate of transistor 914, and the source of transistor 914 is coupled to ground. Node 916 is coupled to the bias input 935 of amplifier 820, which is coupled to the gates of transistors 932 and 942. In this example, the resistance of resistor Rb is used to set the voltage difference between the gates of transistors 932 and 934, and between the gates of transistors 942 and 944. The capacitor Cb helps ensure that the voltage difference remains approximately constant under different self-adjusting biases.

[0056] In this example, the error amplifier 820 also includes a capacitor Cm coupled between the output 130 and the drain of the transistor 944. The capacitor Cm serves as a Miller compensation capacitor to achieve stability and enhance the loop bandwidth during transient response.

[0057] In this example, output buffer 830 includes transistors 950, 952, 954, and 956. The gate of transistor 954 is coupled to input 832 of output buffer 830, and the source of transistor 954 is coupled to output 834 of output buffer 830. As further discussed below, transistor 954 is configured as a source follower to provide low output impedance to buffer 830.

[0058] Transistors 950 and 952 are coupled in a current mirror configuration, wherein the gate of transistor 950 is coupled to the gate of transistor 952 and the drain of transistor 950. The sources of transistors 950 and 952 are coupled to ground. The drain of transistor 952 is coupled to the drain of transistor 954. As further discussed below, transistor 950 receives a bias current, which is mirrored at the drain of transistor 952.

[0059] The gate of transistor 956 is coupled to the drain of transistor 954, the drain of transistor 956 is coupled to the output 834 of buffer 830, and the source of transistor 956 is coupled to ground. In this example, transistor 956 is coupled to transistor 954, which is a super-source follower configuration that further reduces (i.e., attenuates) the output impedance of buffer 830. The super-source follower configuration reduces the output impedance to 1 / (gm1*gm2*ro1), where gm1 is the transconductance of transistor 954, gm2 is the transconductance of transistor 956, and ro1 is the impedance of transistor 954. It will be understood that transistors 952 and 956 can be omitted in some implementations. For implementations that omit transistors 952 and 956, the output impedance of buffer 830 is approximately 1 / gm1.

[0060] In the example shown in Figure 9, the transistor 410 in Figure 7 includes a first transistor 410-1 coupled between the power supply rail 112 and the drain of transistor 914, a second transistor 410-2 coupled between the power supply rail 112 and the source of input transistors 920 and 922, a third transistor 410-3 coupled between the power supply rail 112 and the drain of transistor 950, and a fourth transistor 410-4 coupled between the power supply rail 112 and the source of transistor 954. In this example, the first transistor 410-1 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to transistor 914; the second transistor 410-2 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to the sources of input transistors 920 and 922; the third transistor 410-3 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to transistor 950; and the fourth transistor 410-4 is implemented using a PFET with a source coupled to power rail 112 and a drain coupled to transistor 954. However, it will be understood that each of transistors 410-1 to 410-4 can be implemented in other implementations using a different type of transistor. The gate of each of transistors 410-1 to 410-4 is gate-coupled to the gate of transmission device 115 to sense load current from the gate voltage of transmission device 115 and adjust the corresponding bias current based on the sensed load current. Thus, transistors 410-1 to 410-4 provide a self-adjusting current bias for amplifier circuit 120.

[0061] In the example shown in Figure 9, the transistor 710 shown in Figure 7 includes a first transistor 710-1 coupled between the power supply rail 112 and node 916 of the bias generation circuit 915, a second transistor 710-2 coupled between the power supply rail 112 and the source of the input transistors 920 and 922, a third transistor 710-3 coupled between the power supply rail 112 and the drain of transistor 950, and a fourth transistor 710-4 coupled between the power supply rail 112 and the source of transistor 954. In the example shown in Figure 9, the first transistor 710-1 is implemented using a PFET having a source coupled to power rail 112 and a drain coupled to node 916 of bias generation circuit 915; the second transistor 710-2 is implemented using a PFET having a source coupled to power rail 112 and a drain coupled to the sources of input transistors 920 and 922; the third transistor 710-3 is implemented using a PFET having a source coupled to power rail 112 and a drain coupled to the drain of transistor 950; and the fourth transistor 410-4 is implemented using a PFET having a source coupled to power rail 112 and a drain coupled to the source of transistor 954. However, it will be understood that each of transistors 710-1 to 710-4 can be implemented in other implementations using a different type of transistor. In this example, voltage bias circuit 725 is coupled to the gate of each of transistors 710-1 to 710-4 to bias the gates of transistors 710-1 to 710-4.

[0062] A feedback capacitor 615 is coupled between the output 130 and the gate of each of the transistors 710-1 to 710-4. Therefore, the gate of each of the transistors 710-1 to 710-4 is capacitively coupled to the output 130 via the feedback capacitor 615. This capacitive coupling couples the transient voltage drop in the output voltage Vout to the gate of the transistors 710-1 to 710-4 during a voltage downswing. In response to the transient voltage drop, each of the transistors 710-1 to 710-4 increases (i.e., increases) its corresponding bias current. Therefore, in this example, the transistors 710-1 to 710-4 provide a dynamic current bias for the amplifier circuit 120.

[0063] Figure 10 illustrates an example of a wafer 1010 including an LDO regulator 110 according to certain forms of the present invention. The LDO regulator 110 can be implemented using any of the exemplary implementations shown in Figures 6 through 9. The wafer 1010 includes a power rail 112, a circuit block 170, a power pad 1030, a reference circuit 1040, and a second circuit block 1070. In the following discussion, the circuit block 170 is referred to as the first circuit block 170.

[0064] In this example, power supply pad 1030 is coupled to an external power supply 1020 (i.e., an off-chip power supply). Power supply 1020 may include a battery, a power management integrated circuit (PMIC), and / or another power supply. In an example where power supply 1020 includes a PMIC, the PMIC may include a voltage regulator (not shown) configured to convert the voltage from the battery to a power supply voltage VDD. Power supply pad 1030 may be coupled to power supply 1020 via a metal line 1025 (e.g., on a printed circuit board).

[0065] Power rail 112 is coupled to power pad 1030. In some configurations, power rail 112 is configured to receive a supply voltage VDD from power supply 1020 via power pad 1030. Power rail 112 may include one or more metal layers on wafer 1010. Power rail 112 may also include one or more vias and / or one or more other metal interconnect structures for coupling one or more metal layers.

[0066] In this example, input 105 of LDO regulator 110 is coupled to power rail 112, and output 130 of LDO regulator 110 is coupled to first circuit block 170. As previously described, LDO regulator 110 receives a power supply voltage VDD at input 105 and generates a regulated output voltage Vout from the power supply voltage VDD at output 130. The output voltage Vout is provided to first circuit block 170 to power it. Circuit block 170 may include a disk drive, logic circuitry (e.g., combinational and / or sequential logic), a processor, memory, and / or another type of circuitry.

[0067] Reference circuit 1040 is coupled to the first input 122 of amplifier circuit 120 (not shown in FIG. 10) in LDO regulator 110. Reference circuit 1040 is configured to generate a reference voltage Vref and output the reference voltage Vref to the first input 122 of amplifier circuit 120. As discussed above, LDO regulator 100 regulates the voltage at output 130 based on the reference voltage and the feedback voltage Vfb. Reference circuit 1040 can be implemented using a voltage divider, a bandgap reference circuit, or any combination thereof.

[0068] In this example, the second circuit block 1070 is coupled to and receives a supply voltage VDD from the power rail 112. Therefore, in this example, the first circuit block 170 and the second circuit block 1070 are powered by different voltages. More specifically, the first circuit block 170 is powered by the regulated output voltage Vout of the LDO regulator 110, and the second circuit 1070 is powered by the supply voltage VDD from the power rail 112. In this example, the LDO regulator 110 allows the first circuit block 170 to be powered by a voltage different from the supply voltage VDD on the power rail 112.

[0069] Figure 11 illustrates a method 1100 for operating a voltage regulator according to certain conditions. The voltage regulator (e.g., LDO regulator 110) includes a transmission device (e.g., transmission device 115) coupled between the input and output of the voltage regulator, and an amplifier circuit (e.g., amplifier circuit 120) coupled to the gate of the transmission device.

[0070] At block 1110, a capacitor is used to detect the transient voltage drop at the output of the voltage regulator. This capacitor may correspond to feedback capacitor 615. The transient voltage drop may have a duration between 10 nanoseconds and 1 microsecond.

[0071] At block 1120, a bias current is added to the amplifier circuit based on the detected transient voltage drop. In one example, the voltage regulator may include a transistor (e.g., transistor 710) coupled between a power supply rail (e.g., power supply rail 112) and the amplifier circuit. In this example, the bias current added to the amplifier circuit may include capacitively coupling the transient voltage drop to the gate of the transistor via a capacitor. In one example, the transistor may include a PFET having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0072] An implementation example is described in the following numbered clauses:

[0073] 1. A voltage regulator, comprising:

[0074] A transmission device coupling between the input and output of the voltage regulator;

[0075] An amplifier circuit has a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to the gate of the transmission device;

[0076] A first current source coupled between the power supply rail and the amplifier circuit; and

[0077] A capacitor coupled between the first current source and the output of the voltage regulator.

[0078] 2. The voltage regulator according to Clause 1, wherein the first current source includes a transistor coupled between the power supply rail and the amplifier circuit, wherein the capacitor is coupled between the gate of the transistor and the output of the voltage regulator.

[0079] 3. The voltage regulator according to Clause 2, wherein the transistor includes a p-type field-effect transistor (PFET) having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0080] 4. The voltage regulator according to Clause 2 also includes: a voltage biasing circuit coupled to the gate of the transistor.

[0081] 5. The voltage regulator according to any one of clauses 1 to 4 also includes: a second current source coupled between the power supply rail and the amplifier circuit, wherein the second current source is coupled to the gate of the transmission device.

[0082] 6. According to Clause 5, the voltage regulator, wherein:

[0083] The first current source includes a first transistor coupled between the power supply rail and the amplifier circuit, wherein the capacitor is coupled between the gate of the first transistor and the output of the voltage regulator; and

[0084] The second current source includes a second transistor coupled between the power supply rail and the amplifier circuit, wherein the gate of the second transistor is coupled to the gate of the transmission device.

[0085] 7. According to Clause 6, the voltage regulator, wherein:

[0086] The first transistor includes a first p-type field-effect transistor (PFET) having a source coupled to the power supply rail and a drain coupled to the amplifier circuit; and

[0087] The second transistor includes a second PFET having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0088] 8. The voltage regulator according to clause 6 or 7 also includes: a voltage biasing circuit coupled to the gate of the first transistor.

[0089] 9. The voltage regulator according to any one of clauses 1 to 8, wherein the amplification circuit comprises:

[0090] An amplifier having a first input configured to receive the reference voltage, a second input coupled to the output of the voltage regulator via the feedback path, and an output; and

[0091] A buffer having an input coupled to the output of the amplifier and an output coupled to the gate of the transmission device.

[0092] 10. The voltage regulator according to Clause 9, wherein the first current source comprises:

[0093] A first transistor coupled between the power supply rail and the amplifier, wherein the capacitor is coupled between the gate of the first transistor and the output of the voltage regulator; and

[0094] A second transistor is coupled between the power supply rail and the buffer, wherein the capacitor is coupled between the gate of the second transistor and the output of the voltage regulator.

[0095] 11. The voltage regulator according to Clause 10, wherein:

[0096] The first transistor includes a first p-type field-effect transistor (PFET) having a source coupled to the power supply rail and a drain coupled to the amplifier; and

[0097] The second transistor includes a second PFET having a source coupled to the power supply rail and a drain coupled to the buffer.

[0098] 12. The voltage regulator according to clause 10 or 11 also includes: a voltage biasing circuit coupled to the gate of the first transistor and the gate of the second transistor.

[0099] 13. The voltage regulator according to any one of clauses 9 to 12 also includes: a second current source coupled between the power supply rail and the amplifier circuit, wherein the second current source is coupled to the gate of the transmission device.

[0100] 14. The voltage regulator according to Clause 13, wherein the second current source comprises:

[0101] A third transistor is coupled between the power supply rail and the amplifier, wherein the gate of the third transistor is coupled to the gate of the transmission device; and

[0102] A fourth transistor is coupled between the power supply rail and the buffer, wherein the gate of the third transistor is coupled to the gate of the transmission device.

[0103] 15. The voltage regulator according to any one of clauses 9 to 14, wherein the amplifier comprises a common-source common-gate amplifier.

[0104] 16. The voltage regulator according to any one of clauses 9 to 15 also includes: a bias generating circuit, wherein the bias generating circuit includes:

[0105] A resistor coupled between a first node and a second node, wherein the first node is coupled to the bias input of the amplifier;

[0106] The capacitor coupled between the first node and the second node; and

[0107] A bias transistor having a drain coupled to the second node, a gate coupled to the drain, and a source coupled to ground.

[0108] 17. The voltage regulator according to Clause 16, wherein the first current source comprises:

[0109] A first transistor is coupled between the power supply rail and the first node of the bias generation circuit, wherein the capacitor is coupled between the gate of the first transistor and the output of the voltage regulator;

[0110] A second transistor coupled between the power supply rail and the amplifier, wherein the capacitor is coupled between the gate of the second transistor and the output of the voltage regulator; and

[0111] A third transistor is coupled between the power supply rail and the buffer, wherein the capacitor is coupled between the gate of the third transistor and the output of the voltage regulator.

[0112] 18. The voltage regulator according to Clause 17 also includes: a voltage biasing circuit coupled to the gate of the first transistor, the gate of the second transistor and the gate of the third transistor.

[0113] 19. The voltage regulator according to any one of clauses 9 to 18, wherein the buffer includes a source follower.

[0114] 20. A method of operating a voltage regulator, wherein the voltage regulator includes a transmission means coupled between an input of the voltage regulator and an output of the voltage regulator, and an amplification circuit coupled to a gate of the transmission means, the method comprising:

[0115] The transient voltage drop at the output of the voltage regulator is detected via a capacitor; and

[0116] The bias current to the amplifier circuit is increased based on the detected transient voltage drop.

[0117] 21. According to the method of Clause 20, wherein:

[0118] The voltage regulator includes a transistor coupled between the power supply rail and the amplifier circuit; and

[0119] The bias current added to the amplifier circuit based on the transient voltage drop includes capacitively coupling the transient voltage drop to the gate of the transistor via the capacitor.

[0120] 22. The method according to Clause 21, wherein the transistor includes a first p-type field-effect transistor (PFET) having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0121] 23. The method according to any one of clauses 20 to 22 also includes:

[0122] Detect the gate voltage of the transmission device; and

[0123] The bias current of the amplifier circuit is adjusted based on the detected gate voltage.

[0124] 24. According to the method of Clause 23, wherein:

[0125] The voltage regulator includes a first transistor coupled between the power supply rail and the amplifier circuit;

[0126] The bias current added to the amplifier circuit based on the transient voltage drop includes capacitively coupling the transient voltage drop to the gate of the first transistor via the capacitor;

[0127] The voltage regulator includes a second transistor coupled between the power supply rail and the amplifier circuit; and

[0128] Adjusting the bias current to the amplifier circuit based on the detected gate voltage includes coupling the gate of the second transistor to the gate of the transmission device.

[0129] 25. A chip, comprising:

[0130] solder pads;

[0131] The power rail coupled to this pad;

[0132] A reference circuit, configured to generate a reference voltage; and

[0133] Voltage regulator, comprising:

[0134] A transmission device coupling between the input and output of the voltage regulator, wherein the input of the voltage regulator is coupled to the power supply rail;

[0135] An amplifier circuit has a first input, a second input, and an output, wherein the first input is coupled to the reference circuit, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to the gate of the transmission device;

[0136] A first current source coupled between the power supply rail and the amplifier circuit; and

[0137] A capacitor coupled between the first current source and the output of the voltage regulator.

[0138] 26. The chip according to Clause 25, wherein the first current source includes a transistor coupled between the power supply rail and the amplifier circuit, wherein the capacitor is coupled between the gate of the transistor and the output of the voltage regulator.

[0139] 27. The chip pursuant to Clause 26 also includes: a voltage biasing circuit coupled to the gate of the transistor.

[0140] 28. The chip according to any one of clauses 25 to 27 also includes: a second current source coupled between the power supply rail and the amplifier circuit, wherein the second current source is coupled to the gate of the transmission device.

[0141] 29. The chip according to Clause 28, wherein:

[0142] The first current source includes a first transistor coupled between the power supply rail and the amplifier circuit, wherein the capacitor is coupled between the gate of the first transistor and the output of the voltage regulator; and

[0143] The second current source includes a second transistor coupled between the power supply rail and the amplifier circuit, wherein the gate of the second transistor is coupled to the gate of the transmission device.

[0144] 30. The chip according to Clause 29, wherein:

[0145] The first transistor includes a first p-type field-effect transistor (PFET) having a source coupled to the power supply rail and a drain coupled to the amplifier circuit; and

[0146] The second transistor includes a second PFET having a source coupled to the power supply rail and a drain coupled to the amplifier circuit.

[0147] In this document, any reference to elements using names such as "first," "second," etc., generally does not restrict the number or order of those elements. Rather, in this document, such naming is used as a convenient method of distinguishing between two or more elements or instances of a single element. Therefore, a reference to the first element and the second element does not imply that only two elements can be used or that the first element must precede the second element.

[0148] Within the scope of this document, the term "exemplary" is used to mean "serving as an example, illustration, or explanation." Any implementation or pattern described as "exemplary" herein is not necessarily to be construed as preferred or superior to other patterns in this document. Similarly, the term "pattern" does not require that all patterns in this document include the features, advantages, or modes of operation discussed. As with respect to stated values ​​or mathematical usage herein, the term "approximate" is intended to indicate within 10% of the stated value or property (e.g., between 90% and 110% of the stated value or property).

[0149] To enable anyone skilled in the art to implement or use the content of this application, a prior description of the application has been provided. Various modifications to the application will be readily apparent to those skilled in the art, and the overall principles defined herein can be applied to other variations without departing from the spirit or scope of the application. Therefore, the application is not limited to the examples described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

[0150] 105: Input 110: LDO Regulator 112: Voltage supply rail 115: Transmission device 120: Amplifier Circuit 122: First input 124: Second input 126: Output 130: Output 150: Feedback Path 160: Voltage divider 165: Node 170: Circuit Block 210: Undershoot 220: Overshoot 310: Current source 410: Transistor 410-1: First Transistor 410-2: Second transistor 410-3: Third transistor 410-4: Fourth transistor 610: First bias current source 615: Feedback Capacitor 710: Transistor 710-1: First Transistor 710-2: Second Transistor 710-3: Third transistor 710-4: Fourth Transistor 725: Voltage bias circuit 820: Error Amplifier 822: First Input 824: Second Input 826: Output 830: Output Buffer 832: Input 834: Output 910: Transistor 912: Resistor 914: Bias Transistor 915: Bias Generation Circuit 916: Node 918: Node 920: Input transistor 922: Input transistor 924: Transistor 926: Transistor 930: Transistor 932: Transistor 934: Transistor 935: Bias Input 940: Transistor 942: Transistor 944: Transistor 950: Transistor 952: Transistor 954: Transistor 956: Transistor 1010: Chip 1020: Power Supply 1025: Metal wire 1030: Power supply pad 1040: Reference Circuit 1070: Circuit Block 1100: Method 1110: Square 1120: Square Cb: Capacitor Cm: Capacitor I. Bias: Bias Current I Load: Load current R1: First feedback resistor R 2: Second feedback resistor Rb: Resistor T Delay: Delay T1: Time T2: Time VDD: Power supply voltage V out: Output voltage V ref: Reference voltage Vb: DC bias voltage Vcas: Bias voltage Vfb: Feedback voltage

[0151] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A voltage regulator, comprising: A transmission device coupled between an input of the voltage regulator and an output of the voltage regulator; An amplifier circuit having a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of a voltage regulator via a feedback path, and the output of the amplifier circuit is coupled to a gate of a transmission device; a first current source coupled between a power supply rail and the amplifier circuit, wherein the first current source includes a first transistor coupled between the power supply rail and the amplifier circuit, and a drain of the first transistor is directly coupled to the amplifier circuit, wherein a capacitor is coupled between a gate of the first transistor and the output of the voltage regulator; a second current source coupled between the power supply rail and the amplifier circuit, wherein the second current source includes a second transistor coupled between the power supply rail and the amplifier circuit, a gate of the second transistor is coupled to the gate of the transmission device, and a drain of the second transistor is directly coupled to the amplifier circuit.

2. The voltage regulator according to claim 1, wherein the first transistor includes a p-type field-effect transistor (PFET) having a source coupled to the power supply rail.

3. The voltage regulator according to claim 1 also includes: A voltage bias circuit coupled to the gate of the first transistor.

4. The voltage regulator according to claim 1, wherein the amplifier circuit includes: An amplifier having a first input configured to receive the reference voltage, a second input coupled to the output of the voltage regulator via the feedback path, and the output; and a buffer having an input coupled to the output of the amplifier and an output coupled to the gate of the transmission device.

5. The voltage regulator according to claim 4, wherein the first current source also includes: A third transistor is coupled between the power supply rail and the buffer, wherein the capacitor is coupled between a gate of the third transistor and the output of the voltage regulator.

6. The voltage regulator according to request item 5, wherein: The first transistor includes a first p-type field-effect transistor (PFET) having a source coupled to the power supply rail and a drain coupled to the amplifier; and the third transistor includes a second PFET having a source coupled to the power supply rail and a drain coupled to the buffer.

7. The voltage regulator according to claim 5 also includes: A voltage biasing circuit coupled to the gate of the first transistor and the gate of the third transistor.

8. The voltage regulator according to claim 5, wherein the second current source also includes: A fourth transistor is coupled between the power supply rail and the buffer, wherein a gate of the fourth transistor is coupled to the gate of the transmission device.

9. The voltage regulator according to claim 4, wherein the amplifier includes a common-source common-gate amplifier.

10. The voltage regulator according to claim 4 also includes: A bias generating circuit, wherein the bias generating circuit includes: a resistor coupled between a first node and a second node, wherein the first node is coupled to a bias input of the amplifier; a capacitor coupled between the first node and the second node; and a bias transistor having a drain coupled to the second node, a gate coupled to the drain, and a source coupled to ground.

11. The voltage regulator according to claim 4, wherein the buffer includes a source follower.

12. A chip, comprising: One solder pad; A power rail is coupled to this pad; A reference circuit is configured to generate a reference voltage; And the voltage regulator according to request item 1.

13. A method of operating a voltage regulator, wherein the voltage regulator includes a transmission means coupled between an input of the voltage regulator and an output of the voltage regulator, and an amplifier circuit coupled to a gate of the transmission means, the method comprising the steps of: A transient voltage drop at the output of the voltage regulator is detected via a capacitor; a bias current is increased to the amplifier circuit based on the detected transient voltage drop; a gate voltage of the transmission device is detected; The voltage regulator includes a first transistor coupled between a power supply rail and the amplifier circuit, wherein a drain of the first transistor is directly coupled to the amplifier circuit; the step of increasing the bias current based on the transient voltage drop includes the step of capacitively coupling the transient voltage drop to a gate of the first transistor via the capacitor; the voltage regulator includes a second transistor coupled between the power supply rail and the amplifier circuit, wherein a drain of the second transistor is directly coupled to the amplifier circuit, and a gate of the second transistor is coupled to the gate of the transmission device; and the step of adjusting the bias current based on the detected gate voltage includes the step of coupling a gate of the second transistor to the gate of the transmission device.

14. The method according to request item 13 also includes the following steps: The bias current added to the amplifier circuit based on the transient voltage drop includes capacitively coupling the transient voltage drop to a gate of the first transistor via the capacitor.

15. The method of claim 14, wherein the transistor comprises a first p-type field-effect transistor (PFET).

Images