Analog adders for multi-bit mac arrays in reconfigurable analog based neural networks

Abstract

Various embodiments include apparatus and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of unit MAC outputs by: receiving a plurality of unit MAC outputs from a plurality of unit MAC outputs; and storing the plurality of unit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on the sum of the stored plurality of unit MAC outputs.

Description

[Technical Field]

[0001] This invention relates to an analog adder for a multi-bit MAC array in a neural network based on reconfigurable analogy. [Previous Technology]

[0002] Neural networks are increasingly being used in various computing devices. The power efficiency of these neural networks is a crucial aspect of neural network implementations in computing devices. Digital computation in neural network implementations has proven inefficient for many applications. Analog neural networks have been implemented as a more power-efficient alternative. However, while performance improvements have been demonstrated for analog binary neural networks, analog multi-bit neural networks suffer from computational performance bottlenecks when performing analog computations and lack flexibility for computations using inputs with varying bit widths. [Summary of the Invention]

[0003] The various disclosed embodiments may include apparatus and methods for multi-bit multiplication and accumulation. Various embodiments include a multi-bit multiplier-accumulator (MAC) having an analog adder having a first adder capacitor, wherein the first adder capacitor is configured to add a plurality of unit MAC outputs via: receiving the plurality of unit MAC outputs from the plurality of unit MAC outputs; and storing the plurality of unit MAC outputs; and wherein the analog adder is configured to output a multi-bit MAC output based on the sum of the stored plurality of unit MAC outputs.

[0004] In some embodiments, each of the plurality of unit MACs is configured to: sequentially multiply each bit of a first multi-bit value with different individual bits of a second multi-bit value, wherein the first multi-bit value and the second multi-bit value are represented by digital voltages; and accumulate the results of the multiplications to generate the plurality of unit MAC outputs, wherein the plurality of unit MAC outputs are analog voltages.

[0005] Some embodiments may also include a plurality of unit MAC switches, wherein a first unit MAC switch of the plurality of unit MAC switches is configured to selectively electrically connect the first unit MAC of the plurality of unit MAC switches and the first adder capacitor, as controlled by a control device. In some embodiments, the first adder capacitor is configured such that receiving the plurality of unit MAC outputs from a plurality of unit MACs includes: selectively electrically connecting the first unit MAC and the first adder capacitor in response to the first unit MAC switch; receiving a first unit MAC output from the plurality of unit MAC outputs; and the analog adder includes an operational amplifier having an input and an output, wherein the first adder capacitor is electrically connected between the input and the output, and the operational amplifier is configured to: receive the plurality of unit MAC outputs at the input; add the plurality of unit MAC outputs to generate a weighted average of the plurality of unit MAC outputs; and output the weighted average of the plurality of unit MAC outputs as an analog voltage to an analog-to-digital converter. In some embodiments, the analog adder is configured such that: adding the plurality of unit MAC outputs includes adding the plurality of unit MAC outputs to produce the weighted average of the plurality of unit MAC outputs, and storing the plurality of unit MAC outputs includes storing the weighted average of the plurality of unit MAC outputs. In some embodiments, the analog adder is configured such that outputting a multi-bit MAC output includes outputting the weighted average of the plurality of unit MAC outputs.

[0006] In some embodiments, the analog adder includes: a plurality of designated capacitors, wherein a first designated capacitor of the plurality of designated capacitors is electrically connected between the first unit MAC switch and the first adder capacitor, and the first designated capacitor has a capacitor rating of 2r, where r is the position of a bit in the weighted value of a bit multiplied by the start value used when generating the first unit MAC output, and the first designated capacitor is configured to: receive the first unit MAC output; weight the first unit MAC output; and output the weighted first unit MAC output. In some embodiments, the operational amplifier is configured such that: receiving the plurality of unit MAC outputs includes receiving the weighted first unit MAC output, and adding the plurality of unit MAC outputs includes adding the weighted first unit MAC output.

[0007] Some embodiments may also include a plurality of unit MAC switches, wherein a first unit MAC switch among the plurality of unit MAC switches is configured to selectively electrically connect the first unit MAC and the first adder capacitor, as controlled by a control device. In some embodiments, the first adder capacitor is configured such that receiving the plurality of unit MAC outputs from the plurality of unit MACs includes receiving a first unit MAC output from the plurality of unit MAC outputs in response to the first unit MAC switch selectively electrically connecting the first unit MAC and the first adder capacitor. The analog adder also includes a plurality of adder capacitors, including the first adder capacitor associated with the first unit MAC, wherein the first adder capacitor has a capacitor rating of 2r, and wherein r is the position of a bit in a weighted value of a bit multiplied by a start value used when the first unit MAC output is generated by the first unit MAC. In some embodiments, the first adder capacitor is configured to: weight the first unit MAC output, wherein the analog adder is configured such that storing the plurality of unit MAC outputs includes storing the weighted first unit MAC output; and output the weighted first unit MAC output. In some embodiments, the analog adder includes a plurality of adder switches, each including a first adder switch associated with the first adder capacitor, wherein the first adder switch is configured to: selectively electrically connect the first adder capacitor to the first unit MAC via the first unit MAC switch controlled by the control device; and concurrently selectively electrically connect the first adder capacitor to the electrical transmission bus, as controlled by the control device, by a second adder switch among the plurality of adder switches selectively electrically connecting a second adder capacitor among the plurality of adder capacitors to an electrical transmission bus, thereby outputting a weighted first unit MAC output from the first adder capacitor and generating a weighted average of a plurality of weighted unit MAC outputs including the weighted first unit MAC output. In some embodiments, the analog adder is configured such that outputting a multi-bit MAC output includes outputting the weighted average of the plurality of weighted unit MAC outputs.

[0008] Some embodiments also include a buffer electrically connected between the plurality of unit MAC switches and the plurality of adder switches.

[0009] Some embodiments may also include a plurality of unit MAC switches, wherein a first unit MAC switch among the plurality of unit MAC switches is configured to selectively electrically connect the first unit MAC and the first adder capacitor, as controlled by a control device. In some embodiments, the first adder capacitor is configured such that receiving the plurality of unit MAC outputs from the plurality of unit MACs includes receiving a first unit MAC output from the plurality of unit MAC outputs in response to the first unit MAC switch selectively electrically connecting the first unit MAC and the first adder capacitor. The analog adder includes: a plurality of adder switches, including a first adder switch among the plurality of adder switches associated with the first adder capacitor, and a second adder capacitor, wherein the second adder capacitor is associated with a second adder switch among the plurality of adder switches, and the first adder capacitor and the second adder capacitor have the same capacitance rating. In some embodiments, the first adder switch is configured to: selectively electrically connect the first adder capacitor to the plurality of unit cell MACs via the plurality of unit cell MAC switches controlled by the control device; and selectively electrically connect the first adder capacitor to an electrical transmission bus, as controlled by the control device. In some embodiments, the second adder switch is configured to: selectively electrically connect the second adder capacitor to the electrical transmission bus concurrently with the first adder capacitor, as controlled by the control device, thereby sharing the plurality of unit cell MAC outputs between the first adder capacitor and the second adder capacitor; and selectively electrically connect the second adder capacitor to an analog-to-digital converter to output the shared plurality of unit cell MAC outputs. In some embodiments, the analog adder is configured such that outputting a multi-bit MAC output includes outputting the shared plurality of unit cell MAC outputs.

[0010] In some embodiments, the analog adder includes a buffer electrically connected between the plurality of identity MAC switches and the plurality of adder switches.

[0011] Some embodiments may also include a plurality of unit MAC switches, wherein a first unit MAC switch among the plurality of unit MAC switches is configured to selectively electrically connect the first unit MAC and the first adder capacitor, as controlled by a control device. In some embodiments, the first adder capacitor is configured such that receiving the plurality of unit MAC outputs from a plurality of unit MACs includes selectively electrically connecting the first unit MAC and the first adder capacitor in response to a first unit MAC switch, and receiving a first unit MAC output from the plurality of unit MAC outputs. The analog adder includes: a second adder capacitor, wherein the first adder capacitor and the second adder capacitor have the same capacitance rating; and an adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor, as controlled by the control device, thereby sharing the plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor, wherein the second adder capacitor is configured to output the shared plurality of unit MAC outputs to the analog-to-digital converter. In some embodiments, the analog adder is configured such that outputting a multi-bit MAC output includes outputting the shared plurality of unit MAC outputs.

[0012] Some embodiments include a multi-bit MAC, which includes an analog adder having: a plurality of adder capacitors, including a first adder capacitor; a plurality of unit MAC switches, including a first unit MAC switch configured to selectively electrically connect a first unit MAC among the plurality of unit MACs and the first adder capacitor, as controlled by a control device; wherein the first adder capacitor is configured to add the first plurality of unit MAC outputs by: receiving the first plurality of unit MAC outputs from the first unit MAC in response to the first unit MAC switch selectively electrically connecting the first unit MAC and the first adder capacitor; and storing the first plurality of unit MAC outputs, and wherein the analog adder is configured to output a multi-bit MAC output based on the addition of the stored first plurality of unit MAC outputs.

[0013] In some embodiments, the plurality of adder capacitors includes a second adder capacitor and a third adder capacitor, wherein the summed capacitance rating of the paired second adder capacitors and the third adder capacitors is the same as the capacitance rating of the first adder capacitor; and the analog adder also includes a plurality of adder switches, including: a first adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, thereby sharing the first plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor; a second adder switch configured to selectively electrically connect the second adder capacitor and the third adder capacitor as controlled by the control device, thereby sharing the first plurality of unit MAC outputs between the second adder capacitor and the third adder capacitor. A first plurality of unit MAC outputs, wherein the third adder capacitor is configured to weight the shared first plurality of unit MAC outputs; and a third adder switch configured to selectively electrically connect the third adder capacitor to the analog-to-digital converter via an electrical transmission bus, as controlled by the control device, thereby outputting a weighted shared first plurality of unit MAC outputs to the analog-to-digital converter concurrently with another third adder capacitor of the plurality of adder capacitors outputting a weighted shared second plurality of unit MAC outputs to the analog-to-digital converter via the electrical transmission bus, thereby combining the weighted shared first plurality of unit MAC outputs and the weighted shared second plurality of unit MAC outputs to form a weighted average of the shared plurality of unit MAC outputs. In some embodiments, the analog adder is configured such that outputting a multi-bit MAC output includes outputting the weighted average of the shared plurality of unit MAC outputs.

[0014] In some embodiments, the plurality of adder capacitors also includes a second adder capacitor; and the analog adder also includes a plurality of adder switches, including: a first adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, thereby sharing the first plurality of unit cell MAC output between the first adder capacitor and the second adder capacitor; and a second adder switch configured to selectively electrically connect the second adder capacitor to another second adder capacitor via an electrical transmission bus as controlled by the control device.

[0015] In some embodiments, the first adder switch is configured such that, as controlled by the control device, the first adder capacitor and the second adder capacitor are selectively electrically connected, thereby sharing the first plurality of unit cell MAC output between the first adder capacitor and the second adder capacitor, including dividing the first plurality of unit cell MAC output in half for each of the first adder capacitor and the second adder capacitor; the analog adder is configured to clear half of the first adder capacitor of the first plurality of unit cell MAC output; and the first adder switch is configured such that, as controlled by the control device, the first adder capacitor and the second adder capacitor are selectively electrically connected, thereby sharing the half of the first plurality of unit cell MAC output between the first adder capacitor and the second adder capacitor, thereby dividing the half of the first plurality of unit cell MAC output in half for each of the first adder capacitor and the second adder capacitor, thereby producing a plurality of quarters of the first plurality of unit cell MAC.

[0016] In some embodiments, the plurality of adder switches includes another first adder switch, wherein the other first adder switch is configured to selectively electrically connect another first adder capacitor and the other second adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor and the other second adder capacitor.

[0017] In some embodiments, the plurality of adder switches includes another first adder switch, wherein the other first adder switch is configured to selectively electrically disconnect the other first adder capacitor and the other second adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor and the other second adder capacitor.

[0018] Further embodiments include a method of performing the device functions outlined above. A further embodiment includes a multi-bit MAC having units for performing any of the device functions outlined above.

Implementation Method

[0034] The various forms will be described in detail with reference to the accompanying drawings. Wherever possible, the same element symbols will be used throughout the drawings to refer to the same or similar parts. References to specific examples and implementations are for illustrative purposes and are not intended to limit the scope of the claims.

[0035] Various embodiments may include devices for implementing analog adders for multiplier-accumulator ("MAC") arrays in reconfigurable analog neural networks, and methods for operating such devices. Some embodiments may include switched-capacitor accumulation of analog signals for analog MAC arrays. Some embodiments may include sequential accumulation of analog signals with weighted start bits for analog MAC arrays. Some embodiments may include flexible analog adders for variable bit-width accumulation of analog MAC arrays. Some embodiments may include analog adders that use capacitive charge sharing in different combinations to implement multi-bit MAC operations from inputs of single-bit MAC operation results.

[0036] The terms "multiplier-accumulator" and "MAC" are used interchangeably herein to refer to components of a computing device configured to perform or analogous to the multiplication and accumulation of any number and combination of bits. For example, an identity MAC can perform or analogous to identity multiplication and accumulation. As another example, a multi-bit MAC can perform or analogous to multi-bit multiplication and accumulation. As used herein, a MAC can perform or analogous to multiplication and accumulation at least partially in the analog voltage domain.

[0037] The terms “store,” “charge,” and “load” are used interchangeably herein to refer to the voltage received by and held in a capacitor, since an analog value can be “stored” by charging the capacitor by connecting it to an input voltage. Referring to the voltage provided by a capacitor by discharging it (by connecting it to an output line), the terms “output,” “share,” and “discharge” are used interchangeably herein. Referring to the voltage stored in a capacitor or array of capacitors, the terms “accumulate,” “add,” and “sum” are used interchangeably herein.

[0038] Unless otherwise stated, the terms "processor," "processor core," "controller," and "control device" are used interchangeably herein to refer to a software-configurable processor, a hardware-configurable processor, a general-purpose processor, a special-purpose processor, a single-core processor, a homogeneous multi-core processor, a heterogeneous multi-core processor, a core of a multi-core processor, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), etc., a controller, a microcontroller, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), other programmable logic devices, individual gate logic, transistor logic, etc. A processor may be an integrated circuit that can be configured such that the components of the integrated circuit reside on a monolithic semiconductor material (such as silicon).

[0039] The terms "computing device" and "mobile computing device" are used interchangeably herein to refer to any or all of the following: cellular phones, smartphones, personal or mobile multimedia players, personal digital assistants (PDAs), laptops, tablets, convertible laptops / tablets (2-in-1 computers), smart computers, ultrabooks, netbooks, handheld computers, wireless email receivers, cellular phones with multimedia internet access enabled, mobile game consoles, wireless game controllers, and similar personal electronic devices including memory and programmable processors. The term "computing device" may further refer to static computing devices, including personal computers, desktop computers, all-in-one computers, workstations, supercomputers, mainframe computers, embedded computers, servers, home theater computers, and game consoles.

[0040] Computation in Memory (CIM) and near-memory computing (NMC) systems are deployed in computing devices for rapid processing of data for neural networks. CIM or NMC systems use memory devices, such as static random-access memory (SRAM), modified to perform certain operations, such as matrix multiplication. These matrices can be startup matrices and weight matrices for neural networks. Some CIM and NMC systems may include storage units, each configured to store an identity value and multiply the input identity value by the stored identity value. Some CIM and NMC systems may include storage units, each configured to store a multi-bit value and multiply the input identity value by the stored multi-bit value. Compared to processor-based multiplication, matrix CIM and NMC multiplication saves energy and time by avoiding loading the operation of values ​​into memory for each operation. The result of the multiplication can be output to an analog-to-digital converter and accumulated therefrom. The combination of a CIM or NMC system with an analog-to-digital converter can act as an analog MAC.

[0041] Analog MAC has shown promising performance in binary neural networks using single-bit-width start-ups and weight values. However, analog MAC has been shown to be inefficient for multi-bit-width start-ups and / or weight values ​​due to computational performance bottlenecks when performing analog computations and a lack of flexibility in computations using inputs of different bit widths. Implementing switched-capacitor accumulation for analog MAC arrays can improve flexibility and efficiency for deep neural networks.

[0042] The embodiments described herein address the aforementioned problems of analog adders using an analog adder that can be implemented using switched-capacitor accumulation (using switched capacitors). In some embodiments, the analog adder can use any number of switched capacitors and any combination of switched capacitor configurations. Various configurations of switched capacitors can include switched capacitors as integrator capacitors using hot-code-based weights, integrator capacitors using hard-wired binary weights, binary bit-to-analog converters (DACs), and sequential binary accumulators. The analog adder can be configured for switched-capacitor accumulation of a voltage representation of the output of an analog MAC array.

[0043] An analog MAC array can be implemented by electrically connecting "m" unit MAC outputs to "p" capacitors. Each of the unit MACs can multiply "n" start value bits by one of "m" weight value bits, accumulate the results of the multiplication, and output the result of the multiplication and accumulation as a voltage. In some embodiments, at least one of the start value and weight value can be a multi-bit width value. The multiplication can be implemented such that each bit of the start value is multiplied by one bit of the weight value. The start value can be input to the unit MAC bitwise sequentially from the least significant bit to the most significant bit, and each unit MAC can multiply each input bit by the weight value bit. The unit MAC can accumulate the results of the multiplication. Each unit MAC can output the result of each multiplication and accumulation, which is referred to herein as the unit MAC output. The various embodiments and examples herein are described based on the unit MAC outputs generated by multiplying multiple bits of a multi-bit start value and one bit of a multi-bit weight value from each unit MAC. However, various embodiments and examples can also be implemented using the identity MAC output generated by multiplying one bit of the multi-bit start value and multiple bits of the multi-bit weight value from each identity MAC.

[0044] The multi-bit MAC can be implemented by electrically connecting an array of analog MACs of the unit MACs to any number and combination of analog adders. The unit MACs can be selectively electrically connected to capacitors via switches, and the capacitors can act as analog adders by summing the voltage outputs of the unit MACs. Switches can include any type of electronically controlled switch, such as relays and / or transistors. Switches can control when the unit MAC outputs can be electrically connected to the capacitors. For example, switches can sequentially connect the individual unit MACs to the capacitors. Some switches can electrically connect a specific combination of unit MACs and capacitors when closed. Some switches can output the analog adder result (referred to herein as the multi-bit MAC output) to the ADC when closed. Some switches can reset the capacitors when closed. The controller can control various switches to perform multiplication, summation, and output.

[0045] In some embodiments, the analog adder can be implemented using a switched capacitor as an integrator capacitor employing thermally weighted integrators. The identity MAC can be electrically connected to the analog adder via an identity MAC switch, the analog adder having an operational amplifier and a capacitor electrically connected to the feedback path of the operational amplifier. The identity MAC switches can be controlled such that the identity MAC outputs can be sequentially output to and received by the operational amplifier and the capacitor. For multi-bit start values, the identity MAC switches can be controlled such that each item in the identity MAC output can be output to and received by the operational amplifier 2q times, where "q" can be the position of the start value bit from the least significant bit with q=0 to the most significant bit with q=n-1. Similarly, for multi-bit weight values, the identity MAC switches can be controlled such that each item in the identity MAC output can be output to and received by the operational amplifier 2r times, where "r" can be the position of the weight value bit from the least significant bit with r=0 to the most significant bit with r=m-1. The capacitor can be charged, and the gain and output voltage of the operational amplifier can be increased. The voltage output of the operational amplifier can be the integral of the voltage input to the operational amplifier, which is weighted over time through the impedance of the capacitor. This can act as an addition operation for the identity MAC output.

[0046] In some embodiments, the analog adder can be implemented using a switched capacitor as an integrator capacitor with hard-wired binary weights. In addition to the circuitry described above for integrator capacitors with thermally based weights, integrator capacitors with hard-wired binary weights can include a capacitor electrically connected between the identity MAC and the operational amplifier, wherein the capacitor is electrically connected on the feedback path. The identity MAC can be paired with a designated capacitor rated for different capacitances used to weight the identity MAC output.

[0047] In some embodiments, the analog adder can be implemented using switched capacitors as a binary DAC. The identity MAC can be electrically connected to "m" capacitors via an identity MAC switch to the analog adder. The analog adder may include optional buffer and accumulator switches that can electrically connect capacitors used to receive the identity MAC output. The identity MAC switch and accumulator switch can be controlled such that the output of one identity MAC can be output to and received by a designated capacitor. Each capacitor can be rated for different capacitors used to weight the identity MAC output to produce an average output from all capacitors.

[0048] In some embodiments, switched capacitors can be used to configure the analog adder as a sequential binary accumulator. The identity MAC can be electrically connected in parallel to the paired capacitors via an identity MAC switch configured to connect one identity MAC to the paired capacitors. Optionally, a buffer can be electrically connected between the identity MAC switch and the paired capacitors. The paired capacitors may include a sampler capacitor and an accumulator capacitor rated for the same capacitance. A sampler reset switch can be closed to electrically connect the sampler capacitor to ground to discharge or reset the sampler capacitor. An identity MAC switch can be closed to electrically connect the identity MAC to the sampler capacitor, thereby charging or loading the sampler capacitor using the identity MAC output. An accumulator switch can be closed to charge or load the accumulator capacitor via a shared charge or load on the sampler capacitor. This switch control procedure can be repeated until all multiplications and accumulations of the start value bit and weight value bit are sequentially output to the analog adder.

[0049] In some embodiments, the accumulator capacitor may include multiple capacitors that are cumulatively rated for the same capacitance as the sampler capacitor. Each unit cell MAC may be electrically connected to a pair of sampler capacitors and accumulator capacitors. Multiple MAC array switches for each of the accumulator capacitors may be configured to connect the accumulator capacitors in parallel to the MAC output. The MAC array switches for each of the accumulator capacitors may be controlled to discharge or output the charge or load of the accumulator capacitors in parallel to the MAC output. In this configuration, the combined output of the accumulator capacitors may be the average of the MAC array outputs with appropriate weights.

[0050] FIG1 illustrates a system including a computing device 100 suitable for use with various embodiments. The computing device 100 may include a SoC 102 having a processor 104, memory 106, a communication interface 108, a memory interface 110, a peripheral interface 120, and a MAC controller 124. The computing device 100 may further include communication components 112 (such as a wired or wireless modem), memory 114, an antenna 116 for establishing a wireless communication link, and / or peripheral devices 122. The processor 104 may include any of a variety of processing devices, such as multiple processor cores.

[0051] The terms "System-on-a-Chip" or "SoC" are generally used herein to refer to a set of interconnected electronic circuits, but do not exclusively include processing devices, memory, and communication interfaces. Processor 104 may include various types of processors and / or processor cores, such as general-purpose processors, central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), security processing units (SPUs), intellectual property units (IPUs), subsystem processors for specific components of computing devices (such as image processors for camera subsystems or display processors for displays), auxiliary processors, peripheral processors, single-core processors, multi-core processors, controllers, and / or microcontrollers. The processing device may further embody other hardware and hardware combinations, such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), other programmable logic devices, individual gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and / or time references. Integrated circuits may be configured such that components of the integrated circuit reside on a monolithic semiconductor material such as silicon.

[0052] SoC 102 may include one or more processors 104. Computing device 100 may include more than one SoC 102, thereby increasing the number of processors 104 and processor cores. Computing device 100 may also include processors 104 not associated with SoC 102. A single processor 104 may be a multi-core processor. Processors 104 may each be configured for a specific purpose, and may be the same as or different from other processors 104 of computing device 100. One or more of the processors 104 and processor cores with the same or different configurations may be packaged together. A group of processors 104 or processor cores may be referred to as a multiprocessor cluster.

[0053] The memory 106 of the SoC 102 may be volatile or non-volatile memory, configured to store data and processor-executable code for access by the processor 104 or other components of the SoC 102. The computing device 100 and / or the SoC 102 may include one or more memories 106, 114 configured for various purposes. The one or more memories 106 may include volatile memory, such as random access memory (RAM) or main memory, or cache buffer memory. These memories 106 may be configured to temporarily hold a limited amount of data received from data sensors or subsystems, data and / or processor-executable code instructions requested from non-volatile memory, loaded from non-volatile memory into memory 106 for future access based on various factors, and / or intermediate processing data and / or processor-executable code instructions generated by the processor 104 and temporarily stored for future fast access without being stored in non-volatile memory. In some embodiments, any number and combination of memory 106 may include one-time programmable or read-only memory.

[0054] Memory 106 may be configured to at least temporarily store data and processor executable code loaded into memory 106 from another storage device (such as another memory 106 or memory 114) for access by one or more of the processor 104 or other components of SoC 102. The data or processor executable code loaded into memory 106 may be loaded in response to the execution of a function by other components of processor 104 or SoC 102. Loading data or processor executable code into memory 106 in response to the execution of a function may result from an unsuccessful or "missed" memory access request to memory 106, because the requested data or processor executable code is not located in memory 106. In response to a memory miss, a memory access request may be made to another memory 106 or memory 114 to load the requested data or processor executable code from the other memory 106 or memory 114 into memory 106. Loading data or processor executable code into memory 106 in response to the execution of a function may result from a memory access request to another memory 106 or memory 114, and the data or processor executable code may be loaded into memory 106 for later access.

[0055] Memory interface 110 and memory 114 can work in complete coordination to allow computing device 100 to store data and processor executable code on volatile and / or non-volatile storage media, and to retrieve data and processor executable code from volatile and / or non-volatile storage media. Memory 114 can be configured very similarly to embodiments of memory 106, wherein memory 114 can store data or processor executable code for access by one or more of the processor 104 or other components of SoC 102. In some embodiments, non-volatile memory 114 can retain information after the computing device 100 has been powered off. When power is restored and the computing device 100 is restarted, the information stored in memory 114 can be made available to the computing device 100. In some embodiments, volatile memory 114 can not retain information after the computing device 100 has been powered off. The memory interface 110 can control access to the memory 114 and allow the processor 104 or other components of the SoC 12 to read data from and write data to the memory 114.

[0056] The MAC controller 124 can be configured to control any number and combination of unit MACs 126 and analog adders 128, which can be configured as multi-bit MACs 130 and can combine the outputs of unit MACs 126, as further described herein. In some embodiments, the MAC controller 124 can be configured to control any number and combination of switches to selectively electrically connect unit MACs 126 to components of any number and combination of analog adders 128 via controlling any number and combination of switches of analog adders 128, as further described herein. In some embodiments, the MAC controller 124 can be a processor 104 and / or can be an integral part of the processor 104. In some embodiments, unit MACs 126 and / or analog adders 128 can be an integral part of memory 106.

[0057] Some or all of the components of the computing device 100 and / or SoC 102 may be arranged and / or combined in different ways while still providing the functionality of the various embodiments. The computing device 100 may not be limited to each of the components, and multiple instances of each component may be included in various configurations of the computing device 100.

[0058] FIG2 illustrates an example memory device (e.g., memory 106 in FIG1) suitable for implementing various embodiments, configured to implement a multi-bit MAC using in-memory computing (CIM) and / or near-memory computing (NMC) arrays. The multi-bit MAC 200 (e.g., multi-bit MAC 130 in FIG1) may include any number of identity MACs 206 (e.g., identity MAC 126 in FIG1), sequential integrators 208 (e.g., analog adder 128 in FIG1), multi-bit weight processing units 210, and analog-to-digital converters (ADCs) 212. Identity MACs 206 can be used to convert signals from the digital domain to the analog domain. Sequential integrators 208 and multi-bit weight processing units 210 can be used and generate signals in the analog domain. ADCs 212 can be used to convert signals from the analog domain to the digital domain. Therefore, the multi-bit MAC 200 can operate at least partially in the analog domain.

[0059] The multi-bit MAC 200 can be configured as a grid of CIM and / or NMC cells of a memory device having components for multiplying bits of "n"-bit start values ​​204a, 204b, 204c and bits of "m"-bit weight values ​​in parallel. The bits of the "n"-bit start values ​​204a, 204b, 204c and the "m"-bit weight values ​​can be represented by digital voltage signals to the CIM and / or NMC cells. Each of the CIM and / or NMC cells can multiply one bit of the "n"-bit start values ​​204a, 204b, 204c and one bit of the "m"-bit weight value. The multi-bit MAC 200 can receive the "m"-bit weight value, and each of the CIM and / or NMC cells can store the "m"-bit weight value. For example, each row of the CIM and / or NMC cell grid can store multiple "m"-bit weight values, and each row can store the same multiple "m"-bit weight values. The multi-bit MAC 200 can receive sequential inputs 202 of "n"-bit start values ​​204a, 204b, 204c. For example, start values ​​204a, 204b, 204c can be input into a row of the CIM and / or NMC cell grid. The bits of the "n"-bit start values ​​204a, 204b, 204c can be sequentially input into each of the CIM and / or NMC cells. For example, the "n"-bit start values ​​204a, 204b, 204c can be sequentially input from least significant bit to most significant bit into each CIM and / or NMC cell in a row of the CIM and / or NMC cell grid. Any bit of the "n"-bit start values ​​204a, 204b, 204c input to the CIM and / or NMC cells can be input in parallel to each of the CIM and / or NMC cells. For example, the least significant bit of the "n"-bit start values ​​204a, 204b, 204c can be input in parallel to the CIM and / or NMC cells of the corresponding row in the grid of the CIM and / or NMC cells. In some embodiments, the "n"-bit start values ​​204a, 204b, 204c can be data-streamed from an input interface (not shown) to the CIM and / or NMC cells. In some embodiments, the "n"-bit start values ​​204a, 204b, 204c and / or the "m"-bit weight values ​​can be provided to the CIM and / or NMC cells from memory (not shown) (such as registers, buffers, cache memory, random access memory (RAM), etc.). CIM and / or NMC cells can multiply each of the bits received in sequence from the "n" bit start values ​​204a, 204b, 204c with the stored "m" bit weight value. The output of the multiplication performed by the cells of the CIM and / or NMC mesh can be an analog voltage.Each cell of the CIM and / or NMC grid can be electrically connected to any number and combination of voltage accumulators (not shown) (such as capacitors) configured to accumulate the output of multiplications performed by cells of the CIM and / or NMC grid.

[0060] The combination of cells of the CIM and / or NMC grids and electrically connected voltage accumulators may be referred to herein as the identity cell MAC 206. The identity cell MAC output generated by the multiplication and accumulation performed from the identity cell MAC 206 may be output from the identity cell MAC 206 to the sequential integrator 208. The identity cell MAC output may be represented by an analog voltage signal to the sequential integrator 208.

[0061] The sequential integrator 208 can receive the unit MAC outputs of the unit MAC 206 and can combine the unit MAC outputs via addition or accumulation. Various embodiments include analog adders that can be used to implement the sequential integrator 208. In some embodiments, each sequential integrator 208 can add the single-bit MAC outputs from the single unit MAC 206. The addition of the unit MAC outputs by the sequential integrator 208 can be implemented in various ways as further described herein (e.g., referring to Figures 3-10). The addition of the unit MAC outputs by the sequential integrator 208 can utilize appropriate weights corresponding to the importance of each bit to convert the unit MAC outputs representing the result of bitwise multiplication and accumulation into an accumulated unit MAC output as an analog voltage signal. The accumulated unit MAC output resulting from the addition of the unit MAC outputs by the sequential integrator 208 can be output by the sequential integrator 208 to the multi-bit weighting processing unit 210.

[0062] The multi-bit weighting processing unit 210 can receive the accumulated unit MAC output from the sequential integrator 208 and perform weighted addition on the accumulated unit MAC output to generate a binary weighted average voltage of the accumulated unit MAC output, also referred to herein as the multi-bit MAC output. The binary weighted average voltage can be a voltage representing the product of "n" bit start values ​​204a, 204b, 204c and "m" bit weight values. The binary weighted average voltage can also be an analog signal. The binary weighted average voltage can be output by the multi-bit weighting processing unit 210 to the ADC 212, which can convert the binary weighted average voltage into a digital signal.

[0063] Figures 3-7, 9 and 10 illustrate examples of multi-bit MACs suitable for implementing various embodiments. Referring to Figure 3 and Figures 1 and 2, multi-bit MACs 300, 400, 500, 600, 700, 900, 1000 (e.g., multi-bit MAC 130 in Figure 1, multi-bit MAC 200 in Figure 2) can be circuits having any number of unit MACs 206a, 206b, 206c, 206d (e.g., unit MAC 126 in Figure 1, unit MAC 206 in Figure 2), unit MAC switches 304a, 304b, 304c, 304d, electrical transmission buses 306, 316, and / or ADC 212 (e.g., ADC 212 in Figure 2).

[0064] Each of the identity MACs 206a, 206b, 206c, and 206d can store one bit of an "m"-bit weight value (W1, W2, W3, …, Wm). Each identity MAC 206a, 206b, 206c, and 206d can receive sequential inputs (e.g., sequential input 202 in Figure 2) of an "n"-bit start value (A1, A2, …, An) (e.g., "n"-bit start values ​​204a, 204b, and 204c in Figure 2). Each bit of the "n"-bit start value can be sequentially input into each of the identity MACs 206a, 206b, 206c, and 206d. For example, the "n"-bit start value can be sequentially input into each of the identity MACs 206a, 206b, 206c, and 206d from least significant bit to most significant bit. Any bit of the "n"-bit start value can be input in parallel to each of the unit MACs 206a, 206b, 206c, and 206d. The bits of the "n"-bit start value and the "m"-bit weight value can be represented by digital voltage signals to the unit MACs 206a, 206b, 206c, and 206d. In some embodiments, the "n"-bit start value can be data-streamed from an input interface (not shown) to the unit MACs 206a, 206b, 206c, and 206d. In some embodiments, the "n"-bit start value and / or the "m"-bit weight value can be provided to the unit MACs 206a, 206b, 206c, and 206d from memory (not shown) (such as a register, buffer, cache memory, RAM, etc.). The unit MAC 206a, 206b, 206c, and 206d can multiply each of the bits received in sequence of the "n" bit start value and the bits received and / or stored of the "m" bit weight value (A1, A2, …, An x W1; A1, A2, …, An x W2; A1, A2, …, An x W3; … A1, A2, …, An x Wm), and accumulate the results of the multiplication. The identity MAC outputs generated from the multiplication and accumulation performed by identity MACs 206a, 206b, 206c, and 206d can be output by identity MACs 206a, 206b, 206c, and 206d to analog adders of multi-bit MACs 300, 400, 500, 600, 700, 900, and 1000 (e.g., analog adder 128, sequential integrator 208, and multi-bit weight processing unit 210 in Figures 1 and 2), which are further described herein. The identity MAC outputs can be represented by analog voltage signals to the analog adders of multi-bit MACs 300, 400, 500, 600, 700, 900, and 1000.

[0065] Identity MACs 206a, 206b, 206c, and 206d can be electrically connected to the analog adder via electrical transmission bus 306. A MAC controller (e.g., processor 104 or MAC controller 124 in FIG. 1) can control any number of identity MAC switches 304a, 304b, 304c, and 304d to selectively electrically connect the identity MACs 206a, 206b, 206c, and 206d to the analog adder via electrical transmission bus 306. For example, each identity MAC 206a, 206b, 206c, and 206d can be selectively electrically connected to the analog adder via a designated identity MAC switch 304a, 304b, 304c, and 304d. By controlling designated identity MAC switches 304a, 304b, 304c, and 304d to close the circuit that electrically connects identity MACs 206a, 206b, 206c, and 206d to the analog adder, identity MACs 206a, 206b, 206c, and 206d are selectively electrically connected to the analog adder. This allows the analog adder to output the identity MAC output generated by identity MACs 206a, 206b, 206c, and 206d.

[0066] The identity MAC switches 304a, 304b, 304c, and 304d can be controlled so that the identity MAC output can be sequentially output to the analog adder by the identity MAC switches 206a, 206b, 206c, and 206d, and received by the analog adder. For example, the identity MAC switches 304a, 304b, 304c, and 304d can be controlled to electrically connect the identity MAC switches 206a, 206b, 206c, and 206d after multiplying the least significant bit (A1) of the "n" bit start value with the bits of the "m" bit weight values ​​(W1, W2, W3, …, Wm) and accumulating the multiplication results. The identity MAC switches 304a, 304b, 304c, and 304d can be further controlled to sequentially connect the identity MAC switches 206a, 206b, 206c, and 206d after multiplying and accumulating the bits of the next higher significant bit (A2) of the "n"-bit start value and the "m"-bit weight values ​​(W1, W2, W3, …, Wm). This sequential control of the identity MAC switches 304a, 304b, 304c, and 304d can continue the multiplication and accumulation of the "n"-bit start value up to the most significant bit (An) of the "n"-bit start value, targeting the next higher significant bit. The unit MAC switches 304a, 304b, 304c, and 304d can be further controlled to repeatedly connect the unit MAC switches 206a, 206b, 206c, and 206d, as further described herein, after the multiplication and accumulation of one bit of the "n" bit start value and the bits of the "m" bit weight value, and before the sequential multiplication and accumulation of the higher significant bit of the "n" bit start value and the bits of the "m" bit weight value.

[0067] Figures 3-7 illustrate example embodiments of multi-bit MACs 300, 400, 500, 600, and 700, each having a single analog adder. The example of a single analog adder is for simplicity of illustration and description and is not intended to be limiting. The request is not limited to a single analog adder, and other embodiments of the multi-bit MACs 300, 400, 500, 600, and 700 may each use multiple analog adders. In such embodiments, the outputs of multiple analog adders of the multi-bit MACs 300, 400, 500, 600, and 700 may be combined. Similarly, Figures 9 and 10 illustrate example embodiments of multi-bit MACs 900 and 1000, each having a single analog adder. In some embodiments, the examples in Figures 9 and 10 illustrate a single analog adder of a multi-bit MAC 900, 1000, and each of them may include a plurality of analog adders.

[0068] Figure 3 illustrates an example multi-bit MAC using integrator-based thermal weighting suitable for implementing various embodiments. Referring to Figures 1-3, the multi-bit MAC 300 may include any number of analog adders. In some embodiments, the analog adders may include any number of operational amplifiers 312 and integrator capacitors 314 (also referred to as adder capacitors). In some embodiments, the analog adders may also include any number and combination of clear switches 308 and / or electrical ground 310. The integrator capacitors 314 of the analog adders may be electrically connected to the feedback path of the operational amplifiers 312. The inputs of the integrator capacitors 314 and the operational amplifiers 312 may be selectively electrically connected to the unit MACs 206a, 206b, 206c, 206d via electrical transmission bus 306 and designated unit MAC switches 304a, 304b, 304c, 304d. The inputs of the integrator capacitors 314 and the operational amplifiers 312 may be selectively electrically connected to the electrical ground 310 via clear switches 308. The outputs of integrator capacitor 314 and operational amplifier 312 can be electrically connected to ADC 212 via electrical transmission bus 316.

[0069] The analog adder can receive the identity MAC outputs from identity MACs 206a, 206b, 206c, and 206d at the input of operational amplifier 312 and at integrator capacitor 314. Integrator capacitor 314 can store the identity MAC outputs and, as further identity MAC outputs are received, store the sum of the identity MAC outputs. For a multi-bit "n"-bit start value, identity MAC switches 304a, 304b, 304c, and 304d can be controlled such that each item in the identity MAC output can be output to operational amplifier 312 and integrator capacitor 314 and received therein 2q times, where "q" can be the position of the start value bit from the least significant bit with q=0 to the most significant bit with q=n-1. Similarly, for multi-bit "m"-bit weight values, unit MAC switches 304a, 304b, 304c, and 304d can be controlled such that each item in the unit MAC output can be output to operational amplifier 312 and integrator capacitor 314 and received therein 2r times, where "r" can be the position of the weight value bit from the least significant bit with r=0 to the most significant bit with r=m-1. In some embodiments, 2q x 2r cycles can be spent outputting and receiving all unit MAC outputs. Integrator capacitor 314 can be charged, and the gain and output voltage of operational amplifier 312 can be increased. The analog voltage output of operational amplifier 312 (also referred to herein as multi-bit MAC output) can be the integral of the voltage input to operational amplifier 312, which is weighted over time via the impedance of integrator capacitor 314, and this can be used as a weighted addition operation for the unit MAC output. The analog voltage output by the operational amplifier 312 can be output to the ADC 212 via the electrical transmission bus 316 and received by the ADC 212, and converted into a digital signal by the ADC 212.

[0070] After the multiplication and addition of all bits of the "n"-bit start value and "m"-bit weight value are completed, the multi-bit MAC 300 can be reset or cleared. The clear switch 308 can be controlled by a MAC controller (e.g., processor 104 in FIG. 1, MAC controller 124) to selectively electrically connect the analog adder (including the input of operational amplifier 312 and integrator capacitor 314) to electrical ground 310. Electrically connecting the components of the multi-bit MAC 300 to electrical ground 310 can discharge any residual voltage in the multi-bit MAC 300, allowing the multi-bit MAC 300 to perform the next multiplication and addition of different combinations of the "n"-bit start value and / or "m"-bit weight value.

[0071] A multi-bit MAC 300 using integrator-based hot weights can complete the multiplication and addition of all bits of the "n"-bit start value and the "m"-bit weight value in 2n x 2m cycles. The multi-bit MAC 300 is suitable for scenarios where at least one of the "n"-bit start value and the "m"-bit weight value has a low dynamic range. The multi-bit MAC 300 can be particularly useful when used with binary-weighted multi-bit start values.

[0072] Figure 4 illustrates an example multi-bit MAC using integrator-based hardwired binary weights suitable for implementing various embodiments. Referring to Figures 1-4, the multi-bit MAC 400 may include any number of analog adders. In some embodiments, the analog adders may include any number of operational amplifiers 312, integrator capacitors 314 (also referred to as adder capacitors), and designator capacitors 402a, 402b, 402c, 402d. In some embodiments, the analog adders may also include any number and combination of clear switches 308 and / or electrical grounds 310. The designator capacitors 402a, 402b, 402c, 402d of the analog adders may be selectively electrically connected to the unit MACs 206a, 206b, 206c, 206d via associated unit MAC switches 304a, 304b, 304c, 304d. The integrator capacitor 314 of the analog adders may be electrically connected to the feedback path of the operational amplifier 312. The input terminals of integrator capacitor 314 and operational amplifier 312 can be electrically connected to designated capacitors 402a, 402b, 402c, and 402d via electrical transmission bus 306. The designated capacitors 402a, 402b, 402c, and 402d, the input terminals of integrator capacitor 314, and operational amplifier 312 can be selectively electrically connected to electrical ground 310 via clear switch 308. The output terminals of integrator capacitor 314 and operational amplifier 312 can be electrically connected to ADC 212 via electrical transmission bus 316.

[0073] The analog adder can receive the identity MAC output from identity MACs 206a, 206b, 206c, and 206d at designated capacitors 402a, 402b, 402c, and 402d. Each designated capacitor 402a, 402b, 402c, and 402d can be associated with and selectively electrically connected to a specific identity MAC 206a, 206b, 206c, and 206d. Based on the relationship between the capacitance rating ("C") of specified capacitors 402a, 402b, 402c, and 402d and the position of the bits in the "n"-bit and / or "m"-bit start-up values ​​multiplied by the specific unit MAC 206a, 206b, 206c, and 206d in the range from the least significant bit to the most significant bit, specified capacitors 402a, 402b, 402c, and 402d can be associated with specific unit MAC 206a, 206b, 206c, and 206d. For multi-bit "n"-bit start-up values, a capacitance rating of 2qC is used to rate specified capacitors 402a, 402b, 402c, and 402d, where "q" can be the position of the start-up value bit from the least significant bit with q=0 to the most significant bit with q=n-1. Similarly, for multi-bit "m"-bit weight values, a capacitance rating of 2rC can be used to rate the specified capacitors 402a, 402b, 402c, 402d, where "r" can be the position of the weight value bit from the least significant bit with r=0 to the most significant bit with r=m-1. In some embodiments, each specified capacitor 402a, 402b, 402c, 402d can be a single capacitor with an appropriate capacitance rating for the associated specific unit cell MAC 206a, 206b, 206c, 206d. In some embodiments, each specified capacitor 402a, 402b, 402c, 402d can be multiple capacitors electrically connected in series and / or parallel, which cumulatively have an appropriate capacitance rating for the associated specific unit cell MAC 206a, 206b, 206c, 206d. The capacitance ratings of specified capacitors 402a, 402b, 402c, and 402d can be used as hardwired binary weights for the specified capacitors 402a, 402b, 402c, and 402d to receive the unit MAC output from the associated specific unit MACs 206a, 206b, 206c, and 206d.

[0074] When selectively electrically connected to associated unit cells MAC 206a, 206b, 206c, 206d via associated unit cell MAC switches 304a, 304b, 304c, 304d, designated capacitors 402a, 402b, 402c, 402d can receive and store the unit cell MAC output from associated unit cells MAC 206a, 206b, 206c, 206d. Designated capacitors 402a, 402b, 402c, 402d can be charged by receiving the unit cell MAC output when selectively electrically connected to associated unit cells MAC 206a, 206b, 206c, 206d. The specified capacitors 402a, 402b, 402c, and 402d can output or discharge the unit cell MAC output, which is weighted in relation to the capacitance rating of the specified capacitors 402a, 402b, 402c, and 402d, when the specified capacitors 402a, 402b, 402c, and 402d are selectively electrically disconnected from the associated unit cell MAC 206a, 206b, 206c, and 206d.

[0075] The weighted unit MAC output can be received at the input of operational amplifier 312 and at integrator capacitor 314. Integrator capacitor 314 can store the unit MAC output, for example, in the form of a weighted unit MAC output, and store the sum of the unit MAC outputs as further unit MAC outputs are received, for example, as a sum of weighted unit MAC outputs as further weighted unit MAC outputs are received. Integrator capacitor 314 can be charged, and the gain and output voltage of operational amplifier 312 can be increased. The analog voltage output of operational amplifier 312 (also referred to herein as multi-bit MAC output) can be an integral of the voltage input to operational amplifier 312, which is weighted over time via the impedance of integrator capacitor 314, and this can be used as a weighted addition operation for the unit MAC output. The analog voltage output by the operational amplifier 312 can be output to the ADC 212 via the electrical transmission bus 316 and received by the ADC 212, and converted into a digital signal by the ADC 212.

[0076] After the multiplication and addition of all bits of the "n"-bit start value and "m"-bit weight value are completed, the multi-bit MAC 400 can be reset or cleared. The clear switch 308 can be controlled to selectively electrically connect the analog adders (including designated capacitors 402a, 402b, 402c, 402d, the input of operational amplifier 312, and integrator capacitor 314) to electrical ground 310. Electrically connecting the components of the multi-bit MAC 400 to electrical ground 310 can discharge any residual voltage in the multi-bit MAC 400, allowing the multi-bit MAC 400 to perform the next multiplication and addition of different combinations of the "n"-bit start value and / or "m"-bit weight value.

[0077] A multi-bit MAC 400 using hard-wired binary weighting based on integrators can be similarly configured as a multi-bit MAC using a hot-weighting function based on integrators (e.g., multi-bit MAC 300 in Figure 3), both including an adder with operational amplifier 312, wherein integrator capacitor 314 is electrically connected to the feedback path of operational amplifier 312. However, a multi-bit MAC using a hot-weighting function based on integrators relies on operational amplifier 312 and integrator capacitor 314 to weight the received unit MAC output. Instead, multi-bit MAC 400 uses the capacitance rating of hard-wired specified capacitors 402a, 402b, 402c, 402d to weight the unit MAC output before operational amplifier 312 and integrator capacitor 314 receive the weighted unit MAC output. Therefore, multi-bit MAC 400 can perform the accumulation of the unit MAC output faster than a multi-bit MAC using a hot-weighting function based on integrators. For example, instead of waiting for the integrator capacitor 314 to be charged from the sequentially received single-bit MAC outputs, the multi-bit MAC 400 can charge the designated capacitors 402a, 402b, 402c, and 402d in parallel and output a weighted single-bit MAC output to the operational amplifier 312 and the integrator capacitor 314.

[0078] Figure 5 illustrates an example multi-bit MAC adapted to implement various embodiments using a binary DAC as a load. Referring to Figures 1-5, the multi-bit MAC 500 may include any number of analog adders. In some embodiments, the analog adders may include any number of adder switches 504a, 504b, 504c and adder capacitors 506a, 506b, 506c. In some embodiments, the analog adders may also include any number of optional buffers 502. In some embodiments, the analog adders may also include any number and combination of clear switches 308, electrical grounds 310, and / or designated electrical grounds 508. Adder capacitors 506a, 506b, and 506c of the analog adder can be selectively electrically connected to unit cells MAC 206a, 206b, 206c, and 206d via associated unit cell MAC switches 304a, 304b, 304c, and 304d, associated adder switches 504a, 504b, and 504c, and electrical transmission bus 306. Adder capacitors 506a, 506b, and 506c can be electrically connected between associated adder switches 504a, 504b, and 504c and electrical ground 508. Adder capacitors 506a, 506b, and 506c can be selectively electrically connected to electrical ground 310 via adder switches 504a, 504b, and 504c and clear switch 308. Adder capacitors 506a, 506b, and 506c can be electrically connected to the ADC 212 via electrical transmission bus 316. Adder switches 504a, 504b, and 504c can be controlled by a MAC controller (e.g., processor 104 or MAC controller 124 in Figure 1) to selectively electrically connect adder capacitors 506a, 506b, and 506c to electrical transmission buses 306 and 316.

[0079] The analog adder can receive the identity MAC output from identity MACs 206a, 206b, 206c, and 206d at adder capacitors 506a, 506b, and 506c. Each adder capacitor 506a, 506b, and 506c can be selectively and sequentially electrically connected to identity MACs 206a, 206b, 206c, and 206d. Adder capacitors 506a, 506b, and 506c can have different sequential capacitance ratings ("C"), which can correspond to the number of bits of an "n" bit start value and / or an "m" bit weight value. For multi-bit "n" bit start values, a capacitance rating of 2qC can be used to rate adder capacitors 506a, 506b, and 506c, where "q" can be a value from 0 to n-1. Similarly, for multi-bit "m"-bit weight values, adder capacitors 506a, 506b, and 506c can be rated using a 2rC capacitance rating, where "r" can be a value from 0 to m-1. In some embodiments, each adder capacitor 506a, 506b, and 506c can be a single capacitor with an appropriate capacitance rating for its position in the order of capacitance rating. In some embodiments, each adder capacitor 506a, 506b, and 506c can be a plurality of capacitors electrically connected in series and / or parallel, which cumulatively have an appropriate capacitance rating for its position in the order of capacitance rating. The capacitance ratings of adder capacitors 506a, 506b, and 506c can be used as hardwired binary weights for the adder capacitors 506a, 506b, and 506c to receive the unit MAC output from unit MACs 206a, 206b, 206c, and 206d.

[0080] When the associated unit cell MAC switches 304a, 304b, 304c, 304d and the associated adder switches 504a, 504b, 504c are selectively electrically connected to the unit cells MAC 206a, 206b, 206c, 206d, the adder capacitors 506a, 506b, 506c can receive and store the unit cell MAC output from the unit cells MAC 206a, 206b, 206c, 206d. The unit cell MAC switches 304a, 304b, 304c, 304d and the adder switches 504a, 504b, 504c can be controlled to output the unit cell MAC output from the unit cells MAC 206a, 206b, 206c, 206d, such that each adder capacitor 506a, 506b, 506c receives the unit cell MAC output. For example, the unit cell MAC switches 304a, 304b, 304c, and 304d can be controlled to close the circuit that electrically connects the unit cells MAC 206a, 206b, 206c, and 206d to the analog adder, thereby outputting the unit cell MAC output to the analog adder. The adder switches 504a, 504b, and 504c associated with each adder capacitor 506a, 506b, and 506c can be controlled to sequentially load the unit cell MAC output into each of the adder capacitors 506a, 506b, and 506c by closing the circuit that electrically connects the unit cells MAC 206a, 206b, 206c, and 206d to the associated adder capacitors 506a, 506b, and 506c. In other words, each adder capacitor 506a, 506b, 506c can receive the unit cell MAC output from each of the unit cells MAC 206a, 206b, 206c, 206d. In some embodiments, adder switches 504a, 504b, 504c can be controlled to load the unit cell MAC output into the adder capacitors 506a, 506b, 506c in order of capacitance rating based on the adder capacitors 506a, 506b, 506c. Adder capacitors 506a, 506b, 506c can be charged by receiving the unit cell MAC output when selectively electrically connected to the unit cells MAC 206a, 206b, 206c, 206d.

[0081] When the unit MACs 206a, 206b, 206c, and 206d are selectively electrically disconnected from the unit MACs 206a, 206b, 206c, and 206d via the unit MAC switches 304a, 304b, 304c, and 304d, and are selectively electrically connected to the ADC 212 via the adder switches 504a, 504b, and 504c, the adder capacitors 506a, 506b, and 506c can output or discharge the unit MAC output weighted in relation to the capacitance rating of the adder capacitors 506a, 506b, and 506c. When the unit cell MAC switches 304a, 304b, 304c, and 304d are selectively electrically disconnected from all associated unit cell MACs 206a, 206b, 206c, and 206d, and selectively electrically connected to the ADC 212 via all adder switches 504a, 504b, and 504c, the adder capacitors 506a, 506b, and 506c can output or discharge the weighted unit cell MAC output.

[0082] The weighted unit MAC output can be output as an analog voltage to the electrical transmission bus 316 and the ADC 212. The weighted unit MAC output can be combined by adding the analog voltages on the electrical transmission bus 316 to produce a weighted average of the analog voltages (also referred to herein as the multi-bit MAC output), and converted into a digital signal by the ADC 212.

[0083] After the multiplication and addition of all bits of the "n"-bit start value and the "m"-bit weight value are completed, the multi-bit MAC 500 can be reset or cleared. The clear switch 308 can be controlled to selectively connect the analog adders (including adder capacitors 506a, 506b, 506c) to electrical ground 310. Adder switches 504a, 504b, 504c can also be controlled to electrically connect the adder capacitors 506a, 506b, 506c to electrical ground 310 via the clear switch 308. Connecting the components of the multi-bit MAC 500 to electrical ground 310 can discharge any residual voltage in the multi-bit MAC 500, allowing the multi-bit MAC 500 to perform the next multiplication and addition of different combinations of the "n"-bit start value and / or the "m"-bit weight value.

[0084] In some embodiments, buffer 502 may be electrically connected between the unit cells MAC 206a, 206b, 206c, 206d and the adder capacitors 506a, 506b, 506c. Buffer 502 may be an analog buffer configured to reduce the voltage and / or current load effect of the adder capacitors 506a, 506b, 506c on the unit cells MAC 206a, 206b, 206c, 206d. In some embodiments, buffer 502 may reduce the load effect compared to the load effect without buffer 502. For example, buffer 502 may reduce the voltage drop caused by the mismatched relative impedance of the adder capacitors 506a, 506b, 506c and the unit cells MAC 206a, 206b, 206c, 206d. Buffer 502 can also be configured to improve the linearity of the unit MAC output from the unit MACs 206a, 206b, 206c, 206d to the adder capacitors 506a, 506b, 506c. In some embodiments, buffer 502 can improve linearity compared to the linearity without buffer 502. For example, when losses occur in the transmission of the unit MAC output between the unit MACs 206a, 206b, 206c, 206d and the adder capacitors 506a, 506b, 506c, buffer 502 can improve the linearity of the unit MAC output by linearly amplifying the unit MAC output.

[0085] FIG6 illustrates an example multi-bit MAC adapted to implement various embodiments using a sequential binary accumulator as a load. Referring to FIG1-6, the multi-bit MAC 600 may include any number of analog adders. In some embodiments, the analog adders may include any number of adder switches 604a, 604b and adder capacitors 606a, 606b. In some embodiments, the analog adders may also include any number of optional buffers 502. In some embodiments, the analog adders may also include any number and combination of clear switches 308, electrical grounds 310 and / or designated electrical grounds 508. The adder capacitors 606a, 606b of the analog adders may be selectively electrically connected to the unit MACs 206a, 206b, 206c, 206d via associated unit MAC switches 304a, 304b, 304c, 304d, associated adder switches 604a, 604b and electrical transmission bus 306. Adder capacitors 606a and 606b can be selectively electrically connected to each other via adder switches 604a and 604b and electrical transmission bus 316. Adder capacitors 606a and 606b can be electrically connected between associated adder switches 604a and 604b and electrical ground 508. Adder capacitors 606a and 606b can be selectively electrically connected to electrical ground 310 via adder switches 604a and 604b and clear switch 308. Adder capacitors 606a and 606b can be electrically connected to ADC 212 via electrical transmission bus 316. Adder switches 604a and 604b can be controlled via a MAC controller (e.g., processor 104 and MAC controller 124 in FIG. 1) to selectively electrically connect adder capacitors 606a and 606b to electrical transmission buses 306 and 316.

[0086] The analog adder may receive the identity MAC output from identity MACs 206a, 206b, 206c, and 206d at adder capacitors 606a and 606b. Adder capacitors 606a and 606b may include a sampler capacitor 606a and an accumulator capacitor 606b. Sampler capacitor 606a may be optionally electrically connected to identity MACs 206a, 206b, 206c, and 206d. Accumulator capacitor 606b may be optionally electrically connected to sampler capacitor 606a. Adder capacitors 606a and 606b may have the same capacitance rating ("C"). In some embodiments, each adder capacitor 606a and 606b may be a single capacitor with a capacitance rating. In some embodiments, each adder capacitor 606a and 606b may be a plurality of capacitors electrically connected in series and / or parallel, which cumulatively have capacitance ratings. The capacitance ratings of adder capacitors 606a and 606b can be used as hardwired binary weights for the adder capacitors 606a and 606b to receive the unit MAC outputs from unit MACs 206a, 206b, 206c, and 206d.

[0087] When the associated unit cell MAC switches 304a, 304b, 304c, 304d and the associated adder switches 604a, 604b (i.e., sampler switch 604a) are selectively electrically connected to the unit cells MAC 206a, 206b, 206c, 206d, the sampler capacitor 606a can receive and store the unit cell MAC outputs from the unit cells MAC 206a, 206b, 206c, 206d. The unit cell MAC switches 304a, 304b, 304c, 304d and the sampler switch 604a can be controlled to output the unit cell MAC outputs from the unit cells MAC 206a, 206b, 206c, 206d, such that the sampler capacitor 606a receives the unit cell MAC outputs in a specific order. In some embodiments, the order can be from the least significant bits of the multiplication and accumulation of the "n"-bit start value and the "m"-bit weight value to the most significant bits of the "n"-bit start value and the "m"-bit weight value. For example, identity MAC switches 304a, 304b, 304c, and 304d can be controlled to sequentially close the circuitry electrically connecting identity MACs 206a, 206b, 206c, and 206d to the analog adder to output the identity MAC output to the analog adder. Sampler switch 604a associated with sampler capacitor 606a can be controlled to sequentially load the identity MAC output into sampler capacitor 606a by closing the circuitry electrically connecting identity MACs 206a, 206b, 206c, and 206d to sampler capacitor 606a. In other words, sampler capacitor 606a can receive unit MAC outputs from each of the unit MACs 206a, 206b, 206c, and 206d. In some embodiments, sampler switch 604a can be controlled to load unit MAC outputs into sampler capacitor 606a in order of importance of bits multiplied by an "n"-bit start value and an "m"-bit weight value to produce unit MAC outputs. When selectively electrically connected to unit MACs 206a, 206b, 206c, and 206d, sampler capacitor 606a can be charged by receiving unit MAC outputs. Sampler capacitor 606a can store samples of unit MAC outputs, which may include combinations of received unit MAC outputs modified by sharing samples of unit MAC outputs with accumulator capacitor 606b. Samples of unit MAC outputs are referred to herein as unit MAC output samples. The sampler capacitor 606a can respond to each unit MAC output received to store and output the unit MAC output sample.

[0088] When selectively electrically connected to sampler capacitor 606a via adder switches 604a and 604b (i.e., sampler switch 604a and accumulator switch 604b), accumulator capacitor 606b can receive and store unit cell MAC output samples from sampler capacitor 606a. When sampler capacitor 606a is selectively electrically disconnected from unit cells MAC 206a, 206b, 206c, and 206d and selectively connected to accumulator capacitor 606b via adder switches 604a and 604b, sampler capacitor 606a can share unit cell MAC output samples or output them to accumulator capacitor 606b. Accumulator capacitor 606b can receive and store unit cell MAC output samples. For example, identity MAC switches 304a, 304b, 304c, and 304d can be controlled to selectively electrically disconnect sampler capacitor 606a from identity MACs 206a, 206b, 206c, and 206d. Sampler switch 604a can be controlled to electrically connect sampler capacitor 606a to electrical transmission bus 316, and accumulator switch 604b can be controlled to electrically connect accumulator capacitor 606b to electrical transmission bus 316. Sampler capacitor 606a can sample the identity MAC output to accumulator capacitor 606b. After receiving the identity MAC output, the identity MAC output sample can be shared by sampler capacitor 606a and accumulator capacitor 606b (as further described herein with reference to Figure 8). The procedure of receiving each unit MAC output by sampler capacitor 606a, sampling unit MAC output by sampler capacitor 606a, and receiving unit MAC output by accumulator capacitor 606b can continue for each multiplication and addition of all bits of the "n" bit start value and "m" bit weight value.

[0089] After completing the multiplication and addition of one bit of the "n"-bit start value and the "m"-bit weight value, the sampler capacitor 606a can be reset or cleared. The clear switch 308 can be controlled to selectively electrically connect the sampler capacitor 606a to the electrical ground 310. The sampler switch 604a can be controlled to selectively electrically connect the sampler capacitor 606a to the electrical ground 310. The accumulator switch 604b can be controlled to selectively electrically disconnect the accumulator capacitor 606b from the electrical ground 310. Electrically connecting the components of the multi-bit MAC 600 to the electrical ground 310 can discharge any residual voltage in the components, allowing the multi-bit MAC 600 to perform the next multiplication and addition of different combinations of the "n"-bit start value and / or the "m"-bit weight value.

[0090] When the unit MAC switches 304a, 304b, 304c, and 304d are selectively electrically disconnected from the unit MAC switches 206a, 206b, 206c, and 206d, selectively electrically disconnected from the sampler capacitor 606a via the sampler switch 604a, and selectively electrically connected to the ADC 212 via the accumulator switch 604b, the accumulator capacitor 606b can sample or discharge the unit MAC output. The output of the accumulator capacitor 606b is also referred to herein as the multi-bit MAC output. The sampled unit MAC output can be output as an analog voltage to the electrical transmission bus 316 and the ADC 212. The analog voltage on the electrical transmission bus 316 can be converted into a digital signal by the ADC 212.

[0091] After the multiplication and addition of all bits of the "n"-bit start value and the "m"-bit weight value are completed, the multi-bit MAC 600 can be reset or cleared. The clear switch 308 can be controlled to selectively connect the analog adders (including adder capacitors 606a, 606b) to electrical ground 310. Adder switches 604a, 604b can also be controlled to electrically connect adder capacitors 606a, 606b to electrical ground 310 via the clear switch 308. Electrically connecting the components of the multi-bit MAC 600 to electrical ground 310 can discharge any residual voltage in the multi-bit MAC 600, allowing the multi-bit MAC 600 to perform the next multiplication and addition of different combinations of the "n"-bit start value and / or the "m"-bit weight value.

[0092] In some embodiments, buffer 502 may be electrically connected between unit cells MAC 206a, 206b, 206c, 206d and adder capacitors 606a, 606b. Buffer 502 may be an analog buffer configured to reduce the voltage and / or current load effect of adder capacitors 606a, 606b on unit cells MAC 206a, 206b, 206c, 206d. In some embodiments, buffer 502 may reduce the load effect compared to the load effect without buffer 502. For example, buffer 502 may reduce the voltage drop caused by the mismatched relative impedance of adder capacitors 606a, 606b and unit cells MAC 206a, 206b, 206c, 206d. Buffer 502 can also be configured to improve the linearity of the unit MAC output from the unit MACs 206a, 206b, 206c, 206d to the adder capacitors 606a, 606b. In some embodiments, buffer 502 can improve linearity compared to the linearity without buffer 502. For example, when losses occur in the transmission of the unit MAC output between the unit MACs 206a, 206b, 206c, 206d and the adder capacitors 606a, 606b, buffer 502 can improve the linearity of the unit MAC output by linearly amplifying the unit MAC output. For implementations with large "n"-bit start values ​​and / or "m"-bit weight values, buffer 502 can be omitted. For large "n"-bit start values ​​and / or "m"-bit weight values, the identity MAC outputs of identity MACs 206a, 206b, 206c, and 206d are large because sharing the identity MAC outputs does not introduce too much loss between identity MACs 206a, 206b, 206c, and 206d and sampler capacitor 606a. The loss between identity MACs 206a, 206b, 206c, and 206d and sampler capacitor 606a can be linear and does not lead to non-linearity.

[0093] Figure 7 illustrates an example of a multi-bit MAC adapted to implement various embodiments using a sequential binary accumulator as a load. Referring to Figures 1-7, the multi-bit MAC 700 may include any number of analog adders. In some embodiments, the analog adders may include any number of adder switches 702 and adder capacitors 606a, 606b. In some embodiments, the analog adders may also include any number and combination of clear switches 308a, 308b, electrical grounds 310a, 310b and / or designated electrical grounds 508. The adder capacitors 606a, 606b of the analog adders may be selectively electrically connected to the unit MACs 206a, 206b, 206c, 206d via associated unit MAC switches 304a, 304b, 304c, 304d, associated adder switch 702 and electrical transmission bus 306. Adder capacitors 606a and 606b can be selectively electrically connected to each other via adder switch 702 and electrical transmission bus 316. Adder capacitors 606a and 606b can be electrically connected between electrical transmission bus 316 and electrical ground 508. Adder capacitors 606a and 606b can be selectively electrically connected to electrical ground 310a and 310b via clear switches 308a and 308b. Adder capacitors 606a and 606b can be electrically connected to ADC 212 via electrical transmission bus 316. Adder switch 702 can be controlled by a MAC controller (e.g., processor 104 or MAC controller 124 in FIG. 1) to selectively connect adder capacitors 606a and 606b to each other.

[0094] The analog adder may receive the identity MAC output from identity MACs 206a, 206b, 206c, and 206d at adder capacitors 606a and 606b. Adder capacitors 606a and 606b may include a sampler capacitor 606a and an accumulator capacitor 606b. Sampler capacitor 606a may be optionally electrically connected to identity MACs 206a, 206b, 206c, and 206d. Accumulator capacitor 606b may be optionally electrically connected to sampler capacitor 606a. Adder capacitors 606a and 606b may have the same capacitance rating ("C"). In some embodiments, each adder capacitor 606a and 606b may be a single capacitor with a capacitance rating. In some embodiments, each adder capacitor 606a and 606b may be a plurality of capacitors electrically connected in series and / or parallel, which cumulatively have capacitance ratings. The capacitance ratings of adder capacitors 606a and 606b can be used as hardwired binary weights for the adder capacitors 606a and 606b to receive the unit MAC outputs from unit MACs 206a, 206b, 206c, and 206d.

[0095] When selectively electrically connected to unit MACs 206a, 206b, 206c, 206d via associated unit MAC switches 304a, 304b, 304c, 304d, the sampler capacitor 606a can receive and store unit MAC outputs from unit MACs 206a, 206b, 206c, 206d. Unit MAC switches 304a, 304b, 304c, 304d can be controlled to output unit MAC outputs from unit MACs 206a, 206b, 206c, 206d, such that the sampler capacitor 606a receives unit MAC outputs in a specific order. In some embodiments, this order can be from the multiplication and accumulation of the least significant bits of the "n"-bit start value and the "m"-bit weight value to the most significant bits of the "n"-bit start value and the "m"-bit weight value. For example, the identity element MAC switches 304a, 304b, 304c, and 304d can be controlled to sequentially close the circuit that electrically connects the identity elements MAC 206a, 206b, 206c, and 206d to the analog adder, thereby outputting the identity element MAC output to the analog adder. The identity element MAC output can be sequentially loaded into the sampler capacitor 606a by closing the circuit that electrically connects the identity elements MAC 206a, 206b, 206c, and 206d to the sampler capacitor 606a. In other words, the sampler capacitor 606a can receive the identity element MAC output from each of the identity elements MAC 206a, 206b, 206c, and 206d. In some embodiments, the unit MAC switches 304a, 304b, 304c, and 304d can be controlled to load the unit MAC outputs into the sampler capacitor 606a in an order of importance based on the multiplication and accumulation of "n" bit start values ​​and "m" bit weight values ​​that produce the unit MAC outputs. When selectively electrically connected to the unit MAC switches 206a, 206b, 206c, and 206d, the sampler capacitor 606a can be charged by receiving the unit MAC outputs. The sampler capacitor 606a can store samples of the unit MAC outputs, which may include combinations of received unit MAC outputs modified by sharing samples of the unit MAC outputs with the accumulator capacitor 606b. The sampling of the unit MAC outputs is referred to herein as unit MAC output sampling. The sampler capacitor 606a can store and output unit MAC output samples in response to receiving each unit MAC output.

[0096] When selectively electrically connected to sampler capacitor 606a via adder switch 702, accumulator capacitor 606b can receive and store unit cell MAC output samples from sampler capacitor 606a. When sampler capacitor 606a is selectively electrically disconnected from unit cells MAC 206a, 206b, 206c, 206d and selectively connected to accumulator capacitor 606b via adder switch 702, sampler capacitor 606a can discharge or output unit cell MAC output samples to accumulator capacitor 606b. Accumulator capacitor 606b can receive and store unit cell MAC output samples. For example, unit cell MAC switches 304a, 304b, 304c, 304d can be controlled to selectively electrically disconnect sampler capacitor 606a from unit cells MAC 206a, 206b, 206c, 206d. Adder switch 702 can be controlled to electrically connect sampler capacitor 606a to accumulator capacitor 606b via electrical transmission bus 316. Sampler capacitor 606a can sample the unit MAC output to accumulator capacitor 606b. After receiving the unit MAC output, the unit MAC output sampling can be shared by sampler capacitor 606a and accumulator capacitor 606b, as further described herein with reference to FIG8. The procedure of receiving each unit MAC output by sampler capacitor 606a, and of outputting unit MAC output samples by sampler capacitor 606a and receiving unit MAC output samples by accumulator capacitor 606b can continue for each multiplication and addition of all bits of the "n"-bit start value and "m"-bit weight value.

[0097] After the multiplication and addition of the bits of the "n"-bit start value and the "m"-bit weight value are completed, the sampler capacitor 606a can be reset or cleared. The clear switch 308a can be controlled to selectively connect the sampler capacitor 606a to the electrical ground 310a. The clear switch 308b and the adder switch 702 can be controlled to selectively disconnect the accumulator capacitor 606b from the electrical grounds 310a and 310b. Connecting the components of the multi-bit MAC 700 to the electrical ground 310a can discharge any residual voltage in the components, allowing the multi-bit MAC 700 to perform the next multiplication and addition of different combinations of the "n"-bit start value and / or the "m"-bit weight value.

[0098] When the identity MACs 206a, 206b, 206c, 206d and the sampler capacitor 606a are selectively electrically disconnected via adder switch 702 and selectively electrically connected to the ADC 212 via electrical transfer bus 316, the accumulator capacitor 606b can sample or discharge the identity MAC output. The output of the accumulator capacitor 606b is also referred to herein as the multi-bit MAC output. The identity MAC output sample can be output as an analog voltage to the electrical transfer bus 316 and the ADC 212. The analog voltage on the electrical transfer bus 316 can be converted into a digital signal by the ADC 212.

[0099] After the multiplication and addition of all bits of the "n"-bit start value and the "m"-bit weight value are completed, the multi-bit MAC 700 can be reset or cleared. Clear switches 308a and 308b can be controlled to selectively connect the analog adders (including adder capacitors 606a and 606b) to electrical grounds 310a and 310b. Connecting the components of the multi-bit MAC 700 to electrical grounds 310a and 310b can discharge any residual voltage in the multi-bit MAC 700, allowing the multi-bit MAC 700 to perform the next multiplication and addition of different combinations of the "n"-bit start value and / or the "m"-bit weight value.

[0100] FIG8 illustrates an example signal stream of an example multi-bit MAC using a sequential binary accumulator suitable for implementing various embodiments. Referring to FIG1-8, a signal timing diagram 800 for a multi-bit MAC using a sequential binary accumulator (e.g., multi-bit MAC 700 in FIG7) may include an accumulator clear switch control signal ("accumulator clear switch"), a sampler clear switch control signal ("sampler clear switch") and an adder switch control signal ("adder switch"), multiple identity MAC output signals (e.g., "identity MAC 1", "identity MAC 2", ..., "identity MAC b"), and sampler capacitor voltage measurement ("sampler capacitor voltage") and accumulator capacitor voltage measurement ("accumulator capacitor voltage"). The accumulator clear switch control signal, sampler clear switch control signal, and adder switch control signal can be control signals issued by a control device (not shown) for controlling the accumulator clear switch (e.g., clear switch 308b in FIG. 7), the sampler clear switch (e.g., clear switch 308a in FIG. 7), and the adder switch (e.g., adder switch 702 in FIG. 7). The identity MAC output signal can be the identity MAC output from the identity MAC (e.g., identity MACs 206a, 206b, 206c, 206d in FIG. 7). The sampler capacitor voltage measurement can be the voltage of the sampler capacitor (e.g., sampler capacitor 606a in FIG. 7), and the accumulator capacitor voltage measurement can be the voltage of the accumulator capacitor (e.g., accumulator capacitor 606b in FIG. 7). The example shown in FIG. 8 can be associated with the multi-bit MAC 700 described herein with reference to FIG. 7. However, the example shown in Figure 8 is not intended to limit the scope of the request or specification, as it is evident that similar control signals, unit MAC outputs, and capacitor voltage measurements can be achieved with reference to the various multi-bit MACs 200, 300, 400, 500, and 600 described herein with reference to Figures 2-6.

[0101] In signal timing diagram 800, at time T0, the accumulator clear switch control signal and the sampler clear switch control signal can be asserted by the control device. The accumulator clear switch control signal and the sampler clear switch control signal can be asserted to selectively electrically connect the sampler capacitor and the accumulator capacitor to electrical ground (e.g., electrical grounds 310a, 310b in Figure 7) via clear switches (such as sampler clear switches and accumulator clear switches). Since the sampler capacitor and the accumulator capacitor can be electrically connected to electrical ground, the sampler capacitor voltage measurement and the accumulator capacitor voltage measurement can exhibit little or no voltage. As described herein, the unit cell MAC switches (e.g., unit cell MAC switches 304a, 304b, 304c, 304d in Figure 7) can be controlled to selectively electrically disconnect the unit cell MAC from the sampler capacitor and the accumulator capacitor. Therefore, at time T0, the unit cell MAC output signal may not have any value. The adder switch control signal can be deasserted by the control device at time T0.

[0102] At time T1, the accumulator clear switch control signal and the sampler clear switch control signal can be deasserted by the control device, which can selectively disconnect the sampler capacitor and the accumulator capacitor from electrical ground via the clear switch. The first unit MAC can multiply the "n" bit start value with the least significant bit of the "m" bit weight value, accumulate the result of the multiplication, and output the first unit MAC output (e.g., unit MAC 1). The first unit MAC can be electrically connected to the sampler capacitor via the first unit MAC switch and output the unit MAC output to the sampler capacitor. The sampler capacitor can receive the first unit MAC output and exhibit the first sampler capacitor voltage measurement (Vmult1). The adder switch control signal can be deasserted by the control device at time T0, and the voltage can be separated between the sampler capacitor and the accumulator capacitor. Therefore, starting from time T0, the accumulator capacitor voltage measurement can be maintained at the previous voltage.

[0103] At time T2, the adder switch control signal can be asserted by the control device. In response, the adder switch can selectively electrically connect the sampler capacitor and the accumulator capacitor. The first sampler capacitor voltage measurement can be shared between the sampler capacitor and the accumulator capacitor. Each time the sampler capacitor and the accumulator capacitor share the sampler capacitor voltage measurement, the voltage of the sampler capacitor voltage measurement can be split in half at the sampler capacitor, and half of the voltage can be provided to the accumulator capacitor. Therefore, the first sampler capacitor voltage measurement can become (Vmult1) / 2, and the first accumulator capacitor voltage measurement (e.g., the first unit MAC output sample) can become (Vmult1) / 2.

[0104] At time T3, the control device can deassert the adder switch control signal and assert the sampler clear switch control signal. Deasserting the adder switch control signal can trigger the adder switch to selectively electrically disconnect the sampler capacitor and the accumulator capacitor. Asserting the sampler clear switch control signal can trigger the clear switch to selectively electrically connect the sampler capacitor to ground, which can reduce the first sampler capacitor voltage measurement to zero volts or near zero volts. The first accumulator capacitor voltage measurement can be maintained at (Vmult1) / 2.

[0105] At time T4, the control device can deassert the sampler clear switch control signal, and the second unit MAC can multiply the "n"-bit start value with the next most significant bit of the "m"-bit weight value, accumulate the result of the multiplication, and output the second unit MAC output (e.g., unit MAC 2). Deasserting the sampler clear switch control signal can trigger the clear switch to selectively electrically disconnect the sampler capacitor from electrical ground. The sampler capacitor can receive the second unit MAC output and exhibit the second sampler capacitor voltage measurement (Vmult2).

[0106] At time T5, the adder switch control signal can be asserted by the control device. In response, the adder switch can selectively electrically connect the sampler capacitor and the accumulator capacitor. The second sampler capacitor voltage measurement and the first accumulator capacitor voltage measurement can be shared between the sampler capacitor and the accumulator capacitor. Each time the sampler capacitor and the accumulator capacitor share the accumulator capacitor voltage measurement, the voltage of the accumulator capacitor voltage measurement can be split in half at the accumulator capacitor, and half of the voltage can be provided to the sampler capacitor. Therefore, the second sampler capacitor voltage measurement can become (Vmult1) / 4 + (Vmult2) / 2, and the second accumulator capacitor voltage measurement (e.g., second unit MAC output sampling) can become (Vmult1) / 4 + (Vmult2) / 2.

[0107] At time T6, the control device can deassert the adder switch control signal and assert the sampler clear switch control signal. Deasserting the adder switch control signal can trigger the adder switch to selectively electrically disconnect the sampler capacitor and the accumulator capacitor. Asserting the sampler clear switch control signal can trigger the clear switch to selectively electrically connect the sampler capacitor to ground, which can reduce the second sampler capacitor voltage measurement to zero volts or near zero volts. The second accumulator capacitor voltage measurement can be maintained at (Vmult1) / 4 + (Vmult2) / 2.

[0108] Within different periods, the adder switch control signal and the sampler clear switch control signal can repeat the pattern exhibited at times T1-T6, and various unit MACs can repeatedly multiply the "n"-bit start value with the next most significant bit of the "m"-bit weight value, accumulate the result of the multiplication, and output additional unit MAC outputs. The sampler capacitor voltage measurement and the accumulator capacitor voltage measurement can fluctuate accordingly.

[0109] At time Ts-2, the control device can deassert the adder switch control signal and assert the sampler clear switch control signal. Deasserting the adder switch control signal can trigger the adder switch to selectively electrically disconnect the sampler capacitor and the accumulator capacitor. Asserting the sampler clear switch control signal can trigger the clear switch to selectively electrically connect the sampler capacitor to ground, which can reduce the voltage measurement of the (b-1)th sampler capacitor to zero volts or near zero volts. The voltage measurement of the second accumulator capacitor can be maintained at (Vmult1) / 2b-1 + (Vmult2) / 2b-2 + … + (Vmultb-1) / 2.

[0110] At time Ts-1, the control device can deassert the sampler clear switch control signal, and the b-th unit MAC can multiply the "n"-bit start value with the most significant bit of the "m"-bit weight value, accumulate the result of the multiplication, and output the b-th unit MAC output (e.g., unit MAC b). Deasserting the sampler clear switch control signal can trigger the clear switch to selectively electrically disconnect the sampler capacitor from electrical ground. The sampler capacitor can receive the second unit MAC output and exhibit a second sampler capacitor voltage measurement (Vmultb).

[0111] At time Ts, the adder switch control signal can be asserted by the control device. In response, the adder switch can selectively electrically connect the sampler capacitor and the accumulator capacitor. The voltage measurement of the b-th sampler capacitor and the voltage measurement of the (b-1)-th accumulator capacitor can be shared between the sampler capacitor and the accumulator capacitor. The voltage measurement of the b-th sampler capacitor can become (Vmult1) / 2b + (Vmult2) / 2b-1 + … + (Vmultb-1) / 4 + (Vmultb) / 2, and the voltage measurement of the b-th accumulator capacitor (e.g., the second unit MAC output sampling) can become (Vmult1) / 2b + (Vmult2) / 2b-1 + … + (Vmultb-1) / 4 + (Vmultb) / 2.

[0112] Figure 9 illustrates an example of a unit-bit MAC output adder suitable for implementing various embodiments for multi-bit start values ​​and multi-bit weights. Referring to Figures 1-9, the multi-bit MAC 900 may include any number of analog adders. In some embodiments, the analog adders may include any number of adder switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, 910d, 912a, 912b, 912c, 912d and adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h. In some embodiments, the analog adders may also include any number of designated electrical grounds 508. The adder capacitors 904a, 904b, 904c, and 904d (referred to herein as sampler capacitors) of the analog adder can be selectively electrically connected to the unit cells MAC 206, 206a, 206b, 206c, and 206d via associated unit cell MAC switches 304a, 304b, 304c, and 304d. The adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h can be selectively electrically connected to each other via adder switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, and 910d. Adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h can be electrically connected between electrical transmission bus 316 and electrical ground 508. Adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h can be electrically connected to ADC 212 via electrical transmission bus 316 and adder switches 912a, 912b, 912c, and 912d. Adder switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, 910d, 912a, 912b, 912c, and 912d can be controlled by a MAC controller (e.g., processor 104 or MAC controller 124 in FIG. 1) to selectively electrically connect adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h to each other and to the ADC 212. Furthermore, some embodiments of the multi-bit MAC 900 may include any number and combination of clear switches and electrical grounds as shown in and described with reference to FIG. 10.

[0113] The analog adder can receive the identity MAC output from identity MACs 206, 206a, 206b, 206c, and 206d at sampler capacitors 904a, 904b, 904c, and 904d. Sampler capacitors 904a, 904b, 904c, and 904d can be selectively electrically connected to identity MACs 206, 206a, 206b, 206c, and 206d. Adder capacitors 906a, 906c, 906e, and 906g (referred to herein as the first accumulator capacitors) can be selectively electrically connected to sampler capacitors 904a, 904b, 904c, and 904d. Adder capacitors 906b, 906d, 906f, and 906h (referred to herein as second accumulator capacitors) may be selectively electrically connected to first accumulator capacitors 906a, 906c, 906e, and 906g. Sampler capacitors 904a, 904b, 904c, and 904d, as well as the pairs of first and second accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h, may cumulatively have the same capacitance rating (“C”). The capacitance rating of the second accumulator capacitors 906b, 906d, 906f, and 906h may be proportional to the importance of the bits multiplied by the “m” bit weight value of the “n” bit start-up value, or the bits multiplied by the “n” bit start-up value of the “m” bit weight value. For example, the capacitance rating of the second accumulator capacitors 906b, 906d, 906f, and 906h can be the lowest for the least significant bit and the highest for the most significant bit. As another example, the capacitance rating of the first accumulator capacitors 906a, 906c, 906e, and 906g can be the highest for the least significant bit and the lowest for the most significant bit. The paired accumulating capacitance of the first accumulator capacitors 906a, 906c, 906e, and 906g and the second accumulator capacitors 906b, 906d, 906f, and 906h can be equal to the capacitance of the sampler capacitors 904a, 904b, 904c, and 904d. In some embodiments, each adder capacitor 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h may be a single capacitor. In some embodiments, each adder capacitor 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h may be a plurality of capacitors electrically connected in series and / or in parallel.The capacitance ratings of adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h can be used as hardwired binary weights for analog adders to receive the identity MAC output from identity MACs 206, 206a, 206b, 206c, and 206d.

[0114] When the associated unit cell MAC switches 304a, 304b, 304c, and 304d are selectively electrically connected to the unit cell MACs 206, 206a, 206b, 206c, and 206d, the sampler capacitors 904a, 904b, 904c, and 904d can receive and store the unit cell MAC outputs from the unit cell MACs 206, 206a, 206b, 206c, and 206d. The unit cell MAC switches 304a, 304b, 304c, and 304d can be controlled to output the unit cell MAC outputs from the unit cell MACs 206, 206a, 206b, 206c, and 206d, so that the sampler capacitors 904a, 904b, 904c, and 904d receive the unit cell MAC outputs in a specific order. In some embodiments, the order can be from the least significant bits of the multiplication of the "n"-bit start value and the "m"-bit weight value to the most significant bits of the "n"-bit start value and the "m"-bit weight value. For example, identity MAC switches 304a, 304b, 304c, and 304d can be controlled to sequentially close the circuit electrically connecting identity MACs 206, 206a, 206b, 206c, and 206d to the analog adder to output the identity MAC output to the analog adder. The identity MAC output can be used to load the sampler capacitors 904a, 904b, 904c, and 904d sequentially using the sampler capacitors 904a, 904b, 904c, and 904d via closing the circuit electrically connecting the identity MACs 206, 206a, 206b, 206c, and 206d to the sampler capacitors 904a, 904b, 904c, and 904d. In other words, sampler capacitors 904a, 904b, 904c, and 904d can receive the identity MAC output for each multiplication and accumulation of bits from the "n"-bit start value and "m"-bit weight value of the identity MAC switches 206, 206a, 206b, 206c, and 206d. In some embodiments, the identity MAC switches 304a, 304b, 304c, and 304d can be controlled to load the identity MAC output into sampler capacitors 904a, 904b, 904c, and 904d in order of importance of the bits multiplied based on the "n"-bit start value and "m"-bit weight value to produce the identity MAC output. Sampler capacitors 904a, 904b, 904c, and 904d can be charged by receiving the unit cell MAC output when selectively electrically connected to unit cell MACs 206, 206a, 206b, 206c, and 206d.Sampler capacitors 904a, 904b, 904c, and 904d can store samples of the unit MAC output, which may include combinations of received unit MAC outputs modified by sharing samples of the unit MAC output with accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h. Samples of the unit MAC output are referred to herein as unit MAC output samples. Sampler capacitors 904a, 904b, 904c, and 904d can store and output unit MAC output samples in response to receiving each unit MAC output.

[0115] When the sampler capacitors 904a, 904b, 908c, 908d and / or the adder switches 910a, 910b, 910c, 910d are selectively electrically connected to the sampler capacitors 904a, 904b, 904c, 904d, the accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h can receive and store the unit MAC output samples from the sampler capacitors 904a, 904b, 904c, 904d. When sampler capacitors 904a, 904b, 904c, and 904d are selectively electrically disconnected from the unit cell MAC 206, 206a, 206b, 206c, and 206d and selectively connected to accumulator capacitors 906a, 906b, 906c, and 908d and / or adder switches 910a, 910b, 910c, and 910d, respectively, the sampler capacitors 904a, 904b, 904c, and 904d can sample and discharge the unit cell MAC output or output to the accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h. Accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h can receive and store unit cell MAC output samples. For example, unit cell MAC switches 304a, 304b, 304c, and 304d can be controlled to selectively electrically disconnect sampler capacitors 904a, 904b, 904c, and 904d from unit cell MACs 206, 206a, 206b, 206c, and 206d. Adder switches 908a, 908b, 908c, and 908d can be controlled to electrically connect sampler capacitors 904a, 904b, 904c, and 904d to accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h via electrical transmission bus 316. Adder switches 910a, 910b, 910c, and 910d can also be controlled to electrically connect sampler capacitors 904a, 904b, 904c, and 904d to second accumulator capacitors 906b, 906d, 906f, and 906h via electrical transmission bus 316. Sampler capacitors 904a, 904b, 904c, and 904d can sample the unit MAC output and output it to accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h.After receiving the identity MAC output sample, the identity MAC output sample can be shared by sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h, as further described herein with reference to Figure 8, wherein the pairs of accumulator capacitors 906a and 906b, 906c and 906d, 906e and 906f, 906g and 906h can be represented as a single accumulator capacitor. The program that receives each unit MAC output from sampler capacitors 904a, 904b, 904c, and 904d, and samples the unit MAC output from sampler capacitors 904a, 904b, 904c, and 904d, and samples the unit MAC output from accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h, can continue for each multiplication and addition of all bits of the "n"-bit start value and the "m"-bit weight value.

[0116] When the unit cell MAC 206, 206a, 206b, 206c, 206d, sampler capacitors 904a, 904b, 904c, 904d and first accumulator capacitors 906a, 906c, 906e, 906g are selectively disconnected from the unit cell MAC 206, 206a, 206b, 206c, 206d, and selectively connected to the ADC 212 via the adder switches 912a, 912b, 912c, 912d, the second accumulator capacitors 906b, 906d, 906f, 906h can sample or discharge the unit cell MAC output. Adder switches 910a, 910b, 910c, and 910d can be controlled to selectively electrically disconnect the second accumulator capacitors 906b, 906d, 906f, and 906h from the identity MACs 206, 206a, 206b, 206c, and 206d, the sampler capacitors 904a, 904b, 904c, and 904d, and the first accumulator capacitors 906a, 906c, 906e, and 906g. Adder switches 912a, 912b, 912c, and 912d can be controlled to selectively electrically connect the second accumulator capacitors 906b, 906d, 906f, and 906h to the ADC 212 via the electrical transmission bus 316. The identity MAC output sample can be output as a weighted analog voltage to the electrical transmission bus 316 and the ADC 212. The weight of each analog voltage can be based on the capacitance rating of the second accumulator capacitors 906b, 906d, 906f, and 906h of the output analog voltage. The combination of weighted analog voltages on the transmission bus 316 (also referred to herein as the multi-bit MAC output) can be an addition of weighted analog voltages to produce a weighted average analog voltage. Since the accumulator capacitors 906b, 906d, 906f, and 906h are electrically connected in parallel to the electrical transmission bus 316, this combination can produce a weighted average analog voltage. The weighted average analog voltage on the electrical transmission bus 316 can be converted into a digital signal by the ADC 212.

[0117] Figure 10 illustrates an example of a unit-byte MAC output adder suitable for implementing various embodiments for multi-bit start values ​​and multi-bit weights. Referring to Figures 1-10, the multi-bit MAC 1000 may include any number of analog adders. In some embodiments, the analog adders may include any number of adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d, and adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d. In some embodiments, the analog adders may also include an output switch 1008. In some embodiments, the analog adders may also include any number of designated electrical grounds 508. In some embodiments, the analog adder may also include any number and combination of clear switches 1010a, 1010b, 1010c, 1010d, 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, 1016d and electrical ground 1012. The adder capacitors 904a, 904b, 904c, 904d (referred to herein as sampler capacitors) of the analog adder may be selectively electrically connected to the unit cell MACs 206, 206a, 206b, 206c, 206d via associated unit cell MAC switches 304a, 304b, 304c, 304d. Adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d can be selectively electrically connected to each other via adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, and 1006d. Adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d can be electrically connected between electrical transmission bus 316 and electrical ground 508. Adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d can be selectively electrically connected to electrical ground 508 via clear switches 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, and 1016d. For example, pairs of adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d and clear switches 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, and 1016d can be connected in parallel to electrical ground 508. Adder capacitors 904d and 1002d can be electrically connected to ADC 212 via electrical transmission bus 316 and output switch 1008.Units MAC 206a, 206b, 206c, and 206d can be selectively electrically connected to electrical ground 1012 via clear switches 1010a, 1010b, 1010c, and 1010d. Adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, and 1006d can be controlled to selectively electrically connect adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d to each other. Output switch 1008 can be controlled by a MAC controller (e.g., processor 104 or MAC controller 124 in Figure 1) to selectively electrically connect adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d to ADC 212. The clear switches 1010a, 1010b, 1010c, 1010d, 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, and 1016d can also be controlled by the MAC controller.

[0118] The analog adder can receive the identity MAC output from identity MACs 206, 206a, 206b, 206c, and 206d at sampler capacitors 904a, 904b, 904c, and 904d. Sampler capacitors 904a, 904b, 904c, and 904d can be selectively electrically connected to identity MACs 206, 206a, 206b, 206c, and 206d. Adder capacitors 1002a, 1002b, 1002c, and 1002d (referred to herein as accumulator capacitors) can be selectively electrically connected to sampler capacitors 904a, 904b, 904c, and 904d. Sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d may have the same capacitance rating (“C”). In some embodiments, each adder capacitor 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d may be a single capacitor. In some embodiments, each adder capacitor 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d may be a plurality of capacitors electrically connected in series and / or in parallel. The capacitance ratings of adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d can be used as hardwired binary weights for analog adders to receive the identity MAC output from identity MACs 206, 206a, 206b, 206c, and 206d.

[0119] When the associated unit cell MAC switches 304a, 304b, 304c, and 304d are selectively electrically connected to the unit cell MACs 206, 206a, 206b, 206c, and 206d, the sampler capacitors 904a, 904b, 904c, and 904d can receive and store the unit cell MAC outputs from the unit cell MACs 206, 206a, 206b, 206c, and 206d. The unit cell MAC switches 304a, 304b, 304c, and 304d can be controlled to output the unit cell MAC outputs from the unit cell MACs 206, 206a, 206b, 206c, and 206d, so that the sampler capacitors 904a, 904b, 904c, and 904d receive the unit cell MAC outputs in a specific order. In some embodiments, the order can be from the least significant bits of the multiplication of the "n"-bit start value and the "m"-bit weight value to the most significant bits of the "n"-bit start value and the "m"-bit weight value. For example, identity MAC switches 304a, 304b, 304c, and 304d can be controlled to sequentially close the circuit that electrically connects identity MACs 206, 206a, 206b, 206c, and 206d to the analog adder to output the identity MAC output to the analog adder. The identity MAC output can be used to sequentially load sampler capacitors 904a, 904b, 904c, and 904d using the sampler capacitors 904a, 904b, 904c, and 904d by closing the circuit that electrically connects identity MACs 206, 206a, 206b, 206c, and 206d to the sampler capacitors 904a, 904b, 904c, and 904d. In other words, sampler capacitors 904a, 904b, 904c, and 904d can receive the identity MAC output for each multiplication and accumulation of bits from the "n"-bit start value and "m"-bit weight value from identity MACs 206, 206a, 206b, 206c, and 206d. In some embodiments, identity MAC switches 304a, 304b, 304c, and 304d can be controlled to load the identity MAC output into sampler capacitors 904a, 904b, 904c, and 904d in order of importance of the bits generated by multiplying the "n"-bit start value and "m"-bit weight value. Sampler capacitors 904a, 904b, 904c, and 904d can be charged by receiving the unit cell MAC output when selectively electrically connected to unit cell MACs 206, 206a, 206b, 206c, and 206d. Sampler capacitors 904a, 904b, 904c, and 904d can store samples of the unit cell MAC output, which may include combinations of received unit cell MAC outputs modified by sharing samples of the unit cell MAC output with accumulator capacitors 1002a, 1002b, 1002c, and 1002d.The sampling of the identity MAC output is referred to as identity MAC output sampling in this paper. Sampler capacitors 904a, 904b, 904c, and 904d can be used to store and output identity MAC output samples in response to each identity MAC output received.

[0120] When the sampler capacitors 904a, 904b, 904c, and 904d are selectively electrically connected via adder switches 1004a, 1004b, 1004c, and 1004d, the accumulator capacitors 1002a, 1002b, 1002c, and 1002d can receive and store the unit MAC output samples from the sampler capacitors 904a, 904b, 904c, and 904d. When sampler capacitors 904a, 904b, 904c, and 904d are selectively electrically disconnected from the identity element MAC 206, 206a, 206b, 206c, and 206d and selectively connected to accumulator capacitors 1002a, 1002b, 1002c, and 1002d via adder switches 1004a, 1004b, 1004c, and 1004d, sampler capacitors 904a, 904b, 904c, and 904d can sample and discharge the identity element MAC output or output to accumulator capacitors 1002a, 1002b, 1002c, and 1002d. Accumulator capacitors 1002a, 1002b, 1002c, and 1002d can receive and store identity element MAC output samples. For example, identity MAC switches 304a, 304b, 304c, and 304d can be controlled to selectively electrically disconnect sampler capacitors 904a, 904b, 904c, and 904d from identity MACs 206, 206a, 206b, 206c, and 206d. Adder switches 1004a, 1004b, 1004c, and 1004d can be controlled to electrically connect sampler capacitors 904a, 904b, 904c, and 904d to accumulator capacitors 1002a, 1002b, 1002c, and 1002d via electrical transmission bus 316. Sampler capacitors 904a, 904b, 904c, and 904d can sample the identity MAC output to accumulator capacitors 1002a, 1002b, 1002c, and 1002d. After receiving the identity MAC output sample, the identity MAC output sample can be shared by sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d, as further described herein with reference to Figure 8. The procedure of receiving each identity MAC output by sampler capacitors 904a, 904b, 904c, 904d and outputting identity MAC output samples by sampler capacitors 904a, 904b, 904c, 904d and receiving identity MAC output samples by accumulator capacitors 1002a, 1002b, 1002c, 1002d can continue for each multiplication and addition of all bits of the "n"-bit start value and the "m"-bit weight value.

[0121] In some embodiments, when the identity MAC 206a, 206b, 206c, 206d and sampler capacitors 904a, 904b, 904c, 904d are selectively electrically disconnected via adder switches 1004a, 1004b, 1004c, 1004d and selectively electrically connected to accumulator capacitors 1002a, 1002b, 1002c, 1002d via adder switches 1006a, 1006b, 1006c, 1006d and electrically connected to ADC 212 via output switch 1008, the accumulator capacitors 1002a, 1002b, 1002c, 1002d can sample or discharge the identity MAC output. Accumulator capacitors 1002a, 1002b, 1002c, and 1002d can be charged using sampling of the unit MAC output, and adder switches 1004a, 1004b, 1004c, and 1004d can be controlled to selectively electrically disconnect accumulator capacitors 1002a, 1002b, 1002c, and 1002d from sampler capacitors 904a, 904b, 904c, and 904d. For the least significant bit of the "m" bit weight value (such as the unit MAC output of unit MAC 206a), the analog adder can split the charge sampled from the unit MAC output of accumulator capacitor 1002a in half. For example, the analog adder can reset sampler capacitor 904a while controlling adder switch 1004a to selectively electrically disconnect accumulator capacitor 1002a from sampler capacitor 904a. The adder switch 1004a can be controlled to selectively electrically connect the accumulator capacitor 1002a and the reset sampler capacitor 904a, thereby separating the unit MAC output sampling of the accumulator capacitor 1002a from the sampler capacitor 904a. The adder switch 1004a can also be controlled to selectively electrically disconnect the accumulator capacitor 1002a from the sampler capacitor 904a.

[0122] Adder switches 1006a, 1006b, 1006c, and 1006d can be controlled to sequentially electrically connect accumulator capacitors 1002a, 1002b, 1002c, and 1002d from the least significant bit to the most significant bit. For example, adder switch 1006a can be controlled to selectively electrically connect accumulator capacitors 1002a and 1002b, while adder switch 1006b can be controlled to selectively electrically disconnect accumulator capacitors 1002a and 1002b from accumulator capacitors 1002c and 1002d. Accumulator capacitors 1002a and 1002b can share their unit MAC output sampling, which may include sharing half of the unit MAC output sampling of each accumulator capacitor 1002a and 1002b. For example, accumulator capacitors 1002a and 1002b can share one-quarter of the original unit MAC output sample of accumulator capacitor 1002a (because the unit MAC output sample was previously halved when split with sampler capacitor 904a) and half of the original unit MAC output sample of accumulator capacitor 1002b. The shared unit MAC output sample can be a new unit MAC output sample of accumulator capacitor 1002b. Sequentially, adder switch 1006b can be controlled to selectively electrically connect accumulator capacitors 1002b and 1002c, while adder switches 1006a and 1006c can be controlled to selectively electrically disconnect accumulator capacitors 1002b and 1002c from accumulator capacitors 1002a and 1002d. Accumulator capacitors 1002b and 1002c can share their unit MAC output sample. For example, accumulator capacitors 1002b and 1002c can share half of the new identity MAC output sample of accumulator capacitor 1002b, which can be one-eighth of the original identity MAC output sample of accumulator capacitor 1002a, one-quarter of the original identity MAC output sample of accumulator capacitor 1002b, and half of the original identity MAC output sample of accumulator capacitor 1002c. Similarly, adder switches 1006a, 1006b, 1006c, and 1006d can be sequentially controlled to selectively electrically connect and disconnect accumulator capacitors 1002a, 1002b, 1002c, and 1002d until all accumulator capacitors 1002a, 1002b, 1002c, and 1002d have shared their identity MAC output sample.

[0123] Output switch 1008 can be controlled to selectively connect accumulator capacitor 1006d to ADC 212 via electrical transmission bus 316. The unit MAC output sample on accumulator capacitor 1006d can be a weighted analog voltage of a combination of shared unit MAC output samples from all accumulator capacitors 1002a, 1002b, 1002c, and 1002d that can be output to electrical transmission bus 316 and ADC 212. The weighted average analog voltage on electrical transmission bus 316 can be converted into a digital signal by ADC 212.

[0124] In some embodiments, when the identity MAC switches 304a, 304b, 304c, 304d are selectively electrically disconnected from the identity MAC switches 206, 206a, 206b, 206c, 206d and selectively electrically connected to the sampler capacitors 904a, 904b, 904c, 904d and the accumulator capacitors 1002a, 1002b, 1002c, 1002d via the adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d, and electrically connected to the ADC via the output switch 1008, the ADC is further protected by the ADC protection mechanism. At 212, sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d can sample or discharge the unit cell MAC output. Adder switches 1004a, 1004b, 1004c, 1004d can be controlled to selectively electrically connect pairs of sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d, allowing these pairs to be charged using unit cell MAC output sampling. The identity MAC switches 304a, 304b, 304c, and 304d can be controlled to selectively electrically disconnect paired sampler capacitors 904a, 904b, 904c, and 904d and accumulator capacitors 1002a, 1002b, 1002c, and 1002d from identity MACs 206, 206a, 206b, 206c, and 206d. For the least significant bit of the "m" bit weight value (such as the identity MAC output of identity MAC 206a), the analog adder can split the charge sampled from the identity MAC output of paired sampler capacitors 904a and accumulator capacitor 1002a in half. For example, the analog adder can reset sampler capacitor 904a while controlling adder switch 1004a to selectively electrically disconnect accumulator capacitor 1002a from sampler capacitor 904a. The adder switch 1004a can be controlled to selectively electrically connect the accumulator capacitor 1002a and the reset sampler capacitor 904a, thereby separating the unit MAC output sampling of the accumulator capacitor 1002a from that of the sampler capacitor 904a. The adder switch 1004a can also be controlled to maintain the selective electrical connection of the paired sampler capacitor 904a and accumulator capacitor 1002a.

[0125] Adder switches 1006a, 1006b, 1006c, and 1006d can be controlled to sequentially electrically connect paired sampler capacitors 904a, 904b, 904c, and 904d and accumulator capacitors 1002a, 1002b, 1002c, and 1002d from the least significant bit to the most significant bit. For example, adder switch 1006a can be controlled to selectively electrically connect paired sampler capacitors 904a and accumulator capacitor 1002a, and paired sampler capacitors 904b and accumulator capacitor 1002b. When adder switch 1006a is controlled for selective electrical connection, adder switch 1006b can be controlled to selectively electrically disconnect paired sampler capacitors 904a, 904b and accumulator capacitors 1002a, 1002b from paired sampler capacitors 904c, 904d and accumulator capacitors 1002c, 1002d. Paired sampler capacitors 904a, 904b and accumulator capacitors 1002a, 1002b can share their unit MAC output sampling, which may include sharing half of the unit MAC output sampling of each of the paired sampler capacitors 904a, 904b and accumulator capacitors 1002a, 1002b. For example, pairs of sampler capacitors 904a, 904b and accumulator capacitors 1002a, 1002b can share one-quarter of the original unit MAC output sample of the pair of sampler capacitors 904a and accumulator capacitor 1002a (because the unit MAC output sample was previously halved when splitting between accumulator capacitor 1002a and sampler capacitor 904a) and half of the original unit MAC output sample of the pair of sampler capacitors 904b and accumulator capacitor 1002b. The shared unit MAC output sample can be a new unit MAC output sample of the pair of sampler capacitors 904b and accumulator capacitor 1002b. Sequentially, adder switch 1006b can be controlled to selectively electrically connect pairs of sampler capacitors 904b, 904c and accumulator capacitors 1002b, 1002c. When adder switch 1006b is controlled for selective electrical connection, adder switches 1006a and 1006c can be controlled to selectively electrically disconnect paired sampler capacitors 904b and 904c and accumulator capacitors 1002b and 1002c from paired sampler capacitors 904a and 904d and accumulator capacitors 1002a and 1002d. Paired sampler capacitors 904b and 904c and accumulator capacitors 1002b and 1002c can share their unit cell MAC output sampling.For example, the paired sampler capacitors 904b, 904c and accumulator capacitors 1002b, 1002c can share half of the new unit MAC output sample of the paired sampler capacitors 904b and accumulator capacitor 1002b, which can be one-eighth of the original unit MAC output sample of the paired sampler capacitors 904a and accumulator capacitor 1002a, one-quarter of the original unit MAC output sample of the paired sampler capacitors 904b and accumulator capacitor 1002b, and half of the original unit MAC output sample of the paired sampler capacitors 904c and accumulator capacitor 1002c. Similarly, adder switches 1006a, 1006b, 1006c, and 1006d can be sequentially controlled to selectively connect and disconnect paired sampler capacitors 904a, 904b, 904c, and 904d and accumulator capacitors 1002a, 1002b, 1002c, and 1002d until all paired sampler capacitors 904a, 904b, 904c, and 904d and accumulator capacitors 1002a, 1002b, 1002c, and 1002d have shared their unit MAC output sampling.

[0126] Output switch 1008 can be controlled to selectively electrically connect paired sampler capacitors 904d and accumulator capacitors 1002d to ADC 212 via electrical transmission bus 316. The unit MAC output sample on the paired sampler capacitors 904d and accumulator capacitors 1002d can be a weighted analog voltage, a combination of the unit MAC output samples shared by all paired sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d, which can be output to electrical transmission bus 316 and ADC 212. The weighted average analog voltage on electrical transmission bus 316 can be converted into a digital signal by ADC 212.

[0127] After completing the multiplication and addition of all bits of the "n" bit start value and the "m" bit weight value, the multi-bit MAC 1000 can be reset or cleared. The clear switches 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, and 1016d can be controlled by the MAC controller to selectively electrically connect the analog adders (including adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d) to electrical ground 508. The clear switches 1010a, 1010b, 1010c, and 1010d can be controlled by the MAC controller to selectively electrically connect the identity MACs 206a, 206b, 206c, and 206d to electrical ground 1012. Electrically connecting the components of the multi-bit MAC 1000 to ground 508, 1012 can discharge any residual voltage in the multi-bit MAC 1000, enabling the multi-bit MAC 1000 to perform the next multiplication and addition of different combinations of "n" bit start values ​​and / or "m" bit weight values.

[0128] FIG11 illustrates a method 1100 for controlling a multi-bit MAC according to one embodiment. Referring to FIG1-11, method 1100 may be implemented in a computing device (e.g., mobile computing device 100 in FIG1), in software executing in a processor (e.g., processor 104, MAC controller 124 in FIG1), in general-purpose hardware, in special-purpose hardware (e.g., multi-bit MACs 130, 200, 300, 400, 500, 600, 700, 900, 1000 in FIG1-7, 9 and 10), or in a combination of a software-configured processor and special-purpose hardware (such as a processor executing software within a multi-bit MAC control system (which includes other separate components (e.g., memory 106, 114 shown in FIG1)), and various memory / cache memory controllers). For the purpose of including alternative configurations enabled in the various embodiments, the hardware implementing method 1100 is referred to herein as a "MAC device".

[0129] In block 1102, the MAC device can receive sequential input of the start value bits. The sequential input of the start value bits can include bitwise input of the "n" bit start value from the least significant bit to the most significant bit.

[0130] In block 1104, the MAC device can perform multiplication and accumulation operations on each bit of the sequentially input and one bit of the weight value. The MAC device can multiply each bit of the "n"-bit start value by one bit of the "m"-bit weight value. The MAC device can sequentially multiply each bit of the "n"-bit start value by one bit of the "m"-bit weight value in order from the least significant bit to the most significant bit. In some embodiments, the MAC device can sequentially multiply each bit of the "n"-bit start value by all bits of the "m"-bit weight value. For example, the MAC device can multiply each bit of the "n"-bit start value by one bit of the "m"-bit weight value from the least significant bit to the most significant bit (before multiplying each bit of the "n"-bit start value by another bit of the "m"-bit weight value from the least significant bit to the most significant bit). In some embodiments, the MAC device can multiply each bit of the "n"-bit start value by all bits of the "m"-bit weight value in parallel. For example, the MAC device can concurrently multiply each bit of the "n"-bit start value by one bit of the "m"-bit weight value, from least significant to most significant bits, with another bit multiplied by the "m"-bit weight value from least significant to most significant bits. The MAC device can then sum the results of each multiplication.

[0131] In block 1106, the MAC device can control switches (e.g., identity MAC switches 304a, 304b, 304c, 304d in Figures 3-7, 9, and 10) to output multiplication and accumulation results, referred to herein as identity MAC outputs. In some embodiments, the identity MAC output may comprise, respectively, the result of multiplication and accumulation of each bit of the "n"-bit start value and one bit of the "m"-bit weight value. In some embodiments, the identity MAC output may cumulatively comprise the result of multiplication and accumulation of each bit of the "n"-bit start value and one bit of the "m"-bit weight value. The identity MAC output may be formatted as an analog voltage signal. The MAC device can control the switches to output the identity MAC output in various modes. For example, in some embodiments, the MAC device can control the switches to output each identity MAC output sequentially, such as in order of increasing the importance of the bits of the "n"-bit start value used in the multiplication and subsequently the bits of the "m"-bit weight value. For example, in some embodiments, the MAC device may control a switch to output each unit MAC output once. For example, in some embodiments, the MAC device may control a switch to output each unit MAC output 2q times, where "q" can be the position of the start value bit from the least significant bit with q=0 to the most significant bit with q=n-1. Similarly, for a multi-bit "m"-bit weight value, the MAC device may control a switch to output each unit MAC output 2r times, where "r" can be the position of the weight value bit from the least significant bit with r=0 to the most significant bit with r=m-1. In some embodiments, it may take 2q x 2r cycles to output all unit MAC outputs.

[0132] In block 1108, the MAC device can weight, sum, and / or store the unit cell MAC output. In some embodiments, the MAC device can weight, sum, and / or store the unit cell MAC output in different orders. For example, in some embodiments, the MAC device can weight the unit cell MAC output before summing and storing it. As another example, in some embodiments, the MAC device can sum and store the unit cell MAC output before weighting it. For example, in some embodiments, the MAC device can weight, sum, and store the unit cell MAC output concurrently. As another example, in some embodiments, the MAC device can repeatedly weight, sum, and / or store the unit cell MAC output in various combinations and orders. As another example, in some embodiments, the MAC device can repeatedly weight, sum, and store the unit cell MAC output in any order of different orders. In some embodiments, the analog adder of the MAC device (e.g., adder 128 in FIG1), (as described herein with reference to FIG3-7, 9 and 10), can perform weighted summation and / or storage of the identity MAC output in block 1108. In some embodiments, the MAC device can control various switches (e.g., adder switches 504a, 504b, 504c in FIG. 5, adder switches 604a, 604b in FIG. 6 and 7, adder switch 702 in FIG. 7, adder switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, 910d, 912a, 912b, 912c, 912d in FIG. 9, adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d in FIG. 10) to perform weighted summation and / or storage of the identity MAC output in block 1108. In some embodiments, the capacitors of the MAC device (e.g., integrator capacitor 314 in Figures 3 and 4, capacitors 402a, 402b, 402c, 402d specified in Figure 4, adder capacitors 506a, 506b, 506c in Figure 5, adder capacitors 606a, 606b in Figures 6 and 7, adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h in Figure 9, adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d in Figure 10) can be used to implement weighting, summing, and / or storing the identity MAC output in block 1108.

[0133] In block 1110, the MAC device may average the unit MAC outputs. In some embodiments, averaging the unit MAC outputs may be part of a weighted summation of the unit MAC outputs in block 1108. In some embodiments, averaging the unit MAC outputs may include combining multiple unit MAC outputs into the output of an ADC (e.g., ADC 212 in Figures 2-7, 9, and 10). In some embodiments, the analog adder of the MAC device (as described herein with reference to Figures 3-7, 9, and 10) may average the unit MAC outputs in block 1110. The MAC device can control various switches (e.g., adder switches 912a, 912b, 912c, 912d in Figure 9, and adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d in Figure 10) to combine multiple identity MAC outputs into the output of the ADC.

[0134] In block 1112, the MAC device can output an average unit MAC output, which is also referred to herein as a multi-bit MAC output. The MAC device can output an average unit MAC output to the ADC. In some embodiments, the analog adder of the MAC device (as described herein with reference to Figures 3-7, 9 and 10) can output an average unit MAC output in block 1112. In some embodiments, the MAC device can control various switches (e.g., adder switches 504a, 504b, 504c in Figure 5, adder switches 604a, 604b in Figures 6 and 7, adder switch 702 in Figure 7, adder switches 908a, 908b, 908c, 910a, 910b, 910c, 910d, 912a, 912b, 912c, 912d in Figure 9, and output switch 1008 in Figure 10) to output an average unit MAC output to the ADC.

[0135] In block 1114, the MAC device can clear the storage device of the MAC device. In some embodiments, the analog adder of the MAC device (as described herein with reference to Figures 3-7, 9 and 10) can clear the storage device of the MAC device in block 1114. In some embodiments, the MAC device can control various switches (e.g., clear switches 308, 308a, 308b in Figures 3-7, adder switches 504a, 504b, 504c in Figure 5, adder switches 604a, 604b in Figures 6 and 7, adder switch 702 in Figure 7, adder switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, 910d, 912a, 912b, 912c, 912d in Figure 9, adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d in Figure 10) to access the MAC device's storage device. (For example, integrator capacitor 314 in Figures 3 and 4, designated capacitors 402a, 402b, 402c, 402d in Figure 4, adder capacitors 506a, 506b, 506c in Figure 5, adder capacitors 606a, 606b in Figures 6 and 7, adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f in Figure 9, and adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d in Figure 10) are electrically connected to electrical ground (e.g., electrical ground 310, 310a, 310b in Figures 3-7). Electrically connecting the storage device of a MAC device to electrical ground can reduce the voltage of the memory to zero volts or near zero volts.

[0136] Various embodiments (including, but not limited to, the embodiments described above with reference to FIG1-11) can be implemented in a wide variety of computing systems including mobile computing devices. FIG12 illustrates an example of a mobile computing device suitable for use with the various embodiments. The mobile computing device 1200 may include a processor 1202 coupled to a touch screen controller 1204 and internal memory 1206. The processor 1202 may be one or more multi-core integrated circuits designated for general or specific processing tasks. The internal memory 1206 may be volatile or non-volatile memory, and may also be secure and / or encrypted memory, or insecure and / or unencrypted memory, or any combination thereof. Examples of memory types that can be utilized include, but are not limited to, DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touch screen controller 1204 and processor 1202 can also be coupled to the touch screen panel 1212, such as a resistive touch screen, a capacitive touch screen, an infrared touch screen, etc. Alternatively, the display of the mobile computing device 1200 does not need to have touch screen capability.

[0137] The mobile computing device 1200 may have one or more radio transceivers 1208 (e.g., Peanut, Bluetooth, Zigbee, Wi-Fi, RF radio) and antennas 1210 coupled to each other and / or coupled to the processor 1202 for transmitting and receiving communications. The transceivers 1208 and antennas 1210 may be used together with the circuitry mentioned above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 1200 may include a cellular wireless modem chip 1216, which enables communication via a cellular network and is coupled to the processor.

[0138] The mobile computing device 1200 may include a peripheral device connection interface 1218 coupled to the processor 1202. The peripheral device connection interface 1218 may be specifically configured to accept one type of connection, or may be configured to accept various types of physical and communication connections, public or private, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 1218 may also be coupled to a similarly configured peripheral device port (not shown).

[0139] The mobile computing device 1200 may also include a speaker 1214 for providing audio output. The mobile computing device 1200 may also include a housing 1220 constructed of a combination of plastic, metal, or other materials for housing all or some of the components described herein. The mobile computing device 1200 may include a power source 1222 coupled to the processor 1202, such as a disposable or rechargeable battery. The rechargeable battery may also be coupled to a peripheral device port to receive charging current from a source external to the mobile computing device 1200. The mobile computing device 1200 may also include a physical button 1224 for receiving user input. The mobile computing device 1200 may also include a power button 1226 for turning the mobile computing device 1200 on and off.

[0140] Various embodiments (including, but not limited to, those described above with reference to FIG1-11) can be implemented in a wide variety of computing systems, including laptop computer 1300, an example of which is illustrated in FIG13. Many laptop computers include a touchpad touch surface 1317 that acts as a pointing device for the computer, and thus can receive drag, scroll, and flick gestures similar to those implemented on computing devices equipped with touchscreen displays and described above. Laptop computer 1300 will typically include a processor 1311, which is coupled to volatile memory 1312 and a disk drive 1313 containing large-capacity non-volatile memory (such as flash memory). Additionally, computer 1300 may have one or more antennas 1308 for transmitting and receiving electromagnetic radiation that can be connected to a wireless data link and / or a cellular telephone transceiver 1316 coupled to the processor 1311. Computer 1300 may also include a floppy disk drive 1314 and a compressed optical disc (CD) drive 1315 coupled to processor 1311. In a notebook configuration, the computer casing includes a touchpad 1317, a keyboard 1318, and a display 1319, all of which are coupled to processor 1311. Other configurations of the computing device may include a computer mouse or trackball coupled to the processor (e.g., via USB input), and as is well known, they may also be used in combination with various embodiments.

[0141] Various embodiments (including, but not limited to, those described above with reference to Figures 1-11) can also be implemented in fixed computing systems (such as any of the various commercially available servers). An example server 1400 is illustrated in Figure 14. Such a server 1400 typically includes one or more multi-core processor assemblies 1401 coupled to volatile memory 1402 and mass non-volatile memory (such as a disk drive 1404). As shown in Figure 14, a server 1400 can be added by inserting the multi-core processor assembly 1401 into a rack of the assembly. The server 1400 may also include a floppy disk drive, CD-ROM drive, or DVD drive 1406 coupled to the processor 1401. Server 1400 may also include a network access port 1403 coupled to multi-core processor assembly 1401, which is used to establish a network interface connection with network 1405, such as a local area network, Internet, public switched telephone network and / or cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0142] In the following description, other embodiments are described for the purpose of understanding the present invention.

[0143] Example 1: A multi-bit multiplier-accumulator (MAC) includes: an analog adder having a first adder capacitor, wherein the first adder capacitor is configured to add a plurality of unit MAC outputs by: receiving the plurality of unit MAC outputs from the plurality of unit MAC outputs; and storing the plurality of unit MAC outputs; and wherein the analog adder is configured to output a multi-bit MAC output based on the addition of the stored plurality of unit MAC outputs.

[0144] Example 2: According to the multi-bit MAC of Example 1, wherein each of the plurality of unit MACs is configured to: sequentially multiply each bit of a first multi-bit value with different individual bits of a second multi-bit value, wherein the first multi-bit value and the second multi-bit value are represented by digital voltages; and accumulate the results of the multiplications to generate the plurality of unit MAC outputs, wherein the plurality of unit MAC outputs are analog voltages.

[0145] Example 3: The multi-bit MAC according to any one of Examples 1 or 2 also includes: a plurality of unit MAC switches, wherein a first unit MAC switch among the plurality of unit MAC switches is configured to selectively electrically connect the first unit MAC among the plurality of unit MACs and the first adder capacitor as controlled by a control device; and wherein: the first adder capacitor is configured such that receiving the plurality of unit MAC outputs from the plurality of unit MACs includes: receiving the first unit MAC output from the plurality of unit MAC outputs in response to the first unit MAC switch selectively electrically connecting the first unit MAC and the first adder capacitor; and the analog adder also includes an operational amplifier having an input terminal and an output terminal, wherein the first adder capacitor The device is electrically connected between the input terminal and the output terminal, and the operational amplifier is configured to: receive the plurality of unit MAC outputs at the input terminal; add the plurality of unit MAC outputs to generate a weighted average of the plurality of unit MAC outputs, wherein the analog adder is configured such that: adding the plurality of unit MAC outputs includes adding the plurality of unit MAC outputs to generate the weighted average of the plurality of unit MAC outputs, and storing the plurality of unit MAC outputs includes storing the weighted average of the plurality of unit MAC outputs; and output the weighted average of the plurality of unit MAC outputs as an analog voltage to an analog-to-digital converter, wherein the analog adder is configured such that outputting a multi-bit MAC output includes outputting the weighted average of the plurality of unit MAC outputs.

[0146] Example 4: A multi-bit MAC according to any one of Examples 1, 2 or 3, wherein the analog adder also includes: a plurality of designated capacitors, wherein a first designated capacitor of the plurality of designated capacitors is electrically connected between the first unit MAC switch and the first adder capacitor, and the first designated capacitor has a capacitor rating of 2r, wherein r is the position of a bit in the weighted value of a bit multiplied by the start value used when generating the first unit MAC output, and the first designated capacitor is configured to: receive the first unit MAC output; weight the first unit MAC output; and output the weighted first unit MAC output, wherein the operational amplifier is also configured such that: receiving the plurality of unit MAC outputs includes receiving the weighted first unit MAC output; and adding the plurality of unit MAC outputs includes adding the weighted first unit MAC output.

[0147] Example 5: The multi-bit MAC according to any one of Examples 1 or 2 also includes: a plurality of unit MAC switches, wherein a first unit MAC switch among the plurality of unit MAC switches is configured to selectively electrically connect the first unit MAC among the plurality of unit MACs and the first adder capacitor, as controlled by a control device; and wherein the analog adder also includes: a plurality of adder capacitors, including a first adder capacitor associated with the first unit MAC, wherein the first adder capacitor has a capacitor rating of 2r. Where r is the position of a bit in the weight value of a bit multiplied by the start value used when the first unit MAC output is generated by the first unit MAC, wherein the first adder capacitor is configured such that receiving the plurality of unit MAC outputs from the plurality of unit MACs includes selectively electrically connecting the first unit MAC and the first adder capacitor in response to the first unit MAC switch, receiving the first unit MAC output from the plurality of unit MAC outputs from the first unit MAC, and the first adder capacitor is also configured to: for the first unit The analog adder is configured to store the plurality of unit MAC outputs, including storing a weighted first unit MAC output; and outputting a weighted first unit MAC output; and a plurality of adder switches, including a first adder switch associated with a first adder capacitor, wherein the first adder switch is configured to selectively electrically connect the first adder capacitor to the first unit MAC via the first unit MAC switch controlled by the control device; and to connect the plurality of adders as controlled by the control device. The second adder switch in the switch selectively electrically connects the second adder capacitor of the plurality of adder capacitors to the electrical transmission bus concurrently, and selectively electrically connects the first adder capacitor to the electrical transmission bus, thereby outputting a weighted first unit MAC output from the first adder capacitor, and generating a weighted average of a plurality of weighted unit MAC outputs including the weighted first unit MAC output; and wherein the analog adder is configured such that the output multi-bit MAC output includes the output of the weighted average of the plurality of weighted unit MAC outputs.

[0148] Example 6: The multi-bit MAC according to Example 5 also includes: a buffer electrically connected between the plurality of unit MAC switches and the plurality of adder switches.

[0149] Example 7: A multi-bit MAC according to any one of Examples 1 or 2 also includes: a plurality of unit MAC switches, wherein a first unit MAC switch among the plurality of unit MAC switches is configured to selectively electrically connect the first unit MAC among the plurality of unit MAC switches and the first adder capacitor as controlled by a control device; and wherein: the first adder capacitor is configured such that receiving the plurality of unit MAC outputs from the plurality of unit MAC switches includes receiving the first unit MAC output among the plurality of unit MAC outputs in response to the first unit MAC switch selectively electrically connecting the first unit MAC and the first adder capacitor; the analog adder also includes: a plurality of adder switches, including a first adder switch among the plurality of adder switches associated with the first adder capacitor; and a second adder capacitor, wherein the second adder capacitor is associated with the first adder capacitor among the plurality of adder switches. Two adder switches are associated, the first adder capacitor and the second adder capacitor have the same capacitance rating, and wherein: the first adder switch is configured to: selectively electrically connect the first adder capacitor to the plurality of unit MAC switches controlled by the control device; and selectively electrically connect the first adder capacitor to an electrical transmission bus as controlled by the control device; the second adder switch is configured to: selectively electrically connect the second adder capacitor to the electrical transmission bus concurrently with the first adder capacitor as controlled by the control device, thereby sharing the plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor; and selectively electrically connect the second adder capacitor to an analog-to-digital converter to output the shared plurality of unit MAC outputs; and the analog adder is configured such that outputting a multi-bit MAC output includes outputting the shared plurality of unit MAC outputs.

[0150] Example 8: According to the multi-bit MAC of Example 7, wherein the analog adder also includes: a buffer electrically connected between the plurality of unit MAC switches and the plurality of adder switches.

[0151] Example 9: A multi-bit MAC according to any one of Examples 1 or 2 also includes: a plurality of unit MAC switches, wherein a first unit MAC switch among the plurality of unit MAC switches is configured to selectively electrically connect the first unit MAC and the first adder capacitor, as controlled by a control device; and wherein: the first adder capacitor is configured such that receiving the plurality of unit MAC outputs from the plurality of unit MACs includes receiving the plurality of unit MAC outputs from the first unit MAC in response to the first unit MAC switch selectively electrically connecting the first unit MAC and the first adder capacitor. The analog adder also includes: a first unit MAC output; the analog adder also includes: a second adder capacitor, wherein the first adder capacitor and the second adder capacitor have the same capacitance rating; and an adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, thereby sharing the plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor, wherein the second adder capacitor is configured to output the shared plurality of unit MAC outputs to the analog-to-digital converter, and wherein the analog adder is configured such that outputting a multi-bit MAC output includes outputting the shared plurality of unit MAC outputs.

[0152] Further examples include methods for performing the operations of device functions outlined in Examples 1, 2, 3, 4, 5, 6, 7, 8, or 9. Further examples include a multi-bit MAC having units for performing any of the device functions outlined in Examples 1, 2, 3, 4, 5, 6, 7, 8, or 9.

[0153] Example 10: A multi-bit multiplier-accumulator (MAC) including an analog adder having: a plurality of adder capacitors, including a first adder capacitor; and a plurality of unit MAC switches, including a first unit MAC switch configured to selectively electrically connect a first unit MAC among the plurality of unit MACs and the first adder capacitor as controlled by a control device; wherein the first adder capacitor is configured to add the outputs of the plurality of unit MACs by: receiving the first plurality of unit MAC outputs from the first unit MAC in response to the selective electrical connection of the first unit MAC and the first adder capacitor by the first unit MAC switch; and storing the first plurality of unit MAC outputs, and wherein the analog adder is configured to output a multi-bit MAC output based on the addition of the stored first plurality of unit MAC outputs.

[0154] Example 11: According to the multi-bit MAC of Example 10, wherein: the plurality of adder capacitors also include a second adder capacitor and a third adder capacitor, wherein the cumulative capacitance rating of the paired second adder capacitors and the third adder capacitors is the same as the capacitance rating of the first adder capacitor; and the analog adder also includes a plurality of adder switches, including: a first adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, thereby sharing the first plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor; a second adder switch configured to selectively electrically connect the second adder capacitor and the third adder capacitor as controlled by the control device, thereby sharing the first plurality of unit MAC outputs between the second adder capacitor and the third adder capacitor, wherein the A third adder capacitor is configured to weight the shared first plurality of unit MAC outputs; and a third adder switch is configured to selectively connect the third adder capacitor to the analog-to-digital converter via an electrical transmission bus, as controlled by the control device, thereby outputting a weighted shared first plurality of unit MAC outputs to the analog-to-digital converter concurrently with another third adder capacitor of the plurality of adder capacitors outputting a weighted shared second plurality of unit MAC outputs to the analog-to-digital converter via the electrical transmission bus, thereby combining the weighted shared first plurality of unit MAC outputs and the weighted shared second plurality of unit MAC outputs to form a weighted average of the shared plurality of unit MAC outputs; and the analog adder is configured such that the output multi-bit MAC output includes the output of the weighted average of the shared plurality of unit MAC outputs.

[0155] Example 12: According to the multi-bit MAC of Example 10, wherein: the plurality of adder capacitors also includes a second adder capacitor; and the analog adder also includes a plurality of adder switches, including: a first adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, thereby sharing the first plurality of unit MAC output between the first adder capacitor and the second adder capacitor; and a second adder switch configured to selectively electrically connect the second adder capacitor to another second adder capacitor via an electrical transmission bus as controlled by the control device.

[0156] Example 13: A multi-bit MAC according to Example 12, wherein: the first adder switch is configured such that, as controlled by the control device, the first adder capacitor and the second adder capacitor are selectively electrically connected, thereby sharing the first plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor, including dividing the first plurality of unit MAC outputs in half for each of the first adder capacitor and the second adder capacitor; the analog adder is also configured to clear the first plurality of unit MACs. The first adder capacitor is half of the AC output; and the first adder switch is also configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, so that the first plurality of units MAC output is shared between the first adder capacitor and the second adder capacitor, thereby dividing the first plurality of units MAC output in half for each of the first adder capacitor and the second adder capacitor, thereby producing a plurality of quarters of the first plurality of units MAC.

[0157] Example 14: A multi-bit MAC according to any one of Examples 12 or 13, wherein the plurality of adder switches also includes another first adder switch, wherein the other first adder switch is configured to selectively electrically connect another first adder capacitor and the other second adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor and the other second adder capacitor.

[0158] Example 15: A multi-bit MAC according to any one of Examples 12 or 13, wherein the plurality of adder switches also includes another first adder switch, wherein the other first adder switch is configured to selectively electrically disconnect the other first adder capacitor and the other second adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor and the other second adder capacitor.

[0159] Further examples include methods for performing the device functions outlined in examples 10, 11, 12, 13, 14, or 15. Further examples include a multi-bit MAC having units for performing the functions of any device outlined in any example.

[0160] Computer program code or "program code" for execution on a programmable processor to implement the operations of the various embodiments may be written in a high-level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or various other programming languages. As used in this case, program code or program stored on a computer-readable storage medium may refer to code in a format that is understandable to the processor (such as object code).

[0161] The foregoing method description and program flow diagram are provided as illustrative examples only and are not intended to require or imply that the operations of the various embodiments must be performed in the provided order. As will be understood by those skilled in the art to which this invention pertains, the order of operations in the foregoing embodiments may be performed in any order. Words such as "then," "following," "next," etc., are not intended to limit the order of operations; these words are only used to guide the reader in reading the description of the method. Furthermore, any reference to singular request elements, such as the use of the articles "a," "an," or "the," should not be interpreted as limiting the element to the singular.

[0162] The various illustrative logic blocks, modules, circuits, and algorithmic operations described in conjunction with the various embodiments can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, they have been generally described above in terms of the functionality of the various illustrative components, blocks, modules, circuits, and operations. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art to which this invention pertains can implement the described functionality in alternative ways for each specific application; however, such implementation decisions should not be interpreted as deviating from the scope of the claim.

[0163] Hardware for implementing the various illustrative logic, logic blocks, modules, and circuits described herein can be implemented or performed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, individual gate or transistor logic, individual hardware component, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any general processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by a circuit system specific to a given function.

[0164] In one or more embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, such functionality may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operation of the methods or algorithms disclosed herein may be embodied in a processor-executable software module, which may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium accessible by a computer or processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessible by a computer. As used herein, magnetic disks and optical disks include CDs, laser discs, optical discs, DVDs, floppy disks, and Blu-ray discs, where magnetic disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of the above also fall within the scope of non-transitory computer-readable and processor-readable media. Furthermore, the operation of a method or algorithm may reside as code and / or instructions, or any combination or set thereof, on non-transitory processor-readable and / or computer-readable media, which may be incorporated into a computer program product.

[0165] The above description of the disclosed embodiments is provided to enable any person skilled in the art to implement or use the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the overall principles defined herein can be applied to other embodiments and implementations without departing from the scope of the various embodiments. Therefore, this application is not intended to be limited to the embodiments and implementations described herein, but is accorded the widest scope consistent with the appended claims and the principles and novel features disclosed herein. [Simplified Explanation of the Diagram]

[0019] The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate example examples of various embodiments and, together with the overall description provided above and the detailed description provided below, serve to interpret the features of the claim item.

[0020] Figure 1 is a block diagram of components of an instance computing device suitable for implementing various embodiments.

[0021] FIG2 is a component block diagram illustrating an example memory device suitable for implementing various embodiments, the memory device being configured to implement a multi-bit multiplier-accumulator ("MAC") using in-memory computing (CIM) and / or near-memory computing (NMC) arrays.

[0022] Figure 3 is a circuit diagram showing an example multi-bit MAC using active integrator-based hot weights suitable for implementing various embodiments.

[0023] Figure 4 is a circuit block diagram showing an example multi-bit MAC using hardwired binary weights based on an active integrator suitable for implementing various embodiments.

[0024] Figure 5 is a circuit block diagram showing an example multi-bit MAC using a binary capacitive digital-to-analog converter (DAC) as a load, suitable for implementing various embodiments.

[0025] Figure 6 is a circuit diagram showing an example multi-bit MAC suitable for implementing various embodiments using a sequential binary accumulator as a load.

[0026] Figure 7 is a circuit diagram showing an example multi-bit MAC suitable for implementing various embodiments using a sequential binary accumulator as a load.

[0027] Figure 8 is a timing diagram showing the signal stream of an example multi-bit MAC using a sequential binary accumulator as a load, suitable for implementing various embodiments.

[0028] Figure 9 is a circuit diagram showing an example unit MAC output adder suitable for implementing various embodiments for multi-bit start values ​​and multi-bit weight values.

[0029] Figure 10 is a circuit diagram showing an example unit MAC output adder for multi-bit start values ​​and multi-bit weight values ​​suitable for implementing various embodiments.

[0030] Figure 11 is a flowchart illustrating a method for controlling a multi-bit MAC according to one embodiment.

[0031] Figure 12 is a block diagram of components of an instance action computing device suitable for use with various states.

[0032] Figure 13 is a block diagram of components of an instance action computing device suitable for use with various states.

[0033] Figure 14 is a block diagram of components suitable for use with various types of instance servers. [Biomaterial Storage]

[0167] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A multi-bit multiplier-accumulator (MAC), comprising: An analog adder having a first adder capacitor, wherein the first adder capacitor is configured to add a plurality of unit MAC outputs by: receiving the plurality of unit MAC outputs from the plurality of unit MAC outputs; and storing the plurality of unit MAC outputs; wherein the analog adder is configured to output a multi-bit MAC output based on the sum of the stored plurality of unit MAC outputs; and wherein each of the plurality of unit MACs is configured to: sequentially multiply each bit of a first multi-bit value with a different single bit of a second multi-bit value, wherein the first multi-bit value and the second multi-bit value are represented by digital voltages; and accumulate the results of the multiplications to produce the plurality of unit MAC outputs, wherein the plurality of unit MAC outputs are an analog voltage.

2. According to the multi-bit MAC of request item 1, it also includes: A plurality of unit cell MAC switches, wherein a first unit cell MAC switch of the plurality of unit cell MAC switches is configured to selectively electrically connect the first unit cell MAC and the first adder capacitor, as controlled by a control device; In which: the first adder capacitor is configured to receive the plurality of unit MAC outputs from a plurality of unit MACs including: selectively electrically connecting the first unit MAC and the first adder capacitor in response to the first unit MAC switch, and receiving a first unit MAC output from the plurality of unit MAC outputs; and the analog adder also includes an operational amplifier having an input and an output, wherein the first adder capacitor is electrically connected between the input and the output, and the operational amplifier is configured to: receive the plurality of unit MAC outputs at the input; and add the plurality of unit MAC outputs to produce a weighted average of the plurality of unit MAC outputs, wherein the analog adder is configured such that: Adding a plurality of unit MAC outputs includes adding the plurality of unit MAC outputs to generate the weighted average of the plurality of unit MAC outputs, and storing the plurality of unit MAC outputs includes storing the weighted average of the plurality of unit MAC outputs; and outputting the weighted average of the plurality of unit MAC outputs as an analog voltage to an analog-to-digital converter, wherein the analog adder is configured to output a multi-bit MAC output including outputting the weighted average of the plurality of unit MAC outputs.

3. According to the multi-bit MAC of request item 2, wherein the analog adder also includes: A plurality of designated capacitors, wherein a first designated capacitor of the plurality of designated capacitors is electrically connected between the first unit MAC switch and the first adder capacitor, and the first designated capacitor has a capacitor rating of 2r, where r is a bit in a weighted value used when generating the first unit MAC output by multiplying a start value, and the first designated capacitor is configured to: receive the first unit MAC output; weight the first unit MAC output; and output the weighted first unit MAC output, wherein the operational amplifier is also configured such that: receiving the plurality of unit MAC outputs includes receiving the weighted first unit MAC output; and adding the plurality of unit MAC outputs includes adding the weighted first unit MAC output.

4. The multi-bit MAC according to request item 1 also includes: A plurality of unit cell MAC switches, wherein a first unit cell MAC switch among the plurality of unit cell MAC switches is configured to selectively electrically connect the first unit cell MAC switch among the plurality of unit cell MAC switches and the first adder capacitor, as controlled by a control device; The analog adder also includes: a plurality of adder capacitors, including a first adder capacitor associated with the first unit MAC, wherein the first adder capacitor has a capacitor rating of 2r, where r is a bit in a weighted value used when the first unit MAC output is generated by the first unit MAC, multiplied by a start value; wherein the first adder capacitor is configured such that receiving the plurality of unit MAC outputs from the plurality of unit MACs includes selectively electrically connecting the first unit MAC and the first adder capacitor in response to a first unit MAC switch, receiving one of the plurality of unit MAC outputs from the first unit MAC, and the first adder capacitor is also configured to: The first unit MAC output is weighted, wherein the analog adder is configured such that storing the plurality of unit MAC outputs includes storing the weighted first unit MAC output; and outputting the weighted first unit MAC output; and a plurality of adder switches, each including a first adder switch associated with the first adder capacitor, and wherein the first adder switch is configured to: The first adder capacitor is selectively electrically connected to the first unit MAC via the first unit MAC switch controlled by the control device; and the first adder capacitor is selectively electrically connected to the electrical transmission bus concurrently with a second adder switch of the plurality of adder switches controlled by the control device, thereby outputting a weighted first unit MAC output from the first adder capacitor and generating a weighted average of the plurality of weighted unit MAC outputs including the weighted first unit MAC output; and wherein the analog adder is configured to output a multi-bit MAC output including the weighted average of the plurality of weighted unit MAC outputs.

5. The multi-bit MAC according to request item 4 also includes: A buffer is electrically connected between the plurality of unit MAC switches and the plurality of adder switches.

6. The multi-bit MAC according to request item 1 also includes: A plurality of unit cell MAC switches, wherein a first unit cell MAC switch of the plurality of unit cell MAC switches is configured to selectively electrically connect the first unit cell MAC and the first adder capacitor, as controlled by a control device; And wherein: the first adder capacitor is configured such that receiving the plurality of unit cell MAC outputs from the plurality of unit cell MACs includes selectively electrically connecting the first unit cell MAC and the first adder capacitor in response to the first unit cell MAC switch, and receiving a first unit cell MAC output from the plurality of unit cell MAC outputs; the analog adder also includes: a plurality of adder switches, including a first adder switch among the plurality of adder switches associated with the first adder capacitor; and a second adder capacitor, wherein the second adder capacitor is associated with a second adder switch among the plurality of adder switches, the first adder capacitor and the second adder capacitor having the same capacitance rating, and wherein: the first adder switch is configured to: The first adder capacitor is selectively electrically connected to the plurality of unit MAC switches controlled by the control device; and the first adder capacitor is selectively electrically connected to an electrical transmission bus as controlled by the control device; the second adder switch is configured to: selectively electrically connect the second adder capacitor to the electrical transmission bus concurrently with the first adder capacitor as controlled by the control device, thereby sharing the plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor; and the second adder capacitor is selectively electrically connected to an analog-to-digital converter to output the shared plurality of unit MAC outputs; and the analog adder is configured to output a multi-bit MAC output including the shared plurality of unit MAC outputs.

7. According to the multi-bit MAC of request item 6, wherein the analog adder also includes: A buffer is electrically connected between the plurality of unit MAC switches and the plurality of adder switches.

8. The multi-bit MAC according to request item 1 also includes: A plurality of unit cell MAC switches, wherein a first unit cell MAC switch of the plurality of unit cell MAC switches is configured to selectively electrically connect the first unit cell MAC and the first adder capacitor, as controlled by a control device; and wherein: the first adder capacitor is configured such that receiving the plurality of unit cell MAC outputs from the plurality of unit cell MACs includes receiving a first unit cell MAC output from the plurality of unit cell MAC outputs in response to the first unit cell MAC switch selectively connecting the first unit cell MAC and the first adder capacitor; the analog adder also includes: a second adder capacitor, wherein the first adder capacitor and the second adder capacitor have the same capacitance rating; and an adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor, as controlled by the control device, thereby sharing the plurality of unit cell MAC outputs between the first adder capacitor and the second adder capacitor. The second adder capacitor is configured to output a shared plurality of unit MAC outputs to an analog-to-digital converter, wherein the analog adder is configured to output a multi-bit MAC output including the shared plurality of unit MAC outputs.

9. A method for multi-bit multiplication and accumulation, comprising the following steps: adding a plurality of unit multiplier-accumulator (MAC) outputs via a first adder capacitor of an analog adder by: receiving a plurality of unit MAC outputs from a plurality of unit MACs; and storing the plurality of unit MAC outputs; outputting a multi-bit MAC output by the analog adder based on the sum of the stored plurality of unit MAC outputs; sequentially multiplying each bit of a first multi-bit value with a different single bit of a second multi-bit value, wherein the first multi-bit value and the second multi-bit value are represented by digital voltages; and accumulating the results of the multiplications to produce the plurality of unit MAC outputs, wherein the plurality of unit MAC outputs are analog voltages.

10. The method according to claim 9 also includes the following steps: selectively electrically connecting a first unit MAC of the plurality of unit MACs to the first adder capacitor via a first unit MAC switch, wherein receiving the output of the plurality of unit MACs from the plurality of unit MACs includes: In response to selectively electrically connecting the first unit MAC and the first adder capacitor, receiving a first unit MAC output from the first unit MAC; receiving the plurality of unit MAC outputs at an input of an operational amplifier of the analog adder; adding the plurality of unit MAC outputs to generate a weighted average of the plurality of unit MAC outputs, wherein: adding the plurality of unit MAC outputs includes adding the plurality of unit MAC outputs to generate the weighted average of the plurality of unit MAC outputs, and storing the plurality of unit MAC outputs includes storing the weighted average of the plurality of unit MAC outputs; and outputting the weighted average of the plurality of unit MAC outputs as an analog voltage to an analog-to-digital converter, wherein outputting a multi-bit MAC output includes outputting the weighted average of the plurality of unit MAC outputs.

11. The method according to claim 10 also includes the following steps: receiving the first unit MAC output via a first designated capacitor of the analog adder, wherein the first designated capacitor has a capacitor rating of 2r, where r is a position in a weighted value of a bit multiplied by a start value used when generating the first unit MAC output; weighting the first unit MAC output via the first designated capacitor; and outputting the weighted first unit MAC output via the first designated capacitor, wherein: Receiving the plurality of unit MAC outputs includes receiving a weighted first unit MAC output; and adding the plurality of unit MAC outputs includes adding the weighted first unit MAC outputs.

12. The method according to claim 9 also includes the following steps: selectively electrically connecting a first unit MAC of a plurality of unit MACs to the first adder capacitor via a first unit MAC switch, wherein receiving the outputs of the plurality of unit MACs from the plurality of unit MACs includes receiving a first unit MAC output from the plurality of unit MAC outputs in response to selectively electrically connecting the first unit MAC and the first adder capacitor; selectively electrically connecting a first adder capacitor to the first unit MAC via the first adder switch; weighting the outputs of the first unit MAC via the first adder capacitor, wherein: The first adder capacitor has a capacitor rating of 2r, where r is a bit in a weighted value used when the first unit MAC output is generated by the first unit MAC, multiplied by a start value, and stores the plurality of unit MAC outputs, including storing weighted first unit MAC outputs; outputs weighted first unit MAC outputs via the first adder capacitor; and selectively connects a second adder capacitor to an electrical transmission bus concurrently with a second adder switch, selectively connecting the first adder capacitor to the electrical transmission bus, thereby outputting weighted first unit MAC outputs to the electrical transmission bus via the first adder capacitor, and generating a weighted average of the plurality of weighted unit MAC outputs including the weighted first unit MAC outputs, wherein outputting a multi-bit MAC output includes outputting the weighted average of the plurality of weighted unit MAC outputs.

13. The method according to claim 12 also includes: A buffer is electrically connected between the first unit MAC switch and the first adder switch.

14. The method according to claim 9 also includes the following steps: selectively electrically connecting a first unit MAC of the plurality of unit MACs and the first adder capacitor via a first unit MAC switch, wherein receiving the output of the plurality of unit MACs from the plurality of unit MACs includes receiving a first unit MAC output from the plurality of unit MAC outputs in response to selectively electrically connecting the first unit MAC and the first adder capacitor; selectively electrically connecting the first adder capacitor to the plurality of unit MACs via a first adder switch of the analog adder via a plurality of unit MAC switches including the first unit MAC switch; selectively electrically connecting the first adder capacitor to an electrical transmission bus via the first adder switch; A second adder capacitor is selectively electrically connected to the electrical transmission bus concurrently with the first adder capacitor via a second adder switch, thereby sharing the plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor, wherein the first adder capacitor and the second adder capacitor have the same capacitance rating; and the second adder capacitor is selectively electrically connected to an analog-to-digital converter, thereby outputting the shared plurality of unit MAC outputs, wherein outputting a multi-bit MAC output includes outputting the shared plurality of unit MAC outputs.

15. The method according to claim 14 also includes the step of: electrically connecting a buffer between the plurality of unit MAC switches and the first adder switch.

16. The method according to claim 9 also includes the following steps: selectively electrically connecting a first unit MAC of the plurality of unit MACs to the first adder capacitor via a first unit MAC switch, wherein receiving the plurality of unit MAC outputs from the plurality of unit MACs includes responding to selectively electrically connecting the first unit MAC and the first adder capacitor, and receiving a first unit MAC output from the plurality of unit MAC outputs from the first unit MAC; selectively electrically connecting the first adder capacitor and a second adder capacitor via an adder switch, thereby sharing the plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor, wherein the first adder capacitor and the second adder capacitor have the same capacitance rating; and outputting the shared plurality of unit MAC outputs from the second adder capacitor to an analog-to-digital converter, wherein outputting a multi-bit MAC output includes outputting the shared plurality of unit MAC outputs.

17. A multi-bit multiplier-accumulator (MAC) comprising an analog adder having: a plurality of adder capacitors, including a first adder capacitor; and a plurality of unit MAC switches, including a first unit MAC switch configured to selectively electrically connect a first unit MAC among the plurality of unit MACs and the first adder capacitor, as controlled by a control device; wherein the first adder capacitor is configured to add the first plurality of unit MAC outputs by: receiving the first plurality of unit MAC outputs from the first unit MAC in response to the selective electrical connection of the first unit MAC and the first adder capacitor by the first unit MAC switch; and storing the first plurality of unit MAC outputs; and wherein the analog adder is configured to output a multi-bit MAC output based on the addition of the stored first plurality of unit MAC outputs.

18. Based on the multi-bit MAC of request item 17, where: The plurality of adder capacitors also includes a second adder capacitor and a third adder capacitor, wherein the sum of the capacitance ratings of the pair of second adder capacitors and third adder capacitors is the same as the capacitance rating of the first adder capacitor; and the analog adder also includes a plurality of adder switches, including: a first adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, thereby sharing the first plurality of unit cell MAC outputs between the first adder capacitor and the second adder capacitor; A second adder switch configured to selectively electrically connect the second adder capacitor and the third adder capacitor as controlled by the control device, thereby sharing a shared first plurality of unit cell MAC outputs between the second adder capacitor and the third adder capacitor, wherein the third adder capacitor is configured to weight the shared first plurality of unit cell MAC outputs; and a third adder switch configured to selectively electrically connect the third adder capacitor to an analog-to-digital converter via an electrical transmission bus as controlled by the control device, thereby connecting it to another of the plurality of adder capacitors. A third adder capacitor outputs a weighted, shared second plurality of unit MAC outputs to the analog-to-digital converter via the electrical transmission bus, and concurrently outputs a weighted, shared first plurality of unit MAC outputs to the analog-to-digital converter, thereby combining the weighted, shared first plurality of unit MAC outputs and the weighted, shared second plurality of unit MAC outputs into a weighted average of the shared plurality of unit MAC outputs; and the analog adder is configured to output a multi-bit MAC output including the weighted average of the shared plurality of unit MAC outputs.

19. Based on the multi-bit MAC of request item 17, where: The plurality of adder capacitors also includes a second adder capacitor; and the analog adder also includes a plurality of adder switches, including: a first adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, thereby sharing the first plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor; and a second adder switch configured to selectively electrically connect the second adder capacitor to a third adder capacitor via an electrical transmission bus as controlled by the control device.

20. Based on the multi-bit MAC of request item 19, where: The first adder switch is configured such that, as controlled by the control device, the first adder capacitor and the second adder capacitor are selectively electrically connected, thereby sharing the first plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor, including splitting the first plurality of unit MAC outputs in half for each of the first adder capacitor and the second adder capacitor; the analog adder is also configured to clear half of the first plurality of unit MAC outputs in the first adder capacitor; and the first adder switch is also configured such that, as controlled by the control device, the first adder capacitor and the second adder capacitor are selectively electrically connected, thereby sharing half of the first plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor, thereby splitting half of the first plurality of unit MAC outputs in half for each of the first adder capacitor and the second adder capacitor, thereby producing a plurality of quarters of the first plurality of unit MACs.

21. The multi-bit MAC of claim 19, wherein the plurality of adder switches also includes a third adder switch, wherein the third adder switch is configured to selectively electrically connect a fourth adder capacitor and the third adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor and the third adder capacitor.

22. The multi-bit MAC of claim 19, wherein the plurality of adder switches also includes a third adder switch, wherein the third adder switch is configured to selectively electrically disconnect a fourth adder capacitor and the third adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor and the third adder capacitor.

23. A method for multi-bit multiplication and accumulation, comprising the steps of: selectively electrically connecting a first unit MAC among a plurality of unit multiplier-accumulator (MAC) switches and a first adder capacitor among a plurality of adder capacitors via a first unit MAC switch; adding the first plurality of unit MAC outputs by: receiving the first plurality of unit MAC outputs from the first unit MAC in response to the selective electrical connection of the first unit MAC and the first adder capacitor by the first unit MAC switch; storing the first plurality of unit MAC outputs; and outputting a multi-bit MAC output based on the sum of the stored first plurality of unit MAC outputs.

24. The method according to claim 23 also includes the following steps: selectively electrically connecting a first adder capacitor and a second adder capacitor of the plurality of adder capacitors via a first adder switch of the plurality of adder switches, thereby sharing the first plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor; selectively electrically connecting a second adder capacitor and a third adder capacitor of the plurality of adder capacitors via a second adder switch of the plurality of adder switches, thereby sharing the shared first plurality of unit MAC outputs between the second adder capacitor and the third adder capacitor, wherein a cumulative capacitance rating of the paired second adder capacitor and the third adder capacitor is the same as a capacitance rating of the first adder capacitor; The shared first plurality of unit MAC outputs are weighted via the third adder capacitor; and the third adder capacitor is selectively electrically connected to an analog-to-digital converter via an electrical transmission bus via one of the plurality of adder switches, thereby outputting a weighted shared second plurality of unit MAC output to the analog-to-digital converter concurrently with another third adder capacitor outputting a weighted shared first plurality of unit MAC output to the analog-to-digital converter via the electrical transmission bus, thereby combining the weighted shared first plurality of unit MAC outputs and the weighted shared second plurality of unit MAC outputs into a weighted average of the shared plurality of unit MAC outputs, wherein outputting a multi-bit MAC output includes outputting the weighted average of the shared plurality of unit MAC outputs.

25. The method according to claim 23 also includes the following steps: selectively electrically connecting a first adder capacitor and a second adder capacitor among the plurality of adder capacitors via a first adder switch of the plurality of adder switches, thereby sharing the first plurality of unit MAC outputs between the first adder capacitor and the second adder capacitor; and selectively electrically connecting the second adder capacitor to a third adder capacitor among the plurality of adder capacitors via an electrical transmission bus via a second adder switch of the plurality of adder switches.

26. The method of claim 25, wherein selectively electrically connecting the first adder capacitor and the second adder capacitor to share the first plurality of unit cell MAC outputs between the first adder capacitor and the second adder capacitor includes dividing the first plurality of unit cell MAC outputs in half for each of the first adder capacitor and the second adder capacitor, the method also comprising: Clear half of the first complex unit MAC output in the first adder capacitor; And, if the first adder capacitor and the second adder capacitor are selectively electrically connected under the control of the first adder switch, so that half of the first plurality of unit MAC output is shared between the first adder capacitor and the second adder capacitor, so that half of the first plurality of unit MAC output is divided in half for each of the first adder capacitor and the second adder capacitor, thereby generating a plurality of quarters of the first plurality of unit MAC.

27. The method according to claim 25 also includes the following steps: selectively electrically connecting a fourth adder capacitor and the third adder capacitor among the plurality of adder capacitors via a third adder switch among the plurality of adder switches, while the second adder switch selectively electrically connects the second adder capacitor and the third adder capacitor.

28. The method according to claim 25 also includes the following steps: selectively electrically disconnecting a fourth adder capacitor and the third adder capacitor from the plurality of adder capacitors via a third adder switch of the plurality of adder switches, while selectively electrically connecting a second adder capacitor and the third adder capacitor via a second adder switch.

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