Light-emitting element, display device including the same, and semiconductor structure

Abstract

This invention provides a light-emitting element, comprising a first semiconductor layer, a second semiconductor layer, a light-emitting layer, and an insulating film. The first semiconductor layer is doped with n-type dopant, the second semiconductor layer is doped with p-type dopant, the light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer, and the insulating film surrounds the first semiconductor layer, the second semiconductor layer, and the light-emitting layer. The doping concentration of the first semiconductor layer is within a predetermined range. This invention also provides a display device including this light-emitting element.

Description

Technical Field

[0001] The present invention relates to a light-emitting element, a display device including the light-emitting element, and a semiconductor structure.

Prior Art

[0002] With the continuous development of multimedia, display devices have become increasingly important. Therefore, various types of display devices are being developed and used, such as organic light-emitting displays and liquid crystal displays.

[0003] In a display device, there is a self-emitting display device that may include a light-emitting element. The self-emitting display device may be an organic light-emitting display including an organic material as a light-emitting material for the light-emitting element, or may be an inorganic light-emitting display including an inorganic material as a light-emitting material for the light-emitting element.

[0004] It should be understood that the background part of this technical section is intended to provide useful background for understanding this technology. However, this background of this technical section may also include ideas, concepts, or cognitions that are not part of what is known or understood by those of ordinary skill in the art to which the present invention pertains before the corresponding effective filing date of the subject matter disclosed in this specification.

Summary of the Invention

[0005] Aspects of the present disclosure provide a light-emitting element including a semiconductor layer having a doping concentration index within a specific range, and a display device including the light-emitting element.

[0006] Aspects of the present disclosure also provide a light-emitting element and a semiconductor structure including a semiconductor layer having a doping concentration within a specific range and a doping concentration distribution.

[0007] However, the aspects of the present disclosure are not limited to those described in this specification. Through reference to the detailed description of the present disclosure given below, the above and other aspects of the present disclosure will become clearer to those of ordinary skill in the art to which the present invention pertains.

[0008] A light-emitting element according to an embodiment includes a semiconductor layer having a doping concentration index value equal to or greater than a value of an embodiment to have a large dipole moment.

[0009] A display device according to an embodiment includes the above light-emitting element. Therefore, the proportion of forward-oriented light-emitting elements can be increased, and the light-emitting efficiency and manufacturing yield can be increased.

[0010] According to an embodiment of the present invention, a light-emitting element may include: a first semiconductor layer doped with an n-type dopant; a second semiconductor layer doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and an insulating film surrounding the first semiconductor layer, the second semiconductor layer, and the light-emitting layer, wherein a doping concentration index of the first semiconductor layer represented by Equation 1 may be equal to or greater than about 2.5*1011 atoms / cm: [Equation 1] IDC (doping concentration index) =

[0011] In Equation 1, l0 may be the position of an interface between the first semiconductor layer and the light-emitting layer, l may be the position of an end face opposite to the interface between the first semiconductor layer and the light-emitting layer, x may be the distance from l0 to l, and n(x) may be the doping concentration of a dopant according to an x value of the first semiconductor layer.

[0012] In an embodiment, the doping concentration index of the first semiconductor layer may be equal to or greater than about 4*1011 atoms / cm.

[0013] In an embodiment, the first semiconductor layer may include: a first doped region; and a second doped region having a higher doping concentration of the n-type dopant than the first doped region.

[0014] In an embodiment, a length of the first doped region may be different from a length of the second doped region; and the first doped region may be in contact with the light-emitting layer.

[0015] In an embodiment, the first semiconductor layer may include: a first doped region in contact with the light-emitting layer, a second doped region in contact with the first doped region, and a doping concentration of the n-type dopant in the second doped region may be different from a doping concentration of the n-type dopant in the first doped region, and a third doped region in contact with the second doped region, and a doping concentration of the n-type dopant in the third doped region may be different from a doping concentration of the n-type dopant in the second doped region.

[0016] In an embodiment, the first doped region may be longer than each of the second doped region and the third doped region, and the second doped region may be shorter than the third doped region.

[0017] In an embodiment, a doping concentration of the n-type dopant in the first doped region may be greater than a doping concentration of the n-type dopant in each of the second doped region and the third doped region, and a doping concentration of the n-type dopant in the second doped region may be greater than a doping concentration of the n-type dopant in the third doped region.

[0018] In one embodiment, the first doped region may be shorter than each of the second doped region and the third doped region, and the second doped region may be longer than the third doped region.

[0019] In one embodiment, the doping concentration of the n-type dopants in the first doped region may be less than the doping concentration of the n-type dopants in the second doped region, and the doping concentration of the n-type dopants in the second doped region may be less than the doping concentration of the n-type dopants in the third doped region.

[0020] In one embodiment, the doping concentration of the n-type dopants in the first doped region may be greater than the doping concentration of the n-type dopants in the second doped region, and the doping concentration of the n-type dopants in the third doped region may be the same as the doping concentration of the n-type dopants in the first doped region.

[0021] According to an embodiment of the present disclosure, a display device may include: a first electrode and a second electrode disposed on a substrate and spaced apart from each other; a first insulating layer disposed on the first electrode and the second electrode; a plurality of light-emitting elements disposed on the first insulating layer and disposed on the first electrode and the second electrode; a first connection electrode in contact with one end of each of the plurality of light-emitting elements; and a second connection electrode in contact with the other end of each of the plurality of light-emitting elements, wherein each of the plurality of light-emitting elements may include: a first semiconductor layer doped with an n-type dopant; a second semiconductor layer doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and an insulating film surrounding the first semiconductor layer, the second semiconductor layer, and the light-emitting layer, a doping concentration index of the first semiconductor layer represented by Equation 1 may be equal to or greater than about 2.5*1011 atoms / cm or more: a number of the plurality of light-emitting elements may include a plurality of first ends and a plurality of second ends, the plurality of first ends are provided with the first semiconductor layer, the plurality of second ends are opposite to the plurality of first ends, wherein the first ends may be in contact with the second connection electrode and the second ends may be in contact with the first connection electrode, and among the plurality of light-emitting elements, a proportion of the number of the plurality of light-emitting elements may be equal to or greater than about 60%: [Equation 1] IDC (doping concentration index)= In Equation 1,

[0022] l0 may be a position of an interface between the first semiconductor layer and the light-emitting layer, l may be a position of an end face opposite to the interface between the first semiconductor layer and the light-emitting layer, x is a distance from l0 to l, and n(x) may be a doping concentration of dopants according to an x value of the first semiconductor layer.

[0023] In one embodiment, the doping concentration exponent of the first semiconductor layer in each of the plurality of light-emitting elements may be equal to or greater than about 4*10^11 atoms / cm. The number of the plurality of light-emitting elements includes a plurality of first ends and a plurality of second ends. The first semiconductor layer is disposed at the plurality of first ends, and the plurality of second ends are opposite to the plurality of first ends. Wherein the first ends are in contact with the second connection electrodes and the second ends are in contact with the first connection electrodes, and in the plurality of light-emitting elements, a proportion of the number of the plurality of light-emitting elements is equal to or greater than about 80%.

[0024] In one embodiment, the first semiconductor layer may include: a first doped region in contact with the light-emitting layer, a second doped region, the doping concentration of the n-type dopants in the second doped region being greater than the doping concentration of the n-type dopants in the first doped region, and the first doped region may be longer than the second doped region.

[0025] In one embodiment, the first semiconductor layer may include: a first doped region in contact with the light-emitting layer, a second doped region in contact with the first doped region, and the doping concentration of the n-type dopants in the second doped region being different from the doping concentration of the n-type dopants in the first doped region, and a third doped region in contact with the second doped region, and the doping concentration of the n-type dopants in the third doped region being different from the doping concentration of the n-type dopants in the second doped region.

[0026] In one embodiment, the first doped region may be longer than each of the second doped region and the third doped region, and the second doped region may be shorter than the third doped region. The doping concentration of the n-type dopants in the first doped region may be greater than the doping concentration of the n-type dopants in each of the second doped region and the third doped region, and the doping concentration of the n-type dopants in the second doped region may be greater than the doping concentration of the n-type dopants in the third doped region.

[0027] In one embodiment, the first doped region may be shorter than each of the second doped region and the third doped region, the second doped region may be longer than the third doped region, the doping concentration of the n-type dopants in the first doped region may be less than the doping concentration of the n-type dopants in the second doped region, and the doping concentration of the n-type dopants in the second doped region may be less than the doping concentration of the n-type dopants in the third doped region.

[0028] According to an embodiment of the present disclosure, a semiconductor structure may include: a first semiconductor layer doped with an n-type dopant; a second semiconductor layer doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and an insulating film surrounding the first semiconductor layer, the second semiconductor layer, and the light-emitting layer, wherein a doping concentration of the n-type dopant in the first semiconductor layer is equal to or greater than about 1*10^18 atoms / cm3.

[0029] In an embodiment, the doping concentration of the n-type dopant in the first semiconductor layer is equal to or greater than about 6*10^18 atoms / cm3.

[0030] In an embodiment, the first semiconductor layer may include: a first doped region; and a second doped region, wherein a doping concentration of the n-type dopant in the second doped region is greater than a doping concentration of the n-type dopant in the first doped region.

[0031] In an embodiment, a length of the first doped region may be different from a length of the second doped region, and the first doped region may be in contact with the light-emitting layer.

[0032] In an embodiment, the first semiconductor layer may include: a first doped region in contact with the light-emitting layer, a second doped region in contact with the first doped region, and a doping concentration of the n-type dopant in the second doped region may be different from a doping concentration of the n-type dopant in the first doped region, and a third doped region in contact with the second doped region, and a doping concentration of the n-type dopant in the third doped region may be different from a doping concentration of the n-type dopant in the second doped region.

[0033] In an embodiment, the first doped region may be longer than each of the second doped region and the third doped region, and the second doped region may be shorter than the third doped region.

[0034] In an embodiment, the doping concentration of the n-type dopant in the first doped region may be equal to or greater than about 6*10^18 atoms / cm3, and the doping concentration of the n-type dopant in each of the second doped region and the third doped region may be equal to or less than about 6*10^18 atoms / cm3.

[0035] In one embodiment, the first doped region may be shorter than each of the second doped region and the third doped region, the second doped region may be longer than the third doped region, the doping concentration of the n-type dopants in the first doped region may be less than the doping concentration of the n-type dopants in the second doped region, and the doping concentration of the n-type dopants in the second doped region may be less than the doping concentration of the n-type dopants in the third doped region.

[0036] In one embodiment, the doping concentration of the n-type dopants in each of the first doped region and the second doped region may be equal to or less than about 6*10^18 atoms / cm3, and the doping concentration of the n-type dopants in the third doped region may be equal to or greater than about 6*10^18 atoms / cm3.

[0037] In one embodiment, the doping concentration of the n-type dopants in each of the first doped region and the third doped region may be equal to or greater than about 6*10^18 atoms / cm3, and the doping concentration of the n-type dopants in the second doped region may be equal to or less than about 6*10^18 atoms / cm3.

Embodiments

[0039] The present disclosure will now be described more fully hereinafter with reference to the drawings, in which embodiments are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth in this specification. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art to which this invention pertains.

[0040] In the drawings, the dimensions, thicknesses, ratios, and sizes of elements may be exaggerated for clarity, and the same element numbers represent the same elements.

[0041] In this specification, it should be understood that when an element (or region, layer, part) is referred to as being “on,” “connected to,” or “coupled to” another element, it may be directly “disposed / connected / coupled” “on / to” another element, or one or more intermediate elements may be present between them. In a similar sense, when an element (or region, layer, part, etc.) is described as “covering” another element, it may directly “cover” another element, or one or more intermediate elements may be present between them. It should be understood that the terms "connected to" or "coupled to" may include physical or electrical connection or coupling.

[0043] In this specification, when an element is "directly" "on" another element or layer, or "directly connected to" or "directly coupled to" another element, there is no intermediate element. For example: "directly on" may mean that when two layers or two elements are arranged, there is no additional element, such as an adhesive element between them.

[0044] As used in this specification, unless the context clearly indicates otherwise, expressions used in the singular form, such as "a", "an", and "the", are intended to also include the plural forms.

[0045] As used in this specification, the term "and / or" includes any or all combinations of one or more of the related listed items. For example: "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a combined or separated sense and can be understood to be equivalent to "and / or".

[0046] In the specification and claims, for the purpose of their meaning and interpretation, the term "at least one of" is intended to include the meaning of "at least one selected from the group". For example: "at least one of A and B" can be understood to mean "A, B, or A and B". Before a list of elements, the term "at least one" modifies the entire list of elements, rather than each individual element in the list.

[0047] It should be understood that although terms such as "first" and "second" may be used in this specification to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element may be referred to as the second element. Similarly, without departing from the scope of this disclosure, the second element may be referred to as the first element.

[0048] For ease of description, this specification may use spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. to describe the relationship between one element or component and another element or component as shown in the drawings. It should be understood that, in addition to the directions depicted in the drawings, spatial relative terms are intended to encompass different directions in which the device is used or operated. For example: If the device shown in the drawings is flipped, then a device located "below" or "beneath" another device may be placed "above" another device. Therefore, the descriptive term "below" can include a lower position and an upper position, and the device can also be oriented in other directions, so the spatially related terms can be interpreted differently depending on the direction.

[0049] As used in this specification, the terms "about" or "approximately" are inclusive statements of a stated value and an average value within an acceptable range of deviation from the specific value as determined by one of ordinary skill in the art to which this invention pertains, taking into account the measurements discussed and the associated error measurements and the particular quantities (i.e., the limits of the measurement system). For example: "about" can mean within one or more standard deviations, or within ±20%, 10%, 5% of the stated value.

[0050] It should be understood that the terms "comprises", "comprising", "includes", "including", "have", "having", "contains", "containing", etc. are intended to specify the presence of the stated features, integers, steps, operations, elements, components, or combinations thereof in this disclosure, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0051] Unless otherwise defined or implied in this specification, all terms used (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that, unless explicitly defined in the specification, terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an ideal or overly formal sense.

[0052] Hereinafter, embodiments will be described with reference to the drawings.

[0053] FIG. 1 is a schematic plan view of the display device 10 according to an embodiment.

[0054] As shown in FIG. 1, the display device 10 displays a moving image or a still image, and the display device 10 may refer to any electronic device providing a display screen. Examples of the display device 10 may include a television, a laptop computer, a monitor, a billboard, the Internet of Things (IoT), a mobile phone, a smartphone, a tablet, a personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a game machine, a digital camera, and a video camera, all of which are provided with a display screen.

[0055] The display device 10 may include a display panel provided with a display screen. Examples of the display panel may include an inorganic light-emitting diode display panel, an organic light-emitting display panel, a quantum dot light-emitting display panel, a plasma display panel, and a field emission display panel. Hereinafter, an inorganic light-emitting diode display panel is taken as an example of the display panel for description, but the present invention is not limited thereto, and other display panels may also be applied as long as the same technical spirit can be applied.

[0056] The shape of the display device 10 can be variously modified. For example: The display device 10 may have a shape such as a horizontally long rectangle, a vertically long rectangle, a square, a quadrilateral with rounded corners (vertices), other polygons, or a circle. The shape of the display area DPA of the display device 10 may also be similar to the overall shape of the display device 10. In FIG. 1, a display device 10 having a rectangular shape that is longer in the second direction DR2 is shown.

[0057] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an area where a screen can be displayed, and the non-display area NDA may be an area where there is no display screen. The display area DPA may be referred to as an effective area, and the non-display area NDA may be referred to as an ineffective area. The display area DPA generally may occupy the internal area of the display device 10.

[0058] The display area DPA may include pixels PX, and the pixels PX may be arranged in a matrix form. Each pixel PX may be rectangular or square in a plan view. However, the present disclosure is not limited thereto, and each pixel PX may also have a rhombus shape in which each side is inclined with respect to a direction. The pixels PX may be arranged in a stripe configuration or a PENTILETM configuration. Each pixel PX may display a specific color through a light-emitting element including one or more light rays emitting specific wavelength bands.

[0059] The non-display area NDA can be set around the display area DPA. The non-display area NDA can completely or partially surround the display area DPA. The display area DPA can be rectangular, and the non-display area NDA can be set adjacent to the four sides of the display area DPA. The non-display area NDA can form the border of the display device 10. The wiring or circuit driver included in the display device 10 can be set in each non-display area NDA, or an external device can be installed in the non-display area NDA.

[0060] FIG. 2 is a schematic plan view of a pixel PX of the display device 10 according to an embodiment.

[0061] Referring to FIG. 2, each pixel PX of the display device 10 can include sub-pixels SPXn (where n is from 1 to 3). For example, the pixel PX can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 can emit light of a third color. For example, the first color can be blue, the second color can be green, and the third color can be red. However, the present disclosure is not limited thereto, and the sub-pixels SPXn can emit light of the same color. In one embodiment, the sub-pixels SPXn can each emit blue light. Although the pixel PX includes three sub-pixels SPXn in the figure, the present invention is not limited thereto, and the pixel PX can also include a greater number of sub-pixels SPXn.

[0062] Each sub-pixel SPXn of the display device 10 can include a light-emitting area EMA and a non-light-emitting area. The emission area EMA can be an area where a light-emitting element ED is provided to emit light in a specific wavelength band. This non-light-emitting area can be an area where no light-emitting element ED is provided and no light is output from this area because the light from the light-emitting element ED cannot reach this area.

[0063] The light-emitting area EMA can include an area where the light-emitting element ED is provided and an area adjacent to the light-emitting element ED and from which the light output from the light-emitting element ED exits. However, the present invention is not limited thereto, and the light-emitting area EMA can also include an area from which the light from the light-emitting element ED exits after being reflected or refracted by other components. The light-emitting element ED can be provided in each sub-pixel SPXn, and the area where the light-emitting element ED is provided and the area adjacent to this area can form the emission area EMA.

[0064] Although each light-emitting area EMA of the sub-pixel SPXn has substantially the same area in the drawing, the present disclosure is not limited thereto. In an embodiment, the light-emitting area EMA of each sub-pixel SPXn may have an area that varies according to the color or wavelength band of the light from the light-emitting element ED disposed in the sub-pixel SPXn.

[0065] Each sub-pixel SPXn may further include a sub-region SA disposed in the non-light-emitting area. The sub-region SA may be disposed on one side of the emission area EMA along the first direction DR1, and may be disposed between the emission areas EMA of adjacent sub-pixels SPXn along the first direction DR1. For example, the emission area EMA and the sub-region SA may be repeatedly disposed in the second direction DR2, but may be alternately disposed in the first direction DR1. However, the present disclosure is not limited thereto, and the settings of the light-emitting area EMA and the sub-region SA in the pixel PX may also be different from those in the second drawing.

[0066] A bank layer BNL may be disposed between the sub-region SA and the emission area EMA, and the distance therebetween may vary according to the width of the bank layer BNL. Since the light-emitting element ED is not disposed in the sub-region SA, light may not be emitted from the sub-region SA, but a portion of the electrode RME disposed in each sub-pixel SPXn may be disposed in the sub-region SA. The electrodes RME disposed in different sub-pixels SPXn may be separated from each other in the separated portion ROP of the sub-region SA.

[0067] The bank layer BNL may include portions extending along the first direction DR1 and the second direction DR2 in a plan view to form a grid pattern in the entire display area DPA. The bank layer BNL may be disposed at the boundary of each sub-pixel SPXn to separate adjacent sub-pixels SPXn. The bank layer BNL may surround the emission areas EMA disposed in each sub-pixel SPXn to separate them from each other.

[0068] FIG. 3 is a schematic cross-sectional view taken along the line N1-N1' of FIG. 2, and FIG. 4 is a schematic cross-sectional view taken along the line N2-N2' of FIG. 3. FIG. 3 shows a cross-section of the light-emitting element ED disposed in the first sub-pixel SPX1, while FIG. 3 shows a cross-section of the light-emitting element ED disposed in the first sub-pixel SPX1, and FIG. 4 shows a cross-section of the contact holes CTD and CTS.

[0069] Referring to FIGS. 3 and 4 in conjunction with FIG. 2, the display device 10 may include a substrate SUB and a semiconductor layer, a conductive layer, and an insulating layer provided on the substrate SUB. The semiconductor layer, the conductive layer, and the insulating layer may constitute a circuit layer and a display element layer of the display device 10.

[0070] The substrate SUB may be an insulating substrate. The substrate SUB may be made of an insulating material such as glass, quartz, or a polymer resin. The substrate SUB may be a rigid substrate, but may also be a flexible substrate that can be bent, folded, curled, etc.

[0071] A first conductive layer may be provided on the substrate SUB. The first conductive layer includes a bottom metal layer CAS, and the bottom metal layer CAS overlaps with the active layer ACT1 of the first transistor T1. The bottom metal layer CAS may include a light-shielding material to prevent light from entering the active layer ACT1 of the first transistor T1. However, the bottom metal layer CAS may also be omitted.

[0072] A buffer layer BL may be provided on the bottom metal layer CAS and the substrate SUB. The buffer layer BL may be formed on the substrate SUB. The substrate SUB is easily penetrated by moisture. The buffer layer BL can protect the transistors of the pixel PX from moisture introduced through the substrate SUB and can provide a surface flattening function.

[0073] The semiconductor layer may be provided on the buffer layer BL. The semiconductor layer may include the active layer ACT1 of the first transistor T1. The active layer ACT1 may overlap with the gate G1 portion of the second conductive layer to be described later.

[0074] The semiconductor layer may include polysilicon, single crystal silicon, an oxide semiconductor, etc. In one embodiment, the semiconductor layer may include polysilicon. The oxide semiconductor may be a conductor in which the oxide semiconductor contains indium (In). For example: The oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium, gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0075] Although one first transistor T1 may be provided in each sub-pixel SPXn of the display device 10 in the drawings, the present disclosure is not limited thereto, and the display device 10 may include a greater number of transistors.

[0076] A first gate insulating layer GI may be provided on the semiconductor layer and the buffer layer BL. The first gate insulating layer GI may be used as a gate insulating film of the first transistor T1.

[0077] The second conductive layer may be disposed on the first gate insulating layer GI. The second conductive layer may include the gate G1 of the first transistor T1, and the gate G1 may overlap with the channel region of the active layer ACT1 in the third direction DR3 as the thickness direction.

[0078] The first interlayer insulating layer IL1 may be disposed on the second conductive layer. The first interlayer insulating layer IL1 may serve as an insulating film between the second conductive layer and other layers disposed on the second conductive layer, and may protect the second conductive layer.

[0079] The third conductive layer may be disposed on the first interlayer insulating layer IL1. The third conductive layer may include a first voltage line VL1 and a second voltage line VL2 disposed in the display area DPA, and conductive patterns CDP1 and CDP2.

[0080] The high potential voltage (or the first power supply voltage) supplied to the first electrode RME1 may be applied to the first voltage line VL1, and the low potential voltage (or the second power supply voltage) supplied to the second electrode RME2 may be applied to the second voltage line VL2. A part of the first voltage line VL1 may contact the active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. The first voltage line VL1 may serve as the first drain D1 of the first transistor T1, and the second voltage line VL2 may be directly connected to the second electrode RME2 described later.

[0081] The first conductive pattern CDP1 may contact the active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. The first conductive pattern CDP1 may contact the bottom metal layer CAS through another contact hole. The first conductive pattern CDP1 may serve as the source S1 of the first transistor T1.

[0082] The second conductive pattern CDP2 may be connected to the first electrode RME1 described later. The second conductive pattern CDP2 may be electrically connected to the first transistor T1 through the first conductive pattern CDP1. In the drawing, the first conductive pattern CDP1 and the second conductive pattern CDP2 are separated from each other. However, in an embodiment, the second conductive pattern CDP2 may be integrated with the first conductive pattern CDP1 to form one pattern. The first transistor T1 may transmit the first power supply voltage received from the first voltage line VL1 to the first electrode RME1.

[0083] Although in the schema the first conductive pattern CDP1 and the second conductive pattern CDP2 are formed on the same layer, the invention is not limited to this. In embodiments, the second conductive pattern CDP2 may be formed from a conductive layer different from the first conductive pattern CDP1, e.g. The first voltage line VL1 and the second voltage line VL2 may also be formed by a fourth conductive layer in place of the third conductive layer, and the first voltage line VL1 may be electrically connected to the drawer D1 pattern of the first transistor T1 via another conductive layer.

[0084] Each of the above-mentioned buffer layer BL, the first gate insulation layer GI, and the first interlayer insulation layer IL1 may be constructed of alternately stacked inorganic layers. For example: each of the buffer layer BL, the first gate insulation layer GI, and the first interlayer insulation layer IL1 may be a double layer, wherein the inorganic layer includes at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon nitride (SiOxNy) stacked or may be multiple layers of the above materials stacked alternately. However, the invention is not limited to this, each of the buffer layer BL, the first gate insulation layer GI, and the first interlayer insulation layer IL1 may also be constructed of an inorganic layer comprising any of the above-mentioned insulation materials. In embodiments, the first interlayer insulating layer IL1 may consist of an organic insulating material such as polyimide (PI).

[0085] Each of the second conductive layer and the third conductive layer may be, but is not limited to, a single or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or any one or more of the alloys thereof.

[0086] The through-hole layer VIA may be disposed on a third conductive layer, the through-hole layer VIA may include, for example, an organic insulation material of polyimide (PI) and may provide a surface flattening function.

[0087] The dike wall patterns BP1 and BP2, the electrodes RME (RME1 and RME2), the dike wall layer BNL, the light-emitting element ED and the connecting electrode CNE (CNE1 and CNE2) are set as display element layers on the through-hole layer VIA. The insulation layers PAS1 to PAS3 can be disposed on the through-hole layer VIA.

[0088] The bank patterns BP1 and BP2 can be directly disposed on the via layer VIA. The bank patterns BP1 and BP2 can extend in a first direction DR1 and can be spaced apart from each other in a second direction DR2. For example, the bank patterns BP1 and BP2 can include a first bank pattern BP1 and a second bank pattern BP2 spaced apart from each other in the emission region EMA of each sub-pixel SPXn. The first bank pattern BP1 can be disposed on the left side of the center of the emission region EMA on one side of the second direction DR2, and the second bank pattern BP2 can be disposed on the right side of the center of the emission region EMA. The emission region EMA is the other side of the second direction DR2. The light-emitting element ED can be disposed between the first bank pattern BP1 and the second bank pattern BP2.

[0089] The length of each of the bank patterns BP1 and BP2 extending along the first direction DR1 can be less than the length of the emission region EMA surrounded by the bank layer BNL in the first direction DR1. The bank patterns BP1 and BP2 can be disposed in the emission region EMA of each sub-pixel SPXn in the entire display area DPA to form an island pattern having a narrow width and extending in one direction. Although two bank patterns BP1 and BP2 having the same width are provided in each sub-pixel SPXn in the drawings, the present disclosure is not limited thereto. The number and shape of the bank patterns BP1 and BP2 can vary according to the number or arrangement structure of the electrodes RME.

[0090] At least a portion of each of the bank patterns BP1 and BP2 can protrude from the upper surface of the via layer VIA. The protruding portions of the bank patterns BP1 and BP2 can have inclined side surfaces, and the light from the light-emitting element ED can be reflected upward from the via layer VIA through the electrodes RME disposed on the bank patterns BP1 and BP2. However, the present invention is not limited thereto. Each of the bank patterns BP1 and BP2 can also be a semi-circular or semi-elliptical shape having a curved outer surface. The bank patterns BP1 and BP2 can include, but are not limited to, an organic insulating material such as polyimide (PI).

[0091] Each electrode RME can extend in one direction and can be disposed in each sub-pixel SPXn. The electrode RME can extend in the first direction DR1, can be disposed in the emission region EMA of each sub-pixel SPXn, and can be spaced apart from each other in the second direction DR2. The electrode RME can be electrically connected to the light-emitting element ED. Each electrode RME can be connected to the light-emitting element ED through a connection electrode CNE (CNE1 or CNE2) described later, and can transmit an electrical signal received from a conductive layer disposed therebelow to the light-emitting element ED.

[0092] The display device 10 includes a first electrode RME1 and a second electrode RME2 disposed in each sub-pixel SPXn. The first electrode RME1 may be disposed on the left side of the center of the emission area EMA, and the second electrode RME2 may be spaced apart from the first electrode RME1 in the second direction DR2 and may be disposed on the right side emission area EMA of the center. The first electrode RME1 may be disposed on the first bank pattern BP1, and the second electrode RME2 may be disposed on the second bank pattern BP2. The first electrode RME1 and the second electrode RME2 may extend beyond the bank layer BNL to be partially located in the corresponding sub-pixel SPXn and sub-region SA. The first electrodes RME1 and the second electrodes RME2 of different sub-pixels SPXn may be separated from each other by a separation portion ROP located in the sub-region SA of the sub-pixel SPXn.

[0093] The first electrode RME1 and the second electrode RME2 may be respectively disposed on at least the inclined side surfaces of the bank patterns BP1 and BP2. In an embodiment, the width of each electrode RME measured in the second direction DR2 may be less than the width of each of the bank patterns BP1 and BP2 measured in the second direction DR2. Each of the first electrode RME1 and the second electrode RME2 may cover the side surface of at least the bank pattern BP1 or BP2 to reflect light from the light-emitting element ED.

[0094] The distance between the first electrode RME1 and the second electrode RME2 in the second direction DR2 may be less than the distance between the bank patterns BP1 and BP2. At least a part of each of the first electrode RME1 and the second electrode RME2 may be directly disposed on the via layer VIA such that they are located on the same plane.

[0095] As described above, the electrodes RME may be disposed on the bank patterns BP1 and BP2, and light from the light-emitting element ED disposed between the bank patterns BP1 and BP2 may be reflected upward by the electrodes RME disposed on the bank patterns BP1 and BP2. Each electrode RME may include a conductive material having a high reflectivity to reflect light from the light-emitting element ED.

[0096] Each electrode RME may extend from the emission area EMA to the sub-region SA, and may include a portion overlapping with the bank layer BNL and a portion disposed in the sub-region SA. According to an embodiment, a portion where the upper surface portion of each electrode RME is exposed may be disposed in the sub-region SA. However, the present invention is not limited thereto, and a portion where the upper surface of each electrode RME is partially exposed may also be disposed within the emission area EMA.

[0097] The first electrode RME1 and the second electrode RME2 can each be connected to the third conductive layer through a first contact hole CTD and a second contact hole CTS formed in a portion overlapping with the bank layer BNL, respectively. The first electrode RME1 can contact the second conductive pattern CDP2 through the first contact hole CTD passing through the via layer VIA under the first electrode RME1. The second electrode RME2 can contact the second voltage line VL2 through the second contact hole CTS passing through the via layer VIA under the second electrode RME2. The first electrode RME1 can be electrically connected to the first transistor T1 through the second conductive pattern CDP2 and the first conductive pattern CDP1 to receive the first power supply voltage, and the second electrode RME2 can be electrically connected to the second voltage line VL2 to receive the second power supply voltage.

[0098] The first insulating layer PAS1 can be disposed over the entire display area DPA and can be disposed over the via layer VIA and the electrodes RME. The first insulating layer PAS1 can protect the electrodes RME while insulating them from each other. For example, since the first insulating layer PAS1 covers the electrodes RME before forming the bank layer BNL, the electrodes RME can be prevented from being damaged during the formation of the bank layer BNL. The first insulating layer PAS1 can prevent the light-emitting elements ED disposed thereon from directly contacting other components and thus being damaged.

[0099] In an embodiment, the first insulating layer PAS1 can be stepped such that a part of the upper surface of the first insulating layer PAS1 is recessed between the electrodes RME spaced apart from each other along the second direction DR2. The light-emitting elements ED can be disposed on the stepped upper surface of the first insulating layer PAS1, and a space can be formed between each light-emitting element ED and the first insulating layer PAS1.

[0100] According to an embodiment, the first insulating layer PAS1 can cover the electrodes RME, but can include openings that partially expose the upper surfaces of the electrodes RME. For example, the first insulating layer PAS1 can include contact portions CT1 and CT2, each of which partially exposes the upper surface of the electrode RME. The first contact portion CT1 can be disposed on the first electrode RME1 in the sub-region SA, and the second contact portion CT2 can be disposed on the second electrode RME2 in the sub-region SA. A connection electrode CNE described later can contact the electrodes RME exposed through the first contact portion CT1 and the second contact portion CT2. The first insulating layer PAS1 can expose the upper surface of the via layer VIA in a separation portion ROP where the electrodes RME of different sub-pixels SPXn are separated.

[0101] The bank layer BNL can be disposed on the first insulating layer PAS1. The bank layer BNL can include portions extending along a first direction DR1 and a second direction DR2, and can surround each sub-pixel SPXn. The bank layer BNL can surround the emission area EMA and the sub-area SA of each sub-pixel SPXn to separate them, and can surround the outermost periphery of the display area DPA to separate the display area DPA and the non-display area NDA. The bank layer BNL can be entirely disposed in the display area DPA to form a grid pattern, and the areas of the bank layer BNL exposed in the display area DPA can be the emission area EMA and the sub-area SA.

[0102] Similar to the bank patterns BP1 and BP2, the bank layer BNL can have the height of the embodiment. In the embodiment, the height of the upper surface of the bank layer BNL can be greater than the height of each of the bank patterns BP1 and BP2, and the thickness of the bank layer BNL can be equal to or greater than the thickness of each of the bank patterns BP1 and BP2. During the manufacturing process of the display device 10, the bank layer BNL can prevent ink from overflowing to adjacent sub-pixels SPXn in the inkjet printing process. Similar to the bank patterns BP1 and BP2, the bank layer BNL can include an organic insulating material such as polyimide.

[0103] The light-emitting element ED can be disposed on the first insulating layer PAS1. The light-emitting element ED can extend in one direction, and the direction in which the light-emitting element ED extends can be parallel to the substrate SUB. As will be described below, each light-emitting element ED can include a semiconductor layer disposed along the extending direction, and the semiconductor layers can be sequentially disposed along a direction parallel to the upper surface of the substrate SUB. However, the present invention is not limited thereto. When the light-emitting element ED has a different structure, the semiconductor layer can be disposed in a direction perpendicular to the substrate SUB.

[0104] The light-emitting element ED can be disposed on the electrode RME spaced apart between the bank patterns BP1 and BP2 along the second direction DR2. The length of each light-emitting element ED can be greater than the distance between the electrodes RME spaced apart in the second direction DR2. The light-emitting element ED can be disposed such that at least one end thereof is disposed on any one of the electrodes RME, or the opposite ends of the light-emitting element ED can be respectively disposed on different electrodes RME. The direction in which each electrode RME extends and the direction in which the light-emitting element ED extends can be substantially perpendicular to each other. The light-emitting elements ED can be spaced apart from each other along the first direction DR1 in which each electrode RME extends, and can be arranged substantially parallel to each other. However, the present invention is not limited thereto, and the light-emitting elements ED can also be disposed obliquely with respect to the direction in which each electrode RME extends.

[0105] Depending on the material forming the semiconductor layer described above, the light-emitting elements ED provided in each sub-pixel SPXn can each emit light in a different wavelength band. However, the present disclosure is not limited thereto, and the light-emitting elements ED provided in each sub-pixel SPXn can emit light of the same color by respectively including semiconductor layers made of the same material. The light-emitting elements ED can be electrically connected to the electrode RME and the conductive layer under the via layer VIA through contact connection electrodes CNE (CNE1 and CNE2), and can emit light in a specific wavelength band in response to an electrical signal.

[0106] Each light-emitting element ED can include a semiconductor layer doped with dopants having different types of conductivity, and a dipole moment can be formed by the charges of the dopants used to dope each semiconductor layer. The light-emitting elements ED having a dipole moment can be provided on the electrode RME because their orientation directions and positions are changed by the force applied by the electric field generated on the electrode RME. For example: The connection electrodes CNE (CNE1 and CNE2) contacted by each end of each light-emitting element ED can vary according to the orientation direction of the light-emitting element ED, which can determine whether the light-emitting element ED is electrically connected to the voltage lines VL1 and VL2 in the forward or reverse direction.

[0107] The intensity of the force applied by the electric field to the light-emitting element ED can vary according to the electric field intensity and the magnitude of the dipole moment of the light-emitting element ED. As the intensity of the force applied by the electric field to the light-emitting element ED increases, the number of light-emitting elements ED facing forward in the light-emitting element ED may increase, which means that due to the forward connection between the light-emitting elements ED provided in each sub-pixel SPXn, the proportion of the light-emitting elements ED emitting light normally increases, and the light-emitting efficiency and manufacturing yield of the display device 10 increase.

[0108] According to an embodiment, in each light-emitting element ED, the semiconductor layer doped with different conductivity types can have a doping concentration equal to or greater than the value of the embodiment to have a large dipole moment. When the semiconductor layer has a high doping concentration value, the magnitude of the dipole moment of each light-emitting element ED increases, and the proportion of the light-emitting elements ED facing forward in the light-emitting element ED increases, which will be described in detail below.

[0109] The second insulating layer PAS2 may be disposed on the light-emitting element ED, the first insulating layer PAS1, and the bank layer BNL. The second insulating layer PAS2 may include a pattern extending along a first direction DR1 between the bank patterns BP1 and BP2, and may be disposed on the light-emitting element ED. The pattern may partially cover the outer surface of the light-emitting element ED and may not cover the opposite side or opposite ends of the light-emitting element ED. In a plan view, the pattern may form a linear or island-shaped pattern in each sub-pixel SPXn. During the manufacturing process of the display device 10, the pattern of the second insulating layer PAS2 may protect the light-emitting element ED while fixing the light-emitting element ED. The second insulating layer PAS2 may fill the space between each light-emitting element. The element ED and the first insulating layer PAS1 located below the light-emitting element ED. A part of the second insulating layer PAS2 may be disposed on the bank layer BNL and in the sub-region SA. A part of the second insulating layer PAS2 disposed in the sub-region SA may not be disposed in the first contact portion CT1, the second contact portion CT2, and the separation portion ROP.

[0110] The connection electrodes CNE (CNE1 and CNE2) may be disposed on the electrode RME and the light-emitting element ED, and may contact the electrode RME and the light-emitting element ED. Each connection electrode CNE may contact one end of each light-emitting element ED and contact at least one of the electrodes RME through the contact portion CT1 or CT2 penetrating the first insulating layer PAS1 and the second insulating layer PAS2.

[0111] The first connection electrode CNE1 may extend in the first direction DR1 and may be disposed on the first electrode RME1. A part of the first connection electrode CNE1 disposed on the first bank pattern BP1 may overlap with the first electrode RME1 such that the overlapping portion may extend in the first direction DR1. The first connection electrode CNE1 may extend from the emission region EMA to the sub-region SA outside the bank layer BNL. The first connection electrode CNE1 may contact the first electrode RME1 through the first contact portion CT1 in the sub-region SA. The first connection electrode CNE1 may contact the light-emitting element ED and the first electrode RME1 to transmit the electrical signal received from the first transistor T1 to the light-emitting element ED.

[0112] The second connection electrode CNE2 may extend in the first direction DR1 and may be disposed on the second electrode RME2. A part of the second connection electrode CNE2 disposed on the second bank pattern BP2 may overlap with the second electrode RME2 such that the overlapping part may extend in the first direction DR1. The second connection electrode CNE2 may extend from the emission area EMA to the sub-region SA outside the bank layer BNL. The second connection electrode CNE2 may contact the second electrode RME2 through the second contact portion CT2 in the sub-region SA. The second connection electrode CNE2 may contact the light-emitting element ED and the second electrode RME2 to transmit the electrical signal received from the second voltage line VL2 to the light-emitting element ED.

[0113] The third insulating layer PAS3 may be disposed on the second connection electrode CNE2 and the second insulating layer PAS2. The third insulating layer PAS3 may be entirely disposed on the second insulating layer PAS2 to cover the second connection electrode CNE2, and the first connection electrode CNE1 may be disposed on the third insulating layer PAS3. Except for the area where the first connection electrode CNE1 is disposed, the third insulating layer PAS3 may be entirely disposed on the via layer VIA. The third insulating layer PAS3 may insulate the first connection electrode CNE1 and the second connection electrode CNE2 from each other such that the first connection electrode CNE1 does not directly contact the second connection electrode CNE2.

[0114] The third insulating layer PAS3 may be entirely disposed on the sub-region SA except for the part where the first contact portion CT1 is disposed, and may cover the second contact portion CT2 and the separation portion ROP. Since the first connection electrode CNE1 is disposed in the first contact portion CT1, the third insulating layer PAS3 may expose the first contact portion CT1. Since the second connection electrode CNE2 is disposed in the second contact portion CT2, the third insulating layer PAS3 may cover the second contact portion CT2 together with the second connection electrode CNE2. The third insulating layer PAS3 may cover the separation portion ROP to directly contact the upper surface of the via layer VIA exposed between the electrodes RME spaced apart from each other.

[0115] Although not shown in the drawings, another insulating layer may be further disposed on the third insulating layer PAS3 and the first connection electrode CNE1. The insulating layer may protect the components disposed on the substrate SUB from the external environment.

[0116] The first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 described above may all include an inorganic insulating material or an organic insulating material.

[0117] FIG. 5 is a schematic diagram of a light-emitting element ED according to an embodiment, and FIG. 6 is a schematic cross-sectional view of the light-emitting element ED of FIG. 5. FIG. 6 shows a cross-section taken through the center of the light-emitting element ED of FIG. 5 along the height direction.

[0118] Referring to FIGS. 5 and 6, the light-emitting element ED may be a light-emitting diode. For example, the light-emitting element ED may be an inorganic light-emitting diode having a size from nanometers to micrometers and made of an inorganic material. When an electric field is formed in a specific direction between two electrodes facing each other, the light-emitting element ED may be aligned between the two electrodes having a polarity.

[0119] The light-emitting element ED according to an embodiment may extend in one direction. The shape of the light-emitting element ED may be cylindrical, rod-shaped, linear, tubular, etc. However, the shape of the light-emitting element ED is not limited thereto, and the light-emitting element ED may also have a shape such as a polyhedral prism such as a cube, a cuboid, a hexagonal prism, and a shape having an outer surface that extends in one direction and has a partial inclination.

[0120] The light-emitting element ED may include a semiconductor layer doped with impurities of any conductive type (e.g., p-type or n-type). The semiconductor layer may receive an electrical signal from an external power source and emit light in a specific wavelength band. The light-emitting element ED may include a first semiconductor layer 31, a second semiconductor layer 32, a light-emitting layer 36, an electrode layer 37, and an insulating film 38.

[0121] The first semiconductor layer 31 may be an n-type semiconductor. The first semiconductor layer 31 may include a semiconductor material having the chemical formula AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x + y≤1). For example, the first semiconductor layer 31 may be any one or more of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The n-type dopant for doping the first semiconductor layer 31 may be silicon (Si), germanium (Ge), tin (Sn), etc.

[0122] The second semiconductor layer 32 may be disposed on the first semiconductor layer 31, and the light-emitting layer 36 is inserted therebetween. The second semiconductor layer 32 may be a p-type semiconductor. The second semiconductor layer 32 may include a semiconductor material having the chemical formula AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x + y≤1). For example, the second semiconductor layer 32 may be any one or more of p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The p-type dopant for doping the second semiconductor layer 32 may be magnesium (Mg), zinc (Zn), calcium (Ca), barium (Ba), etc.

[0123] Although each of the first semiconductor layer 31 and the second semiconductor layer 32 is constituted by one layer in the drawings, the present disclosure is not limited thereto. Each of the first semiconductor layer 31 and the second semiconductor layer 32 may further include a greater number of layers. For example, depending on the material of the light-emitting layer 36, it may further include a clad layer or a tensile strain barrier reducing layer.

[0124] The light-emitting layer 36 may be disposed between the first semiconductor layer 31 and the second semiconductor layer 32. The light-emitting layer 36 may include a material having a single quantum well structure or a multi-quantum well structure. When the light-emitting layer 36 includes a material having a multi-quantum well structure, it may have a structure in which quantum layers and well layers are alternately stacked. The light-emitting layer 36 may emit light by the combination of electron-hole pairs according to the electrical signal received through the first semiconductor layer 31 and the second semiconductor layer 32. The light-emitting layer 36 may include a material such as AlGaN or AlGaInN. For example, when the light-emitting layer 36 has a multi-quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include, for example, GaN or AlInN as a material.

[0125] The light-emitting layer 36 may have a structure in which a semiconductor material having a large energy gap and a semiconductor material having a small energy gap are alternately stacked, or may include different group 3 to group 5 semiconductor materials, depending on the wavelength band of the light emitted from the light-emitting layer 36. The light from the light-emitting layer 36 is not limited to light in the blue wavelength band. In an embodiment, the light-emitting layer 36 may emit light in the red or green wavelength band.

[0126] The electrode layer 37 may be an ohmic contact electrode. However, the present invention is not limited thereto, and the electrode layer 37 may also be a Schottky contact electrode. The light-emitting element ED may include at least one electrode layer 37. The light-emitting element ED may include one or more electrode layers 37. However, the present invention is not limited thereto, and the electrode layer 37 may also be omitted.

[0127] When the light-emitting element ED is electrically connected to an electrode or a connection electrode in the display device 10, the electrode layer 37 may reduce the resistance between the light-emitting element ED and the electrode or the connection electrode. The electrode layer 37 may include a conductive metal. For example, the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).

[0128] The insulating film 38 can surround the first semiconductor layer 31, the second semiconductor layer 32, and the electrode layer described above. For example, the insulating film 38 can at least surround the light-emitting layer 36, but can also expose both end portions in the longitudinal direction of the light-emitting element ED. The cross-section of the upper surface of the insulating film 38 in a region adjacent to at least one end of the light-emitting element ED can be circular.

[0129] The insulating film 38 can include a material having insulating properties, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), or aluminum oxide (AlOx). Although the insulating film 38 is shown as a single layer in the drawings, the present disclosure is not limited thereto. In an embodiment, the insulating film 38 can be formed as a stacked multi-layer structure.

[0130] The insulating film 38 can protect the components of the light-emitting element ED. The insulating film 38 can prevent an electrical short circuit that may occur in the light-emitting layer 36 when the light-emitting layer 36 directly contacts an electrode that transmits an electrical signal to the light-emitting element ED through it. The insulating film 38 can prevent a reduction in the light-emitting efficiency of the light-emitting element ED.

[0131] The outer surface of the insulating film 38 can be treated. The light-emitting element ED can be sprayed onto the electrode in a state of being dispersed in ink and can be aligned. The surface of the insulating film 38 can be subjected to a hydrophobic treatment or a hydrophilic treatment so that the light-emitting element ED can be kept separated from other adjacent light-emitting elements ED in the ink without aggregating with them.

[0132] In the light-emitting element ED, the first semiconductor layer 31 and the second semiconductor layer 32 can be doped with dopants of different conductive types and can have a doping concentration index calculated by the following Equation 1: [Equation 1] IDC (doping concentration index) =

[0133] In Equation 1, l0 can be the position of the interface between the semiconductor layer and the light-emitting layer 36, l can be the position of the end face of the semiconductor layer opposite to the interface with the light-emitting layer 36, x can be the distance from l0 to l, and n(x) can be the doping concentration of the dopant according to the x value of the semiconductor layer. In Equation 1, n(x) is measured in atoms / cm3, and the doping concentration index IDC is measured in atoms / cm. When the semiconductor layer is the first semiconductor layer 31, l0 can be the interface position between the first semiconductor layer 31 and the light-emitting layer 36, l can be the position of the opposite end face of the first semiconductor layer 31, x can be the interface with the light-emitting layer 36, and x can be the distance or position variable increasing from l0 to l in the first semiconductor layer 31.

[0134] The doping concentration index (IDC) can be defined as the value obtained by integrating the product of the doping concentration n(x) and the distance x with respect to the distance x. Therefore, the doping concentration index IDC can have different values according to the doping concentration and the doping profile of the dopants in the semiconductor layer 31 or 32. For example, when the dopants are heavily doped into the semiconductor layer 31 or 32, the doping concentration index IDC increases as the value of n(x) increases. When the dopants in the semiconductor layer 31 or 32 have different doping concentrations n(x) according to the position or distance x from the interface l0 with the light-emitting layer 36 to the end face l opposite to the interface, the dopants in the semiconductor layer 31 or 32 can have different doping concentrations n(x) according to the doping concentration profile of the position, and the doping concentration index IDC can vary according to the doping concentration profile.

[0135] As described above, the first connection electrode CNE1 can contact one end of each light-emitting element ED, and the second connection electrode CNE2 can contact the other end of each light-emitting element ED, and the light-emitting element ED can emit light in response to the electrical signals received from the voltage lines VL1 and VL2. Each light-emitting element ED can include a first end and a second end. The first end is provided with a first semiconductor layer 31, and the second end is provided with a second semiconductor layer 32 or an electrode layer 37, and the second end is opposite to the first end. The light-emitting element ED can be classified into two types according to the connection electrode CNE contacting its first end, because the light-emitting element ED may be oriented in the opposite direction. For example, the light-emitting element ED can include a first type of light-emitting element oriented in such a way that the second end contacts the first connection electrode CNE1 and the first end contacts the second connection electrode CNE2, and a second type of light-emitting element whose orientation direction is opposite to that of the first type of light-emitting element. When the first type of light-emitting element is a light-emitting element with a forward orientation, the first type of light-emitting element can emit light in response to the electrical signals received from the voltage lines VL1 and VL2. The second type of light-emitting element can be a light-emitting element with a reverse orientation and may not emit light.

[0136] As the number of forward-oriented light-emitting elements (e.g., the first type of light-emitting element) in the light-emitting elements ED provided in each sub-pixel SPXn increases, the luminous efficiency and the manufacturing yield of the display device 10 can increase. The light-emitting element ED can have a dipole moment according to the charges of the dopants in the first semiconductor layer 31 and the second semiconductor layer 32, and as the magnitude of the dipole moment increases, the light-emitting element ED can withstand a greater force applied by the electric field. As the force applied by the electric field increases, the opposite ends of the light-emitting element ED are more likely to face the expected direction, and the luminous efficiency and the manufacturing yield of the display device 10 can increase.

[0137] In the light-emitting element ED, the first length HA of the first semiconductor layer 31 may be greater than each of the second length HB of the second semiconductor layer 32 and the third length Hc of the light-emitting layer 36. The first length HA of the first semiconductor layer 31 may be equal to or greater than approximately 80% in the total length of the light-emitting element ED. The high doping concentration index IDC of the first semiconductor layer 31 may be an important factor contributing to the large dipole moment of the light-emitting element ED.

[0138] According to an embodiment, in the light-emitting element ED, the first semiconductor layer 31 may have a doping concentration index IDC value equal to or greater than the value of the embodiment, and the dipole moment may have a large value. For example: the n-type dopant of the first semiconductor layer 31 may have a doping concentration index IDC value equal to or greater than about 2.5×1011 atoms / cm, and a plurality of forward-oriented light-emitting elements may include a first end where the first semiconductor layer 31 and a second end opposite to the first end, where the first end contacts the second connection electrode CNE2, the second end contacts the first connection electrode CNE1, and the proportion of the forward-oriented light-emitting quantity of the light-emitting elements ED provided in each sub-pixel SPXn of the display device 10 may be equal to or greater than about 60%. When the first semiconductor layer 31 of the light-emitting element ED has a doping concentration index IDC value equal to or greater than about 2.5×1011 atoms / cm, the light-emitting element ED may have a dipole moment value that enables it to receive a force of sufficient strength applied by an electric field. More than half or equal to or greater than about 60% of the light-emitting elements ED provided in each sub-pixel SPXn may be subjected to a force of sufficient strength, and thus may be forward-oriented by the electric field as expected.

[0139] However, the present invention is not limited thereto, and the number of forward-oriented light-emitting elements ED may increase as the doping concentration index IDC value of the first semiconductor layer 31 increases. In one embodiment, the doping concentration index IDC value of the first semiconductor layer 31 in the light-emitting element ED may be equal to or greater than about 4×1011 atoms / cm, where the proportion of the forward-oriented light-emitting elements provided in each sub-pixel SPXn may be equal to or greater than about 80%. As the doping concentration index IDC value of the first semiconductor layer 31 increases, therefore, the proportion of the forward-oriented light-emitting elements in the light-emitting element ED may increase, and the light-emitting efficiency and manufacturing yield of the display device 10 may increase.

[0140] In an embodiment, the first semiconductor layer 31 in the light-emitting element ED may have a substantially uniform doping concentration n(x) regardless of the position. The doping concentration index IDC may be adjusted according to the doping concentration n(x) and the first length HA of the first semiconductor layer 31. For example, the light-emitting element ED may have a length in the range of about 4 μm to about 6 μm, the first length HA of the first semiconductor layer 31 may be in the range of about 3,500 nm to about 5,000 nm, and the doping concentration n(x) of the n-type dopant may be equal to or greater than about 1×1018 atoms / cm3 regardless of the position. In an embodiment, the doping concentration n(x) of the n-type dopant in the first semiconductor layer 31 may be equal to or greater than about 6×1018 atoms / cm3 regardless of the position. For example, the doping concentration index IDC of the first semiconductor layer 31 may be equal to or greater than about 5×1011 atoms / cm, and the light-emitting element ED may have a large dipole moment.

[0141] Since the value of the doping concentration index IDC of the first semiconductor layer 31 may be a value obtained by integrating the product of the doping concentration n(x) and the distance x from the interface l0 with the light-emitting layer 36 to the end l opposite to the interface. The doping concentration n(x) of the first semiconductor layer 31 may not have to be uniform regardless of the position. In an embodiment, the first semiconductor layer 31 may include regions having different doping concentrations n(x) to have a doping concentration distribution according to the doped regions. The sum of the values of the doping concentration index IDC calculated in each region may be equal to or greater than about 2.5×1011 atoms / cm. Even if the light-emitting element ED includes regions having different doping concentrations, it may have a large dipole moment because it has a doping concentration index value equal to or greater than the value of the embodiment, and the light-emitting efficiency and the manufacturing yield may increase because the proportion of the forward-oriented light-emitting element ED increases. Therefore, the display device 10 may increase.

[0142] A method of manufacturing the display device 10 according to an embodiment will now be described with reference to other drawings.

[0143] FIGS. 7 to 15 are schematic cross-sectional views showing a method of manufacturing a light-emitting element ED according to an embodiment, and FIGS. 7 to 15 sequentially show a method of manufacturing the light-emitting element ED.

[0144] Referring to FIG. 7, the target substrate 100 includes a base substrate 110, a buffer material layer 120 disposed on the base substrate 110, and a sub-semiconductor layer 130 disposed on the buffer material layer 120. The base substrate 110 may include a sapphire substrate (Al2O3) or a transparent substrate such as glass. However, the present invention is not limited thereto, and the base substrate 110 may also be made of a conductive substrate, such as GaN, SiC, ZnO, Si, GaP, or GaAs. The thickness of the base substrate 110 is not particularly limited, but may be, for example, in the range of about 400 μm to about 1,500 μm.

[0145] A semiconductor layer is formed on the base substrate 110, and the semiconductor layer grown by the epitaxial method may be formed by a growth seed. The method of forming the semiconductor layer may include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, or metalorganic chemical vapor deposition (MOCVD), but the present invention is not limited thereto. For example: In one embodiment, the method of forming the semiconductor layer may include MOCVD.

[0146] The precursor material for forming the semiconductor layer is not particularly limited within the range of materials that can generally be selected to form the target material. For example: The precursor material may include a metal precursor, and the metal precursor includes an alkyl group, such as a methyl group or an ethyl group. For example: In the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 36 include any one of AlGaInN, GaN, AlGaN, InGaN, AlN, or InN, as in the light-emitting element ED according to an embodiment. In this embodiment, the metal precursor may be trimethylgallium (Ga(CH3)3), and may also be a compound such as trimethylaluminum (Al(CH3)3) or triethyl phosphate (C2H5)3PO4. However, the present invention is not limited thereto. A semiconductor layer may be formed using a metal precursor and a non-metal precursor through a deposition process. The method and process conditions for forming the semiconductor layer will not be described below, and the method of manufacturing a light emitter will be described in detail with respect to the light-emitting element ED and the structure of each light-emitting element ED.

[0147] The buffer material layer 120 and the sub-semiconductor layer 130 are formed on the base substrate 110, and the buffer material layer 120 and the sub-semiconductor layer 130 may reduce the lattice constant difference between the first semiconductor material layer 310 formed thereon and the base substrate 110.

[0148] For example: the buffer material layer 120 may include an undoped semiconductor and the sub-semiconductor layer 130 may include a lightly doped semiconductor. The buffer material layer 120 and the sub-semiconductor layer 130 may include material that is substantially the same as the first semiconductor material layer 310 , but may include material that is not doped with n-type or p-type, or may have a doping concentration less than the first semiconductor material layer 310 . The first semiconductor material layer 310 . In one embodiment, the buffer material layer 120 and the sub-semiconductor layer 130 may be, but are not limited to, at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN.

[0149] Refer to FIG. The layers included in the semiconductor structure 300 may, respectively, correspond to layers included in the light-emitting element ED according to embodiments. For example: these layers may include the same material as the first semiconductor layer 31 , the emitting layer 36 , the second semiconductor layer 32 , and the electrode layer 37 of the light-emitting element ED , respectively.

[0150] The doping concentration of the first semiconductor material layer 310 can be adjusted by regulating the amount of dopant injected in the method of forming the first semiconductor material layer 310 . As described above, the doping concentration of the first semiconductor material layer 310 can be adjusted such that the doping concentration index IDC of the first semiconductor layer 31 of the respective light-emitting element ED is equal to or greater than the numerical value of the embodiment.

[0151] In one embodiment, in the semiconductor structure 300 , the first semiconductor material layer 310 may have a substantially uniform doping concentration n ( In embodiments, the doping concentration n(x) of the first semiconductor material layer 310 may be equal to or greater than about 6*10 18 atoms / or greater, regardless of position. The doping concentration index IDC of the first semiconductor layer 31 in each light-emitting element ED fabricated in the subsequent method may be equal to or greater than about 5*10 11 atoms / cm, and the light-emitting element ED may have a large dipole moment.

[0152] Referring to Figures 9 to 12, semiconductor column SRs spaced from each other are formed by etching the semiconductor structure 300 . According to embodiments, etching of the semiconductor structure 300 may include forming a photomask layer 400 and a photomask pattern 500 on the semiconductor structure 300 , performing a first etching procedure of etching the photomask layer 400 along the photomask pattern 500 , and performing a second etching procedure of etching the semiconductor structure 300 along the etched photomask layer 400 .

[0153] As shown in FIG. The insulating mask layers 410 and 420 may be etched along the space between the mask patterns 500 , and the semiconductor structure 300 may be etched along the space between the portions of the etched insulation mask layers 410 and 420 . In embodiments, the mask pattern 500 may have the same diameter or width. Since the portion of the semiconductor structure 300 provided with a mask pattern 500 on it and the portion of the semiconductor structure 300 on which the mask pattern 500 is not provided form a semiconductor column SR, the diameter of the mask pattern 500 may be substantially the same as the diameter of the light-emitting element ED. Since the mask pattern 500 has the same diameter or width, the light-emitting element ED can also have substantially the same diameter.

[0154] Both the first insulating photomask layer 410 and the second insulating photomask layer 420 may include an insulating material, and the photomask pattern 500 may include a metallic material. For example: Each insulating photomask layer 410 and 420 may include silicon oxide (SiOx), silicon nitride (SiNx), or silicon nitride (SiOxNy). The mask pattern 500 may include metals such as, but not limited to: chromium (Cr).

[0155] As shown in the figure. Referring to Figures 10 to 12 , a first etching procedure and a second etching procedure were performed to etch the photomask layer 400 along the photomask pattern 500 , and the second etching procedure to etch the semiconductor structure 300 along the etched photomask layer 400 in a direction perpendicular to the upper surface of the target substrate 100 .

[0156] Each of the above etching procedures may be dry etching, wet etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), and so on. Dry etching may be applicable to vertical etching because anisotropic etching is possible. When the above etching procedure is used, the etching agent may be, but is not limited to, Cl2 or O2.

[0157] The mask layer 400 can be etched in the first etching process to form an opening, and the semiconductor structure 300 can be etched along the opening in the second etching process to form semiconductor pillars SR. In one embodiment, the first etching process and the second etching process can be, but are not limited to, dry etching and wet etching, respectively. In an embodiment, the mask layer 400 and the semiconductor structure 300 can be etched along the mask pattern 500 through a continuous etching process.

[0158] The layers of the semiconductor structure 300 can be formed into semiconductor pillars SR through an etching process. Each semiconductor pillar includes a first semiconductor layer 31, a light-emitting layer 36, a second semiconductor layer 32, and an electrode layer 37, and the semiconductor pillars SR can be spaced apart from each other through the openings inserted therebetween. During the etching process, the first semiconductor material layer 310 may not be completely etched, but the lower portion of the first semiconductor material layer 310 can be retained as a residual semiconductor layer 311, and the upper surface of the residual semiconductor layer 311 can be partially exposed and etched in the opening.

[0159] Referring to FIGS. 13 and 14, an insulating film 38 is formed to partially surround the side surfaces of each semiconductor pillar SR. The insulating film 38 can be formed by performing a third etching process of forming an insulating film 380 on the outer surface of the semiconductor pillar SR and partially removing the insulating film 380 to expose the upper surface of the semiconductor pillar SR.

[0160] The insulating film 380 can be an insulating material formed on the outer surface of the semiconductor pillar SR, and can be formed by applying an insulating material on the outer surface of the vertically etched semiconductor pillar SR or using an immersion method. However, the present invention is not limited thereto. For example, the insulating film 380 can be formed by atomic layer deposition (ALD) or CVD.

[0161] The insulating film 380 can be formed not only on the side surfaces and the upper surface of the semiconductor pillar SR, but also on the residual semiconductor layer 311 exposed between the spaced-apart semiconductor pillars SR. The insulating film 380 can be partially removed by a method such as dry etching or back etching as anisotropic etching. In the figure, the upper surface of the insulating film 380 is removed to expose the electrode layer 37, and the electrode layer 37 can also be partially removed during this process. For example, the thickness of the electrode layer 37 of each finally manufactured light-emitting element 30 can be smaller than the thickness of the electrode material layer 370 formed during the manufacturing process of the light-emitting element ED.

[0162] In the drawing, the upper surface of the electrode layer 37 is partially exposed, and the upper surface of the insulating film 38 is flat, but the present invention is not limited thereto. In an embodiment, the outer surface of each insulating film 38 may be partially curved in a region surrounding the electrode layer 37. During the partial removal of the insulating film 380, not only the upper surface of the insulating film but also the side surface 380 of the insulating film may be partially removed. Therefore, the end face of each insulating film 38 surrounding layer may be partially etched. For example, since the upper surface of the insulating film 380 is removed, the outer surface of the insulating film 38 adjacent to the electrode layer 37 in each light-emitting element 30 may be partially removed.

[0163] As shown in FIG. 15, the semiconductor column SR formed with the insulating film 38 is separated from the residual semiconductor layer 311 to manufacture the light-emitting element ED. The semiconductor column SR may be separated along the separation surface SL of the portion of the lower end of the first semiconductor layer 31 connected to the residual semiconductor layer 311. The separation surface SL may be parallel to the upper surface of the residual semiconductor layer 311 exposed in the opening. The length of the first semiconductor layer 31 of the finally manufactured light-emitting element ED may be shorter than the length of the first semiconductor material layer 310 of the semiconductor structure 300. The doping concentration index IDC of each first semiconductor layer 31 may vary according to the distance from the interface with the light-emitting layer 36 to the end face opposite to the interface. The doping concentration of the dopant and the length of the first semiconductor material layer 310 may be adjusted in consideration of the doping concentration index IDC value of the first semiconductor layer 31 in each manufactured light-emitting element ED.

[0164] Hereinafter, embodiments of the display device 10 will be described with reference to other drawings.

[0165] FIG. 16 and FIG. 17 are each a schematic cross-sectional view of light-emitting elements ED1 and ED2 according to an embodiment.

[0166] Referring to FIGS. 16 and 17, in each of the light-emitting elements ED1 and ED2 according to a plurality of embodiments, the first semiconductor layer 31 may include doping regions DA1 and DA2 having different doping concentrations n(x). The first semiconductor layer 31 may include a first doping region DA1 and a second doping region DA2, and the doping concentration of the n-type dopant in the first doping region DA1 may be different from the doping concentration of the n-type dopant in the second doping region. The first doping region DA1 may contact the light-emitting layer 36, and the second doping region DA2 may contact the first doping region DA1.

[0167] The doping concentrations n(x) of the n-type dopants in the first doping region DA1 and the second doping region DA2 can be different from each other, and the doping concentration n(x) of the first semiconductor layer 31 can have a distribution that varies according to the distance x from the first interface l0 between the light-emitting layer 36 and the first doping region DA1. The doping concentration n(x) from the first interface l0 to the second interface l1 between the first doping region DA1 and the second doping region DA2 can be the doping concentration of the n-type dopants in the first doping region DA1, and the concentration n(x) from the second interface l1 to the end face l2 of the first semiconductor layer 31 opposite to the first interface l0 can be the doping concentration of the n-type dopants in the second doping region DA2.

[0168] Therefore, the doping concentration index IDC of the first semiconductor layer 31 can be defined as the sum of the doping concentration index value of the first doping region DA1 and the doping concentration index value of the second doping region DA2. For example: The doping concentration index IDC of the first semiconductor layer 31 can be the sum of the doping concentration index value from the first interface l0 to the second interface l1 and the doping concentration index IDC value from the second interface l1 to the end face l2. The doping concentration index IDC between the first interface l0 and the second interface l1 can be the integral value of the doping concentration n(x) of the first doping region DA1 according to the distance x, and the doping concentration index value IDC between the second interface l1 and the end face l2 of the first semiconductor layer 31 can be the integral value of the doping concentration n(x) of the second doping region DA2 according to the distance x. The doping concentration index IDC of the first semiconductor layer 31 can be expressed as Equation 2: [Equation 2] IDC (doping concentration index) =

[0169] In Equation 2, l0 can be the position of the interface between the first doping region DA1 of the first semiconductor layer 31 and the light-emitting layer 36, l1 can be the position of the interface between the first doping region DA1 and the second doping region DA2, l2 can be the position of the end face of the first semiconductor layer 31 opposite to the interface between the first doping region DA1 and the light-emitting layer 36, x can be the distance from l0 to l2, n1(x) can be the doping concentration of the dopants according to the x value of the first doping region DA1, and n2(x) can be the doping concentration of the dopants according to the x value of the second doping region DA2.

[0170] Since the first semiconductor layer 31 includes a first doping region DA1 and a second doping region DA2, the doping concentration index IDC of the first semiconductor layer 31 can vary according to the doping concentration distribution and the length of each of the doping regions DA1 and DA2. The lengths HA1 and HA2 of the first doping region DA1 and the second doping region DA2 can be adjusted respectively according to the doping concentrations of the doping regions DA1 and DA2. The first doping region DA1 and the second doping region DA2 can have different lengths HA1 and HA2 respectively. For example, as shown in the embodiment of FIG. 16, the length HA1 of the first doping region DA1 can be greater than the length HA2 of the second doping region DA2. For example, the length HA1 of the first doping region DA1 can be in the range of about 2,000 nm to about 2,500 nm, and the length HA2 of the second doping region DA2 can be in the range of about 1,500 nm to about 2,300 nm.

[0171] However, the present invention is not limited thereto. The length HA1 of the first doping region DA1 can be less than the length HA2 of the second doping region DA2, as shown in the embodiment of FIG. 17. For example, the length HA1 of the first doping region DA1 can be in the range of about 1,500 nm to about 2,300 nm, and the length HA2 of the second doping region DA2 can be in the range of about 2,000 nm to about 2,500 nm. Even if the first doping region DA1 and the second doping region DA2 have relatively small lengths HA1 and HA2, each of the lengths HA1 and HA2 of the first doping region DA1 and the second doping region DA2 can be greater than the length HB of the second doping region, the length Hc of the semiconductor layer 32, and the length of the light emitting layer 36 and the electrode layer 37.

[0172] In the embodiment where the first doping region DA1 is smaller than the second doping region DA2, since the proportion of the second doping region DA2 of the first semiconductor layer 31 having a high doping concentration in the light emitting element ED1 of FIG. 16 is smaller than that in the light emitting element ED2 of FIG. 17, the doping concentration index IDC value of the first semiconductor layer 31 can also be smaller than the doping concentration index IDC value of the first semiconductor layer 31 in the light emitting element ED1 of FIG. 16. However, each of the light emitting elements ED1 and ED2 can have a doping concentration n(x) such that the doping concentration index IDC value of the first semiconductor layer 31 has a value greater than about 2.5*1011 atoms / cm, regardless of the lengths HA1 and HA2 of the doping regions DA1 and DA2.

[0173] The light emitting elements ED1 and ED2 of FIGS. 16 and 17 can be manufactured by adjusting the content of dopants in the method of forming the first semiconductor material layer 310 during the manufacturing method.

[0174] FIG. 18 and FIG. 19 are schematic cross-sectional views showing a part of a method of manufacturing the light-emitting element ED1 of FIG. 16.

[0175] Referring to FIGS. 18 and 19, in the process of forming the first semiconductor material layer 310 on the sub-semiconductor layer 130, the base layer 310_L of the first semiconductor material layer 310 may be formed first, and then the upper layer 310_U may be formed by adjusting the content of dopants to be implanted. The first semiconductor material layer 310 may include the upper layer 310_U and the base layer 310_L having different doping concentrations, and the upper layer 310_U and the base layer 310_L may form the first doped region DA1 and the second doped region DA2 of the light-emitting element ED1 or ED2, respectively.

[0176] According to an embodiment, in the light-emitting element ED1 or ED2, the first semiconductor layer 31 may include the doped regions DA1 and DA2 having different doping concentrations, and thus has a doping concentration distribution according to position. However, the doping concentration of each of the doped regions DA1 and DA2 may be adjusted such that the value of the doping concentration index IDC of the first semiconductor layer 31 is equal to or greater than the value of the embodiment. Since the display device 10 includes the light-emitting element ED1 or ED2 having the doped regions DA1 and DA2, the proportion of the forward-oriented light-emitting element ED can be increased, and the light-emitting efficiency and the manufacturing yield can be improved.

[0177] According to an embodiment, in the semiconductor structure 300, the doping concentration of the n-type dopants in the upper layer 310_U of the first semiconductor material layer 310 or the first doped region DA1 may be equal to or greater than about 7×1018 atoms / cm3, and the doping concentration of the n-type dopants in the base layer 310_L of the first semiconductor material layer 310 or the second doped region DA2 may be equal to or greater than about 8×1018 atoms / cm3. The first doped region DA1 or the upper layer 310_U may have a length in the range of about 2,000 nm to about 2,500 nm, and the second doped region DA2 or the base layer 310_L may have a length in the range of about 1,500 nm to about 2,300 nm, and vice versa. When each of the layers 310_U and 310_L of the first semiconductor material layer 310 has the above-mentioned doping concentration n(x) and length HA1 or HA2, the doping concentration index IDC of the first semiconductor layer 31 in the light-emitting element ED1 or ED2 manufactured from the semiconductor structure 300 may be equal to or greater than about 2.5×1011 atoms / cm.

[0178] The first semiconductor layer 31 may further include a larger number of doped regions and may have more doping concentration distributions according to position.

[0179] Figures 20 and 21 are schematic cross-sectional views of the light-emitting elements ED3 and ED4 according to the embodiments, respectively.

[0180] Referring to FIGS. 20 and 21, in each of the light-emitting elements ED3 and ED4 according to the embodiments, the first semiconductor layer 31 may include doping regions DA1 to DA3. The first semiconductor layer 31 may include a first doping region DA1, a second doping region DA2, and a third doping region DA3. The first doping region DA1 is in contact with the light-emitting layer 36, the second doping region DA2 is in contact with the first doping region DA1, and the doping concentration of the n-type dopants in the second doping region DA2 is different from the doping concentration of the n-type dopants in the first doping region DA1. The third doping region DA3 is in contact with the second doping region DA2, and the doping concentration of the n-type dopants in the third doping region DA3 is different from the doping concentration of the n-type dopants in the second doping region DA2. In the first semiconductor layer 31, the first doping region DA1, the second doping region DA2, and the third doping region DA3 may be provided in sequence from the light-emitting layer 36 to the end face.

[0181] The doping regions DA1 to DA3 may have different doping concentrations n(x), and the doping concentration n(x) of the first semiconductor layer 31 may have a distribution that changes according to the distance x from the first interface l0 between the light-emitting layer 36 and the first doping region DA1. The doping concentration n(x) from the first interface l0 to the second interface l1 between the first doping region DA1 and the second doping region DA2 may be the doping concentration of the n-type dopants in the first doping region DA1. The doping concentration n(x) from the second interface l1 to the third interface l2 between the second doping region DA2 and the third doping region DA3 may be the doping concentration of the n-type dopants in the second doping region DA2. The doping concentration n(x) from the third interface l2 to the end face l3 of the first semiconductor layer 31 may be the doping concentration of the n-type dopants in the third doping region DA3. Therefore, the doping concentration index IDC of the first semiconductor layer 31 may be defined as the sum of the doping concentration index values of the first doping region DA1, the doping concentration index values of the second doping region DA2, and the doping concentration index values of the third doping region DA3. The doping concentration index IDC of the first semiconductor layer 31 may be expressed by the following Equation 3: [Equation 3] IDC (doping concentration index) =

[0182] In Equation 3, l0 may be the position of the interface between the first doped region DA1 of the first semiconductor layer 31 and the light-emitting layer 36, l1 may be the position of the interface between the first doped region DA1 and the second doped region DA2, l2 may be the position of the interface between the second doped region DA2 and the third doped region DA3, l3 may be the position of the end face of the first semiconductor layer 31 relative to the interface between the first doped region DA1 and the light-emitting layer 36, x may be the distance from l0 to l3, n1(x) may be the doping concentration of dopants according to the x value of the first doped region DA1, n2(x) may be the doping concentration of dopants according to the x value of the second doped region DA2, and n3(x) may be the doping concentration of dopants according to the x value of the third doped region DA3.

[0183] Since the first semiconductor layer 31 includes a greater number of doped regions DA1 to DA3, the doping concentration index IDC of the first semiconductor layer 31 may vary according to the doping concentration distribution and the lengths of each of the doped regions DA1 to DA3. The lengths HA1 to HA3 of the first to third doped regions DA1 to DA3 may be adjusted respectively according to the doping concentrations of the doped regions DA1 to DA3. For example: as in the embodiment of FIG. 20, the length HA1 of the first doped region DA1 may be greater than each of the length HA2 of the second doped region DA2 and the length HA3 of the third doped region DA3, and the length HA2 of the second doped region DA2 may be less than the length HA3 of the third doped region DA3. However, the present invention is not limited thereto, the length HA1 of the first doped region DA1 may be less than each of the length HA2 of the second doped region DA2 and the length HA3 of the third doped region DA3, and the length HA2 of the second doped region DA2 may be greater than the length HA3 of the third doped region DA3, as shown in the embodiment of FIG. 21. However, the length of the shortest doped region among the doped regions DA1 to DA3 may be at least greater than the length HB of the second semiconductor layer 32, the length Hc of the light-emitting layer 36, and the length of the electrode layer 37.

[0184] The relationship between the dopant concentration magnitudes of the doped regions DA1 to DA3 may vary according to the length relationship between the doped regions DA1 to DA3. As shown in the embodiment of FIG. 20, when the length HA1 of the first doped region DA1 is the largest, the doping concentration of the first doped region DA1 may be greater than each of the doping concentration of the second doped region DA2 and the doping concentration of the third doped region DA3, and the doping concentration of the second doped region DA2 may be greater than the doping concentration of the third doped region DA3. For example: the first semiconductor layer 31 may have a doping concentration distribution in which the doping concentration n(x) decreases from the first interface l0 with the light-emitting layer 36 towards the end face l3. However, the first semiconductor layer 31 may have the same doping concentration regardless of the position within the same doped region DA1, DA2, or DA3.

[0185] Similar to those described with reference to other figures above, the light-emitting element ED3 according to the current embodiment can also be manufactured by adjusting the doping concentration distribution of the first semiconductor material layer 310 of the semiconductor structure 300. The light-emitting element ED3 can be manufactured through the semiconductor structure 300, where each layer of the first semiconductor material layer 310 is adjusted to have different doping concentrations and lengths.

[0186] In an embodiment, in the semiconductor structure 300, the doping concentration of n-type dopants in the first doping region of the first semiconductor material layer 310 can be equal to or greater than about 6*10^18 atoms / cm3, and can be equal to or less than about 6*10^18 atoms / cm3 in the second and third doping regions. The first semiconductor material layer 310 can also have different doping regions DA1 to DA3, such as the first semiconductor layer 31 of the light-emitting element ED3, and the doping regions of the first semiconductor material layer 310 can correspond to the doping regions DA1 to DA3 for the light-emitting elements respectively.

[0187] According to an embodiment, in the first semiconductor layer 31 of the light-emitting element ED3 and the first semiconductor material layer 310 of the semiconductor structure 300, the length HA1 of the first doping region DA1 can be in the range of about 1,800 nm to 2,500 nm, the length HA2 of the second doping region DA2 can be in the range of about 500 nm to about 1,200 nm, and the length HA3 of the third doping region DA3 can be in the range of about 1,500 to about 2,200 nm. When each doping region DA1 to DA3 has the above doping concentration n(x) and length HA1, HA2, or HA3, the doping concentration index IDC of the first semiconductor layer 31 of the light-emitting element ED3 can be equal to or greater than about 2.5*10^11 atoms / cm3.

[0188] When the length HA1 of the first doping region DA1 is the smallest, as shown in the embodiment of FIG. 21, the doping concentration of the first doping region DA1 can be less than each of the doping concentrations of the second doping region DA2 and the third doping region DA3, and the doping concentration of the second doping region DA2 can be less than each of the doping concentrations of the first doping region DA1 and the third doping region DA3. For example: the first semiconductor layer 31 can have a doping concentration distribution where the doping concentration n(x) decreases from the first interface l0 with the light-emitting layer 36 towards the end face l3 or a doping concentration distribution where the doping concentration n(x) decreases and then increases.

[0189] In multiple embodiments, the doping concentration of the first doping region DA1 can be less than each of the doping concentration of the second doping region DA2 and the doping concentration of the third doping region DA3, and the doping concentration of the second doping region DA2 can be less than the doping concentration of the third doping region DA3. For example: in the third doping region DA3, the doping concentration of n-type dopants can be equal to or greater than about 6 * 10^18 atoms / cm3, and the doping concentration of n-type dopants can be equal to or less than about 6 * 10^18 atoms / cm3. It is 6 * 10^18 atoms / cm3 in the first doping region DA1 and the second doping region DA2. The length HA1 of the first doping region DA1 can be in the range of about 500 nm to about 1,200 nm, the length HA2 of the second doping region DA2 can be in the range of about 1,800 nm to about 2,500 nm, and the length HA3 of the third doping region DA3 can be in the range of about 1,500 nm to about 2,200 nm.

[0190] In other embodiments, both the doping concentration of the first doping region DA1 and the doping concentration of the third doping region DA3 can be greater than the doping concentration of the second doping region DA2, and the doping concentration of the first doping region DA1 can be equal to the doping concentration of the third doping region DA3. For example: the doping concentration of n-type dopants in the first doping region DA1 and the doping concentration of n-type dopants in the third doping region DA3 can each independently be equal to or greater than about 6 * 10^18 atoms / cm3, and the doping concentration of n-type dopants in the second doping region DA2 can be equal to or less than about 6 * 10^18 atoms / cm3. The length HA1 of the first doping region DA1 can be in the range of about 500 nm to about 1,200 nm, the length HA2 of the second doping region DA2 can be in the range of about 1,800 nm to about 2,500 nm, and the length HA3 of the third doping region DA3 can be in the range of about 1,500 nm to about 2,200 nm. When each doping region DA1 to DA3 has the above doping concentration n(x) and length HA1, HA2, or HA3, the doping concentration index IDC of the first semiconductor layer 31 of the light-emitting element ED3 can be greater than about 2.5 * 10^11 atoms / cm.

[0191] FIG. 22 is an enlarged view of the second semiconductor layer 32 of the light-emitting element ED5 according to an embodiment.

[0192] Referring to FIG. 22, in the light-emitting element ED5 according to the embodiment, the second semiconductor layer 32 may further include doping regions DA4 and DA5 having different doping concentrations. For example, the second semiconductor layer 32 may include a fourth doping region DA4 and a fifth doping region DA5, and the fifth doping region DA5 has a doping concentration of a p-type dopant different from that of the fourth doping region DA4. The fourth doping region DA4 may be in contact with the light-emitting layer 36, and the fifth doping region DA5 may be disposed between the fourth doping region DA4 and the electrode layer 37. As in Equation 1 above, the doping concentration index of the second semiconductor layer 32 may be defined as a value obtained by integrating the product of the doping concentration n(x) and the distance x from the interface between the fourth doping region DA4 and the light-emitting layer 36 to the interface between the fifth doping region DA5 and the electrode. In the second semiconductor layer 32, the doping concentration of each of the doping regions DA4 and DA5 may be adjusted to have a doping concentration index equal to or greater than the value of the embodiment, so that the dipole moment of the light-emitting element ED5 may have a larger value.

[0193] The shape and material of the light-emitting element ED are not limited to those in FIG. 5. In the embodiment, the light-emitting element ED may include more layers or may have a different shape.

[0194] FIG. 23 is a schematic diagram of a light-emitting element ED6 according to an embodiment, and FIG. 24 is a schematic cross-sectional view of the light-emitting element ED6 in FIG. 23. FIG. 24 shows a schematic cross-section of the light-emitting element ED6 taken along the longitudinal axis direction in FIG. 23 and shows the stacking of the semiconductor layers.

[0195] Referring to FIGS. 23 and 24, the light-emitting element ED6 according to the embodiment may further include a third semiconductor layer 33, a fourth semiconductor layer 34, and a fifth semiconductor layer 35. The third semiconductor layer 33 is disposed between the first semiconductor layer 31 and the light-emitting layer 36, the fourth semiconductor layer 34 is disposed between the first semiconductor layer 34 and the light-emitting layer 36, and the fifth semiconductor layer 35 is disposed between the light-emitting layer 36 and the second semiconductor layer 32. The light-emitting element ED6 in FIGS. 23 and 24 is different from the embodiment in FIG. 5 in that the light-emitting element ED6 further includes semiconductor layers 33 to 35 and electrode layers 37A and 37B, and the light-emitting layer 36 contains different elements. Any redundant description will be omitted, and the differences will be described below.

[0196] In the light-emitting element ED of FIG. 5, the light-emitting layer 36 may include nitrogen (N) to emit blue or green light. In another embodiment, in the light-emitting element ED6 of FIG. 23, each of the light-emitting layer 36 and the other semiconductor layers may be a semiconductor including phosphorus (P). The light-emitting element ED6 according to the embodiment may emit red light having a center wavelength band in the range of about 620 nm to about 750 nm.

[0197] The first semiconductor layer 31 may be an n-type semiconductor layer and may include a semiconductor material having the chemical formula InxAlyGa1-x-yP (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1). The first semiconductor layer 31 may be any one or more of n-type doped InAlGaP, GaP, AlGaP, InGaP, AlP, or InP. For example, the first semiconductor layer 31 may be n-AlGaInP doped with n-type Si.

[0198] The second semiconductor layer 32 may be a p-type semiconductor layer and may include a semiconductor material having the chemical formula InxAlyGa1-x-yP (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1). The second semiconductor layer 32 may be any one or more of p-type doped InAlGaP, GaP, AlGaP, InGaP, AlP, or InP. For example, the second semiconductor layer 32 may be p-GaP doped with p-type Mg.

[0199] The light-emitting layer 36 may be made of a material including phosphorus (P) and may include a material having a single or multiple quantum well structure to emit light in a specific wavelength band. The quantum layer of the light-emitting layer 36 may include AlGaP or AlInGaP, and the well layer may include a material such as GaP or AlInP. For example, the light-emitting layer 36 may include AlGaInP as the quantum layer and AlInP as the well layer to emit red light having a center wavelength band in the range of about 620 nm to about 750 nm.

[0200] The light-emitting element ED6 may include a clad layer disposed adjacent to the light-emitting layer 36. As shown in the figure, the third semiconductor layer 33 and the fourth semiconductor layer 34 below and above the light-emitting layer 36 disposed between the first semiconductor 31 and the second semiconductor layer 32 may be the clad layer.

[0201] The third semiconductor layer 33 may be disposed between the first semiconductor layer 31 and the light-emitting layer 36. Similar to the first semiconductor layer 31, the third semiconductor layer 33 may be an n-type semiconductor and may include a semiconductor material InxAlyGa1-x-yP (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1) having a chemical formula. For example, the first semiconductor layer 31 may be n-AlGaInP and the third semiconductor layer 33 may be n-AlInP, but the present invention is not limited thereto.

[0202] The fourth semiconductor layer 34 may be disposed between the light-emitting layer 36 and the second semiconductor layer 32. Similar to the second semiconductor layer 32, the fourth semiconductor layer 34 may be a p-type semiconductor and may include a semiconductor material InxAlyGa1-x-yP (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1) having a chemical formula. For example, the second semiconductor layer 32 may be p-GaP and the fourth semiconductor layer 34 may be p-AlInP.

[0203] The fifth semiconductor layer 35 may be disposed between the fourth semiconductor layer 34 and the second semiconductor layer 32. Similar to the second semiconductor layer 32 and the fourth semiconductor layer 34, the fifth semiconductor layer 35 may be a p-type doped semiconductor. In an embodiment, the fifth semiconductor layer 35 may reduce the difference in lattice constants between the fourth semiconductor layer 34 and the second semiconductor layer 32. The fifth semiconductor layer 35 may be an tensile strain barrier reducing layer. For example, the fifth semiconductor layer 35 may include, but is not limited to, p-GaInP, p-AlInP, or p-AlGaInP.

[0204] The first electrode layer 37A and the second electrode layer 37B may be respectively disposed on the surfaces of the first semiconductor layer 31 and the second semiconductor layer 32. The first electrode layer 37A may be disposed on the lower surface of the first semiconductor layer 31, and the second electrode layer 37B may be disposed on the upper surface of the second semiconductor layer 32. However, the present invention is not limited thereto, and at least any one of the first electrode layer 37A and the second electrode layer 37B may be omitted. For example, in the light-emitting element ED6, the first electrode layer 37A may not be disposed on the lower surface of the first semiconductor layer 31, and only one second electrode layer 37B may be disposed on the upper surface of the second semiconductor layer 32. The light-emitting element ED6 according to the embodiment may emit red light by including a larger number of semiconductor layers.

[0205] The light-emitting element according to the embodiment includes a semiconductor layer having a doping concentration index value equal to or greater than the value of the embodiment to have a large dipole moment.

[0206] The display device according to the embodiment includes the above light-emitting element. Accordingly, the proportion of the forward-oriented light-emitting elements can be increased, and the light-emitting efficiency and the manufacturing yield can be increased.

[0207] Embodiments have been disclosed in this specification, and although multiple terms have been used, they are only used in a general and descriptive sense and are not intended to be limiting. In some cases, features, characteristics, and / or elements described in connection with the embodiments may be used alone or in combination with other features, characteristics, and / or elements described, unless otherwise specifically stated, by those of ordinary skill in the art to which the present invention pertains. Therefore, those of ordinary skill in the art to which the present invention pertains will understand that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as set forth in the claims.

Brief Description of the Drawings

[0038] The above and other aspects and features of the present invention will become more apparent from the following detailed description of its embodiments with reference to the drawings, in which: FIG. 1 is a schematic top view of a display device according to an embodiment; FIG. 2 is a schematic top view of a pixel of a display device according to an embodiment; FIG. 3 is a schematic cross-sectional view taken along line N1-N1' of FIG. 2; FIG. 4 is a schematic cross-sectional view taken along line N2-N2' of FIG. 3; FIG. 5 is a schematic diagram of a light-emitting element according to an embodiment; FIG. 6 is a schematic cross-sectional view of the light-emitting element of FIG. 5; FIGS. 7 to 15 are schematic cross-sectional views showing a method of manufacturing a light-emitting element according to an embodiment; FIGS. 16 and 17 are schematic cross-sectional views of light-emitting elements according to multiple embodiments; FIGS. 18 and 19 are schematic cross-sectional views showing a part of a method of manufacturing the light-emitting element of FIG. 16; FIGS. 20 and 21 are schematic cross-sectional views of light-emitting elements according to multiple embodiments; FIG. 22 is an enlarged view of a second semiconductor layer of a light-emitting element according to an embodiment; FIG. 23 is a schematic diagram of a light-emitting element according to an embodiment; and FIG. 24 is a schematic cross-sectional view of the light-emitting element of FIG. 23.

Claims

1. A light-emitting element, comprising: A first semiconductor layer, doped with an n-type dopant; A second semiconductor layer, doped with a p-type dopant; A light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer; and an insulating film surrounds the first semiconductor layer, the second semiconductor layer and the light-emitting layer, wherein a doping concentration index of the first semiconductor layer, as expressed by Equation 1, is equal to or greater than 2.5 * 10¹¹ atoms / cm: [Equation 1] IDC (Doping Concentration Index) = Wherein in Equation 1, l0 is the position of an interface between the first semiconductor layer and the light-emitting layer, l is the position of an end face opposite to the interface between the first semiconductor layer and the light-emitting layer, x is the distance from l0 to l, and n(x) is the doping concentration of a dopant based on a value of x of the first semiconductor layer; The first semiconductor layer includes: a first doped region; And a second doped region having a higher doping concentration of the n-type dopant than the first doped region.

2. The light-emitting element as claimed in claim 1, wherein the doping concentration index of the first semiconductor layer is equal to or greater than 4*10¹¹ atoms / cm.

3. The light-emitting element as claimed in claim 1, wherein the first doped region is in contact with the light-emitting layer.

4. The light-emitting element as claimed in claim 1, wherein a length of the first doped region is different from a length of the second doped region; and the first doped region is in contact with the light-emitting layer.

5. A light-emitting element, comprising: A first semiconductor layer, doped with an n-type dopant; A second semiconductor layer, doped with a p-type dopant; A light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer; and an insulating film surrounds the first semiconductor layer, the second semiconductor layer and the light-emitting layer, wherein a doping concentration index of the first semiconductor layer, as expressed by Equation 1, is equal to or greater than 2.5 * 10¹¹ atoms / cm: [Equation 1] IDC (Doping Concentration Index) = Wherein in Equation 1, l0 is the position of an interface between the first semiconductor layer and the light-emitting layer, l is the position of an end face opposite to the interface between the first semiconductor layer and the light-emitting layer, x is the distance from l0 to l, and n(x) is the doping concentration of a dopant based on a value of x of the first semiconductor layer; The first semiconductor layer includes: a first doped region in contact with the light-emitting layer; a second doped region in contact with the first doped region, wherein the doping concentration of the n-type dopant in the second doped region is different from the doping concentration of the n-type dopant in the first doped region; and a third doped region in contact with the second doped region, wherein the doping concentration of the n-type dopant in the third doped region is different from the doping concentration of the n-type dopant in the second doped region.

6. The light-emitting element as claimed in claim 5, wherein the first doped region is longer than each of the second and third doped regions, and the second doped region is shorter than the third doped region.

7. The light-emitting element as claimed in claim 6, wherein the doping concentration of the n-type dopant in the first doped region is greater than the doping concentration of the n-type dopant in each of the second and third doped regions, and the doping concentration of the n-type dopant in the second doped region is greater than the doping concentration of the n-type dopant in the third doped region.

8. The light-emitting element as claimed in claim 5, wherein the first doped region is shorter than each of the second and third doped regions, and the second doped region is longer than the third doped region.

9. The light-emitting element as claimed in claim 8, wherein the doping concentration of the n-type dopant in the first doped region is less than the doping concentration of the n-type dopant in the second doped region, and the doping concentration of the n-type dopant in the second doped region is less than the doping concentration of the n-type dopant in the third doped region.

10. The light-emitting element as claimed in claim 8, wherein the doping concentration of the n-type dopant in the first doped region is greater than the doping concentration of the n-type dopant in the second doped region, and the doping concentration of the n-type dopant in the third doped region is the same as the doping concentration of the n-type dopant in the first doped region.

11. A display device comprising: A first electrode and a second electrode are disposed on a substrate and spaced apart from each other; A first insulating layer is disposed on the first electrode and the second electrode; a plurality of light-emitting elements are disposed on the first insulating layer and on the first electrode and the second electrode; a first connecting electrode is in contact with one end of each of the plurality of light-emitting elements; and a second connecting electrode, contacting the other end of each of the plurality of light-emitting elements, wherein each of the plurality of light-emitting elements includes: a first semiconductor layer doped with an n-type dopant; a second semiconductor layer doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and an insulating film surrounding the first semiconductor layer, the second semiconductor layer and the light-emitting layer, wherein a doping concentration index of the first semiconductor layer, as expressed by Equation 1, is equal to or greater than 2.5*10¹¹ atoms / cm or above: a number of the plurality of light-emitting elements includes a plurality of first ends and a plurality of second ends, the plurality of first ends being disposed of the first semiconductor layer, the plurality of second ends being opposite to the plurality of first ends, wherein the first ends contact the second connecting electrode and the second ends contact the first connecting electrode, and a proportion of the number of the plurality of light-emitting elements is equal to or greater than 60%: [Equation 1] IDC (Doping Concentration Index) = Wherein in Equation 1, l0 is the position of an interface between the first semiconductor layer and the light-emitting layer, l is the position of an end face opposite to the interface between the first semiconductor layer and the light-emitting layer, x is the distance from l0 to l, and n(x) is the doping concentration of a dopant based on a value of x of the first semiconductor layer; wherein the first semiconductor layer includes: a first doped region; and a second doped region, wherein the doping concentration of the n-type dopant in the second doped region is greater than the doping concentration of the n-type dopant in the first doped region.

12. The display device of claim 11, wherein the doping concentration index of the first semiconductor layer in each of the plurality of light-emitting elements is equal to or greater than 4*10¹¹ atoms / cm, and the proportion of the number of the plurality of light-emitting elements is 80% or more.

13. The display device of claim 11, wherein the first doped region is in contact with the light-emitting layer and the first doped region is longer than the second doped region.

14. A display device comprising: A first electrode and a second electrode are disposed on a substrate and spaced apart from each other; A first insulating layer is disposed on the first electrode and the second electrode; a plurality of light-emitting elements are disposed on the first insulating layer and on the first electrode and the second electrode; a first connecting electrode is in contact with one end of each of the plurality of light-emitting elements; and a second connecting electrode, contacting the other end of each of the plurality of light-emitting elements, wherein each of the plurality of light-emitting elements includes: a first semiconductor layer doped with an n-type dopant; a second semiconductor layer doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and an insulating film surrounding the first semiconductor layer, the second semiconductor layer and the light-emitting layer, wherein a doping concentration index of the first semiconductor layer, as expressed by Equation 1, is equal to or greater than 2.5*10¹¹ atoms / cm or above: a number of the plurality of light-emitting elements includes a plurality of first ends and a plurality of second ends, the plurality of first ends being disposed of the first semiconductor layer, the plurality of second ends being opposite to the plurality of first ends, wherein the first ends contact the second connecting electrode and the second ends contact the first connecting electrode, and a proportion of the number of the plurality of light-emitting elements is equal to or greater than 60%: [Equation 1] IDC (Doping Concentration Index) = Wherein in Equation 1, l0 is the position of an interface between the first semiconductor layer and the light-emitting layer, l is the position of an end face opposite to the interface between the first semiconductor layer and the light-emitting layer, x is the distance from l0 to l, and n(x) is the doping concentration of a dopant based on a value of x of the first semiconductor layer; wherein the first semiconductor layer includes: a first doped region in contact with the light-emitting layer, a second doped region in contact with the first doped region, wherein the doping concentration of the n-type dopant in the second doped region is different from the doping concentration of the n-type dopant in the first doped region, and a third doped region in contact with the second doped region, wherein the doping concentration of the n-type dopant in the third doped region is different from the doping concentration of the n-type dopant in the second doped region.

15. The display device of claim 14, wherein the first doped region is shorter than each of the second and third doped regions, and the second doped region is longer than the third doped region, the doping concentration of the n-type dopant in the first doped region is greater than the doping concentration of the n-type dopant in each of the second and third doped regions, and the doping concentration of the n-type dopant in the second doped region is greater than the doping concentration of the n-type dopant in the third doped region.

16. The display device of claim 14, wherein the first doped region is shorter than each of the second and third doped regions, the second doped region is longer than the third doped region, the doping concentration of the n-type dopant in the first doped region is less than the doping concentration of the n-type dopant in the second doped region, and the doping concentration of the n-type dopant in the second doped region is less than the doping concentration of the n-type dopant in the third doped region.

17. A semiconductor structure comprising: A first semiconductor layer, doped with an n-type dopant; A second semiconductor layer, doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and an insulating film surrounding the first semiconductor layer, the second semiconductor layer, and the light-emitting layer, wherein the doping concentration of the n-type dopant in the first semiconductor layer is equal to or greater than 1*10¹⁸ atoms / cm³; wherein the first semiconductor layer includes: a first doped region; And a second doped region, wherein the doping concentration of the n-type dopant in the second doped region is greater than the doping concentration of the n-type dopant in the first doped region.

18. The semiconductor structure as claimed in claim 17, wherein the doping concentration of the n-type dopant in the first semiconductor layer is equal to or greater than 6*10¹⁸ atoms / cm³.

19. The semiconductor structure of claim 17, wherein the first doped region is in contact with the light-emitting layer.

20. The semiconductor structure of claim 17, wherein a length of the first doped region is different from a length of the second doped region, and the first doped region is in contact with the light-emitting layer.

21. A semiconductor structure comprising: A first semiconductor layer, doped with an n-type dopant; A second semiconductor layer, doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and an insulating film surrounding the first semiconductor layer, the second semiconductor layer, and the light-emitting layer, wherein the doping concentration of the n-type dopant in the first semiconductor layer is equal to or greater than 1*10¹⁸ atoms / cm³; wherein the first semiconductor layer includes: a first doped region in contact with the light-emitting layer; a second doped region in contact with the first doped region, wherein the doping concentration of the n-type dopant in the second doped region is different from the doping concentration of the n-type dopant in the first doped region; and a third doped region in contact with the second doped region, wherein the doping concentration of the n-type dopant in the third doped region is different from the doping concentration of the n-type dopant in the second doped region.

22. The semiconductor structure of claim 21, wherein the first doped region is longer than each of the second and third doped regions, and the second doped region is shorter than the third doped region.

23. The semiconductor structure of claim 22, wherein the doping concentration of the n-type dopant in the first doped region is equal to or greater than 6*10¹⁸ atoms / cm³, and the doping concentration of the n-type dopant in each of the second and third doped regions is equal to or less than 6*10¹⁸ atoms / cm³.

24. The semiconductor structure of claim 21, wherein the first doped region is shorter than each of the second and third doped regions, the second doped region is longer than the third doped region, the doping concentration of the n-type dopant in the first doped region is less than the doping concentration of the n-type dopant in the second doped region, and the doping concentration of the n-type dopant in the second doped region is less than the doping concentration of the n-type dopant in the third doped region.

25. The semiconductor structure of claim 24, wherein the doping concentration of the n-type dopant in each of the first doped region and the second doped region is equal to or less than 6*10¹⁸ atoms / cm³, and the doping concentration of the n-type dopant in the third doped region is equal to or greater than 6*10¹⁸ atoms / cm³.

26. The semiconductor structure of claim 21, wherein the doping concentration of the n-type dopant in each of the first doped region and the third doped region is equal to or greater than 6*10¹⁸ atoms / cm³, and the doping concentration of the n-type dopant in the second doped region is equal to or less than 6*10¹⁸ atoms / cm³.

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