Non-volatile memory device

Abstract

A non-volatile memory device includes a memory cell region and a peripheral circuit region located below the memory cell region in a vertical direction. The memory cell region includes an upper substrate, a channel structure extending in a vertical direction, and an upper metal line extending in a first direction. The peripheral circuit region includes a first lower metal line extending in a second direction, a first via structure on the first lower metal line, and a second via structure on the first lower metal line, the top surface of the second via structure contacting the upper substrate. The memory cell region further includes a first through-hole via structure that passes through the upper substrate and the first via structure and electrically connects the upper metal line to the first lower metal line; and the upper metal line is electrically connected to the upper substrate through the first through-hole via structure, the first lower metal line, and the second via structure.

Description

Technical Field

[0001] [Cross - Reference to Related Applications]

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2021 - 0092379, filed with the Korean Intellectual Property Office on July 14, 2021, the disclosure of which is incorporated herein by reference in its entirety.

[0003] The inventive concept relates to a memory device, and more particularly, to a three - dimensional (3D) non - volatile memory device having a cell - over - periphery (COP) structure.

Background Art

[0004] A memory device is used to store data. Memory devices can be classified into volatile memory devices and non - volatile memory devices. In response to the demand for a compact high - capacity non - volatile memory device, 3D non - volatile memory devices having a memory cell array and peripheral circuits arranged in a vertical direction have been developed. When a 3D non - volatile memory device includes a plate - shaped common source line, various wiring methods for applying a voltage to the plate - shaped common source line have been studied.

Summary of the Invention

[0005] The inventive concept provides a non - volatile memory device for reducing the wiring difficulty regarding a plate - shaped common source line and improving the usage efficiency of memory blocks in a cell region.

[0006] According to an aspect of the inventive concept, there is provided a non - volatile memory device including: a memory cell region including an upper substrate, a channel structure extending in a vertical direction on the upper substrate, and an upper metal line extending in a first horizontal direction above the channel structure; and a peripheral circuit region vertically below the memory cell region, the peripheral circuit region including: a first lower metal line extending in a second horizontal direction, a first via structure on the first lower metal line, and a second via structure on the first lower metal line, a top surface of the second via structure contacting the upper substrate, wherein the memory cell region further includes a first through - hole via structure extending in the vertical direction, the first through - hole via structure passing through the upper substrate and the first via structure and electrically connecting the upper metal line to the first lower metal line; and the upper metal line is electrically connected to the upper substrate through the first through - hole via structure, the first lower metal line, and the second via structure.

[0007] According to another aspect of the inventive concept, there is provided a non-volatile memory device including: a first semiconductor layer including a plate-shaped common source line, a channel structure extending in a vertical direction on the plate-shaped common source line, a common source line tap wire extending in a first horizontal direction on the channel structure, and a first through-hole via structure passing through the plate-shaped common source line and extending in the vertical direction; and a second semiconductor layer below the first semiconductor layer in the vertical direction, the second semiconductor layer including a lower substrate, circuit elements on the lower substrate, a plurality of lower metal layers connected to the circuit elements, and a plurality of via structures on a first lower metal layer adjacent to the first semiconductor layer among the plurality of lower metal layers, the first lower metal layer extending in a second horizontal direction, wherein the first through-hole via structure electrically connects the common source line tap wire to the first lower metal layer; and the common source line tap wire is electrically connected to the plate-shaped common source line through the first through-hole via structure, the first lower metal layer, and the plurality of via structures.

[0008] According to a further aspect of the inventive concept, there is provided a non-volatile memory device including: a first semiconductor layer including a first memory block, a second memory block, a first through-hole via region adjacent to the first memory block, a bit line through-hole via region adjacent to the first through-hole via region, and a second through-hole via region between the bit line through-hole via region and the second memory block; and a second semiconductor layer below the first semiconductor layer in the vertical direction, the second semiconductor layer including a first lower metal wire and a second lower metal wire separated from the first lower metal wire in a first horizontal direction, wherein the first through-hole via region includes a first through-hole via structure connecting an upper metal wire to the first lower metal wire, the upper metal wire extending above the first memory block and the second memory block and in the first horizontal direction; and the second through-hole via region includes a second through-hole via structure connecting the upper metal wire to the second lower metal wire.

Embodiments

[0010] Embodiments will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals denote like elements, and repetitive description thereof will be omitted.

[0011] FIG. 1 is a block diagram of a memory device 10 according to an exemplary embodiment. [

[0012] ]Referring to FIG. 1, the memory device 10 may include a memory cell array 100 and peripheral circuits 200. The peripheral circuits 200 may include page buffers 210, column decoders 220, control logic circuits 230, data input / output (I / O) circuits 240, and a common source line driver 250. Although not shown in FIG. 1, the peripheral circuits 200 may further include a voltage generator, a temperature sensor, etc. The memory device 10 herein may refer to a non-volatile memory device. [

[0013] ]The memory cell array 100 may include a plurality of memory blocks BLK1 to BLKp (where "p" is a positive integer). Each of the memory blocks BLK1 to BLKp may include a plurality of memory cells. The memory cell array 100 may be connected to the page buffers 210 through bit lines BL and to the column decoders 220 through word lines WL, string select lines SSL, and ground select lines GSL. For example, the memory cells may include flash memory cells. Hereinafter, the case where the memory cells are NAND flash memory cells will be used to describe the exemplary embodiments. However, the embodiments are not limited thereto. In some embodiments, the memory cells may be resistive memory cells, such as resistive random access memory (ReRAM) cells, phase-change RAM (PRAM) cells, or magnetic RAM (MRAM) cells. [

[0014] ]In an exemplary embodiment, the memory cell array 100 may include a three-dimensional (3D) memory cell array, which may include a plurality of NAND strings. Each of the NAND strings may include memory cells respectively connected to word lines vertically stacked on a substrate. This will be described with reference to FIGS. 2 to 3B. The structures of 3D memory arrays, in which the 3D memory arrays include a plurality of levels and word lines and / or bit lines are shared by the levels, are disclosed in U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application No. 2011 / 0233648, the disclosures of which are incorporated herein by reference in their entirety. However, the embodiments are not limited thereto. In some embodiments, the memory cell array 100 may include a two-dimensional (2D) memory cell array, which may include a plurality of NAND strings in column and row directions.

[0015] The page buffer 210 can be connected to the memory cells of the memory cell array 100 through bit lines BL. The page buffer 210 can operate according to the page buffer control signal PCTL provided by the control logic circuit 230. The page buffer 210 can operate as a write driver in a programming operation and apply a voltage corresponding to the data to be stored in the memory cell array 100 to the bit lines BL, and operate as a sense amplifier in a read operation and sense the data stored in the memory cell array 100.

[0016] The control logic circuit 230 can output various control signals based on commands CMD, addresses ADDR, and control signals CTRL received from the outside, such as column addresses R_ADDR, row addresses C_ADDR, control signal CTRL_BIAS, and page buffer control signal PCTL, to program data into the memory cell array 100, read data from the memory cell array 100, or erase data from the memory cell array 100. The control logic circuit 230 can thus overall control various operations of the memory device 10. For example, the control logic circuit 230 can receive the command CMD, address ADDR, and control signal CTRL from the memory controller.

[0017] In response to the column address R_ADDR from the control logic circuit 230, the column decoder 220 can select one of the memory blocks BLK1 to BLKp, one of the word lines WL of the selected memory block, and one of the string select lines SSL. For example, the column decoder 220 can apply a programming voltage and a programming verification voltage to the selected word line in a programming operation, and apply a read voltage to the selected word line in a read operation.

[0018] The data I / O circuit 240 can exchange data with an external device and can be connected to the page buffer 210 through multiple data lines DLs. In addition, the data I / O circuit 240 can operate in response to the row address C_ADDR from the control logic circuit 230. The peripheral circuit 200 can also include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0019] The common source line driver 250 can be connected to the memory cell array 100 through the common source line CSL. The common source line driver 250 can apply a voltage to the common source line CSL based on the control signal CTRL_BIAS from the control logic circuit 230. For example, the common source line driver 250 can apply a power supply voltage or a ground voltage to the common source line CSL.

[0020] FIG. 2 is a circuit diagram of a memory block BLK according to an exemplary embodiment.

[0021] Referring to FIG. 2, the memory block BLK may correspond to one of the memory blocks BLK1 to BLKp in FIG. 1. The memory block BLK may include NAND strings NS11 to NS33, where each (e.g., NS11) may include a string select transistor SST, a plurality of memory cells MCs, and a ground select transistor GST connected in series with each other. The transistors (e.g., the string select transistor SST and the ground select transistor GST) and the memory cells MCs included in each NAND string may form a stacked structure in the vertical direction on a substrate.

[0022] The first bit lines BL1 to BL3 may extend in a first direction or a first horizontal direction, and the word lines WL1 to WL8 may extend in a second direction or a second horizontal direction. Here, the first horizontal direction refers to the first direction, and the second horizontal direction refers to the second direction. The first horizontal direction and the second horizontal direction are perpendicular to each other and perpendicular to the vertical direction. The NAND strings NS11, NS21, and NS31 may be between the first bit line BL1 and the common source line CSL; the NAND strings NS12, NS22, and NS32 may be between the second bit line BL2 and the common source line CSL; and the NAND strings NS13, NS23, and NS33 may be between the third bit line BL3 and the common source line CSL.

[0023] The string select transistor SST may be connected to a corresponding one of the string select lines SSL1 to SSL3. Each of the memory cells MCs may be connected to a corresponding one of the word lines WL1 to WL8. The ground select transistor GST may be connected to a corresponding one of the ground select lines GSL1 to GSL3. The string select transistor SST may be connected to a corresponding one of the first bit line BL1 to the third bit line BL3, and the ground select transistor GST may be connected to the common source line CSL. Here, the number of NAND strings, word lines, bit lines, ground select lines, and string select lines may vary according to the embodiment.

[0024] FIG. 3A is a perspective view of a memory block BLKA according to an exemplary embodiment.

[0025] Referring to FIG. 3A, the memory block BLKA may correspond to one of the memory blocks BLK1 to BLKp in FIG. 1. The memory block BLKA is formed in the vertical direction VD with respect to the substrate SUB. The substrate SUB has a first conductivity type (e.g., p-type) and extends on the substrate SUB in the second horizontal direction HD2. In an exemplary embodiment, the substrate SUB may include polysilicon, and the plate-shaped common source line CSL may be on the substrate SUB. For example, the plate-shaped common source line CSL may correspond to a region doped with impurities of a second conductivity type (e.g., n-type). A plurality of insulating films IL extending in the second horizontal direction HD2 are sequentially provided on the substrate SUB in the vertical direction VD. The insulating films IL are separated from each other by a certain distance in the vertical direction VD. For example, the insulating film IL may include an insulating material such as silicon oxide.

[0026] A plurality of pillars P are arranged on the substrate SUB in the first horizontal direction HD1. The pillars P pass through the insulating films IL in the vertical direction VD. For example, the pillars P pass through the insulating films IL to contact the substrate SUB. Specifically, the surface layer S of each pillar P may include a silicon material of the first conductivity type and may be used as a channel region. Therefore, in some embodiments, the pillar P may be referred to as a channel structure or a vertical channel structure. The inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0027] A charge storage layer CS is provided along the exposed surfaces of the insulating films IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a tunneling insulating layer (or referred to as a "tunneling dielectric film"), a charge trap layer, and a blocking insulating layer (or referred to as a "blocking dielectric film"). For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Gate electrodes GE, such as select lines (e.g., ground select line GSL and string select line SSL) and word lines WL1 to WL8, are provided on the exposed surface of the charge storage layer CS.

[0028] Drain contacts or drains DR are respectively provided on the pillars P. For example, the drain DR may include a silicon material doped with impurities of a second conductivity type. The first bit lines BL1 to the third bit lines BL3 extend on the drain DR in the first horizontal direction HD1 and are separated from each other by a certain distance in the second horizontal direction HD2.

[0029] FIG. 3B is a perspective view of the memory block BLKB according to an exemplary embodiment.

[0030] Referring to FIG. 3B, the memory block BLKB may correspond to one of the memory blocks BLK1 to BLKp in FIG. 1. The memory block BLKB corresponds to a variation of the memory block BLKA in FIG. 3A, and the description given with reference to FIG. 3A is also applicable to this embodiment. The memory block BLKB may be formed in the vertical direction VD with respect to the substrate SUB. The memory block BLKB may include a first memory stack ST1 and a second memory stack ST2 that can be stacked in the vertical direction VD.

[0031] FIG. 4 is a schematic diagram of a memory device 10 having a cell-on-periphery (COP) structure according to an exemplary embodiment.

[0032] Referring to FIG. 4, the memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2. The first semiconductor layer L1 may be stacked on the second semiconductor layer L2 in the vertical direction VD. Specifically, the second semiconductor layer L2 may be located below the first semiconductor layer L1 in the vertical direction VD.

[0033] In an exemplary embodiment, the memory cell array 100 in FIG. 1 may be formed in the first semiconductor layer L1, and the peripheral circuit 200 in FIG. 1 may be formed in the second semiconductor layer L2. Here, the first semiconductor layer L1 may be referred to as the "memory cell array region", and the second semiconductor layer L2 may be referred to as the "peripheral circuit region". Therefore, the memory device 10 may have a COP structure, in which the memory cell array 100 may be located above the peripheral circuit 200. The COP structure can effectively reduce the horizontal area and increase the integration density of the memory device 10.

[0034] In an exemplary embodiment, the second semiconductor layer L2 may include a lower substrate (e.g., L_SUB in FIG. 11). The peripheral circuit 200 may be formed in the second semiconductor layer L2 by forming transistors and metal patterns interconnecting the transistors on the lower substrate. After forming the peripheral circuit 200 in the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 100 may be formed. Metal patterns may be formed to electrically connect the word lines WL and bit lines BL of the memory cell array 100 to the peripheral circuit 200 in the second semiconductor layer L2. For example, the word lines WL may extend in a first horizontal direction HD1, and the bit lines BL may extend in a second horizontal direction HD2. For example, the memory block BLKA in FIG. 3A or the memory block BLKB in FIG. 3B may be formed in the first semiconductor layer L1.

[0035] FIG. 5 is a plan view of the memory device 10 according to an exemplary embodiment.

[0036] Referring to FIG. 5, the memory device 10 may be divided in the second horizontal direction HD2 into a first cell region CR1, a second cell region CR2, and first to fourth word line staircase regions SR1, SR2, SR3, and SR4. However, the embodiments are not limited thereto. The number of cell regions of the memory device 10 may vary according to the embodiments. In some embodiments, the second word line staircase region SR2 and the third word line staircase region SR3 may be separated from each other in the second horizontal direction HD2. The memory device 10 may further include a pad region PAD in which a plurality of I / O pads are arranged.

[0037] A first memory cell array MCA1 and a second memory cell array MCA2 adjacent to each other in the first horizontal direction HD1 may be arranged in the first cell region CR1, and a third memory cell array MCA3 and a fourth memory cell array MCA4 adjacent to each other in the first horizontal direction HD1 may be arranged in the second cell region CR2. Here, each of the first to fourth memory cell arrays MCA1 to MCA4 may be referred to as a "memory array tile (MAT)". However, the embodiments are not limited thereto. The number of memory cell arrays in each of the first cell region CR1 and the second cell region CR2 may vary according to the embodiments.

[0038] Each of the first to fourth memory cell arrays MCA1 to MCA4 may include a plurality of bit line through hole regions BLTHV_R that extend in the second horizontal direction HD2 and are separated from each other in the first horizontal direction HD1. For example, each of the first to fourth memory cell arrays MCA1 to MCA4 may include three bit line through hole regions BLTHV_R, but the embodiments are not limited thereto. The arrangement of the bit line through hole regions BLTHV_R in each of the first to fourth memory cell arrays MCA1 to MCA4 may vary according to the embodiments.

[0039] FIG. 6 shows a first semiconductor layer L1 and a second semiconductor layer L2 of the memory device 10 according to an exemplary embodiment. The first semiconductor layer L1 and the second semiconductor layer L2 may correspond to a part of the memory device 10 of FIG. 5.

[0040] Referring to FIG. 6, the first semiconductor layer L1 may include a first memory cell array MCA1, a first word line ladder region SR1, and a second word line ladder region SR2, and the first semiconductor layer L1 and the semiconductor layer L2 in FIG. 6 may respectively correspond to the first semiconductor layer L1 and the semiconductor layer L2 in FIG. 4. The first semiconductor layer L1 may include bit line through-hole via regions BLTHV_R, in which a plurality of bit line through-hole vias (bit line through-hole via structures) respectively connected to a plurality of bit lines are arranged. The first semiconductor layer L1 may further include a first region CTHV_R1 and a second region CTHV_R2 respectively located on both sides of each of the bit line through-hole via regions BLTHV_R in a first horizontal direction HD1. Here, the first region CTHV_R1 and the second region CTHV_R2 may correspond to the "common source line through-hole via region", in which common source line through-hole vias connected to common source line tap conductors may be arranged.

[0041] The second semiconductor layer L2 may include a first column decoder region XDEC1 and a second column decoder region XDEC2 respectively corresponding to the first word line ladder region SR1 and the second word line ladder region SR2. For example, the column decoder 220 in FIG. 1 may be arranged in the first column decoder region XDEC1 and the second column decoder region XDEC2. The second semiconductor layer L2 may further include a page buffer region PGBUF, which corresponds to the bit line through-hole via regions BLTHV_R and the first region CTHV_R1 and the second region CTHV_R2. For example, the page buffer 210 in FIG. 1 may be arranged in the page buffer region PGBUF. The control logic circuit 230 in FIG. 1 may be arranged in a region of the first semiconductor layer L1 adjacent to the page buffer region PGBUF in the first horizontal direction HD1.

[0042] FIG. 7 is an enlarged plan view of some elements in the region EX1 in FIG. 6 according to an exemplary embodiment. FIG. 8 is an enlarged perspective view of some elements in the region EX1 in FIG. 6 according to an exemplary embodiment.

[0043] Referring to FIGS. 6 to 8, the memory device 10 may include memory blocks BLKa and BLKb that can extend in the second horizontal direction HD2 on the upper substrate U_SUB. The memory device 10 may further include a plurality of word line cutting regions or word line cutting structures WLC, which can extend in the second horizontal direction HD2 and are separated from each other in the first horizontal direction HD1. For example, each of the memory blocks BLKa and BLKb may be disposed in a region defined by three adjacent word line cutting structures WLC. However, the exemplary embodiments are not limited thereto. In some embodiments, each of the memory blocks BLKa and BLKb may be disposed in a region defined by two adjacent word line cutting structures WLC.

[0044] The memory device 10 may further include a bit line through hole region BLTHV_R that extends in the second horizontal direction HD2. The upper substrate U_SUB may be removed from the bit line through hole region BLTHV_R such that the bit line through hole extends to the second semiconductor layer L2. For example, an insulating film may be disposed in the bit line through hole region BLTHV_R. The memory device 10 may further include a first region CTHV_R1 and a second region CTHV_R2, and the first region CTHV_R1 and the second region CTHV_R2 may be disposed on both sides of the bit line through hole region BLTHV_R in the first horizontal direction HD1 and extend in the second horizontal direction HD2. Here, the first region CTHV_R1 may be between the memory block BLKa and the bit line through hole region BLTHV_R, and the second region CTHV_R2 may be between the bit line through hole region BLTHV_R and the memory block BLKb.

[0045] The memory device 10 may further include a first lower metal line LM2a, a second lower metal line LM2b, and a plurality of through holes (through-hole structures) BVIA. The first lower metal line LM2a, the second lower metal line LM2b, and the through holes BVIA may be disposed in the second semiconductor layer L2. The first lower metal line LM2a and the second lower metal line LM2b may be respectively located below the first region CTHV_R1 and the second region CTHV_R2 in the vertical direction VD and may extend in the second horizontal direction HD2. The through holes BVIA may be separated from each other in the second horizontal direction HD2 in the first lower metal line LM2a and the second lower metal line LM2b. The top surface of the through hole BVIA may contact the upper substrate U_SUB. In other words, the top surface of the through hole BVIA may be at the same horizontal height as the bottom surface of the upper substrate U_SUB in the vertical direction. However, the top surfaces of the first through hole BVIA1 and the third through hole BVIA3 respectively connected to the first through-hole through hole THV1 and the second through-hole through hole THV2 may be at a horizontal height lower than the bottom surface of the upper substrate U_SUB in the vertical direction. According to an exemplary embodiment, the through hole BVIA may be referred to as a "bypass through hole". According to an embodiment, the number of through holes BVIA in each of the first lower metal line LM2a and the second lower metal line LM2b may vary, and the distance between adjacent through holes BVIA may also vary.

[0046] The memory device 10 may further include a common source line tapping conductor CTW, a first through-hole through hole THV1, a second through-hole through hole THV2, and a metal contact MC1. The common source line tapping conductor CTW, the first through-hole through hole THV1, the second through-hole through hole THV2, and the metal contact MC1 may be disposed in the first semiconductor layer L1. The common source line tapping conductor CTW may extend in the first horizontal direction HD1 and may be connected to the first through-hole through hole THV1 and the second through-hole through hole THV2 through the metal contact MC1.

[0047] The first through-hole through hole THV1 may be in the first region CTHV_R1 and may extend in the vertical direction VD to pass through the upper substrate U_SUB and the first through hole BVIA1 and be connected to the first lower metal line LM2a. According to this embodiment, the common source line tapping conductor CTW may be electrically connected to the upper substrate U_SUB through the metal contact MC1, the first through-hole through hole THV1, the first lower metal line LM2a, and a plurality of through holes BVIA including the first through hole BVIA1 and the second BVIA2. Therefore, the voltage applied to the common source line tapping conductor CTW may be provided to the upper substrate U_SUB, that is, the plate-shaped common source line of the upper substrate U_SUB.

[0048] The second through-hole via THV2 can be in the second region CTHV_R2 and can extend in the vertical direction VD to pass through the upper substrate U_SUB and the third via BVIA3 and be connected to the second lower metal line LM2b. The portion of the upper substrate U_SUB is not shown in FIG. 8 to clearly show the structures of the third via BVIA3 and the fourth via BVIA4. Although not shown, the common source line tap wire CTW can be electrically connected to the upper substrate U_SUB through the metal contact MC1, the second through-hole via THV2, the second lower metal line LM2b, and a plurality of vias BVIA including the third via BVIA3 and the fourth via BVIA4. Accordingly, the voltage applied to the common source line tap wire CTW can be provided to the upper substrate U_SUB, that is, the plate-shaped common source line of the upper substrate U_SUB. The first through-hole via THV1 and the second through-hole via THV2 can include a conductive material or a semiconductor material such that electrical connection can be made using the first through-hole via THV1 and the second through-hole via THV2.

[0049] FIG. 9 is a schematic plan view of a portion of the memory device 10a according to an exemplary embodiment. The memory device 10a can correspond to an implementation of the memory device 10 of FIG. 6. The descriptions given with reference to FIGS. 6 to 8 can also be applied to this embodiment.

[0050] Referring to FIG. 9, the memory device 10a can include an upper substrate U_SUB and a gate stack GS including a gate electrode GE on the upper substrate U_SUB. The gate electrode GE can be stacked on the upper substrate U_SUB in the vertical direction VD and be electrically insulated from each other by an insulating film IL (in FIG. 11). The gate electrode GE can extend in the second horizontal direction HD2, and the ends of the gate electrode GE can form a stepped shape in each of the first word line stepped region SR1 and the second word line stepped region SR2. The area of each of the gate electrodes GE can decrease as it is farther from the upper substrate U_SUB. The central portions of the gate electrodes GE that can overlap each other in the vertical direction VD can form a first cell region CR1. The edge portions of the gate electrodes GE can form the first word line stepped region SR1 and the second word line stepped region SR2, respectively. For example, the gate electrode GE can include a ground selection line GSL, word lines WL1 to WL8, and a string selection line SSL.

[0051] Multiple character line cut structures WLC can extend over the first cell region CR1, the first character line step region SR1, and the second character line step region SR2 on the upper substrate U_SUB and in the second horizontal direction HD2. The character line cut structures WLC can be separated from each other in the first horizontal direction HD1. Although not shown, at least one string select line cut structure can be between two adjacent character line cut structures WLC. In an exemplary embodiment, two string select line cut structures can be between two adjacent character line cut structures WLC, and thus, three string select lines can be between two adjacent character line cut structures WLC. For example, the first memory block BLKa can be in the region defined by three adjacent character line cut structures WLC and include six string select lines.

[0052] Each of the memory blocks BLKa and BLKb can include multiple channel structures CH. The channel structures CH can extend in the vertical direction VD and pass through the gate electrode GE and the insulating film IL. Multiple bit line through holes BLTHV can be arranged in the bit line through hole region BLTHV_R. Although the bit line through holes BLTHV are shown arranged in a column in FIG. 9 for convenience, the embodiments are not limited thereto. The number and arrangement of the bit line through holes BLTHV can vary with the embodiments. For example, the bit line through holes BLTHV can be arranged in a zigzag pattern. Multiple vias BVIA and through holes CTHV can be arranged below the first region CTHV_R1 and the second region CTHV_R2. This will be described with reference to FIGS. 10 to 13.

[0053] FIG. 10 is a plan view of a part of the memory device 10a of FIG. 9 according to an exemplary embodiment. FIG. 11 is a cross-sectional view taken along line X1-X1' in FIG. 10 according to an exemplary embodiment. FIG. 12 is a cross-sectional view taken along line Y1-Y1' in FIG. 10 according to an exemplary embodiment. FIG. 13 is a cross-sectional view taken along line Y2-Y2' in FIG. 10 according to an exemplary embodiment.

[0054] Referring to FIGS. 10 to 13, the memory device 10a may include a first semiconductor layer L1 and a second semiconductor layer L2 that overlap each other in the vertical direction VD. The first semiconductor layer L1 may include an upper substrate U_SUB, a gate electrode GE, an insulating film IL, a first through-hole via THV1 and a second through-hole via THV2, a bit line BL including bit lines BLa to BLd, a common source line tap wire CTW, and an upper insulating layer U_IL. In this embodiment, the bit line BL and the common source line tap wire CTW may be at the same horizontal height in the vertical direction and constitute, for example, a first metal layer (first upper metal layer or first upper metal wire) ML1. Although not shown, a plurality of metal layers may be on the first metal layer ML1, and the metal layers at different horizontal heights in the vertical direction may be connected to each other through metal contacts.

[0055] The second semiconductor layer L2 may include a lower substrate L_SUB, circuit elements TR, lower metal layers LM0, LM1, and LM2, lower metal contacts LMC0, LMC1, and LMC2, a plurality of vias BVIA, and a lower insulating layer L_IL. For example, the circuit element TR may correspond to the transistor of the peripheral circuit 200 in FIG. 1. Shallow trench isolation STI may be located between the separate circuit elements TR. For example, the lower metal layers LM0 and LM2 may extend in a first horizontal direction HD1, and the lower metal layer LM1 may extend in a second horizontal direction HD2, but the embodiment is not limited thereto.

[0056] The vias BVIA may be arranged on the lower metal layer LM2 and separated from each other in the second horizontal direction HD2, and the top surface of the via BVIA may contact the bottom surface of the upper substrate U_SUB. In other words, the via BVIA may be located between the upper substrate U_SUB and the lower metal layer LM2. However, due to the etching process performed to form the first through-hole via THV1 and the second through-hole via THV2, the top surfaces of the first via BVIA1 and the third via BVIA3 may be at a lower horizontal height in the vertical direction than the top surfaces of the other vias BVIA. The via BVIA may include a conductive material and may thus be referred to as a "conductive landing via" or a "bypass via". For example, the via BVIA may include a doped semiconductor material or an undoped semiconductor material. For example, the via BVIA may include doped or undoped polysilicon, but is not limited thereto.

[0057] The upper substrate U_SUB may include polysilicon and serve as a common source line CSL. Thus, the upper substrate U_SUB can be used as a source region for supplying current to memory cells on the upper substrate U_SUB. According to some embodiments, the common source line CSL may be formed by doping the upper substrate U_SUB with impurities and may have a plate shape. Thus, the upper substrate U_SUB can be defined as including the plate-shaped common source line.

[0058] The first through-hole via THV1 and the second through-hole via THV2 may extend in the vertical direction VD and pass through the gate electrode GE and the insulating film IL. The first through-hole via THV1 and the second through-hole via THV2 may extend in the vertical direction VD to pass through the upper substrate U_SUB. The first through-hole via THV1 and the second through-hole via THV2 may further extend in the vertical direction VD to pass through the first via BVIA1 and the third via BVIA3, respectively. For example, the first through-hole via THV1 and the second through-hole via THV2 may have an annular shape. However, the exemplary embodiments are not limited thereto. The first through-hole via THV1 and the second through-hole via THV2 may have an elliptical cylindrical shape or a quadrangular cylindrical shape. The common source line tap wire CTW may be above the first through-hole via THV1 and the second through-hole via THV2 and connected to each of the first through-hole via THV1 and the second through-hole via THV2 through a metal contact MC1.

[0059] The insulating ring IL1 may surround each of the first through-hole via THV1 and the second through-hole via THV2. Thus, the first through-hole via THV1 and the second through-hole via THV2 may be electrically insulated from the gate electrode GE. For example, the insulating ring IL1 may include silicon nitride, but the embodiments are not limited thereto.

[0060] In the exemplary embodiment, the lower metal layer LM2 may include a first lower metal line LM2a and a second lower metal line LM2b that extend in the second horizontal direction HD2 and are separated from each other in the first horizontal direction HD1. Here, the first lower metal line LM2a may be located below the first region CTHV_R1 in the vertical direction VD, and the second lower metal line LM2b may be located below the second region CTHV_R2 in the vertical direction VD.

[0061] The first through-hole THV1 in the first region CTHV_R1 can pass through the first via BVIA1 to connect to the first lower metal line LM2a, and can be connected to the upper substrate U_SUB through the via BVIA including the second via BVIA2 on the first lower metal line LM2a. Therefore, the common source line tap wire CTW can be electrically connected to the upper substrate U_SUB through the metal contact MC1, the first through-hole THV1, the first lower metal line LM2a, and the via BVIA including the second via BVIA2. Here, the first through-hole THV1, the first lower metal line LM2a, and the second via BVIA2 can form a voltage path VP, and the voltage applied to the common source line tap wire CTW can be transmitted to the plate-shaped common source line of the upper substrate U_SUB through the voltage path VP. As described above, the plate-shaped common source line can be re-routed through the first lower metal line LM2a and the via BVIA including the second via BVIA2 on the first lower metal line LM2a.

[0062] The second through-hole THV2 in the second region CTHV_R2 can pass through the third via BVIA3 to connect to the second lower metal line LM2b, and can be connected to the upper substrate U_SUB through the via BVIA including the fourth via BVIA4 on the second lower metal line LM2b. Therefore, the common source line tap wire CTW can be electrically connected to the upper substrate U_SUB through the metal contact MC1, the second through-hole THV2, the second lower metal line LM2b, and the via BVIA including the fourth via BVIA4. Here, the second through-hole THV2, the second lower metal line LM2b, and the fourth via BVIA4 can form a voltage path VP, and the voltage applied to the common source line tap wire CTW can be transmitted to the plate-shaped common source line of the upper substrate U_SUB through the voltage path VP. As described above, the plate-shaped common source line can be re-routed through the second lower metal line LM2b and the via BVIA including the fourth via BVIA4 on the second lower metal line LM2b.

[0063] Multiple bit line through-vias BLTHV can be disposed in the bit line through-via region BLTHV_R. The bit line through-vias BLTHV can extend in the vertical direction VD and pass through the upper insulating layer U_IL, the insulating film IL, and the upper substrate U_SUB to be connected to the vias BVIA, respectively. The bit line through-vias BLTHV under the common source line tap wire CTW may not be connected to the common source line tap wire CTW, and the bit line through-vias BLTHV under the bit lines BLa to BLd may be connected to the bit lines BLa to BLd, respectively. For example, the bit line BLa can be connected to the source / drain region SD on the lower substrate L_SUB through the metal contact MC1, the bit line through-via BLTHV, the via BVIA, the lower metal layers LM0 to LM2, and the lower metal contacts LMC0 to LMC2.

[0064] FIG. 14 shows the first semiconductor layer L1 and the second semiconductor layer L2 of the memory device 10b according to an exemplary embodiment. The memory device 10b may correspond to a modification of the memory device 10 of FIG. 6. The descriptions given with reference to FIGS. 6 to 13 may also be applied to this embodiment.

[0065] Referring to FIG. 14, the first semiconductor layer L1 may further include a third region CTHV_R3. Here, the third region CTHV_R3 may not correspond to the page buffer region PGBUF of the second semiconductor layer L2. For example, a control logic circuit (e.g., the control logic circuit 230 in FIG. 1) may be disposed in the region of the second semiconductor layer L2 corresponding to the third region CTHV_R3. However, the embodiment is not limited thereto. The first semiconductor layer L1 may include only the third region CTHV_R3 instead of the first region CTHV_R1 and the second region CTHV_R2.

[0066] FIG. 15 is a schematic plan view of a part of the memory device 10b according to an exemplary embodiment. The memory device 10b may correspond to a modification of the memory device 10a of FIG. 9. The description given with reference to FIG. 9 may also be applied to this embodiment.

[0067] Referring to FIGS. 14 and 15, the memory device 10b may include memory blocks BLKc and BLKd. Each of the memory blocks BLKc and BLKd may include a plurality of channel structures CH. The third region CTHV_R3 may be adjacent to the word line cutting structure WLC. A plurality of vias BVIA and through-vias CTHV may be under the third region CTHV_R3. This will be described with reference to FIGS. 16 to 19.

[0068] FIG. 16 is a plan view of a portion of the memory device 10b of FIG. 15 according to an exemplary embodiment. FIG. 17 is a cross-sectional view taken along line X2-X2' in FIG. 16 according to an exemplary embodiment. FIG. 18 is a cross-sectional view taken along line Y3-Y3' in FIG. 16 according to an exemplary embodiment. FIG. 19 is a cross-sectional view taken along line Y4-Y4' in FIG. 16 according to an exemplary embodiment. The description given with reference to FIGS. 10 to 13 may also be applied to this embodiment, and thus repeated description is omitted.

[0069] Referring to FIGS. 16 to 18, the memory device 10b may include a first semiconductor layer L1 and a second semiconductor layer L2 that overlap each other in a vertical direction VD. The first semiconductor layer L1 may include an upper substrate U_SUB, a gate electrode GE, an insulating film IL, a channel structure CH, a third through-hole THV3, bit lines BL including bit lines BLa to BLd, a common source line tap conductor CTW, and an upper insulating layer U_IL.

[0070] The channel structure CH may extend in the vertical direction VD and pass through the gate electrode GE and the insulating film IL. For example, the channel structure CH may correspond to the pillar P in FIG. 3A or FIG. 3B. The description given with reference to FIGS. 3A and 3B may also be applied to this embodiment. For example, the channel structure CH may have an annular shape. However, the embodiment is not limited thereto. The channel structure CH may have an elliptical cylindrical shape or a rectangular column shape. The channel structures CH may be separated from each other in a first horizontal direction HD1 and a second horizontal direction HD2. Drain DRs may be respectively on the channel structures CH. For example, the drain DRs may include a silicon material doped with impurities of a second conductivity type (e.g., n-type). The bit lines BLa to BLd may be on the drain DRs and are respectively connected to the drain DRs through bit line contacts BLC.

[0071] For example, the memory block BLKc may be in a region defined by three adjacent word line cut structures WLC. Two string select line cut structures SSLC may be between two adjacent word line cut structures WLC. Each of the word line cut structure WLC and the string select line cut structure SSLC may include an insulating structure. In an exemplary embodiment, the insulating structure may include silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. For example, the insulating structure may include a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, a SiCN film, or a combination thereof. In an exemplary embodiment, at least a portion of the insulating structure may include air gaps. The term "air" used herein may refer to the atmosphere or other gases that may be present during the manufacturing process.

[0072] The third through-hole via THV3 can extend in the vertical direction VD and pass through the gate electrode GE, the insulating film IL, and the upper substrate U_SUB. The common source line tap conductor CTW can be above the third through-hole via THV3 and connected to the third through-hole via THV3 through the metal contact MC1. The insulating ring IL1 can surround the third through-hole via THV3. Thus, the third through-hole via THV3 can be electrically insulated from the gate electrode GE.

[0073] In an exemplary embodiment, the lower metal layer LM2 can be located below the third through-hole via THV3 in the vertical direction VD and extend in the second horizontal direction HD2. The third through-hole via THV3 in the third region CTHV_R3 can pass through the fifth via BVIA5 to connect to the lower metal layer LM2 and can be connected to the upper substrate U_SUB through the via BVIA including the sixth via BVIA6 on the lower metal layer LM2. Thus, the common source line tap conductor CTW can be electrically connected to the upper substrate U_SUB through the metal contact MC1, the third through-hole via THV3, the lower metal layer LM2, and the via BVIA including the sixth via BVIA6. Here, the third through-hole via THV3, the lower metal layer LM2, and the sixth via BVIA6 can form a voltage path VP, and the voltage applied to the common source line tap conductor CTW can be transmitted to the plate-shaped common source line of the upper substrate U_SUB through the voltage path VP. As described above, the plate-shaped common source line can be re-routed through the lower metal layer LM2 and the via BVIA including the sixth via BVIA6 on the lower metal layer LM2.

[0074] FIG. 20A is an enlarged cross-sectional view of some elements in the region EX3 in FIG. 19 according to an exemplary embodiment.

[0075] Referring to FIG. 20A, the upper substrate U_SUB can include a substrate 111, a first conductive plate 112, and a second conductive plate 113. The first conductive plate 112 and the second conductive plate 113 can be used as the common source line CSL. Thus, the upper substrate U_SUB can be defined as including a plate-shaped common source line. The substrate 111 can include a semiconductor material such as polysilicon. Each of the first conductive plate 112 and the second conductive plate 113 can include a doped polysilicon film, a metal film, or a combination thereof. For example, the metal film can include tungsten (W), but is not limited thereto.

[0076] The gate dielectric layer 121 may include a tunneling dielectric film TD, a charge trap layer CT, and a blocking dielectric film BD formed in sequence on the channel region 122. The relative thicknesses of the tunneling dielectric film TD, the charge trap layer CT, and the blocking dielectric film BD are not limited to those shown in FIG. 20A and can be varied in various ways. The tunneling dielectric film TD may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, or tantalum oxide. The charge trap layer CT is a region where electrons transmitted from the channel region 122 through the tunneling dielectric film TD can be stored and may include silicon nitride, boron nitride, boron silicon nitride, or doped polysilicon. The blocking dielectric film BD may include silicon oxide, silicon nitride, or a metal oxide having a higher permittivity than silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0077] As shown in FIG. 20A, the first conductive plate 112 may pass through a portion of the gate dielectric layer 121 in the horizontal direction to contact the channel region 122. The thickness (i.e., the vertical dimension) of the portion of the first conductive plate 112 that vertically overlaps the gate dielectric layer 121 may be greater than the thickness (i.e., the vertical dimension) of the portion of the first conductive plate 112 that vertically overlaps the second conductive plate 113. The gate dielectric layer 121 may include a portion covering the sidewalls of the channel region 122 at a higher horizontal height than the first conductive plate 112 in the vertical direction, and a portion covering the lower surface of the channel region 122 at a lower horizontal height than the first conductive plate 112 in the vertical direction. The channel region 122 may be separated from the substrate 111, and the lowest portion of the gate dielectric layer 121 is between the channel region 122 and the substrate 111. The sidewalls of the channel region 122 may contact the first conductive plate 112 and be configured to be electrically connected to the first conductive plate 112.

[0078] The channel region 122 may have a cylindrical shape. The channel region 122 may include doped or undoped polysilicon. The buried insulating layer 123 may fill the internal space of the channel region 122. The buried insulating layer 123 may include an insulating material. For example, the buried insulating layer 123 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the buried insulating layer 123 may be omitted. In this case, the channel region 122 may have a columnar shape without an internal space. The gate dielectric layer 121, the channel region 122, and the buried insulating layer 123 may constitute a channel structure CH.

[0079] FIG. 20B is an enlarged cross-sectional view of some elements in region EX3 in FIG. 19 according to an exemplary embodiment.

[0080] Referring to FIG. 20B, the memory device 10b' may have a configuration substantially the same as that of the memory device 10b of FIG. 20A. However, the memory device 10b' may include a gate dielectric layer 121' instead of the gate dielectric layer 121. The gate dielectric layer 121' may have a structure substantially the same as that of the gate dielectric layer 121, but includes a first barrier dielectric film BD1 and a second barrier dielectric film BD2 instead of the barrier dielectric film BD. The first barrier dielectric film BD1 may extend along the channel region 122, and the second barrier dielectric film BD2 may surround the gate electrode GE. Each of the first barrier dielectric film BD1 and the second barrier dielectric film BD2 may include silicon oxide, silicon nitride, or a metal oxide. For example, the first barrier dielectric film BD1 may include silicon oxide, and the second barrier dielectric film BD2 may include a metal oxide having a higher permittivity than silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0081] FIG. 21 shows a first semiconductor layer L1 and a second semiconductor layer L2 of a memory device 10c according to an exemplary embodiment. The memory device 10c may correspond to a modification of the memory device 10 of FIG. 6. The descriptions given with reference to FIGS. 6 to 13 may also be applied to this embodiment.

[0082] Referring to FIG. 21, the first semiconductor layer L1 may further include a fourth region CTHV_R4. Here, the fourth region CTHV_R4 may not correspond to the page buffer region PGBUF of the second semiconductor layer L2. For example, the fourth region CTHV_R4 may be disposed in the top edge region of the first memory cell array MCA1. However, the embodiment is not limited thereto. The fourth region CTHV_R4 may be disposed in the bottom edge region of the first memory cell array MCA1. However, the embodiment is not limited thereto. The first semiconductor layer L1 may include only the fourth region CTHV_R4 instead of the first region CTHV_R1 and the second region CTHV_R2. In some embodiments, the first semiconductor layer L1 may include the fourth region CTHV_R4 and the third region CTHV_R3 of FIG. 14.

[0083] FIG. 22 is a schematic plan view of a part of a memory device 10c according to an exemplary embodiment. The memory device 10c may correspond to a modification of the memory device 10a of FIG. 9. The description given with reference to FIG. 9 may also be applied to this embodiment.

[0084] Referring to FIGS. 21 and 22, the memory device 10c may include memory blocks BLKe and BLKf. Each of the memory blocks BLKe and BLKf may include a plurality of channel structures CH. The first semiconductor layer L1 may include a fourth region CTHV_R4 and a fifth region CTHV_R5. Here, the fourth region CTHV_R4 and the fifth region CTHV_R5 may not correspond to the page buffer region PGBUF of the second semiconductor layer L2. For example, the fourth region CTHV_R4 may correspond to the top edge region of the first cell region CR1, i.e., the upper stepped region of the gate electrode GE. The fifth region CTHV_R5 may correspond to the bottom edge region of the first cell region CR1, i.e., the lower stepped region of the gate electrode GE. However, the embodiments are not limited thereto. In some embodiments, the memory device 10c may include only one of the fourth region CTHV_R4 and the fifth region CTHV_R5. A plurality of vias BVIA and through-hole vias CTHV may be below the fourth region CTHV_R4 and the fifth region CTHV_R5. This will be described with reference to FIGS. 23 to 26.

[0085] FIG. 23 is a plan view of a portion of the memory device 10c of FIG. 22 according to an exemplary embodiment. FIG. 24 is a cross-sectional view taken along line X3-X3' in FIG. 23 according to an exemplary embodiment. FIG. 25 is a cross-sectional view taken along line Y5-Y5' in FIG. 23 according to an exemplary embodiment. FIG. 26 is a cross-sectional view taken along line Y6-Y6' in FIG. 23 according to an exemplary embodiment. The descriptions given with reference to FIGS. 10 to 13 and FIGS. 16 to 18 may also be applied to this embodiment, and thus repeated descriptions are omitted.

[0086] Referring to FIGS. 23 to 26, the memory device 10c may include a first semiconductor layer L1 and a second semiconductor layer L2 that overlap each other in the vertical direction VD. The first semiconductor layer L1 may include an upper substrate U_SUB, a gate electrode GE, an insulating film IL, a channel structure CH, a fourth through-hole via THV4, bit lines BL including bit lines BLa to BLd, a common source line tap wire CTW, and an upper insulating layer U_IL. For example, the memory block BLKe may be in a region defined by three adjacent word line cut structures WLC. Two string select line cut structures SSLC may be between two adjacent word line cut structures WLC.

[0087] The fourth region CTHV_R4 may include a stacked structure of a silicon nitride film IL2 and an insulating film IL. For example, the silicon nitride film IL2 may include SiN, and the insulating film IL may include a silicon oxide film. Therefore, the stacked structure may be referred to as an ON stacked structure. The silicon nitride film IL2 may be at the same horizontal height as the gate electrode GE in the vertical direction. The fourth through-hole THV4 may extend in the vertical direction VD and pass through the silicon nitride film IL2, the insulating film IL, and the upper substrate U_SUB. The common source line tap wire CTW may be above the fourth through-hole THV4 and connected to the fourth through-hole THV4 through a metal contact MC1.

[0088] In an exemplary embodiment, the lower metal layer LM2 may be located below the fourth region CTHV_R4 in the vertical direction VD and extend in the second horizontal direction HD2. The fourth through-hole THV4 in the fourth region CTHV_R4 may pass through the seventh via BVIA7 to be connected to the lower metal layer LM2 and may be connected to the upper substrate U_SUB through a via BVIA including an eighth via BVIA8 on the lower metal layer LM2. Therefore, the common source line tap wire CTW may be electrically connected to the upper substrate U_SUB through the metal contact MC1, the fourth through-hole THV4, the lower metal layer LM2, and the via BVIA including the eighth via BVIA8. Here, the fourth through-hole THV4, the lower metal layer LM2, and the eighth via BVIA8 may form a voltage path VP, and the voltage applied to the common source line tap wire CTW may be transmitted to the plate-shaped common source line of the upper substrate U_SUB through the voltage path VP. As described above, the plate-shaped common source line may be re-routed through the lower metal layer LM2 and the via BVIA including the eighth via BVIA8 on the lower metal layer LM2.

[0089] FIG. 27 is a cross-sectional view of a memory device having a bonding vertical NAND (B-VNAND) structure according to an exemplary embodiment. When the non-volatile memory of the memory device includes a B-VNAND flash memory, the non-volatile memory may have the structure shown in FIG. 27.

[0090] Referring to FIG. 27, the cell region CELL of the memory device 500 may correspond to the first semiconductor layer L1, and the peripheral circuit region PERI of the memory device 500 may correspond to the second semiconductor layer L2. Each of the peripheral circuit region PERI and the cell region CELL of the memory device 500 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0091] The peripheral circuit region PERI may include a first substrate 610, an interlayer insulating layer 615, a plurality of circuit elements 620a, 620b, and 620c formed on the first substrate 610, first metal layers 630a, 630b, and 630c respectively connected to the plurality of circuit elements 620a, 620b, and 620c, and second metal layers 640a, 640b, and 640c formed on the first metal layers 630a, 630b, and 630c. In an exemplary embodiment, the first metal layers 630a, 630b, and 630c may be formed of tungsten having a relatively high resistivity, and the second metal layers 640a, 640b, and 640c may be formed of copper having a relatively low resistivity.

[0092] In an exemplary embodiment, although only the first metal layers 630a, 630b, and 630c and the second metal layers 640a, 640b, and 640c are shown and described, the exemplary embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 640a, 640b, and 640c. At least a part of the one or more additional metal layers formed on the second metal layers 640a, 640b, and 640c may be formed of aluminum or the like having a resistivity lower than that of the copper forming the second metal layers 640a, 640b, and 640c.

[0093] The interlayer insulating layer 615 may be disposed on the first substrate 610 and cover the plurality of circuit elements 620a, 620b, and 620c, the first metal layers 630a, 630b, and 630c, and the second metal layers 640a, 640b, and 640c. The interlayer insulating layer 615 may include an insulating material such as silicon oxide, silicon nitride, etc.

[0094] Lower bonding metals 671b and 672b may be formed on the second metal layer 640b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 671b and 672b in the peripheral circuit region PERI may be electrically bonded to the upper bonding metals 571b and 572b of the cell region CELL. The lower bonding metals 671b and 672b and the upper bonding metals 571b and 572b may be formed of aluminum, copper, tungsten, etc. In addition, the upper bonding metals 571b and 572b in the cell region CELL may be referred to as first metal pads, and the lower bonding metals 5271b and 5272b in the peripheral circuit region PERI may be referred to as second metal pads.

[0095] The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate 510 and a common source line 520. On the second substrate 510, a plurality of word lines 531 to 538 (i.e., 530) may be stacked in a vertical direction VD perpendicular to the upper surface of the second substrate 510. At least one string selection line and at least one ground selection line may be disposed above and below the plurality of word lines 530, respectively, and the plurality of word lines 530 may be disposed between at least one string selection line and at least one ground selection line.

[0096] In the bit line bonding area BLBA, the channel structure CH may extend in a vertical direction VD perpendicular to the upper surface of the second substrate 510 and pass through the plurality of word lines 530, at least one string selection line, and at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 550c and the second metal layer 560c. For example, the first metal layer 550c may be a bit line contact, and the second metal layer 560c may be a bit line. In an exemplary embodiment, the bit line 560c may extend in a second horizontal direction HD2 parallel to the upper surface of the second substrate 510.

[0097] In an exemplary embodiment, the area where the channel structure CH, the bit line 560c, etc. are provided may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line 560c may be electrically connected to a circuit element 620c that provides a page buffer 593 in the peripheral circuit area PERI. The bit line 560c may be connected to upper bonding metals 571c and 572c in the cell region CELL, and the upper bonding metals 571c and 572c may be connected to lower bonding metals 671c and 672c, and the lower bonding metals 671c and 672c are connected to the circuit element 620c of the page buffer 593.

[0098] In an exemplary embodiment, the memory device 500 may further include a through-hole via THV in the bit line bonding area BLBA. The through-hole via THV may pass through the word line 530 and extend in the vertical direction VD. The through-hole via THV may be connected to the common source line 520 and / or the second substrate 510. Although not shown, an insulating ring may surround the through-hole via THV, and the through-hole via THV may be insulated from the word line 530. The through-hole via THV may be connected to the peripheral circuit area PERI through the upper bonding metal 572d and the lower bonding metal 672d.

[0099] In the word line bonding area WLBA, a plurality of word lines 530 may extend in a first horizontal direction HD1 (the first horizontal direction HD1 is parallel to the upper surface of the second substrate 510) and may be connected to a plurality of cell contact plugs 541 to 547 (i.e., 540). The plurality of word lines 530 and the plurality of cell contact plugs 540 may be connected to each other in the pads, and the pads are provided by at least a portion of the plurality of word lines 530 extending in a second horizontal direction HD2 with different lengths. The first metal layer 550b and the second metal layer 560b may be sequentially connected to the upper portions of the plurality of cell contact plugs 540, and the cell contact plugs 540 are connected to the plurality of word lines 530. The plurality of cell contact plugs 540 in the word line bonding area WLBA may be connected to the peripheral circuit area PERI by the upper bonding metals 571b and 572b of the cell area CELL and the lower bonding metals 671b and 672b of the peripheral circuit area PERI.

[0100] The plurality of cell contact plugs 540 may be electrically connected to the circuit element 620b that provides the column decoder 594 in the peripheral circuit area PERI. In an exemplary embodiment, the operating voltage of the circuit element 620b of the column decoder 594 may be different from the operating voltage of the circuit element 620c that provides the page buffer 593. For example, the operating voltage of the circuit element 620c that provides the page buffer 593 may be greater than the operating voltage of the circuit element 620b that provides the column decoder 594.

[0101] The common source line contact plug 580 may be disposed in the external pad bonding area PA. The common source line contact plug 580 may be formed of a conductive material such as metal, metal compound, polysilicon, etc., and may be electrically connected to the common source line 520. The first metal layer 550a and the second metal layer 560a may be sequentially stacked on the upper portion of the common source line contact plug 580. For example, the area where the common source line contact plug 580, the first metal layer 550a, and the second metal layer 560a are disposed may be defined as the external pad bonding area PA.

[0102] The first input / output pad 605 and the second input / output pad 505 may be disposed in the external pad bonding region PA. The lower insulating film 601 covering the lower surface of the first substrate 610 may be formed under the first substrate 610, and the first input / output pad 605 may be formed on the lower insulating film 601. The first input / output pad 605 may be connected to at least one of the plurality of circuit elements 620a, 620b, and 620c disposed in the peripheral circuit region PERI through the first input / output contact plug 603, and may be separated from the first substrate 610 by the lower insulating film 601. In addition, a side insulating film may be disposed between the first input / output contact plug 603 and the first substrate 610 to electrically separate the first input / output contact plug 603 and the first substrate 610.

[0103] The upper insulating film 501 covering the upper surface of the second substrate 510 may be formed on the second substrate 510, and the second input / output pad 505 may be disposed on the upper insulating film 501. The second input / output pad 505 may be connected to at least one of the plurality of circuit elements 620a, 620b, and 620c disposed in the peripheral circuit region PERI through the second input / output contact plug 503.

[0104] According to an embodiment, the second substrate 510 and the common source line 520 may not be disposed in the region where the second input / output contact plug 503 is disposed. In addition, the second input / output pad 505 may not overlap the word line 530 in the vertical direction VD. The second input / output contact plug 503 may be separated from the second substrate 510 in a direction parallel to the upper surface of the second substrate 510, and may penetrate the interlayer insulating layer of the cell region CELL to be connected to the second input / output pad 505.

[0105] According to an embodiment, the first input / output pad 605 and the second input / output pad 505 may be selectively formed. For example, the memory device 400 may include only the first input / output pad 605 disposed on the first substrate 610 or the second input / output pad 505 disposed on the second substrate 510. Alternatively, the memory device 400 may include both the first input / output pad 605 and the second input / output pad 505.

[0106] In each of the external pad bonding region PA and the bit line bonding region BLBA respectively included in the cell region CELL and the peripheral circuit region PERI, the metal pattern disposed on the uppermost metal layer may be set as a dummy pattern or the uppermost metal layer may not exist.

[0107] In the external pad bonding area PA, the memory device 500 may include a lower metal pattern 673a corresponding to an upper metal pattern 572a formed in the uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern 572a of the cell region CELL to be connected to each other in the uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern 673a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to the contact. Similarly, in the external pad bonding area PA, an upper metal pattern corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL.

[0108] Lower bonding metals 671b and 672b may be formed on the second metal layer 640b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 671b and 672b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 571b and 572b of the cell region CELL by Cu-Cu bonding.

[0109] In addition, in the bit line bonding area BLBA, an upper metal pattern 592 corresponding to a lower metal pattern 652 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same cross-sectional shape as the lower metal pattern 652 may be formed in the uppermost metal layer of the cell region CELL. No contact may be formed on the upper metal pattern 592 formed in the uppermost metal layer of the cell region CELL.

[0110] FIG. 28 is a block diagram of a solid state drive (SSD) system 1000 using a memory device according to an exemplary embodiment.

[0111] Referring to FIG. 28, the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may exchange signals SIG with the host 1100 through a signal connector 1201, and may receive power PWR through a power connector 1202. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1230, a buffer memory 1240, and memory devices 1221, 1222, and 122n. The memory devices 1221, 1222, and 122n may include vertically stacked NAND flash memory devices. Here, the SSD 1200 may be implemented using the embodiments described above with reference to FIGS. 1 to 27.

[0112] In addition, the memory device 10, the host 1100, and the SSD 1200 and / or components included therein may include processing circuitry, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuitry may include, but is not limited to, a central processing unit (CPU), a memory controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0113] Although the inventive concept has been specifically illustrated and described with reference to its embodiments, it should be understood that various changes may be made in form and detail without departing from the spirit and scope of the following claims.

Brief Description of the Drawings

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of a memory device according to an exemplary embodiment. FIG. 2 is a circuit diagram of a memory block according to an exemplary embodiment. FIG. 3A is a perspective view of a memory block according to an exemplary embodiment. FIG. 3B is a perspective view of a memory block according to an exemplary embodiment. FIG. 4 is a schematic diagram of a memory device having a cell-on-periphery (COP) structure according to an exemplary embodiment. FIG. 5 is a plan view of a memory device according to an exemplary embodiment. FIG. 6 shows a first semiconductor layer and a second semiconductor layer of a memory device according to an exemplary embodiment. FIG. 7 is an enlarged plan view of some elements in region EX1 in FIG. 6 according to an exemplary embodiment. FIG. 8 is an enlarged perspective view of some elements in region EX1 in FIG. 6 according to an exemplary embodiment. FIG. 9 is a schematic plan view of a portion of a memory device according to an exemplary embodiment. FIG. 10 is a plan view of a portion of the memory device of FIG. 9 according to an exemplary embodiment. FIG. 11 is a cross-sectional view taken along line X1-X1' in FIG. 10 according to an exemplary embodiment. FIG. 12 is a cross-sectional view taken along line Y1-Y1' in FIG. 10 according to an exemplary embodiment. FIG. 13 is a cross-sectional view taken along line Y2-Y2' in FIG. 10 according to an exemplary embodiment. FIG. 14 shows a first semiconductor layer and a second semiconductor layer of a memory device according to an exemplary embodiment. FIG. 15 is a schematic plan view of a portion of a memory device according to an exemplary embodiment. FIG. 16 is a plan view of a portion of the memory device of FIG. 15 according to an exemplary embodiment. FIG. 17 is a cross-sectional view taken along line X2-X2' in FIG. 16 according to an exemplary embodiment. FIG. 18 is a cross-sectional view taken along line Y3-Y3' in FIG. 16 according to an exemplary embodiment. FIG. 19 is a cross-sectional view taken along line Y4-Y4' in FIG. 16 according to an exemplary embodiment. FIG. 20A is an enlarged cross-sectional view of some elements in region EX3 in FIG. 19 according to an exemplary embodiment. FIG. 20B is an enlarged cross-sectional view of some elements in region EX3 in FIG. 19 according to an exemplary embodiment. FIG. 21 shows a first semiconductor layer and a second semiconductor layer of a memory device according to an exemplary embodiment. FIG. 22 is a schematic plan view of a portion of a memory device according to an exemplary embodiment. FIG. 23 is a plan view of a portion of the memory device of FIG. 22 according to an exemplary embodiment. FIG. 24 is a cross-sectional view taken along line X3-X3' in FIG. 23 according to an exemplary embodiment. FIG. 25 is a cross-sectional view taken along line Y5-Y5' in FIG. 23 according to an exemplary embodiment. FIG. 26 is a cross-sectional view taken along line Y6-Y6' in FIG. 23 according to an exemplary embodiment. FIG. 27 is a cross-sectional view of a memory device having a bonding vertical NAND (B-VNAND) structure according to an exemplary embodiment.FIG. 28 is a block diagram of a solid state drive (SSD) system using a memory device according to an exemplary embodiment.

Claims

1. A non-volatile memory device, comprising: The memory cell region includes an upper substrate, a channel structure, and an upper metal line. The channel structure extends vertically on the upper substrate, and the upper metal line extends horizontally above the channel structure. The peripheral circuit region includes, in the vertical direction below the memory cell region, a first lower metal line extending in the second horizontal direction, a first via structure on the first lower metal line, and a second via structure on the first lower metal line. The top surface of the second via structure contacts the upper substrate. The memory cell region further includes a first through-hole via structure that penetrates the upper substrate in the vertical direction and extends from the memory cell region into the upper portion of the peripheral circuit region to electrically connect the upper metal line to the first lower metal line. The upper metal line is electrically connected to the upper substrate through the first through-hole via structure, the first lower metal line, and the second via structure.

2. The non-volatile memory device as claimed in claim 1, wherein the upper substrate includes a plate-shaped common source line.

3. The non-volatile memory device as claimed in claim 1, wherein the upper metal line corresponds to a common source line tap conductor.

4. The non-volatile memory device as claimed in claim 1, wherein the first horizontal direction is perpendicular to the second horizontal direction.

5. The non-volatile memory device as claimed in claim 1, wherein the memory cell region further comprises: Multiple bit lines are at the same horizontal height as the upper metal line in the vertical direction and extend in the first horizontal direction; And a bitline through-hole structure extending in the second horizontal direction in the bitline through-hole region, the bitline through-hole structure electrically connecting the plurality of bitlines to the peripheral circuit region respectively.

6. The non-volatile memory device as claimed in claim 1, wherein the first through-hole structure is adjacent to the character line cut structure in the first horizontal direction, and the peripheral circuit region further includes control logic circuitry below the character line cut structure and the first through-hole structure in the vertical direction.

7. The non-volatile memory device as claimed in claim 1, wherein the first through-hole structure is located between the top edge of the upper substrate and the character wire cut structure, the character wire cut structure being adjacent to the top edge of the upper substrate.

8. The non-volatile memory device as claimed in claim 1, wherein the first through-hole structure is located between the bottom edge of the upper substrate and the character wire cut structure, the character wire cut structure being adjacent to the bottom edge of the upper substrate.

9. The non-volatile memory device as claimed in claim 1, wherein the upper substrate comprises polysilicon, the polysilicon including impurity-doped regions, and the impurity-doped regions corresponding to a common source line of the plate shape.

10. The non-volatile memory device of claim 1, wherein the upper substrate comprises sequentially stacked polysilicon, a first conductive plate, and a second conductive plate, and the first conductive plate and the second conductive plate correspond to a common source line in the plate shape.

11. A non-volatile memory device, comprising: The first semiconductor layer includes a plate-shaped common source line, a channel structure, a common source line tap wire, and a first through-hole structure. The channel structure extends vertically on the plate-shaped common source line, the common source line tap wire extends horizontally on the channel structure, and the first through-hole structure passes through the plate-shaped common source line and extends vertically. And a second semiconductor layer, located below the first semiconductor layer in the vertical direction, the second semiconductor layer including a lower substrate, circuit elements on the lower substrate, a plurality of lower metal layers connected to the circuit elements, and a plurality of via structures on a first lower metal layer adjacent to the first semiconductor layer among the plurality of lower metal layers, the first lower metal layer extending in a second horizontal direction, wherein the first through-hole via structure extends from the first semiconductor layer to the upper portion of the second semiconductor layer and electrically connects the common source line tap wire to the first lower metal layer, and the common source line tap wire is electrically connected to the plate-shaped common source line through the first through-hole via structure, the first lower metal layer, and the plurality of via structures.

12. The non-volatile memory device as claimed in claim 11, wherein the first semiconductor layer further comprises: Multiple bit lines extend in the first horizontal direction at the same horizontal height as the common source line tap-through conductor in the vertical direction; And a bitline through-hole structure, which extends in the second horizontal direction in the bitline through-hole region, wherein the bitline through-hole structure electrically connects the plurality of bitlines to the peripheral circuit region respectively.

13. The non-volatile memory device of claim 12, wherein the second semiconductor layer further includes a page buffer in the vertical direction below the bit line through-hole region, and the bit line through-hole structure electrically connects the plurality of bit lines to the page buffer.

14. The non-volatile memory device as claimed in claim 12, wherein the first through-hole structure is adjacent to the bitline through-hole region in the first horizontal direction.

15. The non-volatile memory device of claim 11, wherein the first through-hole structure is adjacent to the character line cut structure in the first horizontal direction, and the second semiconductor layer further includes control logic circuitry below the character line cut structure and the first through-hole structure in the vertical direction.

16. A non-volatile memory device, comprising: A first semiconductor layer includes a first memory block, a second memory block, a first through-hole region adjacent to the first memory block, a bit line through-hole region adjacent to the first through-hole region, and a second through-hole region between the bit line through-hole region and the second memory block; and a second semiconductor layer, located below the first semiconductor layer in a vertical direction, the second semiconductor layer including a first lower metal line and a second lower metal line separated from the first lower metal line in a first horizontal direction, wherein the first through-hole region includes a first through-hole structure connecting the upper metal line to the first lower metal line, the upper metal line being above the first memory block and the second memory block and extending in the first horizontal direction, and the second through-hole region including a second through-hole structure connecting the upper metal line to the second lower metal line.

17. The non-volatile memory device of claim 16, wherein the first semiconductor layer further includes a plate-shaped common source line, the second semiconductor layer further includes a first via structure on the first lower metal line and a second via structure on the second lower metal line, the upper metal line being electrically connected to the plate-shaped common source line through the first through-hole via structure, the first lower metal line and the first via structure, and the upper metal line being electrically connected to the plate-shaped common source line through the second through-hole via structure, the second lower metal line and the second via structure.

18. The non-volatile memory device of claim 16, wherein the first semiconductor layer further includes a plurality of bit lines at the same horizontal height as the upper metal line in the vertical direction, and the bit line through-hole region includes a bit line through-hole structure connecting the plurality of bit lines to the second semiconductor layer.

19. The non-volatile memory device as claimed in claim 18, wherein each of the first memory block and the second memory block includes a channel structure extending in the vertical direction and connected to the plurality of bit lines.

20. The non-volatile memory device as claimed in claim 16, wherein the first lower metal line and the second lower metal line are at the same horizontal height relative to each other in the vertical direction and extend in a second horizontal direction perpendicular to the first horizontal direction.

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