Display device and manufacturing method thereof

Abstract

A display device includes a plurality of light-emitting elements disposed on a substrate, wherein each of the plurality of light-emitting elements includes a first semiconductor layer, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, and a porous layer disposed on the second semiconductor layer.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2021 - 0056852, filed with the Korean Intellectual Property Office (KIPO) on April 30, 2021, the entire content of which is incorporated herein by reference.

[0003] Embodiments of the present disclosure relate to a light - emitting display device and a method of manufacturing the same.

Prior Art

[0004] In recent years, with the increasing interest in information display, research and development of display devices have been continuously carried out.

Summary of the Invention

[0005] Aspects of the present disclosure may provide a display device and a method of manufacturing the same that can improve the light output efficiency of a display panel and simplify the manufacturing process.

[0006] Aspects of the present disclosure are not limited to the above, and other aspects not mentioned herein will be clearly understood by those of ordinary skill in the art to which the present disclosure pertains through the following description.

[0007] A display device according to an embodiment may include a light - emitting element disposed on a substrate. Each light - emitting element may include a first semiconductor layer, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, and a porous layer disposed on the second semiconductor layer.

[0008] The porous layer may include nano - scale holes.

[0009] The porous layer and the second semiconductor layer may include the same material.

[0010] The display device may further include a barrier rib pattern disposed on the substrate, wherein each light - emitting element may be disposed between the barrier rib patterns.

[0011] The barrier rib pattern and the light - emitting element may include the same material.

[0012] The display device may further include a color conversion layer disposed on the light - emitting element.

[0013] The display device may further include a reflective layer disposed between the light-emitting elements.

[0014] The display device may further include an insulating layer disposed between the light-emitting element and the reflective layer.

[0015] The light-emitting element may include a first light-emitting element that emits light of a first color, a second light-emitting element that emits light of a second color, and a third light-emitting element that emits light of a third color.

[0016] A method of manufacturing a display device according to an embodiment may include: forming a semiconductor layer; etching the semiconductor layer to form a porous layer; and disposing a light-emitting stack on the porous layer to form a light-emitting element.

[0017] Forming the porous layer may include forming nano-scale holes by etching the semiconductor layer.

[0018] Disposing the light-emitting stack may include etching the porous layer and the light-emitting stack.

[0019] The light-emitting stack may include a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer.

[0020] The second semiconductor layer and the porous layer may be formed of the same material.

[0021] The method of manufacturing the display device may further include etching the porous layer and the light-emitting stack to form a barrier pattern.

[0022] The barrier pattern and the light-emitting element may be formed simultaneously.

[0023] Forming the semiconductor layer may include forming a second semiconductor layer between the porous layer and the light-emitting stack.

[0024] Disposing the light-emitting stack may include disposing the active layer on the second semiconductor layer and disposing the first semiconductor layer on the active layer.

[0025] The method of manufacturing the display device may further include forming a planarization layer between the light-emitting elements.

[0026] The method of manufacturing the display device may further include forming a reflective layer between the light-emitting elements.

[0027] Specific details of other embodiments are included in the specification and the drawings.

[0028] According to an embodiment of the present disclosure, the porous region included in the light-emitting element can scatter the light emitted from the light-emitting region, thereby improving the light output efficiency. Therefore, since the scattering layer separately provided in the pixel can be omitted, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0029] The effects according to the embodiments are not limited to the above examples, and more various effects are included in the specification.

Embodiments

[0031] The advantages and features of the present disclosure and methods for realizing the same will be clarified by the embodiments described below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in various forms. Providing these embodiments will make the present disclosure more complete and fully inform those of ordinary skill in the art to which the present disclosure pertains of the scope of the present disclosure, and the present disclosure will be defined by the scope of the claims including equivalents thereof.

[0032] The terms used in this specification are for the purpose of describing embodiments only and are not intended to limit the present disclosure. In this specification, unless otherwise specified, the singular forms also include the plural forms (and vice versa). The terms "comprises", "comprising", "has", "have", "having", "include", "including" and similar terms used herein do not exclude the presence or addition of one or more other components, steps, operations and / or elements other than the components, steps, operations and / or elements mentioned.

[0033] In addition, the term "connection" or "access" can commonly represent a physical and / or electrical connection or access. In addition, it can commonly represent a direct or indirect connection or access and an overall or non-overall connection or access.

[0034] It can be understood that when an element or layer is referred to as "on" another element or layer, it can be directly on the other element or layer, or there may be intermediate elements or layers. Throughout the specification, the same reference numerals denote the same elements.

[0035] Although the terms "first", "second", and similar terms are used to describe various components, these components are not limited by these terms. These terms are used to distinguish one component from another. Therefore, without departing from the spirit of the present disclosure, the first component described hereinafter may be the second component.

[0036] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0037] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a combined or separate sense and can be understood to be equivalent to "and / or".

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It can be further understood that, unless otherwise clearly defined, terms, such as those defined in a common dictionary, should be interpreted as having a meaning consistent with their meaning in the relevant field and the context of this disclosure, and should not be idealized or interpreted too formally unless clearly defined herein.

[0039] FIG. 1 is a plan schematic view of a display device according to an embodiment.

[0040] FIG. 1 illustrates a display device capable of using a light-emitting element as a light source, specifically, a display panel PNL disposed in the display device.

[0041] For convenience of explanation, the structure of the display panel PNL will be briefly described with reference to the display area DA in FIG. 1. However, at least one driving circuit unit (e.g., at least one of a scan driver and a data driver), lines, and / or pads that are not shown may be further provided on the display panel PNL according to an embodiment.

[0042] Referring to FIG. 1, the display panel PNL may include a substrate SUB and pixel units PXU disposed on the substrate SUB. The pixel units PXU may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. Hereinafter, when at least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be arbitrarily referred to, or when two or more types of pixels can be collectively referred to, they may be referred to as "pixel(s) PXL".

[0043] The substrate SUB may constitute a base member of the display panel PNL and may be a rigid or flexible substrate or film. For example, the substrate SUB may be a rigid substrate made of glass or tempered glass, or a flexible substrate (or film) made of plastic or metal, and there is no particular limitation on the material and / or physical properties of the substrate SUB.

[0044] The display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA other than the display area DA. The pixels PXL may be disposed in the display area DA. Various lines, pads, and / or built-in circuit units connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA. The pixels PXL may be regularly arranged in a stripe arrangement structure or a PENTILE™ arrangement structure. However, the arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in various structures and / or methods in the display area DA.

[0045] According to an embodiment, two or more types of pixels PXL that emit light of different colors may be disposed in the display area DA. For example, in the display area DA, a first pixel PXL1 that emits light of a first color, a second pixel PXL2 that emits light of a second color, and a third pixel PXL3 that emits light of a third color may be arranged in the display area DA. At least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 adjacent to each other may constitute a pixel unit PXU capable of emitting light of various colors. For example, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be a sub-pixel that emits light of one color. According to an embodiment, the first pixel PXL1 may be a red pixel that emits red light, the second pixel PXL2 may be a green pixel that emits green light, and the third pixel PXL3 may be a blue pixel that emits blue light, but the embodiment is not limited thereto.

[0046] In one embodiment, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a light-emitting element that emits light of the same color as each other, and may include color conversion layers and / or color filters of different colors disposed on the respective light-emitting elements to emit light of the first color, the second color, and the third color, respectively. In another embodiment, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may use a light-emitting element of the first color, a light-emitting element of the second color, and a light-emitting element of the third color as light sources, respectively, so as to emit light of the first color, the second color, and the third color, respectively. However, the colors, types, and / or numbers of the pixels PXL constituting the pixel unit PXU are not particularly limited. For example, the colors of the light emitted from the respective pixels PXL may be variously changed.

[0047] The pixel PXL may include at least one light source driven by a control signal (e.g., a scan signal and a data signal) and / or a power source (e.g., a first power source and a second power source). In one embodiment, the light source may include ultra-small pillar light-emitting elements having a size as small as the nanoscale to the microscale. However, the present disclosure is not limited thereto, and various types of light-emitting elements may be used as the light source of the pixel PXL.

[0048] In one embodiment, each pixel PXL may be formed of an active pixel. However, the types, structures, and / or driving methods of the pixels PXL applicable to the display device are not particularly limited. For example, each pixel PXL may be made of pixels of passive or active light-emitting display devices having various structures and / or driving methods.

[0049] FIG. 2 is a circuit schematic diagram of a pixel according to an embodiment.

[0050] FIG. 2 illustrates the electrical connection relationship between the components included in the pixel PXL that can be applied to an active display device. However, the types of components included in the pixel PXL are not limited thereto.

[0051] According to an embodiment, the pixel PXL illustrated in FIG. 2 can be any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 disposed in the display panel PNL of FIG. 1. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can have substantially the same or similar structures to each other.

[0052] Referring to FIG. 2, each pixel PXL can include a light-emitting unit EMU that generates light having a luminance corresponding to a data signal. In addition, the pixel PXL can further include a pixel circuit PXC for driving the light-emitting unit EMU.

[0053] According to an embodiment, the light-emitting unit EMU can include at least one light-emitting element LD, which is electrically connected between a first power line PL1 to which a voltage of a first power supply VDD can be applied and a second power line PL2 to which a voltage of a second power supply VSS can be applied. For example, the light-emitting unit EMU can include a first electrode ET1 connected to the first power supply VDD through the pixel circuit PXC and the first power line PL1, a second electrode ET2 connected to the second power supply VSS through the second power line PL2, and a light-emitting element LD connected between the first electrode ET1 and the second electrode ET2. In one embodiment, the first electrode ET1 can be an anode, and the second electrode ET2 can be a cathode.

[0054] The light-emitting element LD can include one end connected to the first power supply VDD and the other end connected to the second power supply VSS. In an embodiment, one end of the light-emitting element LD can be integrally provided with the first electrode ET1 to be connected to the first electrode ET1, and the other end of the light-emitting element LD can be integrally provided with the second electrode ET2 to be connected to the second electrode ET2. The first power supply VDD and the second power supply VSS can have different potentials. In this case, during the light-emitting period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS can be set to be equal to or greater than the threshold voltage of the light-emitting element LD.

[0055] The light-emitting element LD can constitute an effective light source of the light-emitting unit EMU. The light-emitting element LD can emit light having a brightness corresponding to the driving current supplied through the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC can supply a driving current corresponding to the gray value of the corresponding frame data to the light-emitting unit EMU. The driving current supplied to the light-emitting unit EMU can flow through the light-emitting element LD. Therefore, the light-emitting element LD can emit light having a brightness corresponding to the driving current, and the light-emitting unit EMU can emit light.

[0056] The pixel circuit PXC can be connected to the scan line Si and the data line Dj of the pixel PXL. For example, when the pixel PXL is disposed in the i-th column (i can be a natural number) and the j-th row (j can be a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. According to an embodiment, the pixel circuit PXC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst. However, the structure of the pixel circuit PXC is not limited to the embodiment illustrated in FIG. 2.

[0057] The pixel circuit PXC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0058] The first terminal of the first transistor T1 (i.e., the driving transistor) can be connected to the first power supply VDD, and its second terminal can be electrically connected to the light-emitting element LD. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of the driving current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0059] The first terminal of the second transistor T2 (i.e., the switching transistor) can be connected to the j-th data line Dj, and its second terminal can be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 can be different terminals. For example, when the first terminal is the source electrode, the second terminal can be the drain electrode. The gate electrode of the second transistor T2 can be connected to the i-th scan line Si.

[0060] When a scan signal having a voltage that enables the second transistor T2 to conduct is supplied from the i-th scan line Si, the second transistor T2 can be turned on and can electrically connect the j-th data line Dj and the first node N1. In this case, the data signal of the corresponding frame can be supplied to the j-th data line Dj, and thus, the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be charged into the storage capacitor Cst.

[0061] The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1, and can maintain the charged voltage until the data signal of the next frame can be supplied.

[0062] In FIG. 2, the pixel circuit PXC is illustrated as including a second transistor T2 for transmitting a data signal to the pixel PXL, a storage capacitor Cst for storing the data signal, and a first transistor T1 for supplying a drive current corresponding to the data signal to the light-emitting element LD. However, the present disclosure is not limited thereto, and the structure of the pixel circuit PXC can be variously changed. For example, the pixel circuit PXC may further include at least one transistor element, such as a transistor element for compensating the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the light-emitting time of the light-emitting element LD and the like, or other circuit elements, such as a boosting capacitor for boosting the voltage of the first node N1 and the like. In addition, the first transistor T1 and the second transistor T2 of the pixel circuit PXC are not limited to FIG. 2, and can be variously changed to an N-type metal oxide semiconductor (NMOS) or a P-type metal oxide semiconductor (PMOS).

[0063] FIG. 3 and FIG. 4 are schematic cross-sectional views of a pixel according to an embodiment.

[0064] FIG. 3 and FIG. 4 schematically illustrate the cross-sectional structures of a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 adjacent to each other.

[0065] Referring to FIG. 3 and FIG. 4, the pixel PXL and the display device including the pixel PXL may include a substrate SUB, a barrier rib pattern BNP provided on the substrate SUB, a light-emitting element LD, a color conversion layer CCL, and a color filter layer CFL.

[0066] The substrate SUB may be a driving substrate including circuit elements, and the circuit elements include transistors constituting the pixel circuit PXC (refer to FIG. 2) of each pixel PXL. For example, the substrate SUB may be a driving substrate manufactured in a wafer state. The substrate SUB may use a complementary metal oxide semiconductor (CMOS) substrate including a combination of an N-type metal oxide semiconductor and a P-type metal oxide semiconductor, but the present disclosure is not limited thereto.

[0067] The barrier pattern BNP can be disposed on the boundary between the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 on the substrate SUB. Each barrier pattern BNP can be disposed in a shape extending in one direction. For example, each barrier pattern BNP can be disposed on the substrate SUB in a shape extending in the third direction (i.e., the Z-axis direction) from the substrate SUB.

[0068] The barrier pattern BNP can include a first semiconductor layer B1, an active layer B2, a second semiconductor layer B3, and a porous layer BP. For example, the first semiconductor layer B1, the active layer B2, the second semiconductor layer B3, and the porous layer BP of the barrier pattern BNP can be sequentially stacked on the substrate SUB in the third direction (i.e., the Z-axis direction).

[0069] The first semiconductor layer B1 of the barrier pattern BNP can include, for example, at least one P-type semiconductor layer. For example, the first semiconductor layer B1 of the barrier pattern BNP can include at least one semiconductor material among gallium nitride (GaN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN), and can include a P-type semiconductor layer doped with a first conductive dopant (or P-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), its analogs, or a combination thereof. For example, the first semiconductor layer B1 of the barrier pattern BNP can include a gallium nitride semiconductor material doped with a first conductive dopant (or P-type dopant), but is not limited thereto. The first semiconductor layer B1 of the barrier pattern BNP can be formed of various other materials.

[0070] The active layer B2 of the barrier pattern BNP can be disposed between the first semiconductor layer B1 and the second semiconductor layer B3. The active layer B2 of the barrier pattern BNP can include at least one of a single well structure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but is not limited thereto. The active layer B2 of the barrier pattern BNP can include gallium nitride (GaN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof, and various other materials can constitute the active layer B2 of the barrier pattern BNP.

[0071] The second semiconductor layer B3 of the blocking wall pattern BNP can be disposed on the active layer B2 and can include a semiconductor layer of a different type from the first semiconductor layer B1. In one embodiment, the second semiconductor layer B3 of the blocking wall pattern BNP can include at least one N-type semiconductor layer. For example, the second semiconductor layer B3 of the blocking wall pattern BNP can include at least one semiconductor material among gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN), and can be an N-type semiconductor layer doped with a second conductive dopant (or N-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), and their analogs, or a combination thereof. For example, the second semiconductor layer B3 of the blocking wall pattern BNP can include gallium nitride semiconductor material doped with a second conductive dopant (or N-type dopant). However, the material constituting the second semiconductor layer B3 of the blocking wall pattern BNP is not limited thereto, and the second semiconductor layer B3 of the blocking wall pattern BNP can be formed of various other materials.

[0072] The porous layer BP of the blocking wall pattern BNP can be disposed on the second semiconductor layer B3. The porous layer BP of the blocking wall pattern BNP can include the same material as the second semiconductor layer B3, but is not limited thereto. For example, the porous layer BP of the blocking wall pattern BNP can include at least one N-type semiconductor layer. For example, the porous layer BP of the blocking wall pattern BNP can include at least one semiconductor material among gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN), and can be an N-type semiconductor layer doped with a second conductive dopant (or N-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), and their analogs, or a combination thereof. For example, the porous layer BP of the blocking wall pattern BNP can include gallium nitride semiconductor material doped with a second conductive dopant (or N-type dopant). However, the material constituting the porous layer BP of the blocking wall pattern BNP is not limited thereto, and the porous layer BP of the blocking wall pattern BNP can be formed of various other materials.

[0073] The porous layer BP of the blocking wall pattern BNP can include a plurality of holes P. The holes P can be nano-scale holes P formed by electrochemical etching, but are not limited thereto. This will be described in detail with reference to FIG. 8 below.

[0074] The barrier wall pattern BNP may further include a mask layer (first mask layer MK1, second mask layer MK2) disposed on the porous layer BP. The mask layer may include a first mask layer MK1 disposed on the porous layer BP and a second mask layer MK2 disposed on the first mask layer MK1. The first mask layer MK1 and the second mask layer MK2 may be formed of different materials. For example, the first mask layer MK1 may include silicon oxide (SiOx), and the second mask layer MK2 may include nickel (Ni), but is not limited thereto.

[0075] According to an embodiment, as shown in FIG. 4, the barrier wall pattern BNP may further include a semiconductor layer B4 disposed between the porous layer BP and the mask layer (first mask layer MK1, second mask layer MK2). The semiconductor layer B4 may include a semiconductor material such as undoped gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof, but is not limited thereto. The thickness of the semiconductor layer B4 in the third direction (i.e., the Z-axis direction) may be less than the thickness of the porous layer BP in the third direction (i.e., the Z-axis direction), but is not limited thereto.

[0076] The light-emitting element LD may be disposed in each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The light-emitting element LD may be disposed between the barrier wall patterns BNP on the substrate SUB.

[0077] Each light-emitting element LD may be provided in various shapes. For example, the light-emitting element LD may have a rod-like shape or a bar-like shape that may be longer in the third direction (i.e., the Z-axis direction) (i.e., the aspect ratio is greater than 1), but is not limited thereto. For example, each light-emitting element LD may have a column shape, and the diameter of one end may be different from the diameter of the other end. The light-emitting element LD may be a light-emitting diode (LED) manufactured to have an extremely small size with a diameter and / or length in the nanoscale to the microscale. However, the present disclosure is not limited thereto, and the size of the light-emitting element LD may be variously changed to meet the requirements (or design conditions) of the lighting device or display device to which the light-emitting element LD can be applied.

[0078] Each light-emitting element LD may include a light-emitting region EA and a porous region PA. The light-emitting region EA may be disposed between the substrate SUB and the porous region PA.

[0079] The light-emitting region EA may include a first semiconductor layer L1, a second semiconductor layer L3, and an active layer L2 interposed between the first semiconductor layer L1 and the second semiconductor layer L3. For example, the first semiconductor layer L1, the active layer L2, and the second semiconductor layer L3 of the light-emitting element LD may be sequentially stacked on the substrate SUB in a third direction (i.e., the Z-axis direction).

[0080] The first semiconductor layer L1 of the light-emitting element LD may include, for example, at least one P-type semiconductor layer. For example, the first semiconductor layer L1 of the light-emitting element LD may include at least one semiconductor material among gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN), and may include a P-type semiconductor layer doped with a first conductive dopant (or P-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), its analogs, or a combination thereof. For example, the first semiconductor layer L1 of the light-emitting element LD may include a gallium nitride semiconductor material doped with a first conductive dopant (or P-type dopant), but is not limited thereto. The first semiconductor layer L1 of the light-emitting element LD may be formed of various other materials.

[0081] The active layer L2 of the light-emitting element LD may be disposed between the first semiconductor layer L1 and the second semiconductor layer L3. The active layer L2 of the light-emitting element LD may include at least one of a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but is not limited thereto. The active layer L2 of the light-emitting element LD may include gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof, and various other materials may constitute the active layer L2 of the light-emitting element LD.

[0082] When a signal (or voltage) is applied to each end of the light-emitting element LD, each light-emitting element LD emits light while electron-hole pairs are combined in the active layer L2 of the light-emitting element LD. By using this principle to control the light emission of the light-emitting element LD, the light-emitting element LD can be used as a light source for various light-emitting devices including pixels of a display device.

[0083] According to an embodiment, an electron blocking layer (EBL) may be further disposed between the active layer L2 of the light-emitting element LD and the first semiconductor layer L1. The electron blocking layer may block the escape of the electron current supplied from the second semiconductor layer L3 to the first semiconductor layer L1, thereby increasing the recombination probability of electrons and holes in the active layer L2. The energy bandgap of the electron blocking layer may be greater than the energy bandgap of the active layer L2 and / or the first semiconductor layer L1, but is not limited thereto.

[0084] According to an embodiment, super lattice layers (SLs) may be further disposed between the active layer L2 of the light-emitting element LD and the second semiconductor layer L3. The super lattice layers may relieve the stress between the active layer L2 and the second semiconductor layer L3, thereby improving the quality of the light-emitting element LD. For example, the super lattice layers may be formed in a structure in which indium gallium nitride and gallium nitride are alternately stacked, but are not limited thereto.

[0085] The second semiconductor layer L3 of the light-emitting element LD may be disposed on the active layer L2 and may include a semiconductor layer of a different type from the first semiconductor layer L1. In one embodiment, the second semiconductor layer L3 of the light-emitting element LD may include at least one N-type semiconductor layer. For example, the second semiconductor layer L3 of the light-emitting element LD may include semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof, and may be an N-type semiconductor layer doped with a second conductive dopant (or N-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), and the like, or a combination thereof. For example, the second semiconductor layer L3 of the light-emitting element LD may include gallium nitride semiconductor material doped with a second conductive dopant (or N-type dopant). However, the material constituting the second semiconductor layer L3 of the light-emitting element LD is not limited thereto, and various materials may be used to form the second semiconductor layer L3 of the light-emitting element LD.

[0086] A porous region PA may be disposed on the second semiconductor layer L3 of the light-emitting region EA. For example, the porous region PA may be directly formed on the second semiconductor layer L3 of the light-emitting region EA. The porous region PA may include the same material as the second semiconductor layer L3, but is not limited thereto.

[0087] The porous region PA may include a porous layer LP. The porous layer LP of the light-emitting element LD may include the same material as the second semiconductor layer L3, but is not limited thereto. For example, the porous layer LP of the light-emitting element LD may include at least one N-type semiconductor layer. For example, the porous layer LP of the light-emitting element LD may include semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof, and may be an N-type semiconductor layer doped with a second conductive dopant (or N-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), and the like, or a combination thereof. For example, the porous layer LP of the light-emitting element LD may include a gallium nitride semiconductor material doped with a second conductive dopant (or N-type dopant). However, the material constituting the porous layer LP of the light-emitting element LD is not limited thereto, and various other materials may be used to form the porous layer LP of the light-emitting element LD.

[0088] The porous region PA may include a plurality of holes P present in the porous layer LP. The holes P may be nano-scale holes P formed by electrochemical etching, but are not limited thereto. This will be described in detail with reference to FIG. 8 below.

[0089] The porous region PA may be disposed on the light-emitting region EA to scatter the light emitted from the light-emitting region EA, thereby improving the light output efficiency. For example, the refractive index of the porous region PA may be reduced by the plurality of holes P, thereby improving the light extraction efficiency. For example, the porous region PA may be used as a scattering layer. Thereby, in the case where the porous region PA is included in the light-emitting element LD, a separately provided scattering layer in the pixel PXL may be omitted, thereby simplifying the manufacturing process and reducing the cost. The porous region PA may be disposed between the light-emitting region EA and the color conversion layer CCL to be described below to effectively prevent the color conversion layer CCL from being damaged due to the heat generation of the light-emitting region EA.

[0090] In one embodiment, the light-emitting element LD and the barrier pattern BNP may include the same material. For example, the first semiconductor layer L1, the active layer L2, the second semiconductor layer L3, and / or the porous layer LP of the light-emitting element LD may respectively include the same material as the first semiconductor layer B1, the active layer B2, the second semiconductor layer B3, and / or the porous layer BP of the above-described barrier pattern BNP. In this case, the first semiconductor layer L1, the active layer L2, the second semiconductor layer L3, and / or the porous layer LP of the light-emitting element LD may be simultaneously formed in the same process as the first semiconductor layer B1, the active layer B2, the second semiconductor layer B3, and / or the porous layer BP of the barrier pattern BNP. Therefore, the manufacturing process of the display device can be simplified to ensure the economic efficiency of the process. A detailed description thereof will be given below with reference to FIG. 12.

[0091] The light-emitting element LD may be disposed on the first electrode ET1 provided on the substrate SUB. For example, the first semiconductor layer L1 of the light-emitting element LD may be disposed on the first electrode ET1 to be electrically connected to the first electrode ET1. The first electrode ET1 may include a metal or a metal oxide. For example, the first electrode ET1 may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), its oxide, or its alloy, and the like, and may include an oxide or an alloy, but is not limited thereto.

[0092] According to one embodiment, connection electrodes (the first connection electrode CE1, the second connection electrode CE2) may be further provided between the substrate SUB, the light-emitting element LD, and / or the barrier pattern BNP. The connection electrodes may include the first connection electrode CE1 provided between the light-emitting element LD and the substrate SUB and the second connection electrode CE2 provided between the barrier pattern BNP and the substrate SUB.

[0093] The first connection electrode CE1 may be disposed between the first semiconductor layer L1 of the light-emitting element LD and the first electrode ET1 provided on the substrate SUB. The light-emitting element LD may be electrically connected to the first electrode ET1 provided on the substrate SUB through the first connection electrode CE1.

[0094] The second connection electrode CE2 may include the same material as the first connection electrode CE1. For example, each of the first connection electrode CE1 and the second connection electrode CE2 may include a metal or a metal oxide. For example, each of the first connection electrode CE1 and the second connection electrode CE2 may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), its oxide, or its alloy, and the like, but is not limited thereto. The second connection electrode CE2 may be formed simultaneously in the same process as the first connection electrode CE1, but is not limited thereto.

[0095] A hard mask layer HM may be further disposed between the barrier wall pattern BNP and the second connection electrode CE2. The hard mask layer HM may be disposed between the first semiconductor layer B1 of the barrier wall pattern BNP and the second connection electrode CE2. According to an embodiment, the hard mask layer HM may be omitted.

[0096] An insulating layer INS may be disposed on the surface of the light-emitting element LD and / or the barrier wall pattern BNP. The insulating layer INS may be disposed on the side surface of the light-emitting element LD and / or the barrier wall pattern BNP. The insulating layer INS can prevent an electrical short circuit that may occur when the active layer L2 of the light-emitting element LD contacts a conductive material other than the first semiconductor layer L1 and the second semiconductor layer L3. The insulating layer INS can minimize surface defects of the light-emitting element LD, thereby improving the lifespan and light-emitting efficiency of the light-emitting element LD.

[0097] The insulating layer INS may cover the side surface of the light-emitting element LD and / or the barrier wall pattern BNP, but it may be partially removed to expose the upper surface of the light-emitting element LD and / or the barrier wall pattern BNP. For example, the insulating layer INS may cover the side surface of the light-emitting element LD, but may also be partially removed to expose the porous region PA, i.e., the porous layer LP, of the light-emitting element LD.

[0098] The insulating film INS may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium oxide (TiOx), or a combination thereof, but is not limited thereto.

[0099] The second electrode ET2 can be disposed on the light-emitting element LD. The second electrode ET2 can be directly disposed on the upper surface of the light-emitting element LD exposed by the insulating layer INS. For example, the second electrode ET2 can be directly disposed on the porous region PA, i.e., the porous layer LP, of the light-emitting element LD. The second electrode ET2 can be disposed on the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0100] The second electrode ET2 can be formed of various transparent conductive materials. For example, the second electrode ET2 can include at least one of various transparent conductive materials, and the transparent conductive materials include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), and gallium tin oxide (GTO), and can be implemented to be substantially transparent or semi-transparent to meet the light transmittance. Therefore, the light emitted from the light-emitting element LD can pass through the second electrode ET2 and be emitted to the outside of the display panel PNL.

[0101] The color conversion layer CCL can be disposed on the light-emitting element LD. The color conversion layer CCL can be disposed between the barrier rib patterns BNP. For example, the color conversion layer CCL can be disposed in the space or opening defined by the barrier rib patterns BNP.

[0102] The color conversion layer CCL can include quantum dots as color conversion materials, which convert the light emitted from the light-emitting element LD of each pixel PXL into light of a specific color. For example, the color conversion layer CCL can include a plurality of quantum dots dispersed in a matrix material such as a base resin.

[0103] In one embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a light-emitting element LD that emits light of the same color. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a light-emitting element LD that emits light of a third color (or blue). The color conversion layer CCL may include quantum dots that convert the blue light emitted from the light-emitting element LD into white light. For example, the color conversion layer CCL may include first quantum dots that convert the blue light emitted from the blue light-emitting element into red light and second quantum dots that convert the blue light into green light, but is not limited thereto. In the case of using quantum dots as the color conversion material, the absorption coefficient of the quantum dots can be increased by injecting blue light having a relatively short wavelength in the visible light range into the quantum dots. Therefore, the light-emitting efficiency of the pixel PXL can be improved and excellent color reproducibility can be ensured. The light-emitting units EMU of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be composed of light-emitting elements LD of the same color (e.g., blue light-emitting elements), thereby improving the manufacturing efficiency of the display device. However, the present disclosure is not limited thereto, and the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements LD that emit light of different colors. For example, the first pixel PXL1 may include a light-emitting element LD of a first color (or red), the second pixel PXL2 may include a light-emitting element LD of a second color (or green), and the third pixel PXL3 may include a light-emitting element LD of a third color (or blue).

[0104] According to an embodiment, the reflective layer RF may be disposed between the barrier rib pattern BNP and the color conversion layer CCL. The reflective layer RF may reflect the light emitted from the light-emitting element LD to improve the light output efficiency of the display panel PNL. The reflective layer RF may be disposed on the side surface of the barrier rib pattern BNP to prevent color mixing between adjacent pixels PXL. The material of the reflective layer RF is not particularly limited, and it may include various reflective materials.

[0105] The passivation layer PSV may be disposed on the color conversion layer CCL. The passivation layer PSV may directly cover the color conversion layer CCL. The passivation layer PSV may be disposed on the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The passivation layer PSV may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color conversion layer CCL. The surface of the passivation layer PSV may be in contact with the color conversion layer CCL, and another surface of the passivation layer PSV may be in contact with the color filter layer CFL, which will be described below.

[0106] The passivation layer PSV may include organic materials such as acrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, polyesters resin, polyphenylenesulfides resin, benzocyclobutene (BCB), or a combination thereof, but is not limited thereto.

[0107] According to one embodiment, the passivation layer PSV may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium oxide (TiOx), or a combination thereof.

[0108] The color filter layer CFL may be disposed on the passivation layer PSV. The color filter layer CFL may be disposed between the barrier rib patterns BNP. The color filter layer CFL may include color filters (a first color filter CF1, a second color filter CF2, and a third color filter CF3) corresponding to the colors of the respective pixels PXL. By disposing color filters (a first color filter CF1, a second color filter CF2, and a third color filter CF3) corresponding to the colors of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, respectively, a full-color image may be displayed.

[0109] The color filter layer CFL may include a first color filter CF1 that may be disposed in the first pixel PXL1 and selectively transmits light emitted from the first pixel PXL1, a second color filter CF2 that may be disposed in the second pixel PXL2 and selectively transmits light emitted from the second pixel PXL2, and a third color filter CF3 that may be disposed in the third pixel PXL3 and selectively transmits light emitted from the third pixel PXL3.

[0110] In one embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be a red color filter, a green color filter, and a blue color filter, respectively, but are not limited thereto. Hereinafter, the term "color filter CF" or "color filters CF" may represent any one of the first color filter CF1, the second color filter CF2, and the third color filter CF3, or may collectively represent two or more types of color filters.

[0111] The first color filter CF1 may overlap with the light-emitting element LD and the color conversion layer CCL of the first pixel PXL1 in the third direction (i.e., the Z-axis direction). The first color filter CF1 may include a color filter material that selectively transmits light of a first color (or red). For example, when the first pixel PXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0112] The second color filter CF2 may overlap with the light-emitting element LD and the color conversion layer CCL of the second pixel PXL2 in the third direction (i.e., the Z-axis direction). The second color filter CF2 may include a color filter material that selectively transmits light of a second color (or green). For example, when the second pixel PXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0113] The third color filter CF3 may overlap with the light-emitting element LD and the color conversion layer CCL of the third pixel PXL3 in the third direction (i.e., the Z-axis direction). The third color filter CF3 may include a color filter material that selectively transmits light of a third color (or blue). For example, when the third pixel PXL3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

[0114] According to the above embodiment, by simultaneously forming the light-emitting element LD and the barrier rib pattern BNP, the manufacturing process of the display device can be simplified. The porous region PA embedded in the light-emitting element LD can scatter the light emitted from the light-emitting region EA, thereby improving the light output efficiency. Therefore, since the scattering layer separately provided in the pixel PXL can be omitted, the manufacturing process can be simplified and the cost can be reduced. Since the porous region PA can be provided between the light-emitting region EA and the color conversion layer CCL, it can effectively prevent the color conversion layer CCL from being damaged due to the heat generated by the light-emitting region EA.

[0115] Hereinafter, additional embodiments will be described. In the following embodiments, the same components as those described above will be denoted by the same reference numerals, and redundant descriptions will be omitted or simplified.

[0116] FIG. 5 is a schematic cross-sectional view of a pixel according to another embodiment.

[0117] Referring to FIG. 5, the color conversion layer CCL according to one embodiment is different from the embodiments of FIGS. 1 to 4 in that this embodiment may include a first color conversion layer CC1 provided in the first pixel PXL1, a second color conversion layer CC2 provided in the second pixel PXL2, and a light transmission layer LS provided in the third pixel PXL3.

[0118] In one embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements LD that emit light of the same color. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements LD that emit light of a third color (or blue). The color conversion layer CCL including color conversion particles may be provided on the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 to display a full-color image.

[0119] When the first pixel PXL1 is a red pixel, the first color conversion layer CC1 may include first quantum dots that convert blue light emitted from a blue light-emitting element into red light. The first quantum dots may absorb blue light and shift the wavelength according to an energy transition to emit red light. When the first pixel PXL1 is a pixel of a different color, the first color conversion layer CC1 may include first quantum dots corresponding to the color of the first pixel PXL1.

[0120] When the second pixel PXL2 is a green pixel, the second color conversion layer CC2 may include second quantum dots that convert blue light emitted from a blue light-emitting element into green light. The second quantum dots may absorb blue light and change the wavelength according to an energy transition to emit green light. When the second pixel PXL2 is a pixel of a different color, the second color conversion layer CC2 may include second quantum dots corresponding to the color of the second pixel PXL2.

[0121] Blue light having a relatively short wavelength within the visible light range may be injected into the first quantum dots and the second quantum dots to increase the absorption coefficient of the first quantum dots and the second quantum dots. Therefore, the light-emitting efficiency of the first pixel PXL1 and the second pixel PXL2 can be increased, and ultimately excellent color reproducibility can be ensured. The light-emitting units EMU of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be composed of light-emitting elements LD of the same color (e.g., blue light-emitting elements), thereby improving the manufacturing efficiency of the display device.

[0122] The light transmission layer LS can be provided to effectively use the light of the third color (or blue) emitted from the light emitting element LD. For example, when the light emitting element LD is a blue light emitting element that emits blue light and the third pixel PXL3 is a blue pixel, the light transmission layer LS can include light scattering particles to effectively utilize the light emitted from the light emitting element LD, but is not limited thereto. According to an embodiment, the light transmission layer LS can be omitted or a transparent polymer can be provided to replace the light transmission layer LS.

[0123] FIG. 6 is a schematic cross-sectional view of a pixel according to another embodiment.

[0124] Referring to FIG. 6, the difference between the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 according to one embodiment and the embodiments of FIGS. 1 to 5 is that this embodiment can include a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3, and the color conversion layer CCL (refer to FIG. 3) and the barrier rib pattern BNP (refer to FIG. 3) can be omitted respectively.

[0125] Specifically, the light emitting element LD can include a first light emitting element LD1 provided in the first pixel PXL1, a second light emitting element LD2 provided in the second pixel PXL2, and a third light emitting element LD3 provided in the third pixel PXL3.

[0126] Each of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 can include a light emitting region EA and a porous region PA. The light emitting region EA can be provided between the substrate SUB and the porous region PA.

[0127] The light emitting region EA of each of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 can emit light of different colors. For example, the first light emitting element LD1 can include a light emitting region EA that emits light of the first color (or red), the second light emitting element LD2 can include a light emitting region EA that emits light of the second color (or green), and the third light emitting element LD3 can include a light emitting region EA that emits light of the third color (or blue). As described above, since each of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 includes a light emitting region EA that emits light of different colors, a full-color image can be displayed. Therefore, since the color conversion layer and / or the color filter layer provided in each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be omitted, the manufacturing process can be simplified and the cost can be reduced.

[0128] The light-emitting region EA may include a first semiconductor layer L1, a second semiconductor layer L3, and an active layer L2 interposed between the first semiconductor layer L1 and the second semiconductor layer L3. For example, the first semiconductor layer L1, the active layer L2, and the second semiconductor layer L3 of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be sequentially stacked on the substrate SUB in a third direction (i.e., the Z-axis direction).

[0129] The first semiconductor layer L1 of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may include at least one P-type semiconductor layer. For example, the first semiconductor layer L1 may include semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), gallium phosphide (GaP), their analogs, or combinations thereof, and may include a P-type semiconductor layer doped with a first conductive dopant (or P-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), their analogs, or combinations thereof. For example, the first semiconductor layer L1 may include a gallium nitride semiconductor material doped with a first conductive dopant (or P-type dopant), but is not limited thereto, and the first semiconductor layer L1 may be formed of various materials.

[0130] The active layer L2 of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be disposed between the first semiconductor layer L1 and the second semiconductor layer L3. The active layer L2 may include at least one of a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but is not limited thereto. The active layer L2 may include gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), gallium phosphide (GaP), or combinations thereof. Various materials may constitute the active layer L2.

[0131] When a signal (or voltage) is applied to each end of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, the light-emitting element LD emits light while electron-hole pairs recombine in the active layer L2 of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. By using this principle to control the light emission of each light-emitting element LD, the light-emitting element LD can be used as a light source for various light-emitting devices including the pixel PXL of a display device.

[0132] According to one embodiment, an electron blocking layer (EBL) may be further provided between the active layer L2 and the first semiconductor layer L1. The electron blocking layer may block the escape of the electron current supplied from the second semiconductor layer L3 to the first semiconductor layer L1, thereby increasing the recombination probability of electrons and holes in the active layer L2. The energy bandgap of the electron blocking layer may be greater than the energy bandgap of the active layer L2 and / or the first semiconductor layer L1, but is not limited thereto.

[0133] According to one embodiment, a superlattice layer (SLs) may be further provided between the active layer L2 and the second semiconductor layer L3. The superlattice layer may relieve the stress between the active layer L2 and the second semiconductor layer L3, thereby improving the quality of the light-emitting element LD. The superlattice layer may be formed in a structure in which indium gallium nitride and gallium nitride are alternately stacked, but is not limited thereto.

[0134] The second semiconductor layer L3 of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be provided on the active layer L2 and may include a semiconductor layer of a type different from that of the first semiconductor layer L1. In one embodiment, the second semiconductor layer L3 may include at least one N-type semiconductor layer. For example, the second semiconductor layer L3 may include semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), gallium phosphide (GaP), their analogs, or combinations thereof, and may be an N-type semiconductor layer doped with a second conductive dopant (or N-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), their analogs, or combinations thereof. For example, the second semiconductor layer L3 may include a gallium nitride semiconductor material doped with a second conductive dopant (or N-type dopant). However, the material constituting the second semiconductor layer L3 is not limited thereto, and furthermore, the second semiconductor layer L3 of the light-emitting element LD may be formed of various materials.

[0135] The porous region PA of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be provided on the second semiconductor layer L3 of the light-emitting region EA. For example, the porous region PA may be directly formed on the second semiconductor layer L3 of the light-emitting region EA. The porous region PA may include the same material as the second semiconductor layer L3, but is not limited thereto.

[0136] The porous region PA may include a porous layer LP and a plurality of holes P present in the porous layer LP. The porous region PA may be provided on the light-emitting region EA to scatter the light emitted from the light-emitting region EA, thereby improving the light output efficiency. For example, the refractive index of the porous region PA may be reduced due to the plurality of holes P, thereby improving the light extraction efficiency. For example, the porous region PA may be used as a scattering layer. As described above, in the case where the porous region PA is included in the light-emitting element LD, the scattering layer separately provided in the pixel PXL may be omitted, thereby simplifying the manufacturing process and reducing the cost. Since the porous region PA including the porous layer LP and the holes P has been described in detail with reference to FIG. 3 and other drawings, the repeated description will be omitted.

[0137] Each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be provided on a first electrode ET1 provided on a substrate SUB. For example, the first semiconductor layer L1 of the light-emitting element LD may be provided on the first electrode ET1 to be electrically connected to the first electrode ET1.

[0138] According to an embodiment, a connection electrode CE may be further provided between the substrate SUB and the light-emitting element LD. The connection electrode CE may be provided between the first semiconductor layer L1 of the light-emitting element LD and the first electrode ET1 provided on the substrate SUB. The light-emitting element LD may be electrically connected to the first electrode ET1 provided on the substrate SUB through the connection electrode CE. The connection electrode CE may include a metal or a metal oxide. For example, the connection electrode CE may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), its oxide, or its alloy, and the like, but is not limited thereto.

[0139] An insulating layer INS and a reflective layer RF may be provided between the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The insulating layer INS may be provided between the light-emitting element LD and the reflective layer RF.

[0140] The insulating layer INS can be disposed on the surface of the light-emitting element LD. The insulating layer INS can be disposed on the side surface of the light-emitting element LD. The insulating layer INS can prevent an electrical short circuit that may occur when the active layer L2 of the light-emitting element LD contacts a conductive material other than the first semiconductor layer L1 and the second semiconductor layer L3. The insulating layer INS can minimize surface defects of the light-emitting element LD, thereby improving the lifespan and luminous efficiency of the light-emitting element LD.

[0141] The insulating layer INS can cover the side surface of the light-emitting element LD, but can also be partially removed to expose the upper surface of the light-emitting element LD. For example, the insulating layer INS can cover the side surface of the light-emitting element LD, but can also be partially removed to expose the surface of the porous region PA of the light-emitting element LD.

[0142] The reflective layer RF can be disposed between the light-emitting elements LD. The reflective layer RF can be disposed at the boundary between the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 on the substrate SUB. The reflective layer RF can be disposed between the light-emitting elements LD to reflect light emitted from the light-emitting elements LD, thereby improving the light output efficiency of the display panel PNL. In addition, the reflective layer RF can be disposed at the boundary between the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 to prevent color mixing between adjacent pixels PXL.

[0143] The second electrode ET2 can be disposed on each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The second electrode ET2 can be directly disposed on the upper surface of the light-emitting element LD exposed by the insulating layer INS. For example, the second electrode ET2 can be directly disposed on the porous region PA of the light-emitting element LD, i.e., the porous layer LP. The second electrode ET2 can be disposed in each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0144] According to the above embodiments, since each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 includes a light-emitting region EA that emits light of different colors, the color conversion layer and / or the color filter layer can be omitted, thereby simplifying the manufacturing process and reducing costs. As described above, the porous region PA can be embedded in the light-emitting element LD to improve the light output efficiency of the display panel PNL and at the same time simplify the manufacturing process.

[0145] Next, a manufacturing method of the display device according to the above embodiments will be described.

[0146] FIGS. 7 to 16 are cross-sectional schematic views of steps of a method of manufacturing a display device according to an embodiment. FIGS. 7 to 16 are cross-sectional views illustrating the method of manufacturing the display device of FIG. 3, and components having substantially the same configuration as those in FIG. 3 will be denoted by the same reference numerals, and detailed reference numerals will be omitted in FIGS. 7 to 16.

[0147] Referring to FIG. 7, first, a base layer BSL may be prepared, and a semiconductor layer PL' may be formed on the base layer BSL. The base layer BSL may use a sapphire substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a combination thereof, but is not limited thereto, and a single crystal substrate having a lattice structure may be used. The base layer BSL may further include a buffer layer formed on its surface.

[0148] The semiconductor layer PL' may include at least one N-type semiconductor layer. For example, the semiconductor layer PL' may include semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof, and may be an N-type semiconductor layer doped with a second conductive dopant (or N-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), and the like. For example, the second semiconductor layer L3 may include a gallium nitride semiconductor material doped with a second conductive dopant (or N-type dopant). However, the material constituting the semiconductor layer PL' is not limited thereto, and in addition, the semiconductor layer PL' may be formed of various materials.

[0149] Referring to FIG. 8, a porous layer PL may be formed by etching the semiconductor layer PL'. For example, the semiconductor layer PL' may be electrochemically etched to form nano-level holes P of the porous layer PL. During the electrochemical etching of the semiconductor layer PL', the size, shape, and distribution of the holes P may be variously adjusted according to the etchant, voltage, and / or doping concentration.

[0150] Referring to FIG. 9, a light-emitting stack (first semiconductor layer 11, active layer 12, and second semiconductor layer 13) may be formed on the porous layer PL. The light-emitting stack (first semiconductor layer 11, active layer 12, and second semiconductor layer 13) may be formed by growing seeds through an epitaxial method. In this case, since the stress of the light-emitting stack (first semiconductor layer 11, active layer 12, and second semiconductor layer 13) can be reduced through the porous structure of the porous layer PL, the quality of the light-emitting element LD can be improved.

[0151] According to an embodiment, the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) can be formed by metal organic chemical vapor deposition (MOCVD). However, the present disclosure is not limited thereto, and the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) can be formed by various methods such as electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), and their similar methods, or a combination thereof.

[0152] The light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) can include the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 formed by epitaxial growth.

[0153] The second semiconductor layer 13 can be disposed on the porous layer PL and can be formed of the same material as the porous layer PL. For example, the second semiconductor layer 13 can include at least one N-type semiconductor layer. For example, the second semiconductor layer 13 can include a semiconductor material of at least one or a combination of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN), and can be an N-type semiconductor layer doped with a second conductive dopant (or N-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), and their analogs. For example, the second semiconductor layer 13 can include a gallium nitride semiconductor material doped with a second conductive dopant (or N-type dopant). However, the material constituting the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 can be formed of various materials. The second semiconductor layer 13 can be directly formed on the porous layer PL, but is not limited thereto.

[0154] The active layer 12 may be disposed on the second semiconductor layer 13 and may include a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but is not limited thereto. The active layer 12 may include gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof, and various other materials may constitute the active layer 12 of the barrier pattern.

[0155] The first semiconductor layer 11 may be disposed on the active layer 12 and may include at least one P-type semiconductor layer. For example, the first semiconductor layer 11 may include semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof, and may include a P-type semiconductor layer doped with a first conductive dopant (or P-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), a similar substance, or a combination thereof. For example, the first semiconductor layer 11 may include a gallium nitride semiconductor material doped with a first conductive dopant (or P-type dopant), but is not limited thereto, and the first semiconductor layer 11 may be formed of various materials.

[0156] Referring to FIG. 10, the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) and the porous layer PL may be sequentially bonded to the substrate SUB. The substrate SUB may be a driving substrate including circuit elements, and the circuit elements include transistors constituting the pixel circuit PXC (refer to FIG. 2) of each pixel PXL, and the first electrode ET1, the connection electrode layer CEL, and / or the hard mask layer HM may be disposed on the substrate SUB.

[0157] The first electrode ET1 may be formed at a position where the light-emitting element LD may be disposed, which will be described below. The connection electrode layer CEL may be formed on the entire surface of the substrate SUB, but is not limited thereto. The hard mask layer HM may be formed at a position where the barrier pattern BNP will be disposed to form the lower end of the barrier pattern BNP, which will be described below. However, the present disclosure is not limited thereto, and the hard mask layer HM may be omitted according to an embodiment.

[0158] The first semiconductor layer 11 of the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) may be bonded to the first electrode ET1 formed on the substrate SUB. The first semiconductor layer 11 may be easily bonded to the first electrode ET1 disposed on the substrate SUB through the connection electrode layer CEL. The connection electrode layer CEL may be formed of a metal or a metal oxide.

[0159] After the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) and the porous layer PL can be bonded to the substrate SUB, the base layer BSL can be separated from the surface of the porous layer PL.

[0160] Referring to FIG. 11, a first mask layer MK1 and a second mask layer MK2 can be formed on the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) and the porous layer PL. The first mask layer MK1 and the second mask layer MK2 can be directly formed on the porous layer PL, but are not limited thereto.

[0161] The first mask layer MK1 can be partially formed at positions where the light-emitting element LD and the barrier wall pattern BNP are provided, which will be described below. The second mask layer MK2 can be formed on the first mask layer MK1. The second mask layer MK2 can be selectively formed at positions where the barrier wall pattern BNP will be provided.

[0162] The first mask layer MK1 and the second mask layer MK2 can be formed of different materials. For example, the first mask layer MK1 can include silicon oxide (SiOx), and the second mask layer MK2 can include nickel (Ni), but is not limited thereto.

[0163] Referring to FIG. 12, the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) and the porous layer PL can be patterned to form the light-emitting element LD and the barrier wall pattern BNP. The barrier wall pattern BNP can be formed at the boundary between the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The light-emitting element LD can be formed in each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 between the barrier wall patterns BNP.

[0164] In the process of patterning the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) and the porous layer PL, the first semiconductor layer 11 can be separated into the first semiconductor layer L1 of the light-emitting element LD and the first semiconductor layer B1 of the barrier pattern BNP, the active layer 12 can be separated into the active layer L2 of the light-emitting element LD and the active layer B2 of the barrier pattern BNP, and the second semiconductor layer 13 can be separated into the second semiconductor layer L3 of the light-emitting element LD and the second semiconductor layer B3 of the barrier pattern BNP. Similarly, the porous layer PL can be divided into the porous layer LP of the light-emitting element LD and the porous layer BP of the barrier pattern BNP. The porous layer LP of the light-emitting element LD can constitute the porous region PA of the light-emitting element LD. The first semiconductor layer L1, the active layer L2, and the second semiconductor layer L3 of the light-emitting element LD can constitute the light-emitting region EA of the light-emitting element LD.

[0165] In the process of patterning the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) and the porous layer PL, by using the difference in etching selectivity between the first mask layer MK1 and the second mask layer MK2, the light-emitting element LD and the barrier pattern BNP with different thicknesses can be formed simultaneously.

[0166] According to an embodiment, in the process of patterning the light-emitting stack (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) and the porous layer PL, the connection electrode layer CEL can be separated into the first connection electrode CE1 and the second connection electrode CE2. For example, the connection electrode layer CEL can be separated into the first connection electrode CE1 under the light-emitting element LD and the second connection electrode CE2 under the hard mask layer HM.

[0167] Referring to FIG. 13, the insulating layer INS can be formed on the light-emitting element LD and / or the barrier pattern BNP. The insulating layer INS can be partially formed on the side surfaces of the light-emitting element LD and / or the barrier pattern BNP. After the insulating layer INS can be formed above the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, the insulating layer INS can be partially removed to expose the upper surfaces of the light-emitting element LD and / or the barrier pattern BNP. In one embodiment, when the light-emitting element LD and / or the barrier pattern BNP are formed in the third direction (i.e., the Z-axis direction), that is, perpendicular to the substrate SUB, the insulating layer INS provided on the upper surfaces of the light-emitting element LD and / or the barrier pattern BNP can be etched without using a mask.

[0168] Referring to FIG. 14, the second electrode ET2 can be formed on the light-emitting element LD. The second electrode ET2 can be directly formed on the upper surface of the light-emitting element LD exposed by the insulating layer INS and can be in contact with the porous layer LP of the light-emitting element LD.

[0169] The second electrode ET2 can be formed on the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. For example, the second electrode ET2 can be formed to at least partially cover the barrier rib pattern BNP, but is not limited thereto.

[0170] The second electrode ET2 can be formed of various transparent conductive materials. For example, the second electrode ET2 can be formed of at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), or gallium tin oxide (GTO), and can be implemented as substantially transparent or semi-transparent to meet the light transmittance. Therefore, the light emitted from the light-emitting element LD can pass through the second electrode ET2 and be emitted to the outside of the display panel PNL.

[0171] Referring to FIG. 15, a reflective layer RF can be sequentially formed on the barrier rib pattern BNP. The reflective layer RF can be partially formed on the side surface of the barrier rib pattern BNP. The reflective layer RF can reflect the light emitted from the light-emitting element LD to improve the light output efficiency of the display panel PNL. The reflective layer RF can be disposed on the side surface of the barrier rib pattern BNP to prevent color mixing between adjacent pixels PXL. The material of the reflective layer RF is not particularly limited, and it can be formed of various reflective materials.

[0172] Referring to FIG. 16, a color conversion layer CCL can be sequentially formed on the light-emitting element LD. The color conversion layer CCL can be formed between the barrier rib patterns BNP. For example, the color conversion layer CCL can be formed in a space or opening defined by the barrier rib patterns BNP. The color conversion layer CCL can include quantum dots as a color conversion material, which convert the light emitted from the light-emitting elements LD of the respective pixels PXL into light of a specific color. Since the color conversion layer CCL has been described in detail with reference to FIGS. 3 and the like, repeated description will be omitted.

[0173] Next, the display device of FIG. 3 can be completed by forming a passivation layer PSV and a color filter layer CFL on the color conversion layer CCL. The passivation layer PSV can be formed on the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The passivation layer PSV can directly cover the color conversion layer CCL. The passivation layer PSV can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color conversion layer CCL.

[0174] The color filter layer CFL can include color filters (the first color filter CF1, the second color filter CF2, and the third color filter CF3) corresponding to the colors of the respective pixels PXL. Since the color filter layer CFL has been described in detail with reference to FIGS. 3 and other figures, repeated descriptions will be omitted.

[0175] According to the above embodiment, the manufacturing process of the display device can be simplified by simultaneously forming the light-emitting element LD and the barrier rib pattern BNP. As described above, the porous region PA can be embedded in the light-emitting element LD to improve the light output efficiency of the display panel PNL and simultaneously simplify the manufacturing process.

[0176] Hereinafter, another embodiment will be described. In the following embodiment, components that are the same as those in the above will be denoted by the same reference numerals, and redundant descriptions will be omitted or simplified.

[0177] FIGS. 17 to 26 are cross-sectional schematic views of steps of a method for manufacturing a display device according to another embodiment. FIGS. 17 to 26 are cross-sectional views for explaining the method for manufacturing the display device of FIG. 6, and components that are substantially the same as those in FIG. 6 will be denoted by the same reference numerals, and detailed reference numerals will be omitted in FIGS. 17 to 26.

[0178] Referring to FIG. 17, first, a base layer BSL can be prepared, and a semiconductor layer PL' can be formed on the base layer BSL. Since the base layer BSL and the semiconductor layer PL' have been described in detail with reference to FIG. 7, repeated descriptions will be omitted.

[0179] Referring to FIG. 18, the semiconductor layer PL' can be patterned continuously to form the semiconductor layer PL' in each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. Each of the semiconductor layers PL' of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be formed at a position where a light-emitting element LD can be provided, which will be described below.

[0180] Referring to FIG. 19, a porous layer LP can be formed by subsequently etching at least partially the semiconductor layer PL' of each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. For example, the semiconductor layer PL' can be electrochemically etched to form nano-level holes P of the porous layer LP. During the electrochemical etching of the semiconductor layer PL', the size, shape, and distribution of the holes P can be variously adjusted according to the etchant, voltage, and / or doping concentration. The porous layer LP of each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can constitute a porous region PA of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, which will be described below. The unetched region of the semiconductor layer PL' can be the second semiconductor layer L3, and can together with the first semiconductor layer L1 and the active layer L2 formed in subsequent processes constitute the light-emitting region EA of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0181] Referring to FIG. 20, the first semiconductor layer L1 and the active layer L2 can be formed on the porous layer LP and the second semiconductor layer L3 of each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The first semiconductor layer L1 and / or the active layer L2 of each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be formed by growing a seed through an epitaxial growth method.

[0182] The first semiconductor layer L1, the active layer L2, and the second semiconductor layer L3 disposed on the porous layer LP of each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be a light-emitting stack, and can constitute the light-emitting region EA of each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. As described above, the light-emitting region EA of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be formed to emit light of different colors. For example, the light-emitting region EA of the first light-emitting element LD1 can emit light of the first color (or red), the light-emitting region EA of the second light-emitting element LD2 can emit light of the second color (or green), and the light-emitting region EA of the third light-emitting element LD3 can emit light of the third color (or blue). As described above, since each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 includes a light-emitting region EA that emits light of different colors, a full-color image can be displayed. Therefore, since the color conversion layer and / or the color filter layer respectively provided in each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be omitted, the manufacturing process can be simplified and the cost can be reduced as described above.

[0183] Referring to FIG. 21, a planarization layer PN can be sequentially formed between the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The planarization layer PN can be formed at the boundary between the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The planarization layer PN can be formed between the light-emitting elements LD and is used to planarize the step difference between the light-emitting elements LD. The planarization layer PN can be formed on the side surfaces of the light-emitting elements LD. For example, the planarization layer PN can cover the side surfaces of the light-emitting elements LD but expose the upper surfaces of the light-emitting elements LD.

[0184] In one embodiment, the planarization layer PN can be formed of an organic material such as acrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, polyesters resin, polyphenylenesulfides resin, benzocyclobutene (BCB), or a combination thereof, but is not limited thereto.

[0185] According to one embodiment, the planarization layer PN can be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium oxide (TiOx), or a combination thereof

[0186] Referring to FIG. 22, a connection electrode CE can be sequentially formed on the first light-emitting element LD1, the second light-emitting element LD2, the third light-emitting element LD3, and the planarization layer PN. The connection electrode CE can be formed on the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The connection electrode CE can be formed of a metal or a metal oxide. For example, the connection electrode CE can be formed of copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), its oxide, or an alloy thereof, and the like, but is not limited thereto.

[0187] Referring to FIG. 23, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be bonded to the substrate SUB. The substrate SUB can be a driving substrate including circuit elements, the circuit elements including transistors constituting the pixel circuit PXC (refer to FIG. 2) of each pixel PXL, and the first electrode ET1 can be provided therein.

[0188] The first semiconductor layer L1 of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be bonded to the first electrode ET1 formed on the substrate SUB. The first semiconductor layer L1 can be easily joined to the first electrode ET1 provided on the substrate SUB through the connection electrode CE. After bonding the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 to the substrate SUB, the base layer BSL can be separated from the surface of the porous layer LP.

[0189] Referring to FIG. 24, a second electrode layer ET2' can be successively formed on the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The second electrode layer ET2' can be directly formed on the upper surface of the light-emitting element LD exposed by the planarization layer PN to contact the porous region PA of the light-emitting element LD, that is, the porous layer LP. The second electrode layer ET2' can be formed on the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0190] The second electrode layer ET2' can be formed of various transparent conductive materials. For example, the second electrode layer ET2' can be formed of at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), or a combination thereof, and can be substantially transparent or translucent to meet the light transmittance.

[0191] Referring to FIG. 25, then the second electrode layer ET2' can be successively patterned to form a second electrode ET2 on each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, and the planarization layer PN can be removed.

[0192] Referring to FIG. 26, an insulating layer INS may be formed on the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The insulating layer INS may be partially formed on the side surfaces of the light-emitting element LD and / or the barrier pattern BNP. After the insulating layer INS is formed on the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, a part of it may be removed, so that the upper surface of the light-emitting element LD may be exposed. In one embodiment, when the light-emitting element LD is formed in the third direction (i.e., the Z-axis direction), that is, perpendicular to the substrate SUB, a separate mask may not be used to etch the insulating layer INS provided on the upper surface of the light-emitting element LD.

[0193] Next, a reflective layer RF may be formed between the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 to complete the display device of FIG. 6. The reflective layer RF may reflect the light emitted from the light-emitting element LD to improve the light output efficiency of the display panel PNL. In addition, the reflective layer RF may be disposed at the boundary between the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 to prevent color mixing between adjacent pixels PXL. The material of the reflective layer RF is not particularly limited, and it may be formed of various reflective materials.

[0194] According to the above embodiments, since each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may include a light-emitting region EA that emits light of different colors, the color conversion layer and / or the color filter layer may be omitted, and thus the manufacturing process may be simplified and the cost may be reduced. As described above, the porous region PA may be embedded in the light-emitting element LD to improve the light output efficiency of the display panel PNL and at the same time simplify the manufacturing process.

[0195] Hereinafter, an electronic device of a display device to which the above embodiments may be applied will be described.

[0196] FIGS. 27 to 30 are schematic diagrams of electronic devices according to various embodiments.

[0197] Referring to FIG. 27, the display device according to the above embodiments may be applied to smart glasses. The smart glasses may include a frame 111 and a lens unit 112. The smart glasses are wearable electronic devices that can be worn on the user's face, and a part of the frame 111 may have a structure that can be folded or unfolded. For example, the smart glasses may be wearable devices for augmented reality (AR).

[0198] The frame 111 may include a lens frame 111b that supports the lens unit 112 and temple units 111a for the user to wear. The temple units 111a are connected to the lens frame 111b through a hinge structure and can be folded or unfolded.

[0199] A battery, a touch panel, a microphone, and / or a camera may be embedded in the frame 111. A projector for outputting light and / or a processor for controlling optical signals may be embedded in the frame 111.

[0200] The lens unit 112 may be an optical element that transmits or reflects light. The lens unit 112 may include glass and / or a transparent synthetic resin.

[0201] The display device according to the above embodiment may be applied to the lens unit 112. For example, the user may recognize an image displayed by an optical signal transmitted by the projector of the frame 111 through the lens unit 112. For example, the user may recognize information such as time and date displayed on the lens unit 112.

[0202] Referring to FIG. 28, the display device according to the above embodiment may be applied to a head-mounted display (HMD). The head-mounted display may include a head-mounted strap 121 and a display storage box 122. For example, the head-mounted display may be a wearable electronic device that can be worn on the user's head.

[0203] The head-mounted strap 121 may be connected to the display storage box 122 to fix the display storage box 122. The head-mounted strap 121 may include a horizontal strap and a vertical strap for fixing the head-mounted display to the user's head. As shown in FIG. 28, the horizontal strap may be arranged to surround the side of the user's head, and the vertical strap may be arranged to surround the upper part of the user's head. However, the present disclosure is not limited thereto, and the head-mounted strap 121 may be implemented in the form of a lens frame or a helmet.

[0204] The display storage box 122 may accommodate the display device and may include at least one lens. The at least one lens may provide an image to the user. For example, the display device according to the above embodiment may be applied to the left and right lenses installed in the display storage box 122.

[0205] Referring to FIG. 29, the display device according to the above embodiment can be applied to a smart watch. The smart watch can include a display unit 131 and a wristband unit 132. The smart watch can be a wearable electronic device, and its wristband unit 132 can be installed on the user's wrist. The display device according to the above embodiment can be applied to the display unit 131. For example, the display unit 131 can provide video data including information such as time and date.

[0206] Referring to FIG. 30, the display device according to the above embodiment can be applied to an in-vehicle display. For example, the in-vehicle display can represent an electronic device provided inside and outside the vehicle to provide video data.

[0207] For example, the display device according to the above embodiment can be applied to at least one of an infotainment panel 141, an instrument panel 142, a co-pilot display 143, a head-up display 144, a side mirror display 145, and a rear seat display 146.

[0208] Those of ordinary skill in the art to which this disclosure pertains will understand that this disclosure can be implemented in a modified form without departing from the basic features described. Therefore, the disclosed embodiments should be taken in an illustrative rather than a restrictive sense. The scope of this disclosure is defined by the claims for patent rather than the foregoing description, and all differences within the equivalent scope should be understood to be included within the scope of this disclosure.

Brief Description of the Drawings

[0030] FIG. 1 is a plan schematic view of a display device according to an embodiment. FIG. 2 is a circuit schematic view of a pixel according to an embodiment. FIGS. 3 and 4 are cross-sectional schematic views of a pixel according to an embodiment. FIG. 5 is a cross-sectional schematic view of a pixel according to another embodiment. FIG. 6 is a cross-sectional schematic view of a pixel according to another embodiment. FIGS. 7 to 16 are cross-sectional schematic views of steps of a manufacturing method of a display device according to an embodiment. FIGS. 17 to 26 are cross-sectional schematic views of steps of a manufacturing method of a display device according to another embodiment. FIGS. 27 to 30 are schematic views of electronic devices according to various embodiments.

Claims

1. A display device comprising: a plurality of light-emitting elements disposed on a substrate, wherein each of the plurality of light-emitting elements comprises: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a porous layer disposed on the second semiconductor layer.

2. The display device as claimed in claim 1, wherein the porous layer comprises nanoscale pores.

3. The display device as claimed in claim 1, wherein the porous layer and the second semiconductor layer comprise the same material.

4. The display device as claimed in claim 1, further comprising: a plurality of barrier patterns disposed on the substrate, wherein each of the plurality of light-emitting elements is disposed between the plurality of barrier patterns.

5. The display device as claimed in claim 4, wherein the plurality of barrier patterns and the plurality of light-emitting elements comprise the same material.

6. The display device as claimed in claim 1, further comprising: a color conversion layer disposed on the plurality of light-emitting elements.

7. The display device as claimed in claim 1, further comprising: a reflective layer disposed between the plurality of light-emitting elements.

8. The display device as claimed in claim 7, further comprising: an insulating layer disposed between the plurality of light-emitting elements and the reflective layer.

9. The display device as claimed in claim 1, wherein the plurality of light-emitting elements comprises: a first light-emitting element that emits light of a first color; a second light-emitting element that emits light of a second color; and a third light-emitting element that emits light of a third color.

10. A method for manufacturing a display device, comprising: forming a semiconductor layer; etching the semiconductor layer to form a porous layer; and disposing a light-emitting stack on the porous layer to form a plurality of light-emitting elements.

11. A method of manufacturing a display device as claimed in claim 10, wherein forming the porous layer comprises forming a plurality of nanoscale pores by etching the semiconductor layer.

12. A method of manufacturing a display device as claimed in claim 10, wherein setting the light-emitting stack includes etching the porous layer and the light-emitting stack.

13. A method of manufacturing a display device as claimed in claim 12, wherein the light-emitting stack comprises: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; and an active layer formed between the first semiconductor layer and the second semiconductor layer.

14. A method of manufacturing a display device as claimed in claim 13, wherein the second semiconductor layer and the porous layer are formed of the same material.

15. The method of manufacturing a display device as claimed in claim 12, further comprising: etching the porous layer and the light-emitting stack to form a plurality of barrier patterns.

16. A method of manufacturing a display device as claimed in claim 15, wherein the plurality of barrier patterns and the plurality of light-emitting elements are formed simultaneously.

17. A method of manufacturing a display device as claimed in claim 10, wherein forming the semiconductor layer includes forming a second semiconductor layer between the porous layer and the light-emitting stack.

18. A method of manufacturing a display device as claimed in claim 17, wherein setting the light-emitting stack comprises: setting an active layer on the second semiconductor layer; and setting a first semiconductor layer on the active layer.

19. A method of manufacturing a display device as claimed in claim 10, further comprising: forming a planarization layer between the plurality of light-emitting elements.

20. A method of manufacturing a display device as claimed in claim 10, further comprising: forming a reflective layer between the plurality of light-emitting elements.