Modular wafer table and methods of manufacturing thereof

TWI939486BActive Publication Date: 2026-09-21ASML HLDG NV +1
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Patent Information

Application Number
TW111117582
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Priority Date
2021-05-19
Filing Date
2022-05-11
Publication Date
2026-09-21
Estimated Expiration
2042-05-10

AI Technical Summary

Technical Problem

Current manufacturing processes for wafer tables in lithography systems result in high cycle times and costs, with discarded tables and limitations in applying high-temperature coatings due to material instability at elevated temperatures.

Method used

A method involving the refurbishment of obsolete wafer tables by removing nodules, forming a core module, and integrating knob modules with separate fabrication processes, allowing for high-temperature coatings and improved mechanical properties through bonding techniques like optical contact and solder bonding.

Benefits of technology

Reduces manufacturing costs and cycle times by enabling the application of high-temperature coatings and using diverse materials for nodules, enhancing stability and control over mechanical properties.

✦ Generated by Eureka AI based on patent content.

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Abstract

This invention relates to a modular wafer stage and a method for refurbishing a waste wafer to manufacture the modular wafer stage. For example, one method may include removing one or more nodules from a surface of a wafer stage. The method may also include grinding the surface of the wafer stage after removing the one or more nodules to form a core module. The method may also include forming a nodule module having a plurality of nodules thereon. The method may also include bonding the core module to the nodule module.
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Description

[Technical Field]

[0001] This invention relates to lithography systems, such as modular wafer stages and methods for refurbishing waste wafers to manufacture modular wafer stages. [Previous Technology]

[0002] Lithography equipment is a machine that coats a desired pattern onto a substrate, typically onto a target portion of the substrate. Lithography equipment can be used, for example, in the manufacture of integrated circuits (ICs). In that case, a patterning device (which is alternatively called a mask or magnifying mask) can be used to generate a circuit pattern to be formed on individual layers of the IC. This pattern can be transferred to a target portion (e.g., a portion containing a die, a die, or several dies) on a substrate (e.g., a silicon wafer). The transfer of the pattern is typically performed by imaging onto a radiation-sensitive material (resist) layer provided on the substrate. Generally, a single substrate will contain a group of adjacent target portions that are continuously patterned. Known lithography equipment includes: a so-called stepper, in which each target portion is irradiated by exposing the entire pattern onto the target portion at once; and a so-called scanner, in which each target portion is irradiated by scanning the pattern in a given direction ("scanning" direction) simultaneously with or against this scanning direction using a radiation beam. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.

[0003] Another lithography system is an interferometric lithography system, in which there is no patterning device, but the beam is split into two beams, and the two beams interfere at the target portion of the substrate by using a reflection system. This interference forms a line at the target portion of the substrate.

[0004] During lithography operations, different processing steps typically require different layers to be formed sequentially on a substrate. For each pattern transfer procedure, the layer sequence is usually achieved by changing different magnification masks according to the desired pattern for each layer. Typical lithography systems operate within sub-nanometer tolerances regarding the pattern on the magnification mask and the pattern transferred from the magnification mask to the wafer. [Summary of the Invention]

[0005] The abandoned wafer stage needs to be refurbished.

[0006] In some embodiments, a method includes the following operations: removing one or more nodules from one surface of a wafer anode; grinding the surface of the wafer anode after removing the one or more nodules to form a core module; forming one nodule module having a plurality of nodules thereon; and bonding the core module to the nodule module.

[0007] In some embodiments, a wafer abutment includes the following components: a core module configured to be formed by removing one or more nodules from a surface of the wafer abutment and grinding the surface of the wafer abutment after removing the one or more nodules; a nodule module having a plurality of nodules formed thereon; and a plurality of bonding contacts configured to bond the core module to the nodule module.

[0008] In some embodiments, a method includes the following operations for forming a core module: Removing one or more nodules from a surface of a wafer abutment by mechanically grinding the one or more nodules. Grinding the surface of the wafer abutment after removing the one or more nodules using a chemical mechanical polishing (CMP) process. Forming a nodule module having a plurality of nodules. Joining the core module to the nodule module using techniques such as optical contact / bonding, solder bonding, adhesive bonding, eutectic bonding, anodic bonding, metal-to-metal diffusion bonding, and the like.

[0009] Further features of the invention and the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. It should be noted that the invention is not limited to the specific embodiments described herein. These embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art based on the teachings contained herein.

Implementation Method

[0011] This specification discloses one or more embodiments that contain the features of the present invention. The disclosed embodiments are provided as examples. The scope of the present invention is not limited to the disclosed embodiments. The claimed features are defined by the appended claims.

[0012] The described embodiments and references to "an embodiment," "an example embodiment," etc., in this specification may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, it should be understood that, whether explicitly described or not, implementing this feature, structure, or characteristic in conjunction with other embodiments is within the understanding of those skilled in the art.

[0013] For ease of description, spatial relative terms such as "below," "under," "lower," "above," "on," "upper," and similar terms may be used herein to describe the relationship between one element or feature and another element or feature illustrated in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0014] As used herein, the term "about" indicates a given quantity of value that may vary based on a particular technique. Based on a particular technique, the term "about" may indicate a given quantity of value that varies, for example, within 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0015] Embodiments of the present invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the present invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. The machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, the machine-readable medium may include read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.); and others. Furthermore, firmware, software, conventions, and / or instructions may be described herein as performing specific actions. However, it should be understood that such descriptions are merely for convenience, and such actions are in fact caused by a computing device, processor, controller, or other means of executing firmware, software, conventions, instructions, etc. The term "non-transitory" may be used herein to characterize computer-readable media used for storing data, information, instructions and the like, with the sole exception of transient transmission signals.

[0016] However, before describing these embodiments in more detail, it is presented as an example environment in which embodiments of the invention may be implemented.

[0017] Example Microfilm System

[0018] Figures 1A and 1B respectively show schematic illustrations of lithography apparatus 100 and lithography apparatus 100', in which embodiments of the present invention can be implemented. Lithography apparatus 100 and lithography apparatus 100' each include: an illumination system (illuminator) IL configured to adjust the radiation beam B (e.g., deep ultraviolet or extreme ultraviolet radiation); a support structure (e.g., a mask stage) MT configured to support a patterning device (e.g., a mask, a magnifying mask, or a dynamic patterning device) MA and connected to a first positioner PM configured to accurately position the patterning device MA; and a substrate stage (e.g., a wafer stage) WT configured to hold a substrate (e.g., a resist-coated wafer) W and connected to a second positioner PW configured to accurately position the substrate W. Lithography apparatuses 100 and 100' also include a projection system PS configured to project a pattern imparted by a patterning device MA to a radiating beam B onto a target portion (e.g., comprising one or more grains) C of a substrate W. In lithography apparatus 100, the patterning device MA and the projection system PS are reflective. In lithography apparatus 100', the patterning device MA and the projection system PS are transmissive.

[0019] The lighting system IL may include various types of optical components for guiding, shaping or controlling the radiated beam B, such as refractive, reflective, reflective-refractive, magnetic, electromagnetic, electrostatic or other types of optical components or any combination thereof.

[0020] The support structure MT holds the patterning device MA in a manner dependent on the orientation of the patterning device MA relative to the reference frame, the design of at least one of the lithography devices 100 and 100', and other conditions (such as whether the patterning device MA is held in a vacuum environment). The support structure MT may use mechanical, vacuum, electrostatic, or other clamping techniques to hold the patterning device MA. The support structure MT may be, for example, a frame or a stage, which may be fixed or movable as needed. By using sensors, the support structure MT can ensure that the patterning device MA is, for example, in the desired position relative to the projection system PS.

[0021] The term "patterning device" MA should be broadly interpreted to refer to any device that can be used to impart a pattern to a radiation beam B in its cross-section in order to generate a pattern in a target portion C of the substrate W. The pattern imparted to the radiation beam B may correspond to a specific functional layer in the device generated in the target portion C to form an integrated circuit.

[0022] The patterning device MA can be transmissive (as in the lithography apparatus 100' of FIG. 1B) or reflective (as in the lithography apparatus 100 of FIG. 1A). Examples of the patterning device MA include a magnifying mask, a mask, a programmable mirror array, or a programmable LCD panel. Masks are well known in lithography and include mask types such as binary, alternating phase-shift, or attenuating phase-shift, as well as various hybrid mask types. One example of a programmable mirror array employs a matrix configuration of small mirrors, each of which can be individually tilted so that the incident radiation beam is reflected in different directions. The tilted mirrors impart a pattern to the radiation beam B reflected by the matrix of small mirrors.

[0023] The term "projection system" PS can encompass any type of projection system suitable for the exposure radiation used or for other factors such as the use of a wetting liquid on a substrate W or the use of a vacuum, including refractive, reflective, reflective-refractive, magnetic, electromagnetic, and electrostatic optical systems or any combination thereof. A vacuum environment can be used for EUV or electron beam radiation because other gases can absorb excessive radiation or electrons. Therefore, a vacuum environment can be provided throughout the beam path by means of vacuum walls and vacuum pumps.

[0024] The lithography apparatus 100 and / or the lithography apparatus 100' may be a type having two (dual-stage) or more substrate stages WT (and / or two or more mask stages). In such "multi-stage" machines, additional substrate stages WT can be used in parallel, or preparatory steps can be performed on one or more stages while one or more other substrate stages WT are used for exposure. In some cases, the additional stage may not be a substrate stage WT.

[0025] Lithography apparatuses may also fall into the category of those in which at least a portion of the substrate may be covered by a liquid (e.g., water) having a relatively high refractive index to fill the space between the projection system and the substrate. A wetting liquid may also be applied to other spaces within the lithography apparatus, such as the space between the mask and the projection system. Immersion techniques are well known in this art for increasing the numerical aperture of a projection system. As used herein, the term "immersion" does not mean that a structure such as the substrate must be submerged in the liquid, but only that the liquid is located between the projection system and the substrate during exposure.

[0026] Referring to Figures 1A and 1B, the illuminator IL receives a radiated beam from the radiation source SO. For example, when the source SO is an excimer laser, the source SO and the lithography devices 100, 100' can be separate physical entities. In such cases, the source SO is not considered part of the lithography devices 100 or 100', and the radiated beam B is delivered from the source SO to the illuminator IL by means of a beam delivery system BD (in Figure 1B) including, for example, suitable guide mirrors and / or beam expanders. In other cases, for example, when the source SO is a mercury lamp, the source SO can be an integral part of the lithography devices 100, 100'. The source SO and the illuminator IL, together with the beam delivery system BD (if required), can be referred to as a radiation system.

[0027] The illuminator IL may include an adjuster AD (in Figure 1B) for adjusting the angular intensity distribution of the radiated beam. Generally, it can adjust at least the outer radial range and / or inner radial range (typically referred to as "σ outer" and "σ inner," respectively) of the intensity distribution in the pupil plane of the illuminator. Additionally, the illuminator IL may include various other components (in Figure 1B), such as a beam concentrator IN and a condenser CO. The illuminator IL can be used to adjust the radiated beam B to have a desired uniformity and intensity distribution in its cross-section.

[0028] Referring to FIG. 1A, a radiation beam B is incident on a patterning device (e.g., a mask) MA held on a support structure (e.g., a mask stage) MT and patterned by the patterning device MA. In the lithography apparatus 100, the radiation beam B is reflected from the patterning device (e.g., the mask) MA. After being reflected from the patterning device (e.g., the mask) MA, the radiation beam B passes through a projection system PS, which focuses the radiation beam B onto a target portion C of a substrate W. The substrate stage WT can be accurately moved (e.g., to position different target portions C in the path of the radiation beam B) by means of a second positioner PW and a position sensor IF2 (e.g., an interferometric measuring device, a linear encoder, or a capacitive sensor). Similarly, a first positioner PM and another position sensor IF1 can be used to accurately position the patterning device (e.g., the mask) MA relative to the path of the radiation beam B. The patterning device (e.g., mask) MA and the substrate W can be aligned using mask alignment marks M1, M2 and substrate alignment marks P1, P2.

[0029] Referring to FIG. 1B, the radiating beam B is incident on a patterning device (e.g., a mask MA) held on a support structure (e.g., a mask stage MT) and patterned by the patterning device. Having traversed the mask MA, the radiating beam B passes through a projection system PS, which focuses the beam onto a target portion C of the substrate W. The projection system has a pupil conjugate PPU leading to the illumination system pupil IPU. The radiated portion diverges from the intensity distribution at the illumination system pupil IPU and traverses the mask pattern without being affected by diffraction at the mask pattern, thus producing an image of the intensity distribution at the illumination system pupil IPU.

[0030] The projection system PS projects an image MP' of a mask pattern MP onto a photoresist layer coated on a substrate W, wherein the image MP' is formed by diffracted beams generated from radiation from an intensity distribution in the marked pattern MP. For example, the mask pattern MP may include a linear and spatial array. Diffraction of radiation at the array, which is different from zero-order diffraction, generates a diffracted beam that changes direction in a direction perpendicular to the line. A non-diffracted beam (i.e., a so-called zero-order diffracted beam) traverses the pattern without any change in its propagation direction. The zero-order diffracted beam traverses an upper lens or upper lens group upstream of the pupil conjugate PPU of the projection system PS to reach the pupil conjugate PPU. The portion of the intensity distribution in the plane of the pupil conjugate PPU associated with the zero-order diffracted beam is an image of the intensity distribution in the illumination system pupil IPU of the illumination system IL. For example, the aperture device PD is placed on the plane of the pupil conjugate PPU, which includes the projection system PS, or is substantially placed on that plane.

[0031] The projection system PS is configured to capture not only the zeroth-order diffracted beam, but also the first-order or first-order and higher-order diffracted beams (not shown) by means of a lens or lens group L. In some embodiments, dipole illumination for imaging a line pattern extending in a direction perpendicular to the line can be used to utilize the resolution enhancement effect of dipole illumination. For example, the first-order diffracted beam interferes with the corresponding zero-order diffracted beam at the wafer W level, thereby producing an image of the line pattern MP with the highest possible resolution and program window (i.e., an available depth of focus with a permissible combination of exposure dose deviations). In some embodiments, astigmatic aberration can be reduced by providing a radiating pole (not shown) in the opposite quadrant of the illumination system pupil IPU. Furthermore, in some embodiments, astigmatic aberration can be reduced by blocking the zero-order beam in the projection system pupil conjugate PPU associated with the radiating pole in the opposite quadrant. This situation is described in more detail in US 7,511,799 B2, published on March 31, 2009, which is incorporated herein by reference in its entirety.

[0032] The substrate stage WT can be accurately moved (e.g., to position different target portions C in the path of the radiation beam B) by means of a second positioner PW and a position sensor IF (e.g., an interferometric measuring device, a linear encoder, or a capacitive sensor). Similarly, a first positioner PM and another position sensor (not shown in FIG. 1B) can be used to accurately position the mask MA relative to the path of the radiation beam B (e.g., after being mechanically retrieved from a mask library or during scanning).

[0033] Generally speaking, the movement of the mask stage MT can be achieved by means of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning) forming the components of the first positioner PM. Similarly, the movement of the substrate stage WT can be achieved by means of a long-stroke module and a short-stroke module forming the components of the second positioner PW. In the case of a stepper (relative to a scanner), the mask stage MT may be connected only to the short-stroke actuator, or it may be fixed. Mask alignment marks M1, M2 and substrate alignment marks P1, P2 can be used to align the mask MA and the substrate W. Although the substrate alignment marks (as shown) occupy a dedicated target portion, they may be located in the space between the target portions (called kerf alignment marks). Similarly, when more than one die is disposed on the mask MA, the mask alignment marks may be located between these dies.

[0034] The masking stage MT and the patterning device MA can be located within a vacuum chamber V, where an in-vacuum robot (robotic arm) IVR can be used to move the patterning device, such as the mask, into and out of the vacuum chamber. Alternatively, when the masking stage MT and the patterning device MA are outside the vacuum chamber, similar to the in-vacuum robot IVR, an out-of-vacuum robot can be used for various transport operations. Both the in-vacuum robot and the out-of-vacuum robot need to be calibrated for a fixed kinematic mount to smoothly transfer any payload (e.g., a mask) to the transfer station.

[0035] The lithography devices 100 and 100' can be used in at least one of the following modes:

[0036] 1. In step mode, when the entire pattern applied to the radiation beam B is projected onto the target portion C in one step, the support structure (e.g., mask stage) MT and the substrate stage WT remain substantially stationary (i.e., single static exposure). The substrate stage WT is then shifted in the X and / or Y directions so that different target portions C can be exposed.

[0037] 2. In scanning mode, while the pattern to be applied to the radiation beam B is projected onto the target portion C, the support structure (e.g., mask stage) MT and the substrate stage WT are scanned simultaneously (i.e., single dynamic exposure). The speed and direction of the substrate stage WT relative to the support structure (e.g., mask stage) MT can be determined by the magnification (reduction rate) and image inversion characteristics of the projection system PS.

[0038] 3. In another mode, while projecting the pattern applied to the radiation beam B onto the target portion C, the support structure (e.g., a mask stage) MT is kept substantially stationary, thereby holding the programmable patterning device in place, while the substrate stage WT is moved or scanned. A pulsed radiation source SO can be used, and the programmable patterning device can be updated as needed after each movement of the substrate stage WT or between successive radiation pulses during a scan. This mode of operation can be readily applied to maskless lithography using programmable patterning devices (such as programmable mirror arrays).

[0039] Combinations and / or variations or completely different usage patterns described may also be used.

[0040] In some embodiments, the lithography apparatus can generate DUV and / or EUV radiation. For example, the lithography apparatus 100' can be configured to operate using a DUV source. In another example, the lithography apparatus 100 includes an extreme ultraviolet (EUV) source configured to generate an EUV radiation beam for EUV lithography. Generally, the EUV source is configured to be in a radiation system, and a corresponding illumination system is configured to modulate the EUV radiation beam from the EUV source.

[0041] Figure 2 shows the lithography apparatus 100 in more detail, which includes a source collector device SO, an illumination system IL, and a projection system PS. The source collector device SO is constructed and configured such that a vacuum environment can be maintained within the enclosure structure 220 of the source collector device SO. An EUV radiation emitting plasma 210 can be formed by generating a plasma source through discharge. EUV radiation can be generated by a gas or vapor (e.g., Xe gas, Li vapor, or Sn vapor), wherein an extreme thermal plasma 210 is generated to emit radiation in the EUV range of the electromagnetic spectrum. The extreme thermal plasma 210 is generated, for example, by a discharge that causes at least a partially ionized plasma. Xe, Li, Sn vapor, or any other suitable gas or vapor with a partial pressure of 10 Pa may be required for the effective generation of radiation. In some embodiments, an excited tin (Sn) plasma is provided to generate EUV radiation.

[0042] Radiation emitted by the thermoplasm 210 is transferred from the source chamber 211 to the collector chamber 212 via an optional gas barrier or contaminant trap 230 (also referred to in some cases as a contaminant barrier or foil trap) positioned in or behind an opening in the source chamber 211. The contaminant trap 230 may include a channel structure. The contaminant trap 230 may also include a gas barrier, or a combination of a gas barrier and a channel structure. The contaminant trap or contaminant barrier 230 further indicated herein includes at least a channel structure.

[0043] Collector chamber 212 may include a radiation collector CO, which may be a so-called grazing incidence collector. The radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation traversing the collector CO may be reflected from the grating filter 240 to be focused into a virtual source point IF. The virtual source point IF is commonly referred to as the intermediate focus, and the source collector device is configured such that the intermediate focus IF is located at or near the opening 219 in the enclosure structure 220. The virtual source point IF is an image of the radiative emission plasma 210. The grating filter 240 is used in particular to suppress infrared (IR) radiation.

[0044] Subsequently, radiation traverses the illumination system IL, which may include a faceted field mirror device 222 and a faceted pupil mirror device 224, configured to provide the desired angular distribution of the radiation beam 221 at the patterning device MA and the desired uniformity of radiation intensity at the patterning device MA. After the radiation beam 221 is reflected at the patterning device MA held by the support structure MT, a patterned beam 226 is formed, and the patterned beam 226 is imaged by the projection system PS onto the substrate W held by the wafer stage or substrate stage WT via reflective elements 228 and 229.

[0045] More elements than those shown may typically be present in the illumination optics unit IL and the projection system PS. Depending on the type of lithography device, a grating filter 240 may be present. In addition, more mirrors than those shown in FIG2 may be present; for example, one to six additional reflective elements may be present in the projection system PS in addition to those shown in FIG2.

[0046] As shown in Figure 2, the collector optics CO is depicted as a nested collector with grazing incidence reflectors 253, 254, and 255, serving only as an example of a collector (or collector mirror). The grazing incidence reflectors 253, 254, and 255 are arranged symmetrically around the optical axis O, and this type of collector optics CO is preferably used in conjunction with a discharge plasma source (often referred to as a DPP source).

[0047] Exemplary lithography unit

[0048] Figure 3 illustrates a lithography unit 300 according to some embodiments, sometimes also referred to as a lithocell or cluster. Lithography apparatus 100 or 100' may form part of the lithography unit 300. The lithography unit 300 may also include one or more devices for performing pre-exposure and post-exposure processes on a substrate. Conventionally, such devices include a spin coater SC for depositing a resist layer, a developer DE for developing the exposed resist, a cooling plate CH, and a baking plate BK. A substrate handler or robot RO picks up a substrate from input / output ports I / O1, I / O2, moves the substrate between different process devices, and delivers the substrate to the loading area LB of the lithography apparatus 100 or 100'. These devices, often collectively referred to as a coating and developing system (track), are controlled by a coating and developing system control unit TCU, which is itself controlled by a supervisory control system SCS, which in turn controls the lithography apparatus via a lithography control unit LACU. Therefore, different equipment can be operated to maximize output and processing efficiency.

[0049] Exemplary equipment

[0050] In some embodiments, the wafer stage is used to support the wafer during measurement, alignment, and exposure processes in a lithography process. For example, for both the wetting and drying processes, the wafer stage acts as the surface that contacts the wafer in a lithography apparatus (such as the lithography apparatus shown in FIG. 1A or FIG. 1B). The wafer stage may include a plurality of nodules that minimize to the contact surface of the wafer, providing a flat interface to ensure wafer flatness and providing a defined roughness to minimize the wafer loading grid.

[0051] Current processes for manufacturing wafer abutments may include batch production steps that increase production cycle time and the cost of producing wafer abutments. Processes for manufacturing wafer abutments may produce a large number of unusable waste wafer abutments. Current processes for manufacturing wafer abutments may limit the ability to apply high-temperature coatings to nodules, due to limitations in bonding used in existing wafer abutments. Applying high temperatures (e.g., up to 900°C) to the top of existing wafer abutments to increase high-quality materials and new coatings (new materials with desired properties) is challenging due to the instability of waste wafer abutment materials at such high temperatures.

[0052] FIG4 shows a schematic diagram of a wafer stage 400 according to some embodiments. In some embodiments, the wafer stage 400 may be implemented in a lithography apparatus, such as lithography apparatus 100 and / or 100'.

[0053] The wafer stage 400 may include a core module 410, one or more nodule modules 420, one or more cooling channels 430, a backfill gas (BFG) system 440, and one or more bonding contacts 450. In some embodiments, the wafer stage 400 may be manufactured using parallel processing steps for manufacturing the core module 410 and the one or more nodule modules 420.

[0054] For example, as illustrated in FIG5, a waste wafer stage 500 may be used to form (e.g., manufacture) a core module 410. Continuing to refer to FIG4 and FIG5, in some embodiments, the core module 410 may be manufactured by removing (e.g., by mechanical grinding) a nodule 510 from the top and / or bottom surfaces of the waste wafer stage 500. The nodule 510 may be integrated with the waste wafer stage 500 and is referred to as an integrated nodule. In some embodiments, the nodule 510 removed from the waste wafer stage 500 may not be integrated with the waste wafer stage 500.

[0055] Mechanical grinding of nodules 510 can be performed using any suitable technique for abrasive materials (e.g., silicon carbide (SiSiC)).

[0056] Manufacturing the core module 410 may also include grinding the waste wafer stage 500 after removing the nodule 510. For example, grinding the waste wafer stage 500 may include a chemical mechanical polishing (CMP) process. Those skilled in the art will understand that this is merely an example grinding process, and other grinding processes are further covered according to the present invention.

[0057] In some embodiments, one or more nodule modules 420 may be formed (e.g., manufactured) in a separate manufacturing process. For example, as will be understood by those skilled in the art, one or more nodule modules 420 may be manufactured on a second substrate.

[0058] In some embodiments, fabricating one or more nodule modules 420 on a separate substrate allows the use of materials different from those used for the core module 410. For example, the core module 410 can be fabricated using SiSiC, while one or more nodule modules 420 can be fabricated using materials different from those used for the core module 410. As another example, the different materials may have a different crystal structure on the substrate than those used for the core module 410. For example, silicon (Si), sapphire, silicon carbide (SiC), etc., can be used to fabricate one or more nodule modules 420. Those skilled in the art will understand that these are merely examples of materials that can be used for one or more nodule modules, and other materials are further covered according to the present invention.

[0059] In some embodiments, one or more nodule modules 420 may be manufactured using the same material as the core module 410.

[0060] In some embodiments, when the core module 410 is manufactured using a waste wafer stage, the core module 410 includes an upper layer 410a and a lower layer 410b bonded to each other using a bonding agent 410c. As illustrated in FIG4, the nodule 422 bonded to the upper layer 410a may have a different size and shape than the nodule 422 bonded to the lower layer 410b.

[0061] In addition, since the nodule module 420 can be manufactured in a separate process, the coating 424 of the nodule 422 bonded to the upper layer 410a can be a different material than the coating 424 of the nodule 422 bonded to the lower layer 410b.

[0062] In some embodiments, since one or more nodule modules 420 can be manufactured individually, a high temperature (e.g., up to 900°C) can be used to apply coating 424 to each nodule 422 of one or more nodule modules 420. That is, the bonding 410c is no longer a limiting factor for the temperature at which coating 424 can be applied, and therefore, coating 424 can be a high-temperature coating applied to nodule 422. For example, a high-temperature coating can be a coating that requires a temperature greater than 420°C. As an example, a high-temperature coating can be a high-temperature diamond coating that requires 600°C. According to some embodiments, segmentation of the manufacturing process can allow the application of higher temperatures at which coating 424 can be applied to one or more nodule modules 420 without affecting any structural instabilities / sensitivity associated with the bonding within the core module 410.

[0063] In some embodiments, the wafer stage 400 may be formed by bonding the core module 410 and one or more nodule modules 420 to each other. Techniques such as optical contact, solder bonding, adhesive bonding, eutectic bonding, anodic bonding, metal-to-metal diffusion bonding and / or combinations thereof may be used to bond the core module 410 to one or more nodule modules 420.

[0064] Therefore, some embodiments of the present invention provide a manufacturing process for manufacturing the wafer stage 400 in separate manufacturing steps, for example, where the core module 410 and one or more nodule modules 420 are manufactured separately from each other. For example, the core module 410 can be manufactured by refurbishing a waste wafer stage, and one or more nodule modules 420 can be manufactured in parallel on a separate substrate. After the core module 410 and one or more nodule modules 420 are manufactured separately, the core module 410 and one or more nodule modules 420 can be joined together to form the wafer stage 400.

[0065] Figure 6 illustrates an example method 600 according to some embodiments. In one example, method 600 can be used to manufacture a modular wafer stage. It should be understood that not all steps may be required to perform the disclosure provided herein. Furthermore, some steps may be performed simultaneously or in a different order than that shown in Figure 6, as will be understood by those skilled in the art.

[0066] At step 602, one or more nodules may be removed from the surface of the wafer stage. Removal may include mechanically grinding one or more nodules.

[0067] At step 604, the surface of the wafer stage may be ground to form the core module after one or more nodules are removed. According to some embodiments, grinding may include using a chemical mechanical polishing (CMP) process.

[0068] At step 606, a nodule module having a plurality of nodules may be formed thereon. In some embodiments, forming the nodule module separately from the core module may allow the use of different materials applied at different (e.g., high) temperatures without affecting the core module.

[0069] In step 608, the core module may be bonded to the nodule module. According to some embodiments, bonding the core module to the nodule module may include bonding using solder bonding or optical contact.

[0070] According to some embodiments, method 600 may further include forming a high-temperature coating on each of the plurality of nodules. In a non-limiting example, the high-temperature coating may be, for example, a high-temperature diamond coating. According to some embodiments, method 600 may further include manufacturing the nodule module using the same or different material as the material used for the core module.

[0071] It is understood that the proposed manufacturing method for WTs in a separate manufacturing step offers a range of benefits and cost savings to existing manufacturing processes. It is also understood that separate manufacturing steps (e.g., the nodule structure and the core structure) can be completed individually and / or simultaneously, thereby reducing manufacturing time. According to some embodiments, the separate manufacturing process provided herein allows a high-temperature coating to be applied to the top of the nodule structure. The separate manufacturing process allows the nodule structure to be decoupled from any instabilities associated with the core structure and / or associated joints. This, in turn, allows the use of new material fields that can be used to manufacture nodules. For example, nodules can be manufactured using different stable materials with different crystal structures. Thus, the properties of the nodule can be engineered independently of the core structure / material. According to some embodiments, the separate manufacturing process can reduce the current cycle time for existing WT manufacturing processes and can reduce manufacturing costs by enabling the refurbishment of existing discarded WTs (where nodule patterns can be removed by appropriate grinding and polishing steps). Therefore, new coatings such as high-temperature diamond can be applied to the nodules—thereby enabling the creation of more robust nodules with better control over their mechanical / tribomechanical properties.

[0072] In some embodiments, the proposed modular WT manufacturing process described herein can allow the integration of new materials and coatings into existing WT technology—thereby improving wafer load grid (WLG) and addressing stacking issues at the junctions that result in more robust nodule formation. In some embodiments, this can also allow the use of a single-crystal substrate to further engineer the fabrication of the nodule module's crystal structure.

[0073] The embodiments may be further described using the following clauses: 1. A method comprising: removing one or more nodules from a surface of a wafer abutment; grinding the surface of the wafer abutment after removing the one or more nodules to form a core module; forming a nodule module having a plurality of nodules thereon; and bonding the core module to the nodule module. 2. The method of clause 1, wherein bonding the core module to the nodule module comprises using optical contacts to bond the core module and the nodule module. 3. The method of clause 1, wherein bonding the core module to the nodule module comprises using solder bonding to bond the core module and the nodule module. 4. The method of clause 1, wherein: the removal comprises mechanically grinding the one or more nodules; and the grinding comprises using a chemical mechanical polishing (CMP) process. 5. The method of clause 1, further comprising forming a high-temperature coating on each of the plurality of nodules. 6. The method of claim 5, wherein the high-temperature coating is a high-temperature diamond coating. 7. The method of claim 1, further comprising using a material different from the material used for one of the core modules to manufacture the nodule module. 8. The method of claim 1, further comprising using the same material as the material used for one of the core modules to manufacture the nodule module. 9. A wafer abutment comprising: a core module configured to be formed by removing one or more nodules from a surface of a wafer abutment and grinding the surface of the wafer abutment after removing the one or more nodules; a nodule module having a plurality of nodules formed thereon; and a plurality of bonding contacts configured to bond the core module to the nodule module. 10. The wafer abutment of claim 9, wherein the plurality of bonding contacts includes a plurality of optical contacts. 11. The wafer stage of claim 9, wherein the plurality of bonding contacts comprise a plurality of solder bonding contacts. 12. The wafer stage of claim 9, wherein the nodule module comprises a high-temperature coating formed on each of the plurality of nodules. 13. The wafer stage of claim 12, wherein the high-temperature coating comprises a high-temperature diamond coating. 14. The wafer stage of claim 9, wherein the nodule module comprises a material different from a material used in the core module. 15. The wafer stage of claim 9, wherein the nodule module comprises the same material as a material used in the core module. 16. The wafer stage of claim 9, wherein the core module comprises an upper layer and a lower layer bonded to each other. 17. The wafer stage of claim 9, wherein the plurality of bonding contacts comprise adhesive bonding, eutectic bonding, anodic bonding, metal-to-metal diffusion bonding, or anodic bonding.18. A method comprising: forming a core module by: removing one or more nodules from a surface of a wafer abutment by mechanically grinding the one or more nodules; and grinding the surface of the wafer abutment after removing the one or more nodules using a chemical mechanical polishing (CMP) process; forming a nodule module having a plurality of nodules; and bonding the core module to the nodule module using an optical contact solder joint. 19. The method of claim 18, wherein forming a nodule module further comprises forming a high-temperature coating on each of the plurality of nodules before bonding the core module to the nodule module. 20. The method of claim 19, wherein the high-temperature coating is a high-temperature diamond coating. 21. The method of claim 18, wherein the nodule module uses a material different from a material used for the core module.

[0074] Although reference may be specifically made herein to the use of lithography equipment in IC manufacturing, it should be understood that the lithography equipment described herein may have other applications, such as manufacturing integrated optical systems, guiding and detecting patterns for magnetic domain memory, flat panel displays, LCDs, thin-film magnetic heads, etc. Those skilled in the art will understand that, in the context of these alternative applications, any use of the terms "wafer" or "die" herein may be considered synonymous with the more general terms "substrate" or "target portion," respectively. The substrates mentioned herein may be processed before or after exposure in, for example, in a coating and developing system unit (typically a tool for applying a resist layer to a substrate and developing the exposed resist), a measurement unit, and / or a detection unit. Where applicable, the invention herein may be applied to these and other substrate processing tools. Furthermore, the substrate may be processed more than once, for example to produce a multilayer IC, such that the term "substrate" as used herein may also refer to a substrate that already contains multiple processed layers.

[0075] Although reference has been specifically made to the use of embodiments of the invention within the context of optical lithography, it should be understood that the invention can be used in other applications (e.g., imprinting) and is not limited to optical lithography where the context permits. In imprinting, the topography in a patterning apparatus defines a pattern generated on a substrate. The topography of the patterning apparatus can be pressed into a resist layer supplied to the substrate, where the resist is cured by applying electromagnetic radiation, heat, pressure, or a combination thereof. After the resist has cured, the patterning apparatus is removed from the resist, thereby leaving a pattern therein.

[0076] It should be understood that the wording or terminology used herein is for descriptive purposes rather than limiting purposes, and that the terminology or terminology of this invention shall be interpreted by those skilled in the art in accordance with the teachings herein.

[0077] As used herein, the term "substrate" describes a material on which a material layer has been added. In some embodiments, the substrate itself may be patterned, and the material added on top of the substrate may also be patterned, or may remain unpatterned.

[0078] Although reference may be specifically made herein to the use of the apparatus and / or systems according to the invention in IC manufacturing, it should be clearly understood that such apparatus and / or systems have many other possible applications. For example, they can be used to manufacture integrated optical systems, guiding and detection patterns for magnetic domain memory, LCD panels, thin-film magnetic heads, etc. Those skilled in the art will understand that, in the context of such alternative applications, any use of the terms "mask," "wafer," or "die" herein should be considered to be replaced by the more general terms "mask," "substrate," and "target portion," respectively.

[0079] Although specific embodiments of the present invention have been described above, it should be understood that the present invention may be practiced in other ways different from those described. This description is not intended to limit the present invention.

[0080] It should be understood that the Description of Embodiments section, rather than the Summary and Abstract section, is intended to interpret the scope of the patent application. The Summary and Abstract section may set forth one or more, but not all, exemplary embodiments of the invention as contemplated by the inventors, and therefore is not intended to limit the invention or the scope of the appended patent application in any way.

[0081] The present invention has been described above by means of function building blocks illustrating implementations of specific functions and their relationships. For ease of description, the boundaries of these function building blocks have been arbitrarily defined herein. Alternative boundaries can be defined by appropriately specifying the functions and their relationships.

[0082] The foregoing description of specific embodiments will thus fully reveal the general nature of the invention, enabling others to easily modify and / or adapt these specific embodiments for various applications without departing from the general concept of the invention, by applying the knowledge known to those skilled in the art, without engaging in improper experimentation. Therefore, based on the teachings and guidance presented herein, it is intended that such adaptations and refinements fall within the meaning and scope of equivalents of the disclosed embodiments.

[0083] The breadth and scope of the protected subject matter shall not be limited by any of the above exemplary embodiments, but shall be defined only according to the following claims and their equivalents. [Simplified Explanation of the Diagram]

[0010] The accompanying drawings, which are incorporated herein by reference and form a part of this specification, illustrate the invention and, together with the description, further serve to explain the principles of the invention and enable those skilled in the art to make and use the embodiments described herein. Figure 1A shows a schematic diagram of a reflective lithography apparatus according to some embodiments. Figure 1B shows a schematic diagram of a transmissive lithography apparatus according to some embodiments. Figure 2 shows a more detailed schematic diagram of a reflective lithography apparatus according to some embodiments. Figure 3 shows a schematic diagram of a lithography unit according to some embodiments. Figure 4 shows an example modular wafer stage according to some embodiments. Figure 5 shows an example procedure for refurbishing a waste wafer stage according to some embodiments. Figure 6 shows an example procedure for manufacturing a modular wafer stage according to some embodiments. The features of the invention will become apparent from the detailed description set forth below in conjunction with the drawings, in which the same reference numerals identify corresponding elements throughout. In these drawings, the same reference numerals generally indicate the same, functionally similar, and / or structurally similar elements. Furthermore, generally, the leftmost digit of the reference numeral first appears in the drawing of that reference numeral. Unless otherwise indicated, the drawings provided throughout this invention should not be interpreted as drawn to scale.

Claims

1. A method for forming a modular wafer table, comprising: removing one or more burls from a surface of a wafer table; grinding the surface of the wafer table after removing the one or more burls to form a core module; forming a burl module having a plurality of burls thereon; and bonding the core module to the burl module.

2. The method of claim 1, wherein joining the core module to the nodule module comprises using optical contacts to join the core module and the nodule module.

3. The method of claim 1, wherein joining the core module to the nodule module comprises joining the core module and the nodule module using solder joint.

4. As in request item 1, where: The removal involves mechanically grinding the one or more nodules; and the grinding includes using a chemical mechanical grinding (CMP) procedure.

5. The method of claim 1, further comprising forming a high-temperature coating on each of the plurality of nodules, wherein the high-temperature coating is a high-temperature diamond coating.

6. The method of claim 1, further comprising manufacturing the nodule module using a material different from one of the materials used in the core module.

7. The method of claim 1, further comprising manufacturing the nodule module using the same material as one of the materials used in the core module.

8. A wafer stage comprising: a core module configured to be formed by removing one or more nodules from a surface of the wafer stage and grinding the surface of the wafer stage after removing the one or more nodules; a nodule module having a plurality of nodules formed thereon; and a plurality of bonding contacts configured to bond the core module to the nodule module.

9. The wafer stage of claim 8, wherein the plurality of bonding contacts includes a plurality of optical contacts.

10. The wafer stage of claim 8, wherein the plurality of bonding contacts comprises a plurality of solder bonding contacts.

11. As in request item 8, the wafer stage, wherein: The nodule module includes a high-temperature coating formed on each of the plurality of nodules; and the high-temperature coating includes a high-temperature diamond coating.

12. The wafer stage of claim 8, wherein the nodule module comprises a material different from one of the materials used in the core module.

13. The wafer stage of claim 8, wherein the nodule module comprises the same material as one of the materials used in the core module.

14. The wafer stage of claim 8, wherein the core module comprises an upper layer and a lower layer that are bonded to each other.

15. The wafer stage of claim 8, wherein the plurality of bonding contacts comprises adhesive bonding, eutectic bonding, metal-metal diffusion bonding or anodic bonding.

Citation Information

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