Clock generating circuit and system having the same

Abstract

This invention provides a clock generation circuit, comprising an oscillator, a clock counter, a finite state machine, and non-volatile memory. The oscillator outputs an oscillator clock signal with a period based on a trimmed value. The clock counter counts the oscillator clock signal within a reference time. The finite state machine obtains the count value of the counted oscillator clock signal from the clock counter, and in a test mode, compares the count value with a target count value, modifies the trimmed value based on the comparison result, and determines a final trimmed value based on the modified trimmed value. The non-volatile memory stores the determined final trimmed value.

Description

Technical Field

[0001] This disclosure relates to a circuit and method for trimming the period of an oscillator clock signal, and more particularly, to trimming the period of an oscillator clock signal by using a circuit included in a die on a wafer. Cross-reference to related applications

[0002] This application claims the benefit of priority of Korean Patent Application No. 10-2021-0078994, filed on Jun. 17, 2021, with the Korean Intellectual Property Office, under 35 U.S.C. § 119, the disclosure of which is incorporated herein by reference in its entirety.

Background Art

[0003] The oscillator inside the memory is tested using test code of a subsystem on which a central processing unit (CPU) is installed. However, depending on the memory manufacturing environment, a subsystem on which a CPU is installed may not be used, and in this case, logic for testing the oscillator independently of the CPU is required. In addition, due to reasons such as limitations of test equipment, it is necessary to reduce the complexity and time of oscillator testing.

Summary of the Invention

[0004] One aspect is to provide a clock generation circuit and method for trimming the period of an oscillator clock signal, in which the oscillator can be tested independently of a subsystem on which a central processing unit (CPU) is installed.

[0005] According to an aspect of one or more embodiments, there is provided a clock generation circuit including: an oscillator configured to output an oscillator clock signal having a period based on a trimming value; a clock counter configured to count the oscillator clock signal within a reference time; a finite state machine configured to obtain a count value of the counted oscillator clock signal from the clock counter, and in a test mode, compare the count value with a target count value, change the trimming value based on the comparison result, and determine a final trimming value based on the changed trimming value; and a non-volatile memory storing the determined final trimming value.

[0006] According to another aspect of one or more embodiments, a system is provided that includes a plurality of chips in a wafer and a test device. Each chip includes a clock generation circuit that includes: an oscillator configured to output an oscillator clock signal having a period based on a trimming value; a clock counter configured to count the oscillator clock signal within a reference time; a finite state machine configured to obtain a count value of the counted oscillator clock signal from the clock counter, and in a test mode, compare the count value with a target count value, and change the trimming value based on the comparison result, and determine a final trimming value based on the changed trimming value; and a non-volatile memory that stores the determined final trimming value. The test device is configured to test one or more of the plurality of chips, and the plurality of chips are connected in parallel to the test device.

[0007] According to another aspect of one or more embodiments, a method is provided that includes: outputting, by an oscillator, an oscillator clock signal having a period based on a trimming value; counting, by a clock counter, the oscillator clock signal within a reference time; and obtaining, by a finite state machine, a count value of the counted oscillator clock signal, and in a test mode, comparing the count value with a target count value, and changing the trimming value based on the comparison result, and determining a final trimming value based on the changed trimming value.

Embodiments

[0009] Hereinafter, various embodiments will be described with reference to the accompanying drawings.

[0010] FIG. 1 is a block diagram of a clock generation circuit according to an embodiment.

[0011] Referring to FIG. 1, a clock generation circuit 100 for trimming the period of an oscillator clock signal may include a clock counter 110, a finite state machine 130, a non-volatile memory 150, and / or an oscillator 170.

[0012] The clock generation circuit 100 may be a clock generation circuit included in a chip disposed on a wafer. The clock generation circuit 100 may be connected to a test device for testing the chips disposed on the wafer.

[0013] The clock generation circuit 100 may be a digital circuit. Therefore, an analog circuit for comparing the speed of clock signals may not be required.

[0014] In addition, the clock generation circuit 100 may be implemented using standard cells. Therefore, the clock generation circuit 100 may have low dependency.

[0015] The oscillator 170 can be a module configured to output an oscillator clock signal. The oscillator clock signal can be transmitted to another module that uses the clock signal, such as system on a chip (SoC) logic, embedded non-volatile memory (eNVM), etc., and can be transmitted to the clock counter 110.

[0016] The oscillator 170 can be a module configured to receive a trimming value from the finite state machine 130. The trimming value can be a value used to determine the period of the oscillator clock signal. Therefore, the oscillator 170 can be configured to output an oscillator clock signal having a period determined based on the trimming value.

[0017] The clock counter 110 can be a module configured to count the number of pulses of an input clock signal. The clock counter 110 can receive the oscillator clock signal from the oscillator 170. The clock counter 110 can be configured to count the received oscillator clock signal within a reference time. In some embodiments, the reference time can vary depending on the capabilities of modules such as oscillators included in the clock generation circuit 100. For example, the reference time can be, but is not limited to, about 1 millisecond.

[0018] The clock counter 110 can be configured to output the count value of the counted oscillator clock signal to the finite state machine 130. The count value of the oscillator clock signal can be a value obtained by counting the number of pulses of the oscillator clock counter 110 by the clock counter 110 within the reference time.

[0019] The finite state machine 130 can be a machine with a finite number of states. The finite state machine 130 can be configured to switch states depending on a given input or output an output signal according to a condition.

[0020] The finite state machine 130 can be configured to obtain the count value of the oscillator clock signal counted by the clock counter 110. The finite state machine 130 can be configured to change the trimming value based on the count value. The finite state machine 130 can output a signal with the changed trimming value to the non-volatile memory 150 and / or the oscillator 170.

[0021] The finite state machine 130 can be configured to determine a final trimming value by changing the trimming value. The final trimming value can mean a trimming value that enables the oscillator 170 to output an oscillator clock signal having a target period.

[0022] The finite state machine 130 can be configured to operate in any one of a test mode, a verification mode, and a manual trimming mode. For example, a test device connected to the finite state machine 130 can set the finite state machine 130 to operate in any one of a test mode, a verification mode, and a manual trimming mode.

[0023] The test mode can be a mode for trimming the period of the oscillator clock signal to output an oscillator clock signal having a target period. More specifically, the finite state machine 130 can be configured to determine a final trimming value to be used to output an oscillator clock signal having a target period. For example, the finite state machine 130 can be configured to change the trimming value based on the count value of the oscillator clock signal and the target count value. The target count value can be a count value obtained by counting the oscillator clock signal having a target period.

[0024] The finite state machine 130 can be configured to compare the count value of the oscillator clock signal with the target count value in the test mode, and change the trimming value based on the comparison result. The finite state machine 130 can be configured to determine the final trimming value based on the changed trimming value.

[0025] The period of the oscillator clock signal can be trimmed by the finite state machine 130 such that the clock generation circuit 100 can independently trim the period of the oscillator clock signal without depending on the system on which the central processing unit (CPU) is installed. Thereby, even when the system on which the CPU is installed is unavailable or when the test logic for trimming the period of the oscillator clock signal is omitted in the system on which the CPU is installed, the period of the oscillator clock signal is also trimmed.

[0026] The verification mode can be a mode for verifying whether the count value of the oscillator clock signal having a period determined based on the final trimming value obtained by the operation of the test mode falls within the range of the target count value.

[0027] For example, in the verification mode, the finite state machine 130 can be configured to determine whether the count value of the oscillator clock signal having a period determined based on the final trimming value is less than the upper limit and greater than the lower limit. In other words, in the verification mode, the finite state machine 130 can determine whether the count value is within the threshold range. In the verification mode, the finite state machine 130 can be configured to output the determination result to the test device. The test device that has received the determination result can determine whether the operation of the test mode has been successfully executed based on the determination result. For example, when receiving a determination result indicating that the count value is less than the upper limit and greater than the lower limit, it can be determined that the operation of the test mode has been successfully executed. That is, the test device can be configured to determine that trimming the period of the oscillator clock signal in the test mode is successful when the test device receives a determination result indicating that the count value is less than the upper limit and greater than the lower limit.

[0028] The manual trimming mode can be a mode for identifying the period of the oscillator clock signal.

[0029] For example, in the manual trimming mode, the finite state machine 130 can be configured to obtain the count value of the oscillator clock signal and output the count value to the test device. The test device can obtain the period of the oscillator clock signal based on the count value of the oscillator clock signal. The verification mode and the manual trimming mode will be described in more detail later.

[0030] The non-volatile memory 150 can be configured to store the trimming value. In some embodiments, the stored trimming value can be the final trimming value. The non-volatile memory 150 can be configured to output a signal having the stored trimming value to the oscillator 170.

[0031] After performing the operation of the test mode, the final trimming value can be stored in the non-volatile memory 150. The oscillator 170 can output the oscillator clock signal based on the final trimming value obtained from the non-volatile memory 150. Therefore, the clock generation circuit 100 according to the embodiment can output an oscillator clock signal having a target period by using the final trimming value stored in the non-volatile memory 150, without the need to perform an additional operation of trimming the period of the oscillator clock signal after performing the operation of the test mode. In other words, the clock generation circuit 100 can use the final trimming value to output an oscillator clock signal having a target period, without the need to have a separate mode for trimming the period of the oscillator clock signal.

[0032] FIG. 2 is a block diagram of a clock generation circuit according to an embodiment.

[0033] Referring to FIG. 2, a clock generation circuit 200 for trimming the period of an oscillator clock signal according to an embodiment may include a clock counter 210, a finite state machine 230, a non-volatile memory 250, a multiplexer 260, and / or an oscillator 270.

[0034] The clock counter 210, the finite state machine 230, the non-volatile memory 250, and / or the oscillator 270 may respectively correspond to the clock counter 110, the finite state machine 130, the non-volatile memory 150, and / or the oscillator 170 of FIG. 1, and may be configured to respectively perform functions identical to those of the clock counter 110, the finite state machine 130, the non-volatile memory 150, and / or the oscillator 170 of FIG. 1.

[0035] The oscillator 270 may output an oscillator clock signal OSC Clock to another module that uses the clock signal, such as system-on-chip (SoC) logic, embedded non-volatile memory (eNVM), etc. The oscillator 270 may output the clock signal OSC Clock to the clock counter 210. As described above, the clock counter 210 may receive the oscillator clock signal OSC Clock from the oscillator 270 and count the oscillator clock signal within a reference time. The count value of the counted oscillator clock signal may be output to the finite state machine 230.

[0036] The finite state machine 230 may output a count enable signal count_en to the clock counter 210. The clock counter 210 may determine whether to operate based on the count enable signal count_en. In other words, in some embodiments, the finite state machine 230 may control the operation of the clock counter 210. For example, when a count enable signal count_en having a value of 1 is input to the clock counter 210, the clock counter 210 may be configured to count the oscillator clock signal. When a count enable signal count_en having a value of 0 is input to the clock counter 210, the clock counter 210 may stop counting the oscillator clock signal. However, the embodiments are not limited thereto. In some embodiments, the clock counter 210 may be configured to count the oscillator clock signal, then input a count enable signal count_en having a value of 0 to the clock counter 210, and stop counting the oscillator clock signal when a clock enable signal count_en having a value of 1 is input to the clock counter 210.

[0037] The finite state machine 230 can output a clock enable signal with a value of 1 to enable the operation of the clock counter 210, and after the reference time has passed, it can output a clock enable signal with a value of 0 to stop the operation of the clock counter 210. Therefore, the clock counter 210 can output a signal with a count value obtained by counting the oscillator clock signal within the reference time to the finite state machine 230.

[0038] The finite state machine 230 can be configured to receive a test clock signal Test Clock from a test device. The period of the test clock signal can be determined based on the capabilities of the chip under test, etc., without considering the target period of the oscillator clock signal. The period of the test clock signal can be calculated and determined by the test device. Therefore, the reference clock can be omitted from the clock generation circuit 200. The finite state machine 230 receives an independent test clock signal, such that even when the target frequency of the oscillator clock signal is high, it is not necessary to drive the finite state machine 230 at a high frequency, and thus, when using the clock generation circuit 200, chip testing can be performed with low power. In other words, the finite state machine 230 can receive a test clock signal independent of the oscillator clock signal. In some embodiments, the term "independent" can mean that the test clock signal starts, ends, and / or changes without depending on the start, end, and / or change of the oscillator clock signal, and the oscillator clock signal starts, ends, and / or changes without depending on the start, end, and / or change of the test clock signal. In some embodiments, alternatively or additionally, the term "independent" can mean that the period of the test clock signal is different from the period of the oscillator clock signal.

[0039] The finite state machine 230 can be configured to receive a target count value Target Count from a test device. As described above, the finite state machine 230 can be configured to change the trimming value based on the count value of the oscillator clock signal and the target count value Target Count input to the finite state machine 230.

[0040] The finite state machine 230 can be configured to receive a start signal Start from a test device. The finite state machine 230 can perform operations in response to the start signal Start.

[0041] The finite state machine 230 can be configured to output an end signal Done to the test device. When it is determined that the operation is ended, the finite state machine 230 can output the end signal Done to the test device. In other words, in some embodiments, the test device can control the start and stop operations of the finite state machine 230.

[0042] The finite state machine 230 can be configured to output the result signal Result of the operation to the test device. For example, the finite state machine 230 can be configured to output the count value of the oscillator clock signal obtained in the manual trimming mode as the result signal Result to the test device.

[0043] The finite state machine 230 can receive the mode signal FS Mode from the test device. The mode signal FS Mode can be a signal for determining the mode of operation of the finite state machine 230. As described above, the mode can be any one of the test mode, the verification mode, and the manual trimming mode.

[0044] The finite state machine 230 can be configured to output the trimming value to the non-volatile memory 250 and / or the multiplexer 260. For example, the finite state machine 230 can change the trimming value as described above and can output the changed trimming value to the non-volatile memory 250 and / or the multiplexer 260. The finite state machine 230 can be configured to output a write enable signal write_en to the non-volatile memory 250. For example, when the finite state machine 230 determines that the changed trimming value is the final trimming value, the finite state machine 230 can store the final trimming value in the non-volatile memory 250 by using the write enable signal write_en.

[0045] The non-volatile memory 250 can be configured to store the trimming value in response to the write enable signal write_en.

[0046] The multiplexer 260 can be configured to receive a signal with a trimming value from the finite state machine 230, receive the output signal of the non-volatile memory 250, and receive a test mode signal Test Mode from the test device. The multiplexer 260 can be configured to output the trimming value to the oscillator 270 based on the test mode signal Test Mode. For example, when the test mode is executed in response to the test mode signal Test Mode, the trimming value of the multiplexer 260 can be output to the oscillator 270. When the test mode ends, the trimming value stored in the non-volatile memory 250 can be output to the oscillator 270, but not limited thereto. For example, in some embodiments, when the test mode signal Test Mode has a value of 1, the multiplexer 260 can select the trimming value and output the trimming value to the oscillator 270, and when the test mode signal Test Mode has a value of 0, the multiplexer 260 can select the stored trimming value and output the stored trimming value to the oscillator 270. However, the embodiments are not limited thereto, and in other embodiments, when the test mode signal Test Mode has a value of 0, the multiplexer 260 can select the trimming value and output the trimming value to the oscillator 270, and when the test mode signal Test Mode has a value of 1, the multiplexer 260 can select the stored trimming value and output the stored trimming value to the oscillator 270.

[0047] FIG. 3 is a block diagram of a system according to an embodiment.

[0048] Referring to FIG. 3, a system for trimming the period of an oscillator clock signal according to an embodiment may include a test device 310 and a plurality of chips CHIP_0 330, CHIP_1 331 to CHIP_N 332.

[0049] The test device 310 may be a device for testing the chips in a wafer. For example, the test device 310 may be an automated test equipment (ATE), but not limited thereto.

[0050] Each of the plurality of chips 330, chips 331 to chips 332 (i.e., the plurality of chips CHIP_0 330, CHIP_1 331 to CHIP_N 332) may include a clock generation circuit for trimming the period of the oscillator clock signal according to an embodiment. That is, as described above with reference to FIGS. 1 and 2, each of the plurality of chips 330, chips 331, and chips 332 may include a clock counter, a finite state machine, a non-volatile memory, and / or an oscillator.

[0051] Multiple chips 330, chip 331, and chip 332 can be connected in parallel to the test device 310. When using a clock generation circuit, the test device 310 can identify the test result by determining pass or fail without performing complex calculations or additional calculations on the output value of the clock generation circuit. For example, when a finite state machine operates in the verification mode after performing operations in the test mode, the finite state machine can determine whether the counted value of the oscillator clock signal falls within the range from the upper limit to the lower limit and output the determination result to the test device 310 that can determine pass or fail based on the determination result. Therefore, since there is no need to perform complex calculations or additional calculations, the test device 310 can test multiple chips 330, chip 331, and chip 332 simultaneously in parallel. Therefore, the test time for trimming the period of the oscillator clock signal can be significantly reduced. For example, when testing 256 chips in parallel compared to testing a single chip serially, the test time can be reduced by 1 / 256 times.

[0052] The finite state machine included in each of the multiple chips 330, chip 331, and chip 332 can input and output signals without being restricted by the interface type. In some embodiments, the finite state machine can use an interface for each system-on-chip (SoC). For example, in some embodiments, the finite state machine can include serial wire debug (SWD) and special function register (SFR). The test device 310 can use serial wire debug (SWD) to set the special function register (SFR), and the special function register (SFR) can in turn provide various signals as discussed above to the finite state machine.

[0053] FIG. 4 is a flowchart of a method for trimming the period of an oscillator clock signal according to an embodiment.

[0054] Referring to FIG. 4, the method for trimming the period of an oscillator clock signal according to an embodiment can include multiple operations S410, operation S420, and operation S430.

[0055] In operation S410, an oscillator clock signal having a period determined based on a trimming value can be output. For example, the method for trimming the period of an oscillator clock signal can output an oscillator clock signal having a period determined based on a trimming value by using an oscillator.

[0056] In operation S420, the oscillator clock signal can be counted within a reference time. For example, the method for trimming the period of an oscillator clock signal can count the oscillator clock signal within a reference time by using a clock counter.

[0057] In operation S430, a count value of the counted oscillator clock signal can be obtained, and the count value can be compared with a target count value, and in the test mode, a trimming value can be changed based on the comparison result to determine the final trimming value. For example, a method of trimming the period of the oscillator clock signal can obtain the count value of the counted oscillator clock signal from a clock counter by using a finite state machine, and in the test mode, compare the count value with the target count value and change the trimming value based on the comparison result to determine the final trimming value.

[0058] FIG. 5 is a flowchart of an algorithm for trimming the period of an oscillator clock signal according to an embodiment.

[0059] Referring to FIG. 5, in operation S510, a test mode for trimming the period of the oscillator clock signal can be started.

[0060] In operation S520, the oscillator can output an oscillator clock signal with a preset trimming value. In addition, assuming that the reference time described above is 1 millisecond, a finite state machine (FSM) counter value based on nanosecond units can be set to 1,000,000, and the clock counter can operate via a count enable signal count_en. For example, the value of the count enable signal count_en can be set to 1.

[0061] In operation S530, a value obtained by subtracting the period of the test clock from the FSM counter value can be calculated.

[0062] In operation S540, it can be determined whether the FSM counter value is less than 0. In operation S540, when the value obtained by subtracting the period of the test clock from the FSM counter value is less than 0 (S540, Y), the operation of the clock counter can be stopped by setting the value of the count enable signal count_en to 0. When the value obtained by subtracting the period of the test clock from the FSM counter value is greater than or equal to 0 (S540, N), the period of the test clock can be subtracted from the FSM counter value again. That is, an algorithm for obtaining the count value of the oscillator clock signal can be executed when 1 millisecond has elapsed.

[0063] In operation S550, it can be determined whether the target count value input from the test device is greater than or equal to the count value of the oscillator clock signal counted within the reference time.

[0064] When the target count value is greater than or equal to the count value (S550, Y), in operation S560, the finite state machine can gradually decrease the trimming value. More specifically, the finite state machine can decrease the trimming value by one step (1 step). In this case, the amount of the trimming value decreased by one step can be determined depending on the test environment. The operation performed on the current trimming value can be set to DOWN.

[0065] In operation S561, the finite state machine can determine whether the operation performed on the previous trimming value is DOWN.

[0066] When operation S562 (i.e., the operation performed on the previous trimming value) is DOWN (S562, Y), in operation S573, the finite state machine can determine whether the trimming value is the upper limit MAX or the lower limit MIN.

[0067] When it is determined in operation S561 that the operation performed on the previous trimming value is not DOWN (S561, N), in operation S580, it can be determined whether the operation performed on the current trimming value is DOWN and whether the operation performed on the previous trimming value is UP.

[0068] When it is determined in operation S550 that the target count value is less than the count value (S550, N), in operation S570, the finite state machine can gradually increase the trimming value. More specifically, the finite state machine can increase the trimming value by one step (1 step). In this case, the amount of the trimming value increased by one step can be determined depending on the test environment. The operation performed on the current trimming value can be set to UP.

[0069] In operation S571, the finite state machine can determine whether the operation performed on the previous trimming value is UP.

[0070] When operation S572 (i.e., the operation performed on the previous trimming value) is UP (S571, Y), in operation S573, the finite state machine can determine whether the trimming value is the upper limit or the lower limit.

[0071] When it is determined in operation S571 that the operation performed on the previous trimming value is not UP (S571, N), in operation S580, it can be determined whether the operation performed on the current trimming value is DOWN and whether the operation performed on the previous trimming value is UP.

[0072] When the trimming value is at the upper limit or the lower limit (S573, Y), in operation S590, the current trimming value can be programmed into the non-volatile memory. In some embodiments, the non-volatile memory can be an embedded non-volatile memory (eNVM). When the trimming value is not at the upper limit or not at the lower limit (S573, N), the program can return to operation S530.

[0073] It can be determined in operation S580 whether the operation performed on the current trimming value is DOWN and whether the operation performed on the previous trimming value is UP. When the operation performed on the current trimming value is DOWN and the operation performed on the previous trimming value is UP (S580, Y), in operation S581, the trimming value can be increased by one step.

[0074] When the operation performed on the current trimming value is not DOWN or the operation performed on the previous trimming value is not UP (S580, N), in operation S590, the current trimming value can be programmed into the non-volatile memory. In some embodiments, the non-volatile memory can be an embedded non-volatile memory (eNVM).

[0075] That is, when the count value of the oscillator clock signal is less than or equal to the target count value, the finite state machine can be configured to gradually decrease the trimming value. When the count value of the oscillator clock signal is greater than the target count value, the finite state machine can be configured to gradually increase the trimming value.

[0076] The oscillator can be configured to output an oscillator clock signal with a shorter period as the input trimming value decreases.

[0077] When the trimming value gradually decreases, the finite state machine can be configured to determine the trimming value corresponding to the time when the count value starts to be greater than the target count value as the count value increases as the final trimming value.

[0078] When the trimming value gradually increases, the finite state machine can be configured to determine the trimming value corresponding to the time before the count value is about to start being greater than the target count value as the count value decreases as the final trimming value.

[0079] That is, when the count value exceeds the target count value as the count value increases, the finite state machine can determine the trimming value corresponding to the count value that exceeds the target count value as the final trimming value.

[0080] In addition, when the count value is less than the target count value as the count value decreases, the finite state machine can determine the trimming value corresponding to the count value that is less than the target count value as the final trimming value.

[0081] The finite state machine can be configured to determine the trimming value corresponding to the value closest to the target count value among the count values exceeding the target count value as the final trimming value, but is not limited thereto. That is, the finite state machine can be configured to determine the trimming value corresponding to the value closest to the target count value among the count values less than the target count value as the final trimming value, but is not limited thereto.

[0082] The non-volatile memory can be configured to store the determined final trimming value.

[0083] In operation S591, when the current trimming value is programmed into the non-volatile memory, the algorithm for trimming the period of the oscillator clock signal can end.

[0084] FIG. 6 is a flowchart for describing the verification mode according to an embodiment.

[0085] Referring to FIG. 6, in operation S610, the method according to the embodiment can start the verification mode operation.

[0086] As described above with respect to FIG. 5, assuming that the reference time for counting the oscillator clock signal by the clock counter is 1 millisecond, the FSM counter value can be set to 1000000. To operate the clock counter, the value of the count enable signal count_en can be set to 1.

[0087] In operation S620, the finite state machine can subtract the period of the test clock from the FSM counter value.

[0088] In operation S630, the finite state machine can determine whether the value obtained by subtracting the period of the test clock from the FSM counter value is less than 0. When the value obtained by subtracting the period of the test clock from the FSM counter value is greater than or equal to 0 (S630, N), the program can return to operation S620 and can subtract the period of the test clock from the value obtained by subtracting the period of the test clock from the FSM counter value again.

[0089] When the value obtained by subtracting the period of the test clock from the FSM counter value is less than 0 (S630, Y), the value of the count enable signal count_en can be set to 0 to stop the operation of the clock counter. In operation S640, the finite state machine can determine whether the target count value input from the test device is greater than or equal to the count value of the oscillator clock signal.

[0090] When the count value of the oscillator clock signal is greater than or equal to the target count value (S640, Y), in operation S650, the verification result can be set to DOWN.

[0091] When the count value of the oscillator clock signal is less than the target count value (S640, N), in operation S660, the verification result can be set to UP.

[0092] As described above, when the verification result is set to DOWN or UP, the verification mode can end in operation S670.

[0093] That is, when the current period of the oscillator clock signal is shorter than the target period, since the count value of the oscillator clock signal is greater than the target count value, the method shown in FIG. 6 can set the result value of the verification mode to UP, and in the opposite case, the result value of the verification mode can be set to DOWN. Therefore, the method shown in FIG. 6 can determine whether the count value of the oscillator clock signal is less than the upper limit and whether the count value is greater than the lower limit, and determine whether the period of the oscillator clock signal is trimmed within the required range.

[0094] FIG. 7 is a flowchart for describing the manual trimming mode according to an embodiment.

[0095] Referring to FIG. 7, in operation S710, the method can start the manual trimming mode operation.

[0096] As described above with respect to FIG. 5, assuming that the reference time for counting the oscillator clock signal by the clock counter is 1 millisecond, the FSM counter value can be set to 1000000. To operate the clock counter, the value of the count enable signal count_en can be set to 1.

[0097] In operation S720, the finite state machine can subtract the period of the test clock from the FSM counter value.

[0098] In operation S730, the finite state machine can determine whether the value obtained by subtracting the period of the test clock from the FSM counter value is less than 0. When the value obtained by subtracting the period of the test clock from the FSM counter value is greater than or equal to 0 (S730, N), the program can return to operation S720 and can subtract the period of the test clock from the value obtained by subtracting the period of the test clock from the FSM counter value again.

[0099] When the value obtained by subtracting the period of the test clock from the FSM counter value is less than 0 (S730, Y), the value of the count enable signal count_en can be set to 0 to stop the operation of the clock counter. In operation S740, the finite state machine can set the count value of the oscillator clock signal as the manual result of the manual trimming mode.

[0100] In operation S750, the method can terminate the manual trimming mode.

[0101] FIG. 8 is a timing diagram for describing counting according to an embodiment.

[0102] Referring to FIG. 8, as described above with reference to FIGS. 5 to 7, the FSM counter value can be set to 1,000,000 nanoseconds. The value of 1,000,000 nanoseconds can be based on the assumption that the reference time for counting the oscillator clock signal is 1 millisecond. The period of the test clock signal, 30 nanoseconds, can be subtracted from the FSM counter value, and the count value of the oscillator clock signal, 16554, can be obtained based on the value before it becomes 0 by subtracting the period of the test clock signal from the FSM counter value.

[0103] However, values such as 1 millisecond and 1,000,000 nanoseconds included in the foregoing description are exemplary and the embodiments are not limited thereto. For example, the period of the test clock signal can vary from chip to chip and can be a fixed value or a variable value in each chip.

[0104] FIG. 9 is a diagram for describing the period of the oscillator clock signal trimmed by the clock generation circuit according to an embodiment.

[0105] In FIG. 9, the period of the oscillator clock signal before trimming and the period of the oscillator clock signal trimmed by the clock generation circuit according to an embodiment are plotted as a graph.

[0106] Referring to FIG. 9, the period of the oscillator clock signal before trimming is distributed between 53 nanoseconds and 61 nanoseconds. When the period of the oscillator clock signal is trimmed to a target period of 61 nanoseconds using the method of trimming the period according to an embodiment, the period of the oscillator clock signal can be distributed between 59.5 nanoseconds and 62.5 nanoseconds and the period of the oscillator clock signal can be effectively trimmed.

[0107] Although various embodiments have been specifically illustrated and described with reference to the drawings, it should be understood that various changes can be made in form and detail without departing from the spirit and scope of the following claims.

Brief Description of the Drawings

[0008] The following detailed description in conjunction with the accompanying drawings will more clearly understand various embodiments. In the accompanying drawings: FIG. 1 is a block diagram of a clock generation circuit according to an embodiment. FIG. 2 is a block diagram of a clock generation circuit according to an embodiment. FIG. 3 is a block diagram of a system according to an embodiment. FIG. 4 is a flowchart of a method for trimming the period of an oscillator clock signal according to an embodiment. FIG. 5 is a flowchart of an algorithm for trimming the period of an oscillator clock signal according to an embodiment. FIG. 6 is a flowchart for describing a verification mode according to an embodiment. FIG. 7 is a flowchart for describing a manual trimming mode according to an embodiment. FIG. 8 is a timing diagram for describing counting according to an embodiment. FIG. 9 is a diagram for describing the period of an oscillator clock signal trimmed by a clock generation circuit according to an embodiment.

Claims

1. A clock generation circuit, comprising: An oscillator, configured to output an oscillator clock signal with a period based on a trimmed value; A clock counter is configured to count the oscillator clock signal within a reference time. A finite state machine is configured to obtain the count value of the counted oscillator clock signal from the clock counter, and in test mode, compare the count value with a target count value, modify the trim value based on the comparison result, and determine a final trim value based on the modified trim value. The finite state machine is further configured to: modify the trim value to extend the period based on the count value being greater than the target count value; and modify the trim value to shorten the period based on the count value being less than or equal to the target count value. A non-volatile memory stores the determined final trim value.

2. The clock generation circuit as claimed in claim 1, wherein the oscillator is further configured to output an oscillator clock signal with a shorter period as the trim value decreases.

3. The clock generation circuit as claimed in claim 2, wherein the finite state machine is further configured to: determine the trimmed value corresponding to the count value exceeding the target count value as the final trimmed value when the count value exceeds the target count value as the count value increases; and determine the trimmed value corresponding to the count value less than the target count value as the final trimmed value when the count value decreases and becomes less than the target count value as the final trimmed value.

4. The clock generation circuit as claimed in claim 2, wherein the finite state machine is further configured to determine the trimmed value as the final trimmed value, which corresponds to the value closest to the target count value among the count values ​​exceeding the target count value.

5. The clock generation circuit as claimed in claim 3, wherein the finite state machine is further configured to store the determined final trim value in the non-volatile memory; and the oscillator is further configured to output the oscillator clock signal having a period based on the stored final trim value.

6. The clock generation circuit as claimed in claim 1, wherein the finite state machine is further configured to determine in verification mode whether the count value of the oscillator clock signal having a period based on the final trimmed value is less than an upper limit and greater than a lower limit, and outputs the determination result to a test device.

7. The clock generation circuit as claimed in claim 1, wherein the finite state machine is further configured to output the count value to the test device in a manual trimming mode.

8. The clock generation circuit as claimed in claim 1, wherein the finite state machine is further configured to receive a test clock signal independent of the oscillator clock signal, and such that the clock counter operates according to the test clock signal within the reference time.

9. A system having a clock generation circuit, comprising: A plurality of wafers, each of the plurality of wafers comprising: a clock generation circuit including an oscillator configured to output an oscillator clock signal having a period based on a trimmed value; a clock counter configured to count the oscillator clock signal over a reference time; a finite state machine configured to obtain a count value of the counted oscillator clock signal from the clock counter, and in a test mode, compare the count value with a target count value, modify the trimmed value based on the comparison result, and determine a final trimmed value based on the modified trimmed value; a non-volatile memory storing the determined final trimmed value; and a test apparatus configured to test one or more of the plurality of wafers, wherein the plurality of wafers are connected in parallel to the test apparatus.

10. The system with clock generation circuitry as claimed in claim 9, wherein the finite state machine is further configured to: gradually increase the trim value when the count value is greater than the target count value; And when the count value is less than the target count value, the trim value is gradually reduced; The oscillator is further configured to output an oscillator clock signal with a shorter period as the trim value decreases.

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